mlx_link_speed.h File Reference

#include "../../mlx_lib/mlx_reg_access/mlx_reg_access.h"
#include "../../include/public/mlx_utils.h"

Go to the source code of this file.

Data Structures
struct	mlx_link_speed

Macros
#define	LINK_SPEED_100GB_MASK   (ETH_SPEED_ENABLE_MASK_100GBASECR4 | ETH_SPEED_ENABLE_MASK_100GBASESR4 | ETH_SPEED_ENABLE_MASK_100GBASEKR4 | ETH_SPEED_ENABLE_MASK_100GBASELR4)
#define	LINK_SPEED_56GB_MASK   (ETH_SPEED_ENABLE_MASK_56GBASER4)
#define	LINK_SPEED_50GB_MASK   (ETH_SPEED_ENABLE_MASK_50GBASECR2 | ETH_SPEED_ENABLE_MASK_50GBASEKR2)
#define	LINK_SPEED_40GB_MASK   (ETH_SPEED_ENABLE_MASK_40GBASECR4 | ETH_SPEED_ENABLE_MASK_40GBASEKR4 | ETH_SPEED_ENABLE_MASK_40GBASESR4 | ETH_SPEED_ENABLE_MASK_40GBASELR4)
#define	LINK_SPEED_25GB_MASK   (ETH_SPEED_ENABLE_MASK_25GBASECR | ETH_SPEED_ENABLE_MASK_25GBASEKR | ETH_SPEED_ENABLE_MASK_25GBASESR)
#define	LINK_SPEED_20GB_MASK   (ETH_SPEED_ENABLE_MASK_20GBASER2)
#define	LINK_SPEED_10GB_MASK   (ETH_SPEED_ENABLE_MASK_10GBASECR | ETH_SPEED_ENABLE_MASK_10GBASESR | ETH_SPEED_ENABLE_MASK_10GBASELR | ETH_SPEED_ENABLE_MASK_10GBASEKR)
#define	LINK_SPEED_1GB_MASK   (ETH_SPEED_ENABLE_MASK_1000BASECX | ETH_SPEED_ENABLE_MASK_1000BASEKX | ETH_SPEED_ENABLE_MASK_100BaseTX | ETH_SPEED_ENABLE_MASK_1000BASET)
#define	LINK_SPEED_SDR_MASK   0x1
#define	LINK_SPEED_DDR_MASK   0x2
#define	LINK_SPEED_QDR_MASK   0xC
#define	LINK_SPEED_FDR_MASK   0x10
#define	LINK_SPEED_EDR20_MASK   0x200
#define	LINK_SPEED_EDR_MASK   0x20
#define	LINK_SPEED_WITDH_1_MASK   0x1
#define	LINK_SPEED_WITDH_2_MASK   0x2
#define	LINK_SPEED_WITDH_4_MASK   0x4
#define	LINK_SPEED_WITDH_8_MASK   0x8
#define	LINK_SPEED_WITDH_12_MASK   0x10
#define	GIGA_TO_BIT   0x40000000

Enumerations
enum	{   ETH_SPEED_ENABLE_MASK_1000BASECX = 0x0001, ETH_SPEED_ENABLE_MASK_1000BASEKX = 0x0002, ETH_SPEED_ENABLE_MASK_10GBASECX4 = 0x0004, ETH_SPEED_ENABLE_MASK_10GBASEKX4 = 0x0008,   ETH_SPEED_ENABLE_MASK_10GBASEKR = 0x0010, ETH_SPEED_ENABLE_MASK_20GBASER2 = 0x0020, ETH_SPEED_ENABLE_MASK_40GBASECR4 = 0x0040, ETH_SPEED_ENABLE_MASK_40GBASEKR4 = 0x0080,   ETH_SPEED_ENABLE_MASK_56GBASER4 = 0x0100, ETH_SPEED_ENABLE_MASK_10GBASECR = 0x1000, ETH_SPEED_ENABLE_MASK_10GBASESR = 0x2000, ETH_SPEED_ENABLE_MASK_10GBASELR = 0x4000,   ETH_SPEED_ENABLE_MASK_40GBASESR4 = 0x8000, ETH_SPEED_ENABLE_MASK_40GBASELR4 = 0x10000, ETH_SPEED_ENABLE_MASK_50GBASEKR4 = 0x80000, ETH_SPEED_ENABLE_MASK_100GBASECR4 = 0x100000,   ETH_SPEED_ENABLE_MASK_100GBASESR4 = 0x200000, ETH_SPEED_ENABLE_MASK_100GBASEKR4 = 0x400000, ETH_SPEED_ENABLE_MASK_100GBASELR4 = 0x800000, ETH_SPEED_ENABLE_MASK_100BaseTX = 0x1000000,   ETH_SPEED_ENABLE_MASK_1000BASET = 0x2000000, ETH_SPEED_ENABLE_MASK_10GBASET = 0x4000000, ETH_SPEED_ENABLE_MASK_25GBASECR = 0x8000000, ETH_SPEED_ENABLE_MASK_25GBASEKR = 0x10000000,   ETH_SPEED_ENABLE_MASK_25GBASESR = 0x20000000, ETH_SPEED_ENABLE_MASK_50GBASECR2 = 0x40000000, ETH_SPEED_ENABLE_MASK_50GBASEKR2 = 0x80000000, ETH_SPEED_ENABLE_MASK_BAD = 0xffff }
enum	LINK_SPEED_TYPE { LINK_SPEED_IB = 0, LINK_SPEED_FC, LINK_SPEED_ETH }
enum	LINK_SPEED {   LINK_SPEED_1GB = 0, LINK_SPEED_10GB, LINK_SPEED_40GB, LINK_SPEED_100GB,   LINK_SPEED_SDR, LINK_SPEED_DEFAULT }

Functions
	FILE_LICENCE (GPL2_OR_LATER)
mlx_status	mlx_set_link_speed (IN mlx_utils *utils, IN mlx_uint8 port_num, IN LINK_SPEED_TYPE type, IN LINK_SPEED speed)
mlx_status	mlx_get_max_speed (IN mlx_utils *utils, IN mlx_uint8 port_num, IN LINK_SPEED_TYPE type, OUT mlx_uint64 *speed)

Macro Definition Documentation

LINK_SPEED_100GB_MASK

#define LINK_SPEED_100GB_MASK   (ETH_SPEED_ENABLE_MASK_100GBASECR4 | ETH_SPEED_ENABLE_MASK_100GBASESR4 | ETH_SPEED_ENABLE_MASK_100GBASEKR4 | ETH_SPEED_ENABLE_MASK_100GBASELR4)

Definition at line 28 of file mlx_link_speed.h.

LINK_SPEED_56GB_MASK

#define LINK_SPEED_56GB_MASK   (ETH_SPEED_ENABLE_MASK_56GBASER4)

Definition at line 29 of file mlx_link_speed.h.

LINK_SPEED_50GB_MASK

#define LINK_SPEED_50GB_MASK   (ETH_SPEED_ENABLE_MASK_50GBASECR2 | ETH_SPEED_ENABLE_MASK_50GBASEKR2)

Definition at line 30 of file mlx_link_speed.h.

LINK_SPEED_40GB_MASK

#define LINK_SPEED_40GB_MASK   (ETH_SPEED_ENABLE_MASK_40GBASECR4 | ETH_SPEED_ENABLE_MASK_40GBASEKR4 | ETH_SPEED_ENABLE_MASK_40GBASESR4 | ETH_SPEED_ENABLE_MASK_40GBASELR4)

Definition at line 31 of file mlx_link_speed.h.

LINK_SPEED_25GB_MASK

#define LINK_SPEED_25GB_MASK   (ETH_SPEED_ENABLE_MASK_25GBASECR | ETH_SPEED_ENABLE_MASK_25GBASEKR | ETH_SPEED_ENABLE_MASK_25GBASESR)

Definition at line 32 of file mlx_link_speed.h.

LINK_SPEED_20GB_MASK

#define LINK_SPEED_20GB_MASK   (ETH_SPEED_ENABLE_MASK_20GBASER2)

Definition at line 33 of file mlx_link_speed.h.

LINK_SPEED_10GB_MASK

#define LINK_SPEED_10GB_MASK   (ETH_SPEED_ENABLE_MASK_10GBASECR | ETH_SPEED_ENABLE_MASK_10GBASESR | ETH_SPEED_ENABLE_MASK_10GBASELR | ETH_SPEED_ENABLE_MASK_10GBASEKR)

Definition at line 34 of file mlx_link_speed.h.

LINK_SPEED_1GB_MASK

#define LINK_SPEED_1GB_MASK   (ETH_SPEED_ENABLE_MASK_1000BASECX | ETH_SPEED_ENABLE_MASK_1000BASEKX | ETH_SPEED_ENABLE_MASK_100BaseTX | ETH_SPEED_ENABLE_MASK_1000BASET)

Definition at line 35 of file mlx_link_speed.h.

LINK_SPEED_SDR_MASK

#define LINK_SPEED_SDR_MASK   0x1

Definition at line 37 of file mlx_link_speed.h.

LINK_SPEED_DDR_MASK

#define LINK_SPEED_DDR_MASK   0x2

Definition at line 38 of file mlx_link_speed.h.

LINK_SPEED_QDR_MASK

#define LINK_SPEED_QDR_MASK   0xC

Definition at line 39 of file mlx_link_speed.h.

LINK_SPEED_FDR_MASK

#define LINK_SPEED_FDR_MASK   0x10

Definition at line 40 of file mlx_link_speed.h.

LINK_SPEED_EDR20_MASK

#define LINK_SPEED_EDR20_MASK   0x200

Definition at line 41 of file mlx_link_speed.h.

LINK_SPEED_EDR_MASK

#define LINK_SPEED_EDR_MASK   0x20

Definition at line 42 of file mlx_link_speed.h.

LINK_SPEED_WITDH_1_MASK

#define LINK_SPEED_WITDH_1_MASK   0x1

Definition at line 44 of file mlx_link_speed.h.

LINK_SPEED_WITDH_2_MASK

#define LINK_SPEED_WITDH_2_MASK   0x2

Definition at line 45 of file mlx_link_speed.h.

LINK_SPEED_WITDH_4_MASK

#define LINK_SPEED_WITDH_4_MASK   0x4

Definition at line 46 of file mlx_link_speed.h.

LINK_SPEED_WITDH_8_MASK

#define LINK_SPEED_WITDH_8_MASK   0x8

Definition at line 47 of file mlx_link_speed.h.

LINK_SPEED_WITDH_12_MASK

#define LINK_SPEED_WITDH_12_MASK   0x10

Definition at line 48 of file mlx_link_speed.h.

GIGA_TO_BIT

#define GIGA_TO_BIT   0x40000000

Definition at line 50 of file mlx_link_speed.h.

Enumeration Type Documentation

anonymous enum

anonymous enum

Enumerator
ETH_SPEED_ENABLE_MASK_1000BASECX
ETH_SPEED_ENABLE_MASK_1000BASEKX
ETH_SPEED_ENABLE_MASK_10GBASECX4
ETH_SPEED_ENABLE_MASK_10GBASEKX4
ETH_SPEED_ENABLE_MASK_10GBASEKR
ETH_SPEED_ENABLE_MASK_20GBASER2
ETH_SPEED_ENABLE_MASK_40GBASECR4
ETH_SPEED_ENABLE_MASK_40GBASEKR4
ETH_SPEED_ENABLE_MASK_56GBASER4
ETH_SPEED_ENABLE_MASK_10GBASECR
ETH_SPEED_ENABLE_MASK_10GBASESR
ETH_SPEED_ENABLE_MASK_10GBASELR
ETH_SPEED_ENABLE_MASK_40GBASESR4
ETH_SPEED_ENABLE_MASK_40GBASELR4
ETH_SPEED_ENABLE_MASK_50GBASEKR4
ETH_SPEED_ENABLE_MASK_100GBASECR4
ETH_SPEED_ENABLE_MASK_100GBASESR4
ETH_SPEED_ENABLE_MASK_100GBASEKR4
ETH_SPEED_ENABLE_MASK_100GBASELR4
ETH_SPEED_ENABLE_MASK_100BaseTX
ETH_SPEED_ENABLE_MASK_1000BASET
ETH_SPEED_ENABLE_MASK_10GBASET
ETH_SPEED_ENABLE_MASK_25GBASECR
ETH_SPEED_ENABLE_MASK_25GBASEKR
ETH_SPEED_ENABLE_MASK_25GBASESR
ETH_SPEED_ENABLE_MASK_50GBASECR2
ETH_SPEED_ENABLE_MASK_50GBASEKR2
ETH_SPEED_ENABLE_MASK_BAD

Definition at line 52 of file mlx_link_speed.h.

     {
    ETH_SPEED_ENABLE_MASK_1000BASECX  = 0x0001,
    ETH_SPEED_ENABLE_MASK_1000BASEKX  = 0x0002,
    ETH_SPEED_ENABLE_MASK_10GBASECX4  = 0x0004,
    ETH_SPEED_ENABLE_MASK_10GBASEKX4  = 0x0008,
    ETH_SPEED_ENABLE_MASK_10GBASEKR   = 0x0010,
    ETH_SPEED_ENABLE_MASK_20GBASER2   = 0x0020,
    ETH_SPEED_ENABLE_MASK_40GBASECR4  = 0x0040,
    ETH_SPEED_ENABLE_MASK_40GBASEKR4  = 0x0080,
    ETH_SPEED_ENABLE_MASK_56GBASER4   = 0x0100,
    ETH_SPEED_ENABLE_MASK_10GBASECR   = 0x1000,
    ETH_SPEED_ENABLE_MASK_10GBASESR   = 0x2000,
    ETH_SPEED_ENABLE_MASK_10GBASELR   = 0x4000,
    ETH_SPEED_ENABLE_MASK_40GBASESR4  = 0x8000,
    ETH_SPEED_ENABLE_MASK_40GBASELR4  = 0x10000,
    ETH_SPEED_ENABLE_MASK_50GBASEKR4  = 0x80000,
    ETH_SPEED_ENABLE_MASK_100GBASECR4 = 0x100000,
    ETH_SPEED_ENABLE_MASK_100GBASESR4 = 0x200000,
    ETH_SPEED_ENABLE_MASK_100GBASEKR4 = 0x400000,
    ETH_SPEED_ENABLE_MASK_100GBASELR4 = 0x800000,
    ETH_SPEED_ENABLE_MASK_100BaseTX   = 0x1000000,
    ETH_SPEED_ENABLE_MASK_1000BASET   = 0x2000000,
    ETH_SPEED_ENABLE_MASK_10GBASET    = 0x4000000,
    ETH_SPEED_ENABLE_MASK_25GBASECR   = 0x8000000,
    ETH_SPEED_ENABLE_MASK_25GBASEKR   = 0x10000000,
    ETH_SPEED_ENABLE_MASK_25GBASESR   = 0x20000000,
    ETH_SPEED_ENABLE_MASK_50GBASECR2  = 0x40000000,
    ETH_SPEED_ENABLE_MASK_50GBASEKR2  = 0x80000000,
    ETH_SPEED_ENABLE_MASK_BAD         = 0xffff,
};

LINK_SPEED_TYPE

enum LINK_SPEED_TYPE

Enumerator
LINK_SPEED_IB
LINK_SPEED_FC
LINK_SPEED_ETH

Definition at line 84 of file mlx_link_speed.h.

             {
        LINK_SPEED_IB = 0,
        LINK_SPEED_FC,
        LINK_SPEED_ETH,
} LINK_SPEED_TYPE;

LINK_SPEED

enum LINK_SPEED

Enumerator
LINK_SPEED_1GB
LINK_SPEED_10GB
LINK_SPEED_40GB
LINK_SPEED_100GB
LINK_SPEED_SDR
LINK_SPEED_DEFAULT

Definition at line 90 of file mlx_link_speed.h.

             {
        LINK_SPEED_1GB = 0,
        LINK_SPEED_10GB,
        LINK_SPEED_40GB,
        LINK_SPEED_100GB,
        LINK_SPEED_SDR,
        LINK_SPEED_DEFAULT,
} LINK_SPEED;

Function Documentation

FILE_LICENCE()

FILE_LICENCE

(

GPL2_OR_LATER

)

mlx_set_link_speed()

mlx_status mlx_set_link_speed	(	IN mlx_utils *	utils,
		IN mlx_uint8	port_num,
		IN LINK_SPEED_TYPE	type,
		IN LINK_SPEED	speed
	)

Definition at line 27 of file mlx_link_speed.c.

{
        mlx_status status = MLX_SUCCESS;
        struct mlx_link_speed link_speed;
        mlx_uint32 reg_status;

        if (utils == NULL) {
                status = MLX_INVALID_PARAMETER;
                goto bad_param;
        }

        mlx_memory_set(utils, &link_speed, 0, sizeof(link_speed));

        link_speed.loacl_port = port_num;
        link_speed.proto_mask = 1 << type;

        status = mlx_reg_access(utils, REG_ID_PTYS, REG_ACCESS_READ, &link_speed,
                        sizeof(link_speed), &reg_status);

        MLX_CHECK_STATUS(utils, status, reg_err, "mlx_reg_access failed ");
        if (reg_status != 0) {
                MLX_DEBUG_ERROR(utils,"mlx_reg_access failed with status = %d\n", reg_status);
                status = MLX_FAILED;
                goto reg_err;
        }
        switch (speed) {
        case LINK_SPEED_1GB:
                link_speed.eth_proto_admin = link_speed.eth_proto_capability & LINK_SPEED_1GB_MASK;
                break;
        case LINK_SPEED_10GB:
                link_speed.eth_proto_admin = link_speed.eth_proto_capability & LINK_SPEED_10GB_MASK;
                break;
        case LINK_SPEED_40GB:
                link_speed.eth_proto_admin = link_speed.eth_proto_capability & LINK_SPEED_40GB_MASK;
                break;
        case LINK_SPEED_100GB:
                link_speed.eth_proto_admin = link_speed.eth_proto_capability & LINK_SPEED_100GB_MASK;
                break;
        case LINK_SPEED_SDR:
                link_speed.ib_proto_admin = link_speed.ib_proto_capability & LINK_SPEED_SDR_MASK;
                break;
        case LINK_SPEED_DEFAULT:
                if (type == LINK_SPEED_ETH) {
                        link_speed.eth_proto_admin = link_speed.eth_proto_capability;
                } else {
                        link_speed.ib_proto_admin = link_speed.ib_proto_capability;
                }
                break;
        }
        status = mlx_reg_access(utils, REG_ID_PTYS, REG_ACCESS_WRITE, &link_speed,
                                sizeof(link_speed), &reg_status);
        MLX_CHECK_STATUS(utils, status, reg_err, "mlx_reg_access failed ");
        if (reg_status != 0) {
                MLX_DEBUG_ERROR(utils,"mlx_reg_access failed with status = %d\n", reg_status);
                status = MLX_FAILED;
                goto reg_err;
        }
reg_err:
bad_param:
        return status;
}

References mlx_link_speed::eth_proto_admin, mlx_link_speed::eth_proto_capability, mlx_link_speed::ib_proto_admin, mlx_link_speed::ib_proto_capability, LINK_SPEED_100GB, LINK_SPEED_100GB_MASK, LINK_SPEED_10GB, LINK_SPEED_10GB_MASK, LINK_SPEED_1GB, LINK_SPEED_1GB_MASK, LINK_SPEED_40GB, LINK_SPEED_40GB_MASK, LINK_SPEED_DEFAULT, LINK_SPEED_ETH, LINK_SPEED_SDR, LINK_SPEED_SDR_MASK, mlx_link_speed::loacl_port, MLX_CHECK_STATUS, MLX_DEBUG_ERROR, MLX_FAILED, MLX_INVALID_PARAMETER, mlx_memory_set(), mlx_reg_access(), MLX_SUCCESS, NULL, port_num, mlx_link_speed::proto_mask, REG_ACCESS_READ, REG_ACCESS_WRITE, REG_ID_PTYS, status, and type.

Referenced by golan_set_link_speed().

mlx_get_max_speed()

mlx_status mlx_get_max_speed	(	IN mlx_utils *	utils,
		IN mlx_uint8	port_num,
		IN LINK_SPEED_TYPE	type,
		OUT mlx_uint64 *	speed
	)

Definition at line 95 of file mlx_link_speed.c.

{
        mlx_status status = MLX_SUCCESS;
        struct mlx_link_speed link_speed;
        mlx_uint32 reg_status;
        mlx_uint64 speed_giga = 0;
        mlx_uint8  lanes_number = 1;

        *speed = 0;
        if (utils == NULL) {
                status = MLX_INVALID_PARAMETER;
                goto bad_param;
        }

        mlx_memory_set(utils, &link_speed, 0, sizeof(link_speed));

        link_speed.loacl_port = port_num;
        link_speed.proto_mask = 1 << type;

        status = mlx_reg_access(utils, REG_ID_PTYS, REG_ACCESS_READ, &link_speed,
                        sizeof(link_speed), &reg_status);
        MLX_CHECK_STATUS(utils, status, reg_err, "mlx_reg_access failed ");
        if (reg_status != 0) {
                MLX_DEBUG_ERROR(utils,"mlx_reg_access failed with status = %d\n", reg_status);
                status = MLX_FAILED;
                goto reg_err;
        }

        if ( type == LINK_SPEED_ETH ) {
                if ( link_speed.eth_proto_capability & LINK_SPEED_100GB_MASK ) {
                        speed_giga = 100;
                } else if ( link_speed.eth_proto_capability & LINK_SPEED_56GB_MASK ) {
                        speed_giga = 56;
                } else if ( link_speed.eth_proto_capability & LINK_SPEED_50GB_MASK ) {
                        speed_giga = 50;
                } else if ( link_speed.eth_proto_capability & LINK_SPEED_40GB_MASK ) {
                        speed_giga = 40;
                } else if (link_speed.eth_proto_capability & LINK_SPEED_25GB_MASK) {
                        speed_giga = 25;
                } else if ( link_speed.eth_proto_capability & LINK_SPEED_20GB_MASK ) {
                        speed_giga = 20;
                } else if ( link_speed.eth_proto_capability & LINK_SPEED_10GB_MASK) {
                        speed_giga = 10;
                } else if ( link_speed.eth_proto_capability & LINK_SPEED_1GB_MASK ) {
                        speed_giga = 1;
                }
        } else {
                if ( link_speed.ib_proto_capability & LINK_SPEED_EDR_MASK ) {
                        speed_giga = 25;
                } else if ( link_speed.ib_proto_capability & LINK_SPEED_EDR20_MASK ) {
                        speed_giga = 20;
                } else if ( link_speed.ib_proto_capability & LINK_SPEED_FDR_MASK ) {
                        speed_giga = 14;
                } else if ( link_speed.ib_proto_capability & LINK_SPEED_QDR_MASK ) {
                        speed_giga = 10;
                } else if ( link_speed.ib_proto_capability & LINK_SPEED_DDR_MASK ) {
                        speed_giga = 5;
                } else if ( link_speed.ib_proto_capability & LINK_SPEED_SDR_MASK ) {
                        speed_giga = 2.5;
                }
                if ( link_speed.ib_link_width_capability & LINK_SPEED_WITDH_12_MASK ) {
                        lanes_number = 12;
                } else if ( link_speed.ib_link_width_capability & LINK_SPEED_WITDH_8_MASK ) {
                        lanes_number = 8;
                } else if (link_speed.ib_link_width_capability & LINK_SPEED_WITDH_4_MASK ) {
                        lanes_number = 4;
                } else if (link_speed.ib_link_width_capability & LINK_SPEED_WITDH_2_MASK ) {
                        lanes_number = 2;
                } else if (link_speed.ib_link_width_capability & LINK_SPEED_WITDH_1_MASK ) {
                        lanes_number = 1;
                }
                speed_giga = speed_giga * lanes_number;
        }
        // Return data in bits
        *speed = speed_giga * GIGA_TO_BIT;
reg_err:
bad_param:
        return status;
}

References mlx_link_speed::eth_proto_capability, GIGA_TO_BIT, mlx_link_speed::ib_link_width_capability, mlx_link_speed::ib_proto_capability, LINK_SPEED_100GB_MASK, LINK_SPEED_10GB_MASK, LINK_SPEED_1GB_MASK, LINK_SPEED_20GB_MASK, LINK_SPEED_25GB_MASK, LINK_SPEED_40GB_MASK, LINK_SPEED_50GB_MASK, LINK_SPEED_56GB_MASK, LINK_SPEED_DDR_MASK, LINK_SPEED_EDR20_MASK, LINK_SPEED_EDR_MASK, LINK_SPEED_ETH, LINK_SPEED_FDR_MASK, LINK_SPEED_QDR_MASK, LINK_SPEED_SDR_MASK, LINK_SPEED_WITDH_12_MASK, LINK_SPEED_WITDH_1_MASK, LINK_SPEED_WITDH_2_MASK, LINK_SPEED_WITDH_4_MASK, LINK_SPEED_WITDH_8_MASK, mlx_link_speed::loacl_port, MLX_CHECK_STATUS, MLX_DEBUG_ERROR, MLX_FAILED, MLX_INVALID_PARAMETER, mlx_memory_set(), mlx_reg_access(), MLX_SUCCESS, NULL, port_num, mlx_link_speed::proto_mask, REG_ACCESS_READ, REG_ID_PTYS, status, and type.