36 #define PSEUDOBIT_LITTLE_ENDIAN 97 #define QIB7322_SENDBUFAVAIL_ALIGN 64 163 #define QIB7322_BAR0_SIZE 0x400000 166 #define QIB7322_PORT_BASE 1 169 #define QIB7322_MAX_PORTS 2 172 #define QIB7322_MAX_WIDTH 4 187 #define QIB7322_GPIO_SCL 0 190 #define QIB7322_GPIO_SDA 1 193 #define QIB7322_EEPROM_GUID_OFFSET 3 196 #define QIB7322_EEPROM_GUID_SIZE 8 199 #define QIB7322_EEPROM_SERIAL_OFFSET 12 202 #define QIB7322_EEPROM_SERIAL_SIZE 12 205 #define QIB7322_SMALL_SEND_BUF_SIZE 4096 208 #define QIB7322_SMALL_SEND_BUF_START 0 211 #define QIB7322_SMALL_SEND_BUF_COUNT 128 214 #define QIB7322_LARGE_SEND_BUF_SIZE 8192 217 #define QIB7322_LARGE_SEND_BUF_START 128 220 #define QIB7322_LARGE_SEND_BUF_COUNT 32 223 #define QIB7322_VL15_PORT0_SEND_BUF_START 160 226 #define QIB7322_VL15_PORT0_SEND_BUF_COUNT 1 229 #define QIB7322_VL15_PORT0_SEND_BUF_SIZE 8192 232 #define QIB7322_VL15_PORT1_SEND_BUF_START 161 235 #define QIB7322_VL15_PORT1_SEND_BUF_COUNT 1 238 #define QIB7322_VL15_PORT1_SEND_BUF_SIZE 8192 246 #define QIB7322_SMALL_SEND_BUF_USED 32 252 #define QIB7322_NUM_CONTEXTS 6 262 #define QIB7322_EAGER_ARRAY_SIZE_6CTX_KERNEL 1024 263 #define QIB7322_EAGER_ARRAY_SIZE_6CTX_USER 4096 264 #define QIB7322_EAGER_ARRAY_SIZE_10CTX_KERNEL 1024 265 #define QIB7322_EAGER_ARRAY_SIZE_10CTX_USER 2048 266 #define QIB7322_EAGER_ARRAY_SIZE_18CTX_KERNEL 1024 267 #define QIB7322_EAGER_ARRAY_SIZE_18CTX_USER 1024 270 #define QIB7322_EAGER_BUFFER_ALIGN 2048 287 #define QIB7322_RECV_HEADER_COUNT 8 293 #define QIB7322_RECV_HEADER_SIZE 96 296 #define QIB7322_RECV_HEADERS_SIZE \ 297 ( QIB7322_RECV_HEADER_SIZE * QIB7322_RECV_HEADER_COUNT ) 300 #define QIB7322_RECV_HEADERS_ALIGN 64 306 #define QIB7322_RECV_PAYLOAD_SIZE 2048 313 #define QIB7322_MAX_CREDITS ( ( 65536 / 64 ) / QIB7322_MAX_PORTS ) 320 #define QIB7322_MAX_CREDITS_VL15 9 326 #define QIB7322_MAX_CREDITS_VL0 \ 327 ( QIB7322_MAX_CREDITS - QIB7322_MAX_CREDITS_VL15 ) 334 #define QIB7322_QP_IDETH 0xdead0 337 #define QIB7322_AHB_MAX_WAIT_US 500 340 #define QIB7322_AHB_LOC_ADDRESS( _location ) ( (_location) & 0xffff ) 341 #define QIB7322_AHB_LOC_TARGET( _location ) ( (_location) >> 16 ) 342 #define QIB7322_AHB_CHAN_0 0 343 #define QIB7322_AHB_CHAN_1 1 344 #define QIB7322_AHB_PLL 2 345 #define QIB7322_AHB_CHAN_2 3 346 #define QIB7322_AHB_CHAN_3 4 347 #define QIB7322_AHB_SUBSYS 5 348 #define QIB7322_AHB_CHAN( _channel ) ( (_channel) + ( (_channel) >> 1 ) ) 349 #define QIB7322_AHB_TARGET_0 2 350 #define QIB7322_AHB_TARGET_1 3 351 #define QIB7322_AHB_TARGET( _port ) ( (_port) + 2 ) 352 #define QIB7322_AHB_LOCATION( _port, _channel, _register ) \ 353 ( ( QIB7322_AHB_TARGET(_port) << 16 ) | \ 354 ( QIB7322_AHB_CHAN(_channel) << 7 ) | \ 355 ( (_register) << 1 ) ) 367 #define QIB7322_LINK_STATE_MAX_WAIT_US 20 pseudo_bit_t _unused_0[58]
pseudo_bit_t Reserved2[3]
FILE_LICENCE(GPL2_OR_LATER_OR_UBDL)
QIB7322 send per-buffer control word.
qib7322_contextcfg
ContextCfg values for different numbers of contexts.
PSEUDO_BIT_STRUCT(struct QIB_7322_scalar_pb)
pseudo_bit_t UseEgrBfr[1]
PSEUDO_BIT_STRUCT(struct QIB_7322_SendPbc_pb)
pseudo_bit_t ContextEnable[18]
pseudo_bit_t Reserved[48]
PSEUDO_BIT_STRUCT(struct QIB_7322_GPIO_pb)
pseudo_bit_t _unused_0[46]
pseudo_bit_t Reserved1[4]
unsigned char pseudo_bit_t
Datatype used to represent a bit in the pseudo-structures.
pseudo_bit_t LengthP1_trigger[11]
pseudo_bit_t Reserved2[8]
pseudo_bit_t RcvPartitionKeyDisable[1]
qib7322_eager_buffer_size
Eager buffer size encodings.
qib7322_link_state
QIB7322 link states.
A QIB7322 general scalar register.
QIB7322 receive header flags.
pseudo_bit_t RcvQPMapEnable[1]
pseudo_bit_t Reserved4[1]
pseudo_bit_t _unused_1[21]
pseudo_bit_t StaticRateControlCnt[14]
PSEUDO_BIT_STRUCT(struct QIB_7322_RcvHdrFlags_pb)
PSEUDO_BIT_STRUCT(struct QIB_7322_RcvEgr_pb)
pseudo_bit_t InUseCheck[162][2]
QIB7322 send buffer availability.
A QIB7322 eager receive descriptor.
pseudo_bit_t Reserved1[3]
PSEUDO_BIT_STRUCT(struct QIB_7322_SendBufAvail_pb)
PSEUDO_BIT_STRUCT(struct QIB_7322_feature_mask_pb)
pseudo_bit_t HdrqOffset[11]
pseudo_bit_t Reserved[60]
pseudo_bit_t Reserved3[12]
pseudo_bit_t LengthP1_toibc[11]
pseudo_bit_t ParityErr[1]
pseudo_bit_t Port0_Link_Speed_Supported[3]
pseudo_bit_t RcvResetCredit[1]
QIB7322 port-specific receive control.
pseudo_bit_t Reserved[24]
pseudo_bit_t _unused_2[21]
PSEUDO_BIT_STRUCT(struct QIB_7322_RcvCtrl_P_pb)
pseudo_bit_t RcvIBPortEnable[1]
PSEUDO_BIT_STRUCT(struct QIB_7322_IBSD_DDS_MAP_TABLE_pb)
QIB7322 DDS tuning parameters.
pseudo_bit_t Port1_Link_Speed_Supported[3]
qib7322_board_id
QIB7322 board identifiers.
pseudo_bit_t EgrIndex[12]