iPXE
qib_7322_regs.h
Go to the documentation of this file.
1 /*
2  * Copyright (c) 2008, 2009 QLogic Corporation. All rights reserved.
3  *
4  * This software is available to you under a choice of one of two
5  * licenses. You may choose to be licensed under the terms of the GNU
6  * General Public License (GPL) Version 2, available from the file
7  * COPYING in the main directory of this source tree, or the
8  * OpenIB.org BSD license below:
9  *
10  * Redistribution and use in source and binary forms, with or
11  * without modification, are permitted provided that the following
12  * conditions are met:
13  *
14  * - Redistributions of source code must retain the above
15  * copyright notice, this list of conditions and the following
16  * disclaimer.
17  *
18  * - Redistributions in binary form must reproduce the above
19  * copyright notice, this list of conditions and the following
20  * disclaimer in the documentation and/or other materials
21  * provided with the distribution.
22  *
23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30  * SOFTWARE.
31  */
32 /* This file is mechanically generated from RTL. Any hand-edits will be lost! */
33 
34 /* This file has been further processed by ./drivers/infiniband/qib_genbits.pl */
35 
36 FILE_LICENCE ( GPL2_ONLY );
37 
38 #define QIB_7322_Revision_offset 0x00000000UL
48 };
51 };
52 /* Default value: 0x0000000002010601 */
53 
54 #define QIB_7322_Control_offset 0x00000008UL
64 };
67 };
68 /* Default value: 0x0000000000000000 */
69 
70 #define QIB_7322_PageAlign_offset 0x00000010UL
71 /* Default value: 0x0000000000001000 */
72 
73 #define QIB_7322_ContextCnt_offset 0x00000018UL
74 /* Default value: 0x0000000000000012 */
75 
76 #define QIB_7322_Scratch_offset 0x00000020UL
77 /* Default value: 0x0000000000000000 */
78 
79 #define QIB_7322_CntrRegBase_offset 0x00000028UL
80 /* Default value: 0x0000000000011000 */
81 
82 #define QIB_7322_SendRegBase_offset 0x00000030UL
83 /* Default value: 0x0000000000003000 */
84 
85 #define QIB_7322_UserRegBase_offset 0x00000038UL
86 /* Default value: 0x0000000000200000 */
87 
88 #define QIB_7322_DebugPortSel_offset 0x00000040UL
99 };
102 };
103 /* Default value: 0x0000000000000000 */
104 
105 #define QIB_7322_DebugPortNibbleSel_offset 0x00000048UL
123 };
126 };
127 /* Default value: 0xFEDCBA9876543210 */
128 
129 #define QIB_7322_DebugSigsIntSel_offset 0x00000050UL
150 };
153 };
154 /* Default value: 0x0000000000000000 */
155 
156 #define QIB_7322_DebugPortValueReg_offset 0x00000058UL
157 
158 #define QIB_7322_IntBlocked_offset 0x00000060UL
214 };
217 };
218 /* Default value: 0x0000000000000000 */
219 
220 #define QIB_7322_IntMask_offset 0x00000068UL
276 };
279 };
280 /* Default value: 0x0000000000000000 */
281 
282 #define QIB_7322_IntStatus_offset 0x00000070UL
338 };
341 };
342 /* Default value: 0x0000000000000000 */
343 
344 #define QIB_7322_IntClear_offset 0x00000078UL
400 };
403 };
404 /* Default value: 0x0000000000000000 */
405 
406 #define QIB_7322_ErrMask_offset 0x00000080UL
428 };
431 };
432 /* Default value: 0x0000000000000000 */
433 
434 #define QIB_7322_ErrStatus_offset 0x00000088UL
456 };
459 };
460 /* Default value: 0x0000000000000000 */
461 
462 #define QIB_7322_ErrClear_offset 0x00000090UL
484 };
487 };
488 /* Default value: 0x0000000000000000 */
489 
490 #define QIB_7322_HwErrMask_offset 0x00000098UL
514 };
517 };
518 /* Default value: 0x0000000000000000 */
519 
520 #define QIB_7322_HwErrStatus_offset 0x000000a0UL
544 };
547 };
548 /* Default value: 0x0000000000000000 */
549 
550 #define QIB_7322_HwErrClear_offset 0x000000a8UL
574 };
577 };
578 /* Default value: 0x0000000000000000 */
579 
580 #define QIB_7322_HwDiagCtrl_offset 0x000000b0UL
594 };
597 };
598 /* Default value: 0x0000000000000000 */
599 
600 #define QIB_7322_EXTStatus_offset 0x000000c0UL
607 };
610 };
611 /* Default value: 0x000000000000X000 */
612 
613 #define QIB_7322_EXTCtrl_offset 0x000000c8UL
622 };
625 };
626 /* Default value: 0x0000000000000000 */
627 
628 #define QIB_7322_GPIODebugSelReg_offset 0x000000d8UL
633 };
636 };
637 /* Default value: 0x0000000000000000 */
638 
639 #define QIB_7322_GPIOOut_offset 0x000000e0UL
640 /* Default value: 0x0000000000000000 */
641 
642 #define QIB_7322_GPIOMask_offset 0x000000e8UL
643 /* Default value: 0x0000000000000000 */
644 
645 #define QIB_7322_GPIOStatus_offset 0x000000f0UL
646 /* Default value: 0x0000000000000000 */
647 
648 #define QIB_7322_GPIOClear_offset 0x000000f8UL
649 /* Default value: 0x0000000000000000 */
650 
651 #define QIB_7322_RcvCtrl_offset 0x00000100UL
662 };
665 };
666 /* Default value: 0x0000000000000000 */
667 
668 #define QIB_7322_RcvHdrSize_offset 0x00000110UL
669 /* Default value: 0x0000000000000000 */
670 
671 #define QIB_7322_RcvHdrCnt_offset 0x00000118UL
672 /* Default value: 0x0000000000000000 */
673 
674 #define QIB_7322_RcvHdrEntSize_offset 0x00000120UL
675 /* Default value: 0x0000000000000000 */
676 
677 #define QIB_7322_RcvTIDBase_offset 0x00000128UL
678 /* Default value: 0x0000000000050000 */
679 
680 #define QIB_7322_RcvTIDCnt_offset 0x00000130UL
681 /* Default value: 0x0000000000000200 */
682 
683 #define QIB_7322_RcvEgrBase_offset 0x00000138UL
684 /* Default value: 0x0000000000014000 */
685 
686 #define QIB_7322_RcvEgrCnt_offset 0x00000140UL
687 /* Default value: 0x0000000000001000 */
688 
689 #define QIB_7322_RcvBufBase_offset 0x00000148UL
690 /* Default value: 0x0000000000080000 */
691 
692 #define QIB_7322_RcvBufSize_offset 0x00000150UL
693 /* Default value: 0x0000000000005000 */
694 
695 #define QIB_7322_RxIntMemBase_offset 0x00000158UL
696 /* Default value: 0x0000000000077000 */
697 
698 #define QIB_7322_RxIntMemSize_offset 0x00000160UL
699 /* Default value: 0x0000000000007000 */
700 
701 #define QIB_7322_encryption_key_low_offset 0x00000180UL
702 /* Default value: 0x0000000000000000 */
703 
704 #define QIB_7322_encryption_key_high_offset 0x00000188UL
705 /* Default value: 0x0000000000000000 */
706 
707 #define QIB_7322_feature_mask_offset 0x00000190UL
708 /* Default value: 0x00000000000000XX */
709 
710 #define QIB_7322_active_feature_mask_offset 0x00000198UL
719 };
722 };
723 /* Default value: 0x00000000000000XX */
724 
725 #define QIB_7322_SendCtrl_offset 0x000001c0UL
739 };
742 };
743 /* Default value: 0x0000000000000000 */
744 
745 #define QIB_7322_SendBufBase_offset 0x000001c8UL
751 };
754 };
755 /* Default value: 0x0018000000100000 */
756 
757 #define QIB_7322_SendBufSize_offset 0x000001d0UL
763 };
766 };
767 /* Default value: 0x0000108000000880 */
768 
769 #define QIB_7322_SendBufCnt_offset 0x000001d8UL
775 };
778 };
779 /* Default value: 0x0000002000000080 */
780 
781 #define QIB_7322_SendBufAvailAddr_offset 0x000001e0UL
786 };
789 };
790 /* Default value: 0x0000000000000000 */
791 
792 #define QIB_7322_TxIntMemBase_offset 0x000001e8UL
793 /* Default value: 0x0000000000064000 */
794 
795 #define QIB_7322_TxIntMemSize_offset 0x000001f0UL
796 /* Default value: 0x000000000000C000 */
797 
798 #define QIB_7322_SendBufErr0_offset 0x00000240UL
801 };
804 };
805 /* Default value: 0x0000000000000000 */
806 
807 #define QIB_7322_AvailUpdCount_offset 0x00000268UL
811 };
814 };
815 /* Default value: 0x0000000000000000 */
816 
817 #define QIB_7322_RcvHdrAddr0_offset 0x00000280UL
822 };
825 };
826 /* Default value: 0x0000000000000000 */
827 
828 #define QIB_7322_RcvHdrTailAddr0_offset 0x00000340UL
833 };
836 };
837 /* Default value: 0x0000000000000000 */
838 
839 #define QIB_7322_EEPCtlStat_offset 0x000003e8UL
850 };
853 };
854 /* Default value: 0x0000000000000002 */
855 
856 #define QIB_7322_EEPAddrCmd_offset 0x000003f0UL
861 };
864 };
865 /* Default value: 0x0000000000000000 */
866 
867 #define QIB_7322_EEPData_offset 0x000003f8UL
868 /* Default value: 0x0000000000000000 */
869 
870 #define QIB_7322_efuse_control_reg_offset 0x00000410UL
881 };
884 };
885 /* Default value: 0x0000000080000000 */
886 
887 #define QIB_7322_efuse_data_reg_offset 0x00000418UL
888 /* Default value: 0x0000000000000000 */
889 
890 #define QIB_7322_voltage_margin_reg_offset 0x00000428UL
895 };
898 };
899 /* Default value: 0x0000000000000000 */
900 
901 #define QIB_7322_VTSense_reg_offset 0x00000430UL
914 };
917 };
918 /* Default value: 0x0000000000000020 */
919 
920 #define QIB_7322_procmon_reg_offset 0x00000438UL
929 };
932 };
933 /* Default value: 0x0000000000000000 */
934 
935 #define QIB_7322_PcieRbufTestReg0_offset 0x00000440UL
936 /* Default value: 0x0000000000000000 */
937 
938 #define QIB_7322_ahb_access_ctrl_offset 0x00000460UL
943 };
946 };
947 /* Default value: 0x0000000000000000 */
948 
949 #define QIB_7322_ahb_transaction_reg_offset 0x00000468UL
958 };
961 };
962 /* Default value: 0x0000000080000000 */
963 
964 #define QIB_7322_SPC_JTAG_ACCESS_REG_offset 0x00000470UL
973 };
976 };
977 /* Default value: 0x0000000000000001 */
978 
979 #define QIB_7322_LAControlReg_offset 0x00000478UL
989 };
992 };
993 /* Default value: 0x0000000100000001 */
994 
995 #define QIB_7322_PcieRhdrTestReg0_offset 0x00000480UL
996 /* Default value: 0x0000000000000000 */
997 
998 #define QIB_7322_SendCheckMask0_offset 0x000004c0UL
1001 };
1004 };
1005 /* Default value: 0x0000000000000000 */
1006 
1007 #define QIB_7322_SendGRHCheckMask0_offset 0x000004e0UL
1010 };
1013 };
1014 /* Default value: 0x0000000000000000 */
1015 
1016 #define QIB_7322_SendIBPacketMask0_offset 0x00000500UL
1019 };
1022 };
1023 /* Default value: 0x0000000000000000 */
1024 
1025 #define QIB_7322_IntRedirect0_offset 0x00000540UL
1040 };
1043 };
1044 /* Default value: 0x0000000000000000 */
1045 
1046 #define QIB_7322_Int_Granted_offset 0x00000570UL
1047 /* Default value: 0x0000000000000000 */
1048 
1049 #define QIB_7322_vec_clr_without_int_offset 0x00000578UL
1050 /* Default value: 0x0000000000000000 */
1051 
1052 #define QIB_7322_DCACtrlA_offset 0x00000580UL
1060 };
1063 };
1064 /* Default value: 0x0000000000000000 */
1065 
1066 #define QIB_7322_DCACtrlB_offset 0x00000588UL
1078 };
1081 };
1082 /* Default value: 0x0000000000000000 */
1083 
1084 #define QIB_7322_DCACtrlC_offset 0x00000590UL
1096 };
1099 };
1100 /* Default value: 0x0000000000000000 */
1101 
1102 #define QIB_7322_DCACtrlD_offset 0x00000598UL
1114 };
1117 };
1118 /* Default value: 0x0000000000000000 */
1119 
1120 #define QIB_7322_DCACtrlE_offset 0x000005a0UL
1132 };
1135 };
1136 /* Default value: 0x0000000000000000 */
1137 
1138 #define QIB_7322_DCACtrlF_offset 0x000005a8UL
1148 };
1151 };
1152 /* Default value: 0x0000000000000000 */
1153 
1154 #define QIB_7322_MemErrCtrlA_offset 0x00000600UL
1205 };
1208 };
1209 /* Default value: 0x0000000000000000 */
1210 
1211 #define QIB_7322_MemErrCtrlB_offset 0x00000608UL
1258 };
1261 };
1262 /* Default value: 0x0000000000000000 */
1263 
1264 #define QIB_7322_MemMultiUnCorErrMask_offset 0x00000610UL
1311 };
1314 };
1315 /* Default value: 0x0000000000000000 */
1316 
1317 #define QIB_7322_MemMultiUnCorErrStatus_offset 0x00000618UL
1364 };
1367 };
1368 /* Default value: 0x0000000000000000 */
1369 
1370 #define QIB_7322_MemMultiUnCorErrClear_offset 0x00000620UL
1417 };
1420 };
1421 /* Default value: 0x0000000000000000 */
1422 
1423 #define QIB_7322_MemUnCorErrMask_offset 0x00000628UL
1470 };
1473 };
1474 /* Default value: 0x0000000000000000 */
1475 
1476 #define QIB_7322_MemUnCorErrStatus_offset 0x00000630UL
1523 };
1526 };
1527 /* Default value: 0x0000000000000000 */
1528 
1529 #define QIB_7322_MemUnCorErrClear_offset 0x00000638UL
1576 };
1579 };
1580 /* Default value: 0x0000000000000000 */
1581 
1582 #define QIB_7322_MemMultiCorErrMask_offset 0x00000640UL
1629 };
1632 };
1633 /* Default value: 0x0000000000000000 */
1634 
1635 #define QIB_7322_MemMultiCorErrStatus_offset 0x00000648UL
1682 };
1685 };
1686 /* Default value: 0x0000000000000000 */
1687 
1688 #define QIB_7322_MemMultiCorErrClear_offset 0x00000650UL
1735 };
1738 };
1739 /* Default value: 0x0000000000000000 */
1740 
1741 #define QIB_7322_MemCorErrMask_offset 0x00000658UL
1788 };
1791 };
1792 /* Default value: 0x0000000000000000 */
1793 
1794 #define QIB_7322_MemCorErrStatus_offset 0x00000660UL
1841 };
1844 };
1845 /* Default value: 0x0000000000000000 */
1846 
1847 #define QIB_7322_MemCorErrClear_offset 0x00000668UL
1894 };
1897 };
1898 /* Default value: 0x0000000000000000 */
1899 
1900 #define QIB_7322_MsixTableUnCorErrLogA_offset 0x00000680UL
1903 };
1906 };
1907 /* Default value: 0x0000000000000000 */
1908 
1909 #define QIB_7322_MsixTableUnCorErrLogB_offset 0x00000688UL
1916 };
1919 };
1920 /* Default value: 0x0000000000000000 */
1921 
1922 #define QIB_7322_MsixTableUnCorErrLogC_offset 0x00000690UL
1928 };
1931 };
1932 /* Default value: 0x0000000000000000 */
1933 
1934 #define QIB_7322_MsixEntryWithUncorErr_offset 0x00000698UL
1935 /* Default value: 0x0000000000000000 */
1936 
1937 #define QIB_7322_MsixTableCorErrLogA_offset 0x000006a0UL
1940 };
1943 };
1944 /* Default value: 0x0000000000000000 */
1945 
1946 #define QIB_7322_MsixTableCorErrLogB_offset 0x000006a8UL
1953 };
1956 };
1957 /* Default value: 0x0000000000000000 */
1958 
1959 #define QIB_7322_MsixTableCorErrLogC_offset 0x000006b0UL
1965 };
1968 };
1969 /* Default value: 0x0000000000000000 */
1970 
1971 #define QIB_7322_PcieCplDataBufrUnCorErrLogA_offset 0x00000700UL
1974 };
1977 };
1978 /* Default value: 0x0000000000000000 */
1979 
1980 #define QIB_7322_PcieCplDataBufrUnCorErrLogB_offset 0x00000708UL
1983 };
1986 };
1987 /* Default value: 0x0000000000000000 */
1988 
1989 #define QIB_7322_PcieCplDataBufrUnCorErrLogC_offset 0x00000710UL
1995 };
1998 };
1999 /* Default value: 0x0000000000000000 */
2000 
2001 #define QIB_7322_PcieCplHdrBufrUnCorErrLogA_offset 0x00000720UL
2004 };
2007 };
2008 /* Default value: 0x0000000000000000 */
2009 
2010 #define QIB_7322_PcieCplHdrBufrUnCorErrLogB_offset 0x00000728UL
2014 };
2017 };
2018 /* Default value: 0x0000000000000000 */
2019 
2020 #define QIB_7322_PcieCplHdrBufrUnCorErrLogC_offset 0x00000730UL
2025 };
2028 };
2029 /* Default value: 0x0000000000000000 */
2030 
2031 #define QIB_7322_PciePDataBufrUnCorErrLogA_offset 0x00000740UL
2034 };
2037 };
2038 /* Default value: 0x0000000000000000 */
2039 
2040 #define QIB_7322_PciePDataBufrUnCorErrLogB_offset 0x00000748UL
2043 };
2046 };
2047 /* Default value: 0x0000000000000000 */
2048 
2049 #define QIB_7322_PciePDataBufrUnCorErrLogC_offset 0x00000750UL
2055 };
2058 };
2059 /* Default value: 0x0000000000000000 */
2060 
2061 #define QIB_7322_PciePHdrBufrUnCorErrLogA_offset 0x00000760UL
2064 };
2067 };
2068 /* Default value: 0x0000000000000000 */
2069 
2070 #define QIB_7322_PciePHdrBufrUnCorErrLogB_offset 0x00000768UL
2074 };
2077 };
2078 /* Default value: 0x0000000000000000 */
2079 
2080 #define QIB_7322_PciePHdrBufrUnCorErrLogC_offset 0x00000770UL
2085 };
2088 };
2089 /* Default value: 0x0000000000000000 */
2090 
2091 #define QIB_7322_PcieRetryBufrUnCorErrLogA_offset 0x00000780UL
2094 };
2097 };
2098 /* Default value: 0x0000000000000000 */
2099 
2100 #define QIB_7322_PcieRetryBufrUnCorErrLogB_offset 0x00000788UL
2103 };
2106 };
2107 /* Default value: 0x0000000000000000 */
2108 
2109 #define QIB_7322_PcieRetryBufrUnCorErrLogC_offset 0x00000790UL
2115 };
2118 };
2119 /* Default value: 0x0000000000000000 */
2120 
2121 #define QIB_7322_RxTIDArrayUnCorErrLogA_offset 0x00000800UL
2126 };
2129 };
2130 /* Default value: 0x0000000000000000 */
2131 
2132 #define QIB_7322_RxTIDArrayUnCorErrLogB_offset 0x00000808UL
2136 };
2139 };
2140 /* Default value: 0x0000000000000000 */
2141 
2142 #define QIB_7322_RxEagerArrayUnCorErrLogA_offset 0x00000810UL
2147 };
2150 };
2151 /* Default value: 0x0000000000000000 */
2152 
2153 #define QIB_7322_RxEagerArrayUnCorErrLogB_offset 0x00000818UL
2157 };
2160 };
2161 /* Default value: 0x0000000000000000 */
2162 
2163 #define QIB_7322_SBufMainArrayUnCorErrLogA_offset 0x00000880UL
2166 };
2169 };
2170 /* Default value: 0x0000000000000000 */
2171 
2172 #define QIB_7322_SBufMainArrayUnCorErrLogB_offset 0x00000888UL
2175 };
2178 };
2179 /* Default value: 0x0000000000000000 */
2180 
2181 #define QIB_7322_SBufMainArrayUnCorErrLogC_offset 0x00000890UL
2187 };
2190 };
2191 /* Default value: 0x0000000000000000 */
2192 
2193 #define QIB_7322_SBufExtraArrayUnCorErrLogA_offset 0x00000898UL
2196 };
2199 };
2200 /* Default value: 0x0000000000000000 */
2201 
2202 #define QIB_7322_SBufExtraArrayUnCorErrLogB_offset 0x000008a0UL
2205 };
2208 };
2209 /* Default value: 0x0000000000000000 */
2210 
2211 #define QIB_7322_SBufExtraArrayUnCorErrLogC_offset 0x000008a8UL
2217 };
2220 };
2221 /* Default value: 0x0000000000000000 */
2222 
2223 #define QIB_7322_SendPbcArrayUnCorErrLog_offset 0x000008b0UL
2229 };
2232 };
2233 /* Default value: 0x0000000000000000 */
2234 
2235 #define QIB_7322_SBufVL15ArrayUnCorErrLogA_offset 0x000008c0UL
2238 };
2241 };
2242 /* Default value: 0x0000000000000000 */
2243 
2244 #define QIB_7322_PcieCplDataBufrCorErrLogA_offset 0x00000900UL
2247 };
2250 };
2251 /* Default value: 0x0000000000000000 */
2252 
2253 #define QIB_7322_PcieCplDataBufrCorErrLogB_offset 0x00000908UL
2256 };
2259 };
2260 /* Default value: 0x0000000000000000 */
2261 
2262 #define QIB_7322_PcieCplDataBufrCorErrLogC_offset 0x00000910UL
2268 };
2271 };
2272 /* Default value: 0x0000000000000000 */
2273 
2274 #define QIB_7322_PcieCplHdrBufrCorErrLogA_offset 0x00000920UL
2277 };
2280 };
2281 /* Default value: 0x0000000000000000 */
2282 
2283 #define QIB_7322_PcieCplHdrBufrCorErrLogB_offset 0x00000928UL
2287 };
2290 };
2291 /* Default value: 0x0000000000000000 */
2292 
2293 #define QIB_7322_PcieCplHdrBufrCorErrLogC_offset 0x00000930UL
2298 };
2301 };
2302 /* Default value: 0x0000000000000000 */
2303 
2304 #define QIB_7322_PciePDataBufrCorErrLogA_offset 0x00000940UL
2307 };
2310 };
2311 /* Default value: 0x0000000000000000 */
2312 
2313 #define QIB_7322_PciePDataBufrCorErrLogB_offset 0x00000948UL
2316 };
2319 };
2320 /* Default value: 0x0000000000000000 */
2321 
2322 #define QIB_7322_PciePDataBufrCorErrLogC_offset 0x00000950UL
2328 };
2331 };
2332 /* Default value: 0x0000000000000000 */
2333 
2334 #define QIB_7322_PciePHdrBufrCorErrLogA_offset 0x00000960UL
2337 };
2340 };
2341 /* Default value: 0x0000000000000000 */
2342 
2343 #define QIB_7322_PciePHdrBufrCorErrLogB_offset 0x00000968UL
2347 };
2350 };
2351 /* Default value: 0x0000000000000000 */
2352 
2353 #define QIB_7322_PciePHdrBufrCorErrLogC_offset 0x00000970UL
2358 };
2361 };
2362 /* Default value: 0x0000000000000000 */
2363 
2364 #define QIB_7322_PcieRetryBufrCorErrLogA_offset 0x00000980UL
2367 };
2370 };
2371 /* Default value: 0x0000000000000000 */
2372 
2373 #define QIB_7322_PcieRetryBufrCorErrLogB_offset 0x00000988UL
2376 };
2379 };
2380 /* Default value: 0x0000000000000000 */
2381 
2382 #define QIB_7322_PcieRetryBufrCorErrLogC_offset 0x00000990UL
2388 };
2391 };
2392 /* Default value: 0x0000000000000000 */
2393 
2394 #define QIB_7322_RxTIDArrayCorErrLogA_offset 0x00000a00UL
2399 };
2402 };
2403 /* Default value: 0x0000000000000000 */
2404 
2405 #define QIB_7322_RxTIDArrayCorErrLogB_offset 0x00000a08UL
2409 };
2412 };
2413 /* Default value: 0x0000000000000000 */
2414 
2415 #define QIB_7322_RxEagerArrayCorErrLogA_offset 0x00000a10UL
2420 };
2423 };
2424 /* Default value: 0x0000000000000000 */
2425 
2426 #define QIB_7322_RxEagerArrayCorErrLogB_offset 0x00000a18UL
2430 };
2433 };
2434 /* Default value: 0x0000000000000000 */
2435 
2436 #define QIB_7322_SBufMainArrayCorErrLogA_offset 0x00000a80UL
2439 };
2442 };
2443 /* Default value: 0x0000000000000000 */
2444 
2445 #define QIB_7322_SBufMainArrayCorErrLogB_offset 0x00000a88UL
2448 };
2451 };
2452 /* Default value: 0x0000000000000000 */
2453 
2454 #define QIB_7322_SBufMainArrayCorErrLogC_offset 0x00000a90UL
2460 };
2463 };
2464 /* Default value: 0x0000000000000000 */
2465 
2466 #define QIB_7322_SBufExtraArrayCorErrLogA_offset 0x00000a98UL
2469 };
2472 };
2473 /* Default value: 0x0000000000000000 */
2474 
2475 #define QIB_7322_SBufExtraArrayCorErrLogB_offset 0x00000aa0UL
2478 };
2481 };
2482 /* Default value: 0x0000000000000000 */
2483 
2484 #define QIB_7322_SBufExtraArrayCorErrLogC_offset 0x00000aa8UL
2490 };
2493 };
2494 /* Default value: 0x0000000000000000 */
2495 
2496 #define QIB_7322_SendPbcArrayCorErrLog_offset 0x00000ab0UL
2502 };
2505 };
2506 /* Default value: 0x0000000000000000 */
2507 
2508 #define QIB_7322_SBufVL15ArrayCorErrLogA_offset 0x00000ac0UL
2511 };
2514 };
2515 /* Default value: 0x0000000000000000 */
2516 
2517 #define QIB_7322_RcvAvailTimeOut0_offset 0x00000c00UL
2522 };
2525 };
2526 /* Default value: 0x0000000000000000 */
2527 
2528 #define QIB_7322_CntrRegBase_0_offset 0x00001028UL
2529 /* Default value: 0x0000000000012000 */
2530 
2531 #define QIB_7322_ErrMask_0_offset 0x00001080UL
2578 };
2581 };
2582 /* Default value: 0x0000000000000000 */
2583 
2584 #define QIB_7322_ErrStatus_0_offset 0x00001088UL
2631 };
2634 };
2635 /* Default value: 0x0000000000000000 */
2636 
2637 #define QIB_7322_ErrClear_0_offset 0x00001090UL
2684 };
2687 };
2688 /* Default value: 0x0000000000000000 */
2689 
2690 #define QIB_7322_TXEStatus_0_offset 0x000010b8UL
2706 };
2709 };
2710 /* Default value: 0x0000000XC00080FF */
2711 
2712 #define QIB_7322_RcvCtrl_0_offset 0x00001100UL
2723 };
2726 };
2727 /* Default value: 0x0000000000000000 */
2728 
2729 #define QIB_7322_RcvBTHQP_0_offset 0x00001108UL
2733 };
2736 };
2737 /* Default value: 0x0000000000000000 */
2738 
2739 #define QIB_7322_RcvQPMapTableA_0_offset 0x00001110UL
2748 };
2751 };
2752 /* Default value: 0x0000000000000000 */
2753 
2754 #define QIB_7322_RcvQPMapTableB_0_offset 0x00001118UL
2763 };
2766 };
2767 /* Default value: 0x0000000000000000 */
2768 
2769 #define QIB_7322_RcvQPMapTableC_0_offset 0x00001120UL
2778 };
2781 };
2782 /* Default value: 0x0000000000000000 */
2783 
2784 #define QIB_7322_RcvQPMapTableD_0_offset 0x00001128UL
2793 };
2796 };
2797 /* Default value: 0x0000000000000000 */
2798 
2799 #define QIB_7322_RcvQPMapTableE_0_offset 0x00001130UL
2808 };
2811 };
2812 /* Default value: 0x0000000000000000 */
2813 
2814 #define QIB_7322_RcvQPMapTableF_0_offset 0x00001138UL
2819 };
2822 };
2823 /* Default value: 0x0000000000000000 */
2824 
2825 #define QIB_7322_PSStat_0_offset 0x00001140UL
2826 /* Default value: 0x0000000000000000 */
2827 
2828 #define QIB_7322_PSStart_0_offset 0x00001148UL
2829 /* Default value: 0x0000000000000000 */
2830 
2831 #define QIB_7322_PSInterval_0_offset 0x00001150UL
2832 /* Default value: 0x0000000000000000 */
2833 
2834 #define QIB_7322_RcvStatus_0_offset 0x00001160UL
2839 };
2842 };
2843 /* Default value: 0x0000000000000000 */
2844 
2845 #define QIB_7322_RcvPartitionKey_0_offset 0x00001168UL
2846 /* Default value: 0x0000000000000000 */
2847 
2848 #define QIB_7322_RcvQPMulticastContext_0_offset 0x00001170UL
2852 };
2855 };
2856 /* Default value: 0x0000000000000000 */
2857 
2858 #define QIB_7322_RcvPktLEDCnt_0_offset 0x00001178UL
2862 };
2865 };
2866 /* Default value: 0x0000000000000000 */
2867 
2868 #define QIB_7322_SendDmaIdleCnt_0_offset 0x00001180UL
2872 };
2875 };
2876 /* Default value: 0x0000000000000000 */
2877 
2878 #define QIB_7322_SendDmaReloadCnt_0_offset 0x00001188UL
2882 };
2885 };
2886 /* Default value: 0x0000000000000000 */
2887 
2888 #define QIB_7322_SendDmaDescCnt_0_offset 0x00001190UL
2892 };
2895 };
2896 /* Default value: 0x0000000000000000 */
2897 
2898 #define QIB_7322_SendCtrl_0_offset 0x000011c0UL
2915 };
2918 };
2919 /* Default value: 0x0000000000000000 */
2920 
2921 #define QIB_7322_SendDmaBase_0_offset 0x000011f8UL
2925 };
2928 };
2929 /* Default value: 0x0000000000000000 */
2930 
2931 #define QIB_7322_SendDmaLenGen_0_offset 0x00001200UL
2936 };
2939 };
2940 /* Default value: 0x0000000000000000 */
2941 
2942 #define QIB_7322_SendDmaTail_0_offset 0x00001208UL
2946 };
2949 };
2950 /* Default value: 0x0000000000000000 */
2951 
2952 #define QIB_7322_SendDmaHead_0_offset 0x00001210UL
2958 };
2961 };
2962 /* Default value: 0x0000000000000000 */
2963 
2964 #define QIB_7322_SendDmaHeadAddr_0_offset 0x00001218UL
2968 };
2971 };
2972 /* Default value: 0x0000000000000000 */
2973 
2974 #define QIB_7322_SendDmaBufMask0_0_offset 0x00001220UL
2977 };
2980 };
2981 /* Default value: 0x0000000000000000 */
2982 
2983 #define QIB_7322_SendDmaStatus_0_offset 0x00001238UL
3001 };
3004 };
3005 /* Default value: 0x0000000042000000 */
3006 
3007 #define QIB_7322_SendDmaPriorityThld_0_offset 0x00001258UL
3011 };
3014 };
3015 /* Default value: 0x0000000000000000 */
3016 
3017 #define QIB_7322_SendHdrErrSymptom_0_offset 0x00001260UL
3027 };
3030 };
3031 /* Default value: 0x0000000000000000 */
3032 
3033 #define QIB_7322_RxCreditVL0_0_offset 0x00001280UL
3039 };
3042 };
3043 /* Default value: 0x0000000000000000 */
3044 
3045 #define QIB_7322_SendDmaBufUsed0_0_offset 0x00001480UL
3048 };
3051 };
3052 /* Default value: 0x0000000000000000 */
3053 
3054 #define QIB_7322_SendDmaReqTagUsed_0_offset 0x00001498UL
3058 };
3061 };
3062 /* Default value: 0x0000000000000000 */
3063 
3064 #define QIB_7322_SendCheckControl_0_offset 0x000014a8UL
3072 };
3075 };
3076 /* Default value: 0x0000000000000000 */
3077 
3078 #define QIB_7322_SendIBSLIDMask_0_offset 0x000014b0UL
3082 };
3085 };
3086 /* Default value: 0x0000000000000000 */
3087 
3088 #define QIB_7322_SendIBSLIDAssign_0_offset 0x000014b8UL
3092 };
3095 };
3096 /* Default value: 0x0000000000000000 */
3097 
3098 #define QIB_7322_IBCStatusA_0_offset 0x00001540UL
3123 };
3126 };
3127 /* Default value: 0x0000000000000X02 */
3128 
3129 #define QIB_7322_IBCStatusB_0_offset 0x00001548UL
3140 };
3143 };
3144 /* Default value: 0x00000000XXXXXXXX */
3145 
3146 #define QIB_7322_IBCCtrlA_0_offset 0x00001560UL
3162 };
3165 };
3166 /* Default value: 0x0000000000000000 */
3167 
3168 #define QIB_7322_IBCCtrlB_0_offset 0x00001568UL
3190 };
3193 };
3194 /* Default value: 0x00000000000305FF */
3195 
3196 #define QIB_7322_IBCCtrlC_0_offset 0x00001570UL
3201 };
3204 };
3205 /* Default value: 0x0000000000000301 */
3206 
3207 #define QIB_7322_HRTBT_GUID_0_offset 0x00001588UL
3208 /* Default value: 0x0000000000000000 */
3209 
3210 #define QIB_7322_IB_SDTEST_IF_TX_0_offset 0x00001590UL
3222 };
3225 };
3226 /* Default value: 0x0000000000000000 */
3227 
3228 #define QIB_7322_IB_SDTEST_IF_RX_0_offset 0x00001598UL
3237 };
3240 };
3241 /* Default value: 0x0000000000000000 */
3242 
3243 #define QIB_7322_IBNCModeCtrl_0_offset 0x000015b8UL
3256 };
3259 };
3260 /* Default value: 0x0000000000000000 */
3261 
3262 #define QIB_7322_IBSerdesStatus_0_offset 0x000015d0UL
3263 /* Default value: 0x0000000000000000 */
3264 
3265 #define QIB_7322_IBPCSConfig_0_offset 0x000015d8UL
3273 };
3276 };
3277 /* Default value: 0x0000000000000007 */
3278 
3279 #define QIB_7322_IBSerdesCtrl_0_offset 0x000015e0UL
3297 };
3300 };
3301 /* Default value: 0x0000000000FFA00F */
3302 
3303 #define QIB_7322_IBSD_TX_DEEMPHASIS_OVERRIDE_0_offset 0x00001600UL
3314 };
3317 };
3318 /* Default value: 0x0000000000000000 */
3319 
3320 #define QIB_7322_ADAPT_DISABLE_STATIC_SDR_0_offset 0x00001640UL
3335 };
3338 };
3339 /* Default value: 0x0000000000000000 */
3340 
3341 #define QIB_7322_ADAPT_DISABLE_DYNAMIC_SDR_0_offset 0x00001648UL