iPXE
rfbuffer.h
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1 /*
2  * RF Buffer handling functions
3  *
4  * Copyright (c) 2009 Nick Kossifidis <mickflemm@gmail.com>
5  *
6  * Permission to use, copy, modify, and distribute this software for any
7  * purpose with or without fee is hereby granted, provided that the above
8  * copyright notice and this permission notice appear in all copies.
9  *
10  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
11  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
12  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
13  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
14  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
15  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
16  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
17  *
18  */
19 
20 FILE_SECBOOT ( FORBIDDEN );
21 
22 /*
23  * There are some special registers on the RF chip
24  * that control various operation settings related mostly to
25  * the analog parts (channel, gain adjustment etc).
26  *
27  * We don't write on those registers directly but
28  * we send a data packet on the chip, using a special register,
29  * that holds all the settings we need. After we 've sent the
30  * data packet, we write on another special register to notify hw
31  * to apply the settings. This is done so that control registers
32  * can be dynamicaly programmed during operation and the settings
33  * are applied faster on the hw.
34  *
35  * We call each data packet an "RF Bank" and all the data we write
36  * (all RF Banks) "RF Buffer". This file holds initial RF Buffer
37  * data for the different RF chips, and various info to match RF
38  * Buffer offsets with specific RF registers so that we can access
39  * them. We tweak these settings on rfregs_init function.
40  *
41  * Also check out reg.h and U.S. Patent 6677779 B1 (about buffer
42  * registers and control registers):
43  *
44  * http://www.google.com/patents?id=qNURAAAAEBAJ
45  */
46 
47 
48 /*
49  * Struct to hold default mode specific RF
50  * register values (RF Banks)
51  */
52 struct ath5k_ini_rfbuffer {
53  u8 rfb_bank; /* RF Bank number */
54  u16 rfb_ctrl_register; /* RF Buffer control register */
55  u32 rfb_mode_data[5]; /* RF Buffer data for each mode */
56 };
57 
58 /*
59  * Struct to hold RF Buffer field
60  * infos used to access certain RF
61  * analog registers
62  */
63 struct ath5k_rfb_field {
64  u8 len; /* Field length */
65  u16 pos; /* Offset on the raw packet */
66  u8 col; /* Column -used for shifting */
67 };
68 
69 /*
70  * RF analog register definition
71  */
72 struct ath5k_rf_reg {
73  u8 bank; /* RF Buffer Bank number */
74  u8 index; /* Register's index on rf_regs_idx */
75  struct ath5k_rfb_field field; /* RF Buffer field for this register */
76 };
77 
78 /* Map RF registers to indexes
79  * We do this to handle common bits and make our
80  * life easier by using an index for each register
81  * instead of a full rfb_field */
82 enum ath5k_rf_regs_idx {
83  /* BANK 6 */
84  AR5K_RF_OB_2GHZ = 0,
85  AR5K_RF_OB_5GHZ,
86  AR5K_RF_DB_2GHZ,
87  AR5K_RF_DB_5GHZ,
88  AR5K_RF_FIXED_BIAS_A,
89  AR5K_RF_FIXED_BIAS_B,
90  AR5K_RF_PWD_XPD,
91  AR5K_RF_XPD_SEL,
92  AR5K_RF_XPD_GAIN,
93  AR5K_RF_PD_GAIN_LO,
94  AR5K_RF_PD_GAIN_HI,
95  AR5K_RF_HIGH_VC_CP,
96  AR5K_RF_MID_VC_CP,
97  AR5K_RF_LOW_VC_CP,
98  AR5K_RF_PUSH_UP,
99  AR5K_RF_PAD2GND,
100  AR5K_RF_XB2_LVL,
101  AR5K_RF_XB5_LVL,
102  AR5K_RF_PWD_ICLOBUF_2G,
103  AR5K_RF_PWD_84,
104  AR5K_RF_PWD_90,
105  AR5K_RF_PWD_130,
106  AR5K_RF_PWD_131,
107  AR5K_RF_PWD_132,
108  AR5K_RF_PWD_136,
109  AR5K_RF_PWD_137,
110  AR5K_RF_PWD_138,
111  AR5K_RF_PWD_166,
112  AR5K_RF_PWD_167,
113  AR5K_RF_DERBY_CHAN_SEL_MODE,
114  /* BANK 7 */
115  AR5K_RF_GAIN_I,
116  AR5K_RF_PLO_SEL,
117  AR5K_RF_RFGAIN_SEL,
118  AR5K_RF_RFGAIN_STEP,
119  AR5K_RF_WAIT_S,
120  AR5K_RF_WAIT_I,
121  AR5K_RF_MAX_TIME,
122  AR5K_RF_MIXVGA_OVR,
123  AR5K_RF_MIXGAIN_OVR,
124  AR5K_RF_MIXGAIN_STEP,
125  AR5K_RF_PD_DELAY_A,
126  AR5K_RF_PD_DELAY_B,
127  AR5K_RF_PD_DELAY_XR,
128  AR5K_RF_PD_PERIOD_A,
129  AR5K_RF_PD_PERIOD_B,
130  AR5K_RF_PD_PERIOD_XR,
131 };
132 
133 
134 /*******************\
135 * RF5111 (Sombrero) *
136 \*******************/
137 
138 /* BANK 6 len pos col */
139 #define AR5K_RF5111_OB_2GHZ { 3, 119, 0 }
140 #define AR5K_RF5111_DB_2GHZ { 3, 122, 0 }
141 
142 #define AR5K_RF5111_OB_5GHZ { 3, 104, 0 }
143 #define AR5K_RF5111_DB_5GHZ { 3, 107, 0 }
144 
145 #define AR5K_RF5111_PWD_XPD { 1, 95, 0 }
146 #define AR5K_RF5111_XPD_GAIN { 4, 96, 0 }
147 
148 /* Access to PWD registers */
149 #define AR5K_RF5111_PWD(_n) { 1, (135 - _n), 3 }
150 
151 /* BANK 7 len pos col */
152 #define AR5K_RF5111_GAIN_I { 6, 29, 0 }
153 #define AR5K_RF5111_PLO_SEL { 1, 4, 0 }
154 #define AR5K_RF5111_RFGAIN_SEL { 1, 36, 0 }
155 #define AR5K_RF5111_RFGAIN_STEP { 6, 37, 0 }
156 /* Only on AR5212 BaseBand and up */
157 #define AR5K_RF5111_WAIT_S { 5, 19, 0 }
158 #define AR5K_RF5111_WAIT_I { 5, 24, 0 }
159 #define AR5K_RF5111_MAX_TIME { 2, 49, 0 }
160 
161 static const struct ath5k_rf_reg rf_regs_5111[] = {
162  {6, AR5K_RF_OB_2GHZ, AR5K_RF5111_OB_2GHZ},
163  {6, AR5K_RF_DB_2GHZ, AR5K_RF5111_DB_2GHZ},
164  {6, AR5K_RF_OB_5GHZ, AR5K_RF5111_OB_5GHZ},
165  {6, AR5K_RF_DB_5GHZ, AR5K_RF5111_DB_5GHZ},
166  {6, AR5K_RF_PWD_XPD, AR5K_RF5111_PWD_XPD},
167  {6, AR5K_RF_XPD_GAIN, AR5K_RF5111_XPD_GAIN},
168  {6, AR5K_RF_PWD_84, AR5K_RF5111_PWD(84)},
169  {6, AR5K_RF_PWD_90, AR5K_RF5111_PWD(90)},
170  {7, AR5K_RF_GAIN_I, AR5K_RF5111_GAIN_I},
171  {7, AR5K_RF_PLO_SEL, AR5K_RF5111_PLO_SEL},
172  {7, AR5K_RF_RFGAIN_SEL, AR5K_RF5111_RFGAIN_SEL},
173  {7, AR5K_RF_RFGAIN_STEP, AR5K_RF5111_RFGAIN_STEP},
174  {7, AR5K_RF_WAIT_S, AR5K_RF5111_WAIT_S},
175  {7, AR5K_RF_WAIT_I, AR5K_RF5111_WAIT_I},
176  {7, AR5K_RF_MAX_TIME, AR5K_RF5111_MAX_TIME}
177 };
178 
179 /* Default mode specific settings */
180 static const struct ath5k_ini_rfbuffer rfb_5111[] = {
181  { 0, 0x989c,
182  /* mode a/XR mode aTurbo mode b mode g mode gTurbo */
183  { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
184  { 0, 0x989c,
185  { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
186  { 0, 0x989c,
187  { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
188  { 0, 0x989c,
189  { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
190  { 0, 0x989c,
191  { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
192  { 0, 0x989c,
193  { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
194  { 0, 0x989c,
195  { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
196  { 0, 0x989c,
197  { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
198  { 0, 0x989c,
199  { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
200  { 0, 0x989c,
201  { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
202  { 0, 0x989c,
203  { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
204  { 0, 0x989c,
205  { 0x00380000, 0x00380000, 0x00380000, 0x00380000, 0x00380000 } },
206  { 0, 0x989c,
207  { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
208  { 0, 0x989c,
209  { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
210  { 0, 0x989c,
211  { 0x00000000, 0x00000000, 0x000000c0, 0x00000080, 0x00000080 } },
212  { 0, 0x989c,
213  { 0x000400f9, 0x000400f9, 0x000400ff, 0x000400fd, 0x000400fd } },
214  { 0, 0x98d4,
215  { 0x00000000, 0x00000000, 0x00000004, 0x00000004, 0x00000004 } },
216  { 1, 0x98d4,
217  { 0x00000020, 0x00000020, 0x00000020, 0x00000020, 0x00000020 } },
218  { 2, 0x98d4,
219  { 0x00000010, 0x00000014, 0x00000010, 0x00000010, 0x00000014 } },
220  { 3, 0x98d8,
221  { 0x00601068, 0x00601068, 0x00601068, 0x00601068, 0x00601068 } },
222  { 6, 0x989c,
223  { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
224  { 6, 0x989c,
225  { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
226  { 6, 0x989c,
227  { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
228  { 6, 0x989c,
229  { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
230  { 6, 0x989c,
231  { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
232  { 6, 0x989c,
233  { 0x10000000, 0x10000000, 0x10000000, 0x10000000, 0x10000000 } },
234  { 6, 0x989c,
235  { 0x04000000, 0x04000000, 0x04000000, 0x04000000, 0x04000000 } },
236  { 6, 0x989c,
237  { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
238  { 6, 0x989c,
239  { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
240  { 6, 0x989c,
241  { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
242  { 6, 0x989c,
243  { 0x00000000, 0x00000000, 0x0a000000, 0x00000000, 0x00000000 } },
244  { 6, 0x989c,
245  { 0x003800c0, 0x00380080, 0x023800c0, 0x003800c0, 0x003800c0 } },
246  { 6, 0x989c,
247  { 0x00020006, 0x00020006, 0x00000006, 0x00020006, 0x00020006 } },
248  { 6, 0x989c,
249  { 0x00000089, 0x00000089, 0x00000089, 0x00000089, 0x00000089 } },
250  { 6, 0x989c,
251  { 0x000000a0, 0x000000a0, 0x000000a0, 0x000000a0, 0x000000a0 } },
252  { 6, 0x989c,
253  { 0x00040007, 0x00040007, 0x00040007, 0x00040007, 0x00040007 } },
254  { 6, 0x98d4,
255  { 0x0000001a, 0x0000001a, 0x0000001a, 0x0000001a, 0x0000001a } },
256  { 7, 0x989c,
257  { 0x00000040, 0x00000048, 0x00000040, 0x00000040, 0x00000040 } },
258  { 7, 0x989c,
259  { 0x00000010, 0x00000010, 0x00000010, 0x00000010, 0x00000010 } },
260  { 7, 0x989c,
261  { 0x00000008, 0x00000008, 0x00000008, 0x00000008, 0x00000008 } },
262  { 7, 0x989c,
263  { 0x0000004f, 0x0000004f, 0x0000004f, 0x0000004f, 0x0000004f } },
264  { 7, 0x989c,
265  { 0x000000f1, 0x000000f1, 0x00000061, 0x000000f1, 0x000000f1 } },
266  { 7, 0x989c,
267  { 0x0000904f, 0x0000904f, 0x0000904c, 0x0000904f, 0x0000904f } },
268  { 7, 0x989c,
269  { 0x0000125a, 0x0000125a, 0x0000129a, 0x0000125a, 0x0000125a } },
270  { 7, 0x98cc,
271  { 0x0000000e, 0x0000000e, 0x0000000f, 0x0000000e, 0x0000000e } },
272 };
273 
274 
275 
276 /***********************\
277 * RF5112/RF2112 (Derby) *
278 \***********************/
279 
280 /* BANK 7 (Common) len pos col */
281 #define AR5K_RF5112X_GAIN_I { 6, 14, 0 }
282 #define AR5K_RF5112X_MIXVGA_OVR { 1, 36, 0 }
283 #define AR5K_RF5112X_MIXGAIN_OVR { 2, 37, 0 }
284 #define AR5K_RF5112X_MIXGAIN_STEP { 4, 32, 0 }
285 #define AR5K_RF5112X_PD_DELAY_A { 4, 58, 0 }
286 #define AR5K_RF5112X_PD_DELAY_B { 4, 62, 0 }
287 #define AR5K_RF5112X_PD_DELAY_XR { 4, 66, 0 }
288 #define AR5K_RF5112X_PD_PERIOD_A { 4, 70, 0 }
289 #define AR5K_RF5112X_PD_PERIOD_B { 4, 74, 0 }
290 #define AR5K_RF5112X_PD_PERIOD_XR { 4, 78, 0 }
291 
292 /* RFX112 (Derby 1) */
293 
294 /* BANK 6 len pos col */
295 #define AR5K_RF5112_OB_2GHZ { 3, 269, 0 }
296 #define AR5K_RF5112_DB_2GHZ { 3, 272, 0 }
297 
298 #define AR5K_RF5112_OB_5GHZ { 3, 261, 0 }
299 #define AR5K_RF5112_DB_5GHZ { 3, 264, 0 }
300 
301 #define AR5K_RF5112_FIXED_BIAS_A { 1, 260, 0 }
302 #define AR5K_RF5112_FIXED_BIAS_B { 1, 259, 0 }
303 
304 #define AR5K_RF5112_XPD_SEL { 1, 284, 0 }
305 #define AR5K_RF5112_XPD_GAIN { 2, 252, 0 }
306 
307 /* Access to PWD registers */
308 #define AR5K_RF5112_PWD(_n) { 1, (302 - _n), 3 }
309 
310 static const struct ath5k_rf_reg rf_regs_5112[] = {
311  {6, AR5K_RF_OB_2GHZ, AR5K_RF5112_OB_2GHZ},
312  {6, AR5K_RF_DB_2GHZ, AR5K_RF5112_DB_2GHZ},
313  {6, AR5K_RF_OB_5GHZ, AR5K_RF5112_OB_5GHZ},
314  {6, AR5K_RF_DB_5GHZ, AR5K_RF5112_DB_5GHZ},
315  {6, AR5K_RF_FIXED_BIAS_A, AR5K_RF5112_FIXED_BIAS_A},
316  {6, AR5K_RF_FIXED_BIAS_B, AR5K_RF5112_FIXED_BIAS_B},
317  {6, AR5K_RF_XPD_SEL, AR5K_RF5112_XPD_SEL},
318  {6, AR5K_RF_XPD_GAIN, AR5K_RF5112_XPD_GAIN},
319  {6, AR5K_RF_PWD_130, AR5K_RF5112_PWD(130)},
320  {6, AR5K_RF_PWD_131, AR5K_RF5112_PWD(131)},
321  {6, AR5K_RF_PWD_132, AR5K_RF5112_PWD(132)},
322  {6, AR5K_RF_PWD_136, AR5K_RF5112_PWD(136)},
323  {6, AR5K_RF_PWD_137, AR5K_RF5112_PWD(137)},
324  {6, AR5K_RF_PWD_138, AR5K_RF5112_PWD(138)},
325  {7, AR5K_RF_GAIN_I, AR5K_RF5112X_GAIN_I},
326  {7, AR5K_RF_MIXVGA_OVR, AR5K_RF5112X_MIXVGA_OVR},
327  {7, AR5K_RF_MIXGAIN_OVR, AR5K_RF5112X_MIXGAIN_OVR},
328  {7, AR5K_RF_MIXGAIN_STEP, AR5K_RF5112X_MIXGAIN_STEP},
329  {7, AR5K_RF_PD_DELAY_A, AR5K_RF5112X_PD_DELAY_A},
330  {7, AR5K_RF_PD_DELAY_B, AR5K_RF5112X_PD_DELAY_B},
331  {7, AR5K_RF_PD_DELAY_XR, AR5K_RF5112X_PD_DELAY_XR},
332  {7, AR5K_RF_PD_PERIOD_A, AR5K_RF5112X_PD_PERIOD_A},
333  {7, AR5K_RF_PD_PERIOD_B, AR5K_RF5112X_PD_PERIOD_B},
334  {7, AR5K_RF_PD_PERIOD_XR, AR5K_RF5112X_PD_PERIOD_XR},
335 };
336 
337 /* Default mode specific settings */
338 static const struct ath5k_ini_rfbuffer rfb_5112[] = {
339  { 1, 0x98d4,
340  /* mode a/XR mode aTurbo mode b mode g mode gTurbo */
341  { 0x00000020, 0x00000020, 0x00000020, 0x00000020, 0x00000020 } },
342  { 2, 0x98d0,
343  { 0x03060408, 0x03070408, 0x03060408, 0x03060408, 0x03070408 } },
344  { 3, 0x98dc,
345  { 0x00a0c0c0, 0x00a0c0c0, 0x00e0c0c0, 0x00e0c0c0, 0x00e0c0c0 } },
346  { 6, 0x989c,
347  { 0x00a00000, 0x00a00000, 0x00a00000, 0x00a00000, 0x00a00000 } },
348  { 6, 0x989c,
349  { 0x000a0000, 0x000a0000, 0x000a0000, 0x000a0000, 0x000a0000 } },
350  { 6, 0x989c,
351  { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
352  { 6, 0x989c,
353  { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
354  { 6, 0x989c,
355  { 0x00660000, 0x00660000, 0x00660000, 0x00660000, 0x00660000 } },
356  { 6, 0x989c,
357  { 0x00db0000, 0x00db0000, 0x00db0000, 0x00db0000, 0x00db0000 } },
358  { 6, 0x989c,
359  { 0x00f10000, 0x00f10000, 0x00f10000, 0x00f10000, 0x00f10000 } },
360  { 6, 0x989c,
361  { 0x00120000, 0x00120000, 0x00120000, 0x00120000, 0x00120000 } },
362  { 6, 0x989c,
363  { 0x00120000, 0x00120000, 0x00120000, 0x00120000, 0x00120000 } },
364  { 6, 0x989c,
365  { 0x00730000, 0x00730000, 0x00730000, 0x00730000, 0x00730000 } },
366  { 6, 0x989c,
367  { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
368  { 6, 0x989c,
369  { 0x000c0000, 0x000c0000, 0x000c0000, 0x000c0000, 0x000c0000 } },
370  { 6, 0x989c,
371  { 0x00ff0000, 0x00ff0000, 0x00ff0000, 0x00ff0000, 0x00ff0000 } },
372  { 6, 0x989c,
373  { 0x00ff0000, 0x00ff0000, 0x00ff0000, 0x00ff0000, 0x00ff0000 } },
374  { 6, 0x989c,
375  { 0x008b0000, 0x008b0000, 0x008b0000, 0x008b0000, 0x008b0000 } },
376  { 6, 0x989c,
377  { 0x00600000, 0x00600000, 0x00600000, 0x00600000, 0x00600000 } },
378  { 6, 0x989c,
379  { 0x000c0000, 0x000c0000, 0x000c0000, 0x000c0000, 0x000c0000 } },
380  { 6, 0x989c,
381  { 0x00840000, 0x00840000, 0x00840000, 0x00840000, 0x00840000 } },
382  { 6, 0x989c,
383  { 0x00640000, 0x00640000, 0x00640000, 0x00640000, 0x00640000 } },
384  { 6, 0x989c,
385  { 0x00200000, 0x00200000, 0x00200000, 0x00200000, 0x00200000 } },
386  { 6, 0x989c,
387  { 0x00240000, 0x00240000, 0x00240000, 0x00240000, 0x00240000 } },
388  { 6, 0x989c,
389  { 0x00250000, 0x00250000, 0x00250000, 0x00250000, 0x00250000 } },
390  { 6, 0x989c,
391  { 0x00110000, 0x00110000, 0x00110000, 0x00110000, 0x00110000 } },
392  { 6, 0x989c,
393  { 0x00110000, 0x00110000, 0x00110000, 0x00110000, 0x00110000 } },
394  { 6, 0x989c,
395  { 0x00510000, 0x00510000, 0x00510000, 0x00510000, 0x00510000 } },
396  { 6, 0x989c,
397  { 0x1c040000, 0x1c040000, 0x1c040000, 0x1c040000, 0x1c040000 } },
398  { 6, 0x989c,
399  { 0x000a0000, 0x000a0000, 0x000a0000, 0x000a0000, 0x000a0000 } },
400  { 6, 0x989c,
401  { 0x00a10000, 0x00a10000, 0x00a10000, 0x00a10000, 0x00a10000 } },
402  { 6, 0x989c,
403  { 0x00400000, 0x00400000, 0x00400000, 0x00400000, 0x00400000 } },
404  { 6, 0x989c,
405  { 0x03090000, 0x03090000, 0x03090000, 0x03090000, 0x03090000 } },
406  { 6, 0x989c,
407  { 0x06000000, 0x06000000, 0x06000000, 0x06000000, 0x06000000 } },
408  { 6, 0x989c,
409  { 0x000000b0, 0x000000b0, 0x000000a8, 0x000000a8, 0x000000a8 } },
410  { 6, 0x989c,
411  { 0x0000002e, 0x0000002e, 0x0000002e, 0x0000002e, 0x0000002e } },
412  { 6, 0x989c,
413  { 0x006c4a41, 0x006c4a41, 0x006c4af1, 0x006c4a61, 0x006c4a61 } },
414  { 6, 0x989c,
415  { 0x0050892a, 0x0050892a, 0x0050892b, 0x0050892b, 0x0050892b } },
416  { 6, 0x989c,
417  { 0x00842400, 0x00842400, 0x00842400, 0x00842400, 0x00842400 } },
418  { 6, 0x989c,
419  { 0x00c69200, 0x00c69200, 0x00c69200, 0x00c69200, 0x00c69200 } },
420  { 6, 0x98d0,
421  { 0x0002000c, 0x0002000c, 0x0002000c, 0x0002000c, 0x0002000c } },
422  { 7, 0x989c,
423  { 0x00000094, 0x00000094, 0x00000094, 0x00000094, 0x00000094 } },
424  { 7, 0x989c,
425  { 0x00000091, 0x00000091, 0x00000091, 0x00000091, 0x00000091 } },
426  { 7, 0x989c,
427  { 0x0000000a, 0x0000000a, 0x00000012, 0x00000012, 0x00000012 } },
428  { 7, 0x989c,
429  { 0x00000080, 0x00000080, 0x00000080, 0x00000080, 0x00000080 } },
430  { 7, 0x989c,
431  { 0x000000c1, 0x000000c1, 0x000000c1, 0x000000c1, 0x000000c1 } },
432  { 7, 0x989c,
433  { 0x00000060, 0x00000060, 0x00000060, 0x00000060, 0x00000060 } },
434  { 7, 0x989c,
435  { 0x000000f0, 0x000000f0, 0x000000f0, 0x000000f0, 0x000000f0 } },
436  { 7, 0x989c,
437  { 0x00000022, 0x00000022, 0x00000022, 0x00000022, 0x00000022 } },
438  { 7, 0x989c,
439  { 0x00000092, 0x00000092, 0x00000092, 0x00000092, 0x00000092 } },
440  { 7, 0x989c,
441  { 0x000000d4, 0x000000d4, 0x000000d4, 0x000000d4, 0x000000d4 } },
442  { 7, 0x989c,
443  { 0x000014cc, 0x000014cc, 0x000014cc, 0x000014cc, 0x000014cc } },
444  { 7, 0x989c,
445  { 0x0000048c, 0x0000048c, 0x0000048c, 0x0000048c, 0x0000048c } },
446  { 7, 0x98c4,
447  { 0x00000003, 0x00000003, 0x00000003, 0x00000003, 0x00000003 } },
448 };
449 
450 /* RFX112A (Derby 2) */
451 
452 /* BANK 6 len pos col */
453 #define AR5K_RF5112A_OB_2GHZ { 3, 287, 0 }
454 #define AR5K_RF5112A_DB_2GHZ { 3, 290, 0 }
455 
456 #define AR5K_RF5112A_OB_5GHZ { 3, 279, 0 }
457 #define AR5K_RF5112A_DB_5GHZ { 3, 282, 0 }
458 
459 #define AR5K_RF5112A_FIXED_BIAS_A { 1, 278, 0 }
460 #define AR5K_RF5112A_FIXED_BIAS_B { 1, 277, 0 }
461 
462 #define AR5K_RF5112A_XPD_SEL { 1, 302, 0 }
463 #define AR5K_RF5112A_PDGAINLO { 2, 270, 0 }
464 #define AR5K_RF5112A_PDGAINHI { 2, 257, 0 }
465 
466 /* Access to PWD registers */
467 #define AR5K_RF5112A_PWD(_n) { 1, (306 - _n), 3 }
468 
469 /* Voltage regulators */
470 #define AR5K_RF5112A_HIGH_VC_CP { 2, 90, 2 }
471 #define AR5K_RF5112A_MID_VC_CP { 2, 92, 2 }
472 #define AR5K_RF5112A_LOW_VC_CP { 2, 94, 2 }
473 #define AR5K_RF5112A_PUSH_UP { 1, 254, 2 }
474 
475 /* Power consumption */
476 #define AR5K_RF5112A_PAD2GND { 1, 281, 1 }
477 #define AR5K_RF5112A_XB2_LVL { 2, 1, 3 }
478 #define AR5K_RF5112A_XB5_LVL { 2, 3, 3 }
479 
480 static const struct ath5k_rf_reg rf_regs_5112a[] = {
481  {6, AR5K_RF_OB_2GHZ, AR5K_RF5112A_OB_2GHZ},
482  {6, AR5K_RF_DB_2GHZ, AR5K_RF5112A_DB_2GHZ},
483  {6, AR5K_RF_OB_5GHZ, AR5K_RF5112A_OB_5GHZ},
484  {6, AR5K_RF_DB_5GHZ, AR5K_RF5112A_DB_5GHZ},
485  {6, AR5K_RF_FIXED_BIAS_A, AR5K_RF5112A_FIXED_BIAS_A},
486  {6, AR5K_RF_FIXED_BIAS_B, AR5K_RF5112A_FIXED_BIAS_B},
487  {6, AR5K_RF_XPD_SEL, AR5K_RF5112A_XPD_SEL},
488  {6, AR5K_RF_PD_GAIN_LO, AR5K_RF5112A_PDGAINLO},
489  {6, AR5K_RF_PD_GAIN_HI, AR5K_RF5112A_PDGAINHI},
490  {6, AR5K_RF_PWD_130, AR5K_RF5112A_PWD(130)},
491  {6, AR5K_RF_PWD_131, AR5K_RF5112A_PWD(131)},
492  {6, AR5K_RF_PWD_132, AR5K_RF5112A_PWD(132)},
493  {6, AR5K_RF_PWD_136, AR5K_RF5112A_PWD(136)},
494  {6, AR5K_RF_PWD_137, AR5K_RF5112A_PWD(137)},
495  {6, AR5K_RF_PWD_138, AR5K_RF5112A_PWD(138)},
496  {6, AR5K_RF_PWD_166, AR5K_RF5112A_PWD(166)},
497  {6, AR5K_RF_PWD_167, AR5K_RF5112A_PWD(167)},
498  {6, AR5K_RF_HIGH_VC_CP, AR5K_RF5112A_HIGH_VC_CP},
499  {6, AR5K_RF_MID_VC_CP, AR5K_RF5112A_MID_VC_CP},
500  {6, AR5K_RF_LOW_VC_CP, AR5K_RF5112A_LOW_VC_CP},
501  {6, AR5K_RF_PUSH_UP, AR5K_RF5112A_PUSH_UP},
502  {6, AR5K_RF_PAD2GND, AR5K_RF5112A_PAD2GND},
503  {6, AR5K_RF_XB2_LVL, AR5K_RF5112A_XB2_LVL},
504  {6, AR5K_RF_XB5_LVL, AR5K_RF5112A_XB5_LVL},
505  {7, AR5K_RF_GAIN_I, AR5K_RF5112X_GAIN_I},
506  {7, AR5K_RF_MIXVGA_OVR, AR5K_RF5112X_MIXVGA_OVR},
507  {7, AR5K_RF_MIXGAIN_OVR, AR5K_RF5112X_MIXGAIN_OVR},
508  {7, AR5K_RF_MIXGAIN_STEP, AR5K_RF5112X_MIXGAIN_STEP},
509  {7, AR5K_RF_PD_DELAY_A, AR5K_RF5112X_PD_DELAY_A},
510  {7, AR5K_RF_PD_DELAY_B, AR5K_RF5112X_PD_DELAY_B},
511  {7, AR5K_RF_PD_DELAY_XR, AR5K_RF5112X_PD_DELAY_XR},
512  {7, AR5K_RF_PD_PERIOD_A, AR5K_RF5112X_PD_PERIOD_A},
513  {7, AR5K_RF_PD_PERIOD_B, AR5K_RF5112X_PD_PERIOD_B},
514  {7, AR5K_RF_PD_PERIOD_XR, AR5K_RF5112X_PD_PERIOD_XR},
515 };
516 
517 /* Default mode specific settings */
518 static const struct ath5k_ini_rfbuffer rfb_5112a[] = {
519  { 1, 0x98d4,
520  /* mode a/XR mode aTurbo mode b mode g mode gTurbo */
521  { 0x00000020, 0x00000020, 0x00000020, 0x00000020, 0x00000020 } },
522  { 2, 0x98d0,
523  { 0x03060408, 0x03070408, 0x03060408, 0x03060408, 0x03070408 } },
524  { 3, 0x98dc,
525  { 0x00a020c0, 0x00a020c0, 0x00e020c0, 0x00e020c0, 0x00e020c0 } },
526  { 6, 0x989c,
527  { 0x0f000000, 0x0f000000, 0x0f000000, 0x0f000000, 0x0f000000 } },
528  { 6, 0x989c,
529  { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
530  { 6, 0x989c,
531  { 0x00800000, 0x00800000, 0x00800000, 0x00800000, 0x00800000 } },
532  { 6, 0x989c,
533  { 0x002a0000, 0x002a0000, 0x002a0000, 0x002a0000, 0x002a0000 } },
534  { 6, 0x989c,
535  { 0x00010000, 0x00010000, 0x00010000, 0x00010000, 0x00010000 } },
536  { 6, 0x989c,
537  { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
538  { 6, 0x989c,
539  { 0x00180000, 0x00180000, 0x00180000, 0x00180000, 0x00180000 } },
540  { 6, 0x989c,
541  { 0x00600000, 0x00600000, 0x006e0000, 0x006e0000, 0x006e0000 } },
542  { 6, 0x989c,
543  { 0x00c70000, 0x00c70000, 0x00c70000, 0x00c70000, 0x00c70000 } },
544  { 6, 0x989c,
545  { 0x004b0000, 0x004b0000, 0x004b0000, 0x004b0000, 0x004b0000 } },
546  { 6, 0x989c,
547  { 0x04480000, 0x04480000, 0x04480000, 0x04480000, 0x04480000 } },
548  { 6, 0x989c,
549  { 0x004c0000, 0x004c0000, 0x004c0000, 0x004c0000, 0x004c0000 } },
550  { 6, 0x989c,
551  { 0x00e40000, 0x00e40000, 0x00e40000, 0x00e40000, 0x00e40000 } },
552  { 6, 0x989c,
553  { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
554  { 6, 0x989c,
555  { 0x00fc0000, 0x00fc0000, 0x00fc0000, 0x00fc0000, 0x00fc0000 } },
556  { 6, 0x989c,
557  { 0x00ff0000, 0x00ff0000, 0x00ff0000, 0x00ff0000, 0x00ff0000 } },
558  { 6, 0x989c,
559  { 0x043f0000, 0x043f0000, 0x043f0000, 0x043f0000, 0x043f0000 } },
560  { 6, 0x989c,
561  { 0x000c0000, 0x000c0000, 0x000c0000, 0x000c0000, 0x000c0000 } },
562  { 6, 0x989c,
563  { 0x02190000, 0x02190000, 0x02190000, 0x02190000, 0x02190000 } },
564  { 6, 0x989c,
565  { 0x00240000, 0x00240000, 0x00240000, 0x00240000, 0x00240000 } },
566  { 6, 0x989c,
567  { 0x00b40000, 0x00b40000, 0x00b40000, 0x00b40000, 0x00b40000 } },
568  { 6, 0x989c,
569  { 0x00990000, 0x00990000, 0x00990000, 0x00990000, 0x00990000 } },
570  { 6, 0x989c,
571  { 0x00500000, 0x00500000, 0x00500000, 0x00500000, 0x00500000 } },
572  { 6, 0x989c,
573  { 0x002a0000, 0x002a0000, 0x002a0000, 0x002a0000, 0x002a0000 } },
574  { 6, 0x989c,
575  { 0x00120000, 0x00120000, 0x00120000, 0x00120000, 0x00120000 } },
576  { 6, 0x989c,
577  { 0xc0320000, 0xc0320000, 0xc0320000, 0xc0320000, 0xc0320000 } },
578  { 6, 0x989c,
579  { 0x01740000, 0x01740000, 0x01740000, 0x01740000, 0x01740000 } },
580  { 6, 0x989c,
581  { 0x00110000, 0x00110000, 0x00110000, 0x00110000, 0x00110000 } },
582  { 6, 0x989c,
583  { 0x86280000, 0x86280000, 0x86280000, 0x86280000, 0x86280000 } },
584  { 6, 0x989c,
585  { 0x31840000, 0x31840000, 0x31840000, 0x31840000, 0x31840000 } },
586  { 6, 0x989c,
587  { 0x00f20080, 0x00f20080, 0x00f20080, 0x00f20080, 0x00f20080 } },
588  { 6, 0x989c,
589  { 0x00270019, 0x00270019, 0x00270019, 0x00270019, 0x00270019 } },
590  { 6, 0x989c,
591  { 0x00000003, 0x00000003, 0x00000003, 0x00000003, 0x00000003 } },
592  { 6, 0x989c,
593  { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
594  { 6, 0x989c,
595  { 0x000000b2, 0x000000b2, 0x000000b2, 0x000000b2, 0x000000b2 } },
596  { 6, 0x989c,
597  { 0x00b02084, 0x00b02084, 0x00b02084, 0x00b02084, 0x00b02084 } },
598  { 6, 0x989c,
599  { 0x004125a4, 0x004125a4, 0x004125a4, 0x004125a4, 0x004125a4 } },
600  { 6, 0x989c,
601  { 0x00119220, 0x00119220, 0x00119220, 0x00119220, 0x00119220 } },
602  { 6, 0x989c,
603  { 0x001a4800, 0x001a4800, 0x001a4800, 0x001a4800, 0x001a4800 } },
604  { 6, 0x98d8,
605  { 0x000b0230, 0x000b0230, 0x000b0230, 0x000b0230, 0x000b0230 } },
606  { 7, 0x989c,
607  { 0x00000094, 0x00000094, 0x00000094, 0x00000094, 0x00000094 } },
608  { 7, 0x989c,
609  { 0x00000091, 0x00000091, 0x00000091, 0x00000091, 0x00000091 } },
610  { 7, 0x989c,
611  { 0x00000012, 0x00000012, 0x00000012, 0x00000012, 0x00000012 } },
612  { 7, 0x989c,
613  { 0x00000080, 0x00000080, 0x00000080, 0x00000080, 0x00000080 } },
614  { 7, 0x989c,
615  { 0x000000d9, 0x000000d9, 0x000000d9, 0x000000d9, 0x000000d9 } },
616  { 7, 0x989c,
617  { 0x00000060, 0x00000060, 0x00000060, 0x00000060, 0x00000060 } },
618  { 7, 0x989c,
619  { 0x000000f0, 0x000000f0, 0x000000f0, 0x000000f0, 0x000000f0 } },
620  { 7, 0x989c,
621  { 0x000000a2, 0x000000a2, 0x000000a2, 0x000000a2, 0x000000a2 } },
622  { 7, 0x989c,
623  { 0x00000052, 0x00000052, 0x00000052, 0x00000052, 0x00000052 } },
624  { 7, 0x989c,
625  { 0x000000d4, 0x000000d4, 0x000000d4, 0x000000d4, 0x000000d4 } },
626  { 7, 0x989c,
627  { 0x000014cc, 0x000014cc, 0x000014cc, 0x000014cc, 0x000014cc } },
628  { 7, 0x989c,
629  { 0x0000048c, 0x0000048c, 0x0000048c, 0x0000048c, 0x0000048c } },
630  { 7, 0x98c4,
631  { 0x00000003, 0x00000003, 0x00000003, 0x00000003, 0x00000003 } },
632 };
633 
634 
635 
636 /******************\
637 * RF2413 (Griffin) *
638 \******************/
639 
640 /* BANK 6 len pos col */
641 #define AR5K_RF2413_OB_2GHZ { 3, 168, 0 }
642 #define AR5K_RF2413_DB_2GHZ { 3, 165, 0 }
643 
644 static const struct ath5k_rf_reg rf_regs_2413[] = {
645  {6, AR5K_RF_OB_2GHZ, AR5K_RF2413_OB_2GHZ},
646  {6, AR5K_RF_DB_2GHZ, AR5K_RF2413_DB_2GHZ},
647 };
648 
649 /* Default mode specific settings
650  * XXX: a/aTurbo ???
651  */
652 static const struct ath5k_ini_rfbuffer rfb_2413[] = {
653  { 1, 0x98d4,
654  /* mode a/XR mode aTurbo mode b mode g mode gTurbo */
655  { 0x00000020, 0x00000020, 0x00000020, 0x00000020, 0x00000020 } },
656  { 2, 0x98d0,
657  { 0x02001408, 0x02011408, 0x02001408, 0x02001408, 0x02011408 } },
658  { 3, 0x98dc,
659  { 0x00a020c0, 0x00a020c0, 0x00e020c0, 0x00e020c0, 0x00e020c0 } },
660  { 6, 0x989c,
661  { 0xf0000000, 0xf0000000, 0xf0000000, 0xf0000000, 0xf0000000 } },
662  { 6, 0x989c,
663  { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
664  { 6, 0x989c,
665  { 0x03000000, 0x03000000, 0x03000000, 0x03000000, 0x03000000 } },
666  { 6, 0x989c,
667  { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
668  { 6, 0x989c,
669  { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
670  { 6, 0x989c,
671  { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
672  { 6, 0x989c,
673  { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
674  { 6, 0x989c,
675  { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
676  { 6, 0x989c,
677  { 0x40400000, 0x40400000, 0x40400000, 0x40400000, 0x40400000 } },
678  { 6, 0x989c,
679  { 0x65050000, 0x65050000, 0x65050000, 0x65050000, 0x65050000 } },
680  { 6, 0x989c,
681  { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
682  { 6, 0x989c,
683  { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
684  { 6, 0x989c,
685  { 0x00420000, 0x00420000, 0x00420000, 0x00420000, 0x00420000 } },
686  { 6, 0x989c,
687  { 0x00b50000, 0x00b50000, 0x00b50000, 0x00b50000, 0x00b50000 } },
688  { 6, 0x989c,
689  { 0x00030000, 0x00030000, 0x00030000, 0x00030000, 0x00030000 } },
690  { 6, 0x989c,
691  { 0x00f70000, 0x00f70000, 0x00f70000, 0x00f70000, 0x00f70000 } },
692  { 6, 0x989c,
693  { 0x009d0000, 0x009d0000, 0x009d0000, 0x009d0000, 0x009d0000 } },
694  { 6, 0x989c,
695  { 0x00220000, 0x00220000, 0x00220000, 0x00220000, 0x00220000 } },
696  { 6, 0x989c,
697  { 0x04220000, 0x04220000, 0x04220000, 0x04220000, 0x04220000 } },
698  { 6, 0x989c,
699  { 0x00230018, 0x00230018, 0x00230018, 0x00230018, 0x00230018 } },
700  { 6, 0x989c,
701  { 0x00280000, 0x00280000, 0x00280060, 0x00280060, 0x00280060 } },
702  { 6, 0x989c,
703  { 0x005000c0, 0x005000c0, 0x005000c3, 0x005000c3, 0x005000c3 } },
704  { 6, 0x989c,
705  { 0x0004007f, 0x0004007f, 0x0004007f, 0x0004007f, 0x0004007f } },
706  { 6, 0x989c,
707  { 0x00000458, 0x00000458, 0x00000458, 0x00000458, 0x00000458 } },
708  { 6, 0x989c,
709  { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
710  { 6, 0x989c,
711  { 0x0000c000, 0x0000c000, 0x0000c000, 0x0000c000, 0x0000c000 } },
712  { 6, 0x98d8,
713  { 0x00400230, 0x00400230, 0x00400230, 0x00400230, 0x00400230 } },
714  { 7, 0x989c,
715  { 0x00006400, 0x00006400, 0x00006400, 0x00006400, 0x00006400 } },
716  { 7, 0x989c,
717  { 0x00000800, 0x00000800, 0x00000800, 0x00000800, 0x00000800 } },
718  { 7, 0x98cc,
719  { 0x0000000e, 0x0000000e, 0x0000000e, 0x0000000e, 0x0000000e } },
720 };
721 
722 
723 
724 /***************************\
725 * RF2315/RF2316 (Cobra SoC) *
726 \***************************/
727 
728 /* BANK 6 len pos col */
729 #define AR5K_RF2316_OB_2GHZ { 3, 178, 0 }
730 #define AR5K_RF2316_DB_2GHZ { 3, 175, 0 }
731 
732 static const struct ath5k_rf_reg rf_regs_2316[] = {
733  {6, AR5K_RF_OB_2GHZ, AR5K_RF2316_OB_2GHZ},
734  {6, AR5K_RF_DB_2GHZ, AR5K_RF2316_DB_2GHZ},
735 };
736 
737 /* Default mode specific settings */
738 static const struct ath5k_ini_rfbuffer rfb_2316[] = {
739  { 1, 0x98d4,
740  /* mode a/XR mode aTurbo mode b mode g mode gTurbo */
741  { 0x00000020, 0x00000020, 0x00000020, 0x00000020, 0x00000020 } },
742  { 2, 0x98d0,
743  { 0x02001408, 0x02011408, 0x02001408, 0x02001408, 0x02011408 } },
744  { 3, 0x98dc,
745  { 0x00a020c0, 0x00a020c0, 0x00e020c0, 0x00e020c0, 0x00e020c0 } },
746  { 6, 0x989c,
747  { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
748  { 6, 0x989c,
749  { 0xc0000000, 0xc0000000, 0xc0000000, 0xc0000000, 0xc0000000 } },
750  { 6, 0x989c,
751  { 0x0f000000, 0x0f000000, 0x0f000000, 0x0f000000, 0x0f000000 } },
752  { 6, 0x989c,
753  { 0x02000000, 0x02000000, 0x02000000, 0x02000000, 0x02000000 } },
754  { 6, 0x989c,
755  { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
756  { 6, 0x989c,
757  { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
758  { 6, 0x989c,
759  { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
760  { 6, 0x989c,
761  { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
762  { 6, 0x989c,
763  { 0xf8000000, 0xf8000000, 0xf8000000, 0xf8000000, 0xf8000000 } },
764  { 6, 0x989c,
765  { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
766  { 6, 0x989c,
767  { 0x95150000, 0x95150000, 0x95150000, 0x95150000, 0x95150000 } },
768  { 6, 0x989c,
769  { 0xc1000000, 0xc1000000, 0xc1000000, 0xc1000000, 0xc1000000 } },
770  { 6, 0x989c,
771  { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
772  { 6, 0x989c,
773  { 0x00080000, 0x00080000, 0x00080000, 0x00080000, 0x00080000 } },
774  { 6, 0x989c,
775  { 0x00d50000, 0x00d50000, 0x00d50000, 0x00d50000, 0x00d50000 } },
776  { 6, 0x989c,
777  { 0x000e0000, 0x000e0000, 0x000e0000, 0x000e0000, 0x000e0000 } },
778  { 6, 0x989c,
779  { 0x00dc0000, 0x00dc0000, 0x00dc0000, 0x00dc0000, 0x00dc0000 } },
780  { 6, 0x989c,
781  { 0x00770000, 0x00770000, 0x00770000, 0x00770000, 0x00770000 } },
782  { 6, 0x989c,
783  { 0x008a0000, 0x008a0000, 0x008a0000, 0x008a0000, 0x008a0000 } },
784  { 6, 0x989c,
785  { 0x10880000, 0x10880000, 0x10880000, 0x10880000, 0x10880000 } },
786  { 6, 0x989c,
787  { 0x008c0060, 0x008c0060, 0x008c0060, 0x008c0060, 0x008c0060 } },
788  { 6, 0x989c,
789  { 0x00a00000, 0x00a00000, 0x00a00080, 0x00a00080, 0x00a00080 } },
790  { 6, 0x989c,
791  { 0x00400000, 0x00400000, 0x0040000d, 0x0040000d, 0x0040000d } },
792  { 6, 0x989c,
793  { 0x00110400, 0x00110400, 0x00110400, 0x00110400, 0x00110400 } },
794  { 6, 0x989c,
795  { 0x00000060, 0x00000060, 0x00000060, 0x00000060, 0x00000060 } },
796  { 6, 0x989c,
797  { 0x00000001, 0x00000001, 0x00000001, 0x00000001, 0x00000001 } },
798  { 6, 0x989c,
799  { 0x00000b00, 0x00000b00, 0x00000b00, 0x00000b00, 0x00000b00 } },
800  { 6, 0x989c,
801  { 0x00000be8, 0x00000be8, 0x00000be8, 0x00000be8, 0x00000be8 } },
802  { 6, 0x98c0,
803  { 0x00010000, 0x00010000, 0x00010000, 0x00010000, 0x00010000 } },
804  { 7, 0x989c,
805  { 0x00006400, 0x00006400, 0x00006400, 0x00006400, 0x00006400 } },
806  { 7, 0x989c,
807  { 0x00000800, 0x00000800, 0x00000800, 0x00000800, 0x00000800 } },
808  { 7, 0x98cc,
809  { 0x0000000e, 0x0000000e, 0x0000000e, 0x0000000e, 0x0000000e } },
810 };
811 
812 
813 
814 /******************************\
815 * RF5413/RF5424 (Eagle/Condor) *
816 \******************************/
817 
818 /* BANK 6 len pos col */
819 #define AR5K_RF5413_OB_2GHZ { 3, 241, 0 }
820 #define AR5K_RF5413_DB_2GHZ { 3, 238, 0 }
821 
822 #define AR5K_RF5413_OB_5GHZ { 3, 247, 0 }
823 #define AR5K_RF5413_DB_5GHZ { 3, 244, 0 }
824 
825 #define AR5K_RF5413_PWD_ICLOBUF2G { 3, 131, 3 }
826 #define AR5K_RF5413_DERBY_CHAN_SEL_MODE { 1, 291, 2 }
827 
828 static const struct ath5k_rf_reg rf_regs_5413[] = {
829  {6, AR5K_RF_OB_2GHZ, AR5K_RF5413_OB_2GHZ},
830  {6, AR5K_RF_DB_2GHZ, AR5K_RF5413_DB_2GHZ},
831  {6, AR5K_RF_OB_5GHZ, AR5K_RF5413_OB_5GHZ},
832  {6, AR5K_RF_DB_5GHZ, AR5K_RF5413_DB_5GHZ},
833  {6, AR5K_RF_PWD_ICLOBUF_2G, AR5K_RF5413_PWD_ICLOBUF2G},
834  {6, AR5K_RF_DERBY_CHAN_SEL_MODE, AR5K_RF5413_DERBY_CHAN_SEL_MODE},
835 };
836 
837 /* Default mode specific settings */
838 static const struct ath5k_ini_rfbuffer rfb_5413[] = {
839  { 1, 0x98d4,
840  /* mode a/XR mode aTurbo mode b mode g mode gTurbo */
841  { 0x00000020, 0x00000020, 0x00000020, 0x00000020, 0x00000020 } },
842  { 2, 0x98d0,
843  { 0x00000008, 0x00000008, 0x00000008, 0x00000008, 0x00000008 } },
844  { 3, 0x98dc,
845  { 0x00a000c0, 0x00a000c0, 0x00e000c0, 0x00e000c0, 0x00e000c0 } },
846  { 6, 0x989c,
847  { 0x33000000, 0x33000000, 0x33000000, 0x33000000, 0x33000000 } },
848  { 6, 0x989c,
849  { 0x01000000, 0x01000000, 0x01000000, 0x01000000, 0x01000000 } },
850  { 6, 0x989c,
851  { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
852  { 6, 0x989c,
853  { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
854  { 6, 0x989c,
855  { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
856  { 6, 0x989c,
857  { 0x1f000000, 0x1f000000, 0x1f000000, 0x1f000000, 0x1f000000 } },
858  { 6, 0x989c,
859  { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
860  { 6, 0x989c,
861  { 0x00b80000, 0x00b80000, 0x00b80000, 0x00b80000, 0x00b80000 } },
862  { 6, 0x989c,
863  { 0x00b70000, 0x00b70000, 0x00b70000, 0x00b70000, 0x00b70000 } },
864  { 6, 0x989c,
865  { 0x00840000, 0x00840000, 0x00840000, 0x00840000, 0x00840000 } },
866  { 6, 0x989c,
867  { 0x00980000, 0x00980000, 0x00980000, 0x00980000, 0x00980000 } },
868  { 6, 0x989c,
869  { 0x00c00000, 0x00c00000, 0x00c00000, 0x00c00000, 0x00c00000 } },
870  { 6, 0x989c,
871  { 0x00ff0000, 0x00ff0000, 0x00ff0000, 0x00ff0000, 0x00ff0000 } },
872  { 6, 0x989c,
873  { 0x00ff0000, 0x00ff0000, 0x00ff0000, 0x00ff0000, 0x00ff0000 } },
874  { 6, 0x989c,
875  { 0x00ff0000, 0x00ff0000, 0x00ff0000, 0x00ff0000, 0x00ff0000 } },
876  { 6, 0x989c,
877  { 0x00ff0000, 0x00ff0000, 0x00ff0000, 0x00ff0000, 0x00ff0000 } },
878  { 6, 0x989c,
879  { 0x00d70000, 0x00d70000, 0x00d70000, 0x00d70000, 0x00d70000 } },
880  { 6, 0x989c,
881  { 0x00610000, 0x00610000, 0x00610000, 0x00610000, 0x00610000 } },
882  { 6, 0x989c,
883  { 0x00fe0000, 0x00fe0000, 0x00fe0000, 0x00fe0000, 0x00fe0000 } },
884  { 6, 0x989c,
885  { 0x00de0000, 0x00de0000, 0x00de0000, 0x00de0000, 0x00de0000 } },
886  { 6, 0x989c,
887  { 0x007f0000, 0x007f0000, 0x007f0000, 0x007f0000, 0x007f0000 } },
888  { 6, 0x989c,
889  { 0x043d0000, 0x043d0000, 0x043d0000, 0x043d0000, 0x043d0000 } },
890  { 6, 0x989c,
891  { 0x00770000, 0x00770000, 0x00770000, 0x00770000, 0x00770000 } },
892  { 6, 0x989c,
893  { 0x00440000, 0x00440000, 0x00440000, 0x00440000, 0x00440000 } },
894  { 6, 0x989c,
895  { 0x00980000, 0x00980000, 0x00980000, 0x00980000, 0x00980000 } },
896  { 6, 0x989c,
897  { 0x00100080, 0x00100080, 0x00100080, 0x00100080, 0x00100080 } },
898  { 6, 0x989c,
899  { 0x0005c034, 0x0005c034, 0x0005c034, 0x0005c034, 0x0005c034 } },
900  { 6, 0x989c,
901  { 0x003100f0, 0x003100f0, 0x003100f0, 0x003100f0, 0x003100f0 } },
902  { 6, 0x989c,
903  { 0x000c011f, 0x000c011f, 0x000c011f, 0x000c011f, 0x000c011f } },
904  { 6, 0x989c,
905  { 0x00510040, 0x00510040, 0x00510040, 0x00510040, 0x00510040 } },
906  { 6, 0x989c,
907  { 0x005000da, 0x005000da, 0x005000da, 0x005000da, 0x005000da } },
908  { 6, 0x989c,
909  { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
910  { 6, 0x989c,
911  { 0x00004044, 0x00004044, 0x00004044, 0x00004044, 0x00004044 } },
912  { 6, 0x989c,
913  { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
914  { 6, 0x989c,
915  { 0x000060c0, 0x000060c0, 0x000060c0, 0x000060c0, 0x000060c0 } },
916  { 6, 0x989c,
917  { 0x00002c00, 0x00002c00, 0x00003600, 0x00003600, 0x00002c00 } },
918  { 6, 0x98c8,
919  { 0x00000403, 0x00000403, 0x00040403, 0x00040403, 0x00040403 } },
920  { 7, 0x989c,
921  { 0x00006400, 0x00006400, 0x00006400, 0x00006400, 0x00006400 } },
922  { 7, 0x989c,
923  { 0x00000800, 0x00000800, 0x00000800, 0x00000800, 0x00000800 } },
924  { 7, 0x98cc,
925  { 0x0000000e, 0x0000000e, 0x0000000e, 0x0000000e, 0x0000000e } },
926 };
927 
928 
929 
930 /***************************\
931 * RF2425/RF2417 (Swan/Nala) *
932 * AR2317 (Spider SoC) *
933 \***************************/
934 
935 /* BANK 6 len pos col */
936 #define AR5K_RF2425_OB_2GHZ { 3, 193, 0 }
937 #define AR5K_RF2425_DB_2GHZ { 3, 190, 0 }
938 
939 static const struct ath5k_rf_reg rf_regs_2425[] = {
940  {6, AR5K_RF_OB_2GHZ, AR5K_RF2425_OB_2GHZ},
941  {6, AR5K_RF_DB_2GHZ, AR5K_RF2425_DB_2GHZ},
942 };
943 
944 /* Default mode specific settings
945  * XXX: a/aTurbo ?
946  */
947 static const struct ath5k_ini_rfbuffer rfb_2425[] = {
948  { 1, 0x98d4,
949  /* mode a/XR mode aTurbo mode b mode g mode gTurbo */
950  { 0x00000020, 0x00000020, 0x00000020, 0x00000020, 0x00000020 } },
951  { 2, 0x98d0,
952  { 0x02001408, 0x02001408, 0x02001408, 0x02001408, 0x02001408 } },
953  { 3, 0x98dc,
954  { 0x00a020c0, 0x00a020c0, 0x00e020c0, 0x00e020c0, 0x00e020c0 } },
955  { 6, 0x989c,
956  { 0x10000000, 0x10000000, 0x10000000, 0x10000000, 0x10000000 } },
957  { 6, 0x989c,
958  { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
959  { 6, 0x989c,
960  { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
961  { 6, 0x989c,
962  { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
963  { 6, 0x989c,
964  { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
965  { 6, 0x989c,
966  { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
967  { 6, 0x989c,
968  { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
969  { 6, 0x989c,
970  { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
971  { 6, 0x989c,
972  { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
973  { 6, 0x989c,
974  { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
975  { 6, 0x989c,
976  { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
977  { 6, 0x989c,
978  { 0x002a0000, 0x002a0000, 0x002a0000, 0x002a0000, 0x002a0000 } },
979  { 6, 0x989c,
980  { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
981  { 6, 0x989c,
982  { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
983  { 6, 0x989c,
984  { 0x00100000, 0x00100000, 0x00100000, 0x00100000, 0x00100000 } },
985  { 6, 0x989c,
986  { 0x00020000, 0x00020000, 0x00020000, 0x00020000, 0x00020000 } },
987  { 6, 0x989c,
988  { 0x00730000, 0x00730000, 0x00730000, 0x00730000, 0x00730000 } },
989  { 6, 0x989c,
990  { 0x00f80000, 0x00f80000, 0x00f80000, 0x00f80000, 0x00f80000 } },
991  { 6, 0x989c,
992  { 0x00e70000, 0x00e70000, 0x00e70000, 0x00e70000, 0x00e70000 } },
993  { 6, 0x989c,
994  { 0x00140000, 0x00140000, 0x00140000, 0x00140000, 0x00140000 } },
995  { 6, 0x989c,
996  { 0x00910040, 0x00910040, 0x00910040, 0x00910040, 0x00910040 } },
997  { 6, 0x989c,
998  { 0x0007001a, 0x0007001a, 0x0007001a, 0x0007001a, 0x0007001a } },
999  { 6, 0x989c,
1000  { 0x00410000, 0x00410000, 0x00410000, 0x00410000, 0x00410000 } },
1001  { 6, 0x989c,
1002  { 0x00810000, 0x00810000, 0x00810060, 0x00810060, 0x00810060 } },
1003  { 6, 0x989c,
1004  { 0x00020800, 0x00020800, 0x00020803, 0x00020803, 0x00020803 } },
1005  { 6, 0x989c,
1006  { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
1007  { 6, 0x989c,
1008  { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
1009  { 6, 0x989c,
1010  { 0x00001660, 0x00001660, 0x00001660, 0x00001660, 0x00001660 } },
1011  { 6, 0x989c,
1012  { 0x00001688, 0x00001688, 0x00001688, 0x00001688, 0x00001688 } },
1013  { 6, 0x98c4,
1014  { 0x00000001, 0x00000001, 0x00000001, 0x00000001, 0x00000001 } },
1015  { 7, 0x989c,
1016  { 0x00006400, 0x00006400, 0x00006400, 0x00006400, 0x00006400 } },
1017  { 7, 0x989c,
1018  { 0x00000800, 0x00000800, 0x00000800, 0x00000800, 0x00000800 } },
1019  { 7, 0x98cc,
1020  { 0x0000000e, 0x0000000e, 0x0000000e, 0x0000000e, 0x0000000e } },
1021 };
1022 
1023 /*
1024  * TODO: Handle the few differences with swan during
1025  * bank modification and get rid of this
1026  */
1027 static const struct ath5k_ini_rfbuffer rfb_2317[] = {
1028  { 1, 0x98d4,
1029  /* mode a/XR mode aTurbo mode b mode g mode gTurbo */
1030  { 0x00000020, 0x00000020, 0x00000020, 0x00000020, 0x00000020 } },
1031  { 2, 0x98d0,
1032  { 0x02001408, 0x02011408, 0x02001408, 0x02001408, 0x02011408 } },
1033  { 3, 0x98dc,
1034  { 0x00a020c0, 0x00a020c0, 0x00e020c0, 0x00e020c0, 0x00e020c0 } },
1035  { 6, 0x989c,
1036  { 0x10000000, 0x10000000, 0x10000000, 0x10000000, 0x10000000 } },
1037  { 6, 0x989c,
1038  { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
1039  { 6, 0x989c,
1040  { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
1041  { 6, 0x989c,
1042  { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
1043  { 6, 0x989c,
1044  { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
1045  { 6, 0x989c,
1046  { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
1047  { 6, 0x989c,
1048  { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
1049  { 6, 0x989c,
1050  { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
1051  { 6, 0x989c,
1052  { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
1053  { 6, 0x989c,
1054  { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
1055  { 6, 0x989c,
1056  { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
1057  { 6, 0x989c,
1058  { 0x002a0000, 0x002a0000, 0x002a0000, 0x002a0000, 0x002a0000 } },
1059  { 6, 0x989c,
1060  { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
1061  { 6, 0x989c,
1062  { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
1063  { 6, 0x989c,
1064  { 0x00100000, 0x00100000, 0x00100000, 0x00100000, 0x00100000 } },
1065  { 6, 0x989c,
1066  { 0x00020000, 0x00020000, 0x00020000, 0x00020000, 0x00020000 } },
1067  { 6, 0x989c,
1068  { 0x00730000, 0x00730000, 0x00730000, 0x00730000, 0x00730000 } },
1069  { 6, 0x989c,
1070  { 0x00f80000, 0x00f80000, 0x00f80000, 0x00f80000, 0x00f80000 } },
1071  { 6, 0x989c,
1072  { 0x00e70000, 0x00e70000, 0x00e70000, 0x00e70000, 0x00e70000 } },
1073  { 6, 0x989c,
1074  { 0x00140100, 0x00140100, 0x00140100, 0x00140100, 0x00140100 } },
1075  { 6, 0x989c,
1076  { 0x00910040, 0x00910040, 0x00910040, 0x00910040, 0x00910040 } },
1077  { 6, 0x989c,
1078  { 0x0007001a, 0x0007001a, 0x0007001a, 0x0007001a, 0x0007001a } },
1079  { 6, 0x989c,
1080  { 0x00410000, 0x00410000, 0x00410000, 0x00410000, 0x00410000 } },
1081  { 6, 0x989c,
1082  { 0x00810000, 0x00810000, 0x00810060, 0x00810060, 0x00810060 } },
1083  { 6, 0x989c,
1084  { 0x00020800, 0x00020800, 0x00020803, 0x00020803, 0x00020803 } },
1085  { 6, 0x989c,
1086  { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
1087  { 6, 0x989c,
1088  { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
1089  { 6, 0x989c,
1090  { 0x00001660, 0x00001660, 0x00001660, 0x00001660, 0x00001660 } },
1091  { 6, 0x989c,
1092  { 0x00009688, 0x00009688, 0x00009688, 0x00009688, 0x00009688 } },
1093  { 6, 0x98c4,
1094  { 0x00000001, 0x00000001, 0x00000001, 0x00000001, 0x00000001 } },
1095  { 7, 0x989c,
1096  { 0x00006400, 0x00006400, 0x00006400, 0x00006400, 0x00006400 } },
1097  { 7, 0x989c,
1098  { 0x00000800, 0x00000800, 0x00000800, 0x00000800, 0x00000800 } },
1099  { 7, 0x98cc,
1100  { 0x0000000e, 0x0000000e, 0x0000000e, 0x0000000e, 0x0000000e } },
1101 };
1102 
1103 /*
1104  * TODO: Handle the few differences with swan during
1105  * bank modification and get rid of this
1106  * XXX: a/aTurbo ?
1107  */
1108 static const struct ath5k_ini_rfbuffer rfb_2417[] = {
1109  { 1, 0x98d4,
1110  /* mode a/XR mode aTurbo mode b mode g mode gTurbo */
1111  { 0x00000020, 0x00000020, 0x00000020, 0x00000020, 0x00000020 } },
1112  { 2, 0x98d0,
1113  { 0x02001408, 0x02001408, 0x02001408, 0x02001408, 0x02001408 } },
1114  { 3, 0x98dc,
1115  { 0x00a020c0, 0x00a020c0, 0x00e020c0, 0x00e020c0, 0x00e020c0 } },
1116  { 6, 0x989c,
1117  { 0x10000000, 0x10000000, 0x10000000, 0x10000000, 0x10000000 } },
1118  { 6, 0x989c,
1119  { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
1120  { 6, 0x989c,
1121  { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
1122  { 6, 0x989c,
1123  { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
1124  { 6, 0x989c,
1125  { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
1126  { 6, 0x989c,
1127  { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
1128  { 6, 0x989c,
1129  { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
1130  { 6, 0x989c,
1131  { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
1132  { 6, 0x989c,
1133  { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
1134  { 6, 0x989c,
1135  { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
1136  { 6, 0x989c,
1137  { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
1138  { 6, 0x989c,
1139  { 0x002a0000, 0x002a0000, 0x002a0000, 0x002a0000, 0x002a0000 } },
1140  { 6, 0x989c,
1141  { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
1142  { 6, 0x989c,
1143  { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
1144  { 6, 0x989c,
1145  { 0x00100000, 0x00100000, 0x00100000, 0x00100000, 0x00100000 } },
1146  { 6, 0x989c,
1147  { 0x00020000, 0x00020000, 0x00020000, 0x00020000, 0x00020000 } },
1148  { 6, 0x989c,
1149  { 0x00730000, 0x00730000, 0x00730000, 0x00730000, 0x00730000 } },
1150  { 6, 0x989c,
1151  { 0x00f80000, 0x00f80000, 0x00f80000, 0x00f80000, 0x00f80000 } },
1152  { 6, 0x989c,
1153  { 0x00e70000, 0x00e70000, 0x80e70000, 0x80e70000, 0x00e70000 } },
1154  { 6, 0x989c,
1155  { 0x00140000, 0x00140000, 0x00140000, 0x00140000, 0x00140000 } },
1156  { 6, 0x989c,
1157  { 0x00910040, 0x00910040, 0x00910040, 0x00910040, 0x00910040 } },
1158  { 6, 0x989c,
1159  { 0x0007001a, 0x0007001a, 0x0207001a, 0x0207001a, 0x0007001a } },
1160  { 6, 0x989c,
1161  { 0x00410000, 0x00410000, 0x00410000, 0x00410000, 0x00410000 } },
1162  { 6, 0x989c,
1163  { 0x00810000, 0x00810000, 0x00810060, 0x00810060, 0x00810060 } },
1164  { 6, 0x989c,
1165  { 0x00020800, 0x00020800, 0x00020803, 0x00020803, 0x00020803 } },
1166  { 6, 0x989c,
1167  { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
1168  { 6, 0x989c,
1169  { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
1170  { 6, 0x989c,
1171  { 0x00001660, 0x00001660, 0x00001660, 0x00001660, 0x00001660 } },
1172  { 6, 0x989c,
1173  { 0x00001688, 0x00001688, 0x00001688, 0x00001688, 0x00001688 } },
1174  { 6, 0x98c4,
1175  { 0x00000001, 0x00000001, 0x00000001, 0x00000001, 0x00000001 } },
1176  { 7, 0x989c,
1177  { 0x00006400, 0x00006400, 0x00006400, 0x00006400, 0x00006400 } },
1178  { 7, 0x989c,
1179  { 0x00000800, 0x00000800, 0x00000800, 0x00000800, 0x00000800 } },
1180  { 7, 0x98cc,
1181  { 0x0000000e, 0x0000000e, 0x0000000e, 0x0000000e, 0x0000000e } },
1182 };
u16
uint16_t u16
Definition: stdint.h:22
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Definition: rfbuffer.h:644
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Definition: rfbuffer.h:63
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Definition: rfbuffer.h:729
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Definition: rfbuffer.h:480
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Definition: rfbuffer.h:72
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Definition: rfbuffer.h:310
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Definition: rfbuffer.h:464
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Definition: rfbuffer.h:730
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Definition: rfbuffer.h:471
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Definition: rfbuffer.h:454
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Definition: rfbuffer.h:939
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Definition: rfbuffer.h:74
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#define AR5K_RF5112A_LOW_VC_CP
Definition: rfbuffer.h:472
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Definition: rfbuffer.h:286
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Definition: rfbuffer.h:838
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Definition: rfbuffer.h:470
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Definition: rfbuffer.h:1108
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Definition: rfbuffer.h:822
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Definition: rfbuffer.h:819
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Definition: rfbuffer.h:477
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Definition: rfbuffer.h:463
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Definition: rfbuffer.h:140
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Definition: rfbuffer.h:301
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Definition: rfbuffer.h:823
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Definition: rfbuffer.h:55
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Definition: rfbuffer.h:295
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Definition: rfbuffer.h:73
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Definition: rfbuffer.h:157
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Definition: rfbuffer.h:828
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struct ath5k_rfb_field field
Definition: rfbuffer.h:75
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Definition: rfbuffer.h:285
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Definition: rfbuffer.h:289
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Definition: rfbuffer.h:296
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Definition: rfbuffer.h:738
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Definition: rfbuffer.h:64
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Definition: rfbuffer.h:338
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Definition: rfbuffer.h:476
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Definition: rfbuffer.h:732
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Definition: rfbuffer.h:149
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Definition: rfbuffer.h:947
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Definition: rfbuffer.h:66
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Definition: rfbuffer.h:467
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Definition: rfbuffer.h:161
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Definition: rfbuffer.h:152
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Definition: rfbuffer.h:652
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Definition: rfbuffer.h:54
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#define AR5K_RF5112A_XPD_SEL
Definition: rfbuffer.h:462
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Definition: rfbuffer.h:518
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Definition: rfbuffer.h:459
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Definition: rfbuffer.h:52
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Definition: rfbuffer.h:53
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Definition: rfbuffer.h:453
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Definition: rfbuffer.h:308
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Definition: rfbuffer.h:65
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Definition: rfbuffer.h:288
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Definition: stdint.h:20
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Definition: stdint.h:24
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Definition: rfbuffer.h:825
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Definition: rfbuffer.h:180
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