13 #define RHINE_BAR_SIZE 256 16 #define RHINE_TIMEOUT_US 10000 26 #define RHINE_DES0_OWN (1 << 31) 27 #define RHINE_DES1_IC (1 << 23) 28 #define RHINE_TDES1_EDP (1 << 22) 29 #define RHINE_TDES1_STP (1 << 21) 30 #define RHINE_TDES1_TCPCK (1 << 20) 31 #define RHINE_TDES1_UDPCK (1 << 19) 32 #define RHINE_TDES1_IPCK (1 << 18) 33 #define RHINE_TDES1_TAG (1 << 17) 34 #define RHINE_TDES1_CRC (1 << 16) 35 #define RHINE_DES1_CHAIN (1 << 15) 36 #define RHINE_DES1_SIZE(_x) ((_x) & 0x7ff) 37 #define RHINE_DES0_GETSIZE(_x) (((_x) >> 16) & 0x7ff) 39 #define RHINE_RDES0_RXOK (1 << 15) 40 #define RHINE_RDES0_VIDHIT (1 << 14) 41 #define RHINE_RDES0_MAR (1 << 13) 42 #define RHINE_RDES0_BAR (1 << 12) 43 #define RHINE_RDES0_PHY (1 << 11) 44 #define RHINE_RDES0_CHN (1 << 10) 45 #define RHINE_RDES0_STP (1 << 9) 46 #define RHINE_RDES0_EDP (1 << 8) 47 #define RHINE_RDES0_BUFF (1 << 7) 48 #define RHINE_RDES0_FRAG (1 << 6) 49 #define RHINE_RDES0_RUNT (1 << 5) 50 #define RHINE_RDES0_LONG (1 << 4) 51 #define RHINE_RDES0_FOV (1 << 3) 52 #define RHINE_RDES0_FAE (1 << 2) 53 #define RHINE_RDES0_CRCE (1 << 1) 54 #define RHINE_RDES0_RERR (1 << 0) 56 #define RHINE_TDES0_TERR (1 << 15) 57 #define RHINE_TDES0_UDF (1 << 11) 58 #define RHINE_TDES0_CRS (1 << 10) 59 #define RHINE_TDES0_OWC (1 << 9) 60 #define RHINE_TDES0_ABT (1 << 8) 61 #define RHINE_TDES0_CDH (1 << 7) 62 #define RHINE_TDES0_COLS (1 << 4) 63 #define RHINE_TDES0_NCR(_x) ((_x) & 0xf) 65 #define RHINE_RING_ALIGN 4 68 #define RHINE_RXDESC_NUM 4 69 #define RHINE_TXDESC_NUM 8 70 #define RHINE_RX_MAX_LEN 1536 73 #define RHINE_MAC 0x00 76 #define RHINE_RCR 0x06 77 #define RHINE_RCR_FIFO_TRSH(_x) (((_x) & 0x7) << 5) 78 #define RHINE_RCR_PHYS_ACCEPT (1 << 4) 79 #define RHINE_RCR_BCAST_ACCEPT (1 << 3) 80 #define RHINE_RCR_MCAST_ACCEPT (1 << 2) 81 #define RHINE_RCR_RUNT_ACCEPT (1 << 1) 82 #define RHINE_RCR_ERR_ACCEPT (1 << 0) 85 #define RHINE_TCR 0x07 86 #define RHINE_TCR_LOOPBACK(_x) (((_x) & 0x3) << 1) 87 #define RHINE_TCR_TAGGING (1 << 0) 90 #define RHINE_CR0 0x08 91 #define RHINE_CR0_RXSTART (1 << 6) 92 #define RHINE_CR0_TXSTART (1 << 5) 93 #define RHINE_CR0_TXEN (1 << 4) 94 #define RHINE_CR0_RXEN (1 << 3) 95 #define RHINE_CR0_STOPNIC (1 << 2) 96 #define RHINE_CR0_STARTNIC (1 << 1) 99 #define RHINE_CR1 0x09 100 #define RHINE_CR1_RESET (1 << 7) 101 #define RHINE_CR1_RXPOLL (1 << 6) 102 #define RHINE_CR1_TXPOLL (1 << 5) 103 #define RHINE_CR1_AUTOPOLL (1 << 3) 104 #define RHINE_CR1_FDX (1 << 2) 105 #define RIHNE_CR1_ACCUNI (1 << 1) 108 #define RHINE_TXQUEUE_WAKE 0x0a 111 #define RHINE_ISR0 0x0c 112 #define RHINE_ISR0_MIBOVFL (1 << 7) 113 #define RHINE_ISR0_PCIERR (1 << 6) 114 #define RHINE_ISR0_RXRINGERR (1 << 5) 115 #define RHINE_ISR0_TXRINGERR (1 << 4) 116 #define RHINE_ISR0_TXERR (1 << 3) 117 #define RHINE_ISR0_RXERR (1 << 2) 118 #define RHINE_ISR0_TXDONE (1 << 1) 119 #define RHINE_ISR0_RXDONE (1 << 0) 122 #define RHINE_ISR1 0x0d 123 #define RHINE_ISR1_GPI (1 << 7) 124 #define RHINE_ISR1_PORTSTATE (1 << 6) 125 #define RHINE_ISR1_TXABORT (1 << 5) 126 #define RHINE_ISR1_RXNOBUF (1 << 4) 127 #define RHINE_ISR1_RXFIFOOVFL (1 << 3) 128 #define RHINE_ISR1_RXFIFOUNFL (1 << 2) 129 #define RHINE_ISR1_TXFIFOUNFL (1 << 1) 130 #define RHINE_ISR1_EARLYRX (1 << 0) 133 #define RHINE_IMR0 0x0e 136 #define RHINE_IMR1 0x0f 139 #define RHINE_RXQUEUE_BASE 0x18 142 #define RHINE_TXQUEUE_BASE 0x1c 145 #define RHINE_MII_CFG 0x6c 148 #define RHINE_MII_SR 0x6d 149 #define RHINE_MII_SR_PHYRST (1 << 7) 150 #define RHINE_MII_SR_LINKNWAY (1 << 4) 151 #define RHINE_MII_SR_PHYERR (1 << 3) 152 #define RHINE_MII_SR_DUPLEX (1 << 2) 153 #define RHINE_MII_SR_LINKPOLL (1 << 1) 154 #define RHINE_MII_SR_LINKSPD (1 << 0) 157 #define RHINE_MII_BCR0 0x6e 160 #define RHINE_MII_BCR1 0x6f 163 #define RHINE_MII_CR 0x70 164 #define RHINE_MII_CR_AUTOPOLL (1 << 7) 165 #define RHINE_MII_CR_RDEN (1 << 6) 166 #define RHINE_MII_CR_WREN (1 << 5) 167 #define RHINE_MII_CR_DIRECT (1 << 4) 168 #define RHINE_MII_CR_MDIOOUT (1 << 3) 171 #define RHINE_MII_ADDR 0x71 172 #define RHINE_MII_ADDR_MSRCEN (1 << 6) 173 #define RHINE_MII_ADDR_MDONE (1 << 5) 176 #define RHINE_MII_RDWR 0x72 179 #define RHINE_EEPROM_CTRL 0x74 180 #define RHINE_EEPROM_CTRL_STATUS (1 << 7) 181 #define RHINE_EEPROM_CTRL_RELOAD (1 << 5) 184 #define RHINE_CHIPCFG_A 0x78 186 #define RHINE_CHIPCFG_A_MMIO (1 << 5) 189 #define RHINE_CHIPCFG_B 0x79 192 #define RHINE_CHIPCFG_C 0x7a 195 #define RHINE_CHIPCFG_D 0x7b 197 #define RHINE_CHIPCFG_D_MMIO (1 << 7) 199 #define RHINE_REVISION_OLD 0x20 unsigned long ioaddr
I/O address (some PIO access is always required)
unsigned int cons
Consumer index.
unsigned int reg
Register address.
struct rhine_ring __attribute__
FILE_LICENCE(GPL2_OR_LATER)
A VIA Rhine descriptor ring.
#define RHINE_RXDESC_NUM
Rhine descriptor rings sizes.
struct mii_interface mdio
MII interface.
A VIA Rhine network card.
struct mii_device mii
MII device.
struct io_buffer * rx_iobuf[RHINE_RXDESC_NUM]
Receive I/O buffers.
static unsigned int count
struct rhine_ring rx
Receive descriptor ring.
unsigned int count
Number of descriptors.
uint8_t cr1
Cached value of CR1 (to avoid read-modify-write on fast path)
struct rhine_descriptor * desc
Descriptors.
unsigned int prod
Producer index.
struct rhine_ring tx
Transmit descriptor ring.
static unsigned int unsigned int reg