iPXE
rhine.h
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1 #ifndef _RHINE_H
2 #define _RHINE_H
3 
4 /** @file
5  *
6  * VIA Rhine network driver
7  *
8  */
9 
10 FILE_LICENCE ( GPL2_OR_LATER );
11 
12 /** Rhine BAR size */
13 #define RHINE_BAR_SIZE 256
14 
15 /** Default timeout */
16 #define RHINE_TIMEOUT_US 10000
17 
18 /** Rhine descriptor format */
24 } __attribute__ (( packed ));
25 
26 #define RHINE_DES0_OWN (1 << 31) /*< Owned descriptor */
27 #define RHINE_DES1_IC (1 << 23) /*< Generate interrupt */
28 #define RHINE_TDES1_EDP (1 << 22) /*< End of packet */
29 #define RHINE_TDES1_STP (1 << 21) /*< Start of packet */
30 #define RHINE_TDES1_TCPCK (1 << 20) /*< HW TCP checksum */
31 #define RHINE_TDES1_UDPCK (1 << 19) /*< HW UDP checksum */
32 #define RHINE_TDES1_IPCK (1 << 18) /*< HW IP checksum */
33 #define RHINE_TDES1_TAG (1 << 17) /*< Tagged frame */
34 #define RHINE_TDES1_CRC (1 << 16) /*< No CRC */
35 #define RHINE_DES1_CHAIN (1 << 15) /*< Chained descriptor */
36 #define RHINE_DES1_SIZE(_x) ((_x) & 0x7ff) /*< Frame size */
37 #define RHINE_DES0_GETSIZE(_x) (((_x) >> 16) & 0x7ff)
38 
39 #define RHINE_RDES0_RXOK (1 << 15)
40 #define RHINE_RDES0_VIDHIT (1 << 14)
41 #define RHINE_RDES0_MAR (1 << 13)
42 #define RHINE_RDES0_BAR (1 << 12)
43 #define RHINE_RDES0_PHY (1 << 11)
44 #define RHINE_RDES0_CHN (1 << 10)
45 #define RHINE_RDES0_STP (1 << 9)
46 #define RHINE_RDES0_EDP (1 << 8)
47 #define RHINE_RDES0_BUFF (1 << 7)
48 #define RHINE_RDES0_FRAG (1 << 6)
49 #define RHINE_RDES0_RUNT (1 << 5)
50 #define RHINE_RDES0_LONG (1 << 4)
51 #define RHINE_RDES0_FOV (1 << 3)
52 #define RHINE_RDES0_FAE (1 << 2)
53 #define RHINE_RDES0_CRCE (1 << 1)
54 #define RHINE_RDES0_RERR (1 << 0)
55 
56 #define RHINE_TDES0_TERR (1 << 15)
57 #define RHINE_TDES0_UDF (1 << 11)
58 #define RHINE_TDES0_CRS (1 << 10)
59 #define RHINE_TDES0_OWC (1 << 9)
60 #define RHINE_TDES0_ABT (1 << 8)
61 #define RHINE_TDES0_CDH (1 << 7)
62 #define RHINE_TDES0_COLS (1 << 4)
63 #define RHINE_TDES0_NCR(_x) ((_x) & 0xf)
64 
65 #define RHINE_RING_ALIGN 4
66 
67 /** Rhine descriptor rings sizes */
68 #define RHINE_RXDESC_NUM 4
69 #define RHINE_TXDESC_NUM 8
70 #define RHINE_RX_MAX_LEN 1536
71 
72 /** Rhine MAC address registers */
73 #define RHINE_MAC 0x00
74 
75 /** Receive control register */
76 #define RHINE_RCR 0x06
77 #define RHINE_RCR_FIFO_TRSH(_x) (((_x) & 0x7) << 5) /*< RX FIFO threshold */
78 #define RHINE_RCR_PHYS_ACCEPT (1 << 4) /*< Accept matching PA */
79 #define RHINE_RCR_BCAST_ACCEPT (1 << 3) /*< Accept broadcast */
80 #define RHINE_RCR_MCAST_ACCEPT (1 << 2) /*< Accept multicast */
81 #define RHINE_RCR_RUNT_ACCEPT (1 << 1) /*< Accept runt frames */
82 #define RHINE_RCR_ERR_ACCEPT (1 << 0) /*< Accept erroneous frames */
83 
84 /** Transmit control register */
85 #define RHINE_TCR 0x07
86 #define RHINE_TCR_LOOPBACK(_x) (((_x) & 0x3) << 1) /*< Transmit loop mode */
87 #define RHINE_TCR_TAGGING (1 << 0) /*< 802.1P/Q packet tagging */
88 
89 /** Command 0 register */
90 #define RHINE_CR0 0x08
91 #define RHINE_CR0_RXSTART (1 << 6)
92 #define RHINE_CR0_TXSTART (1 << 5)
93 #define RHINE_CR0_TXEN (1 << 4) /*< Transmit enable */
94 #define RHINE_CR0_RXEN (1 << 3) /*< Receive enable */
95 #define RHINE_CR0_STOPNIC (1 << 2) /*< Stop NIC */
96 #define RHINE_CR0_STARTNIC (1 << 1) /*< Start NIC */
97 
98 /** Command 1 register */
99 #define RHINE_CR1 0x09
100 #define RHINE_CR1_RESET (1 << 7) /*< Software reset */
101 #define RHINE_CR1_RXPOLL (1 << 6) /*< Receive poll demand */
102 #define RHINE_CR1_TXPOLL (1 << 5) /*< Xmit poll demand */
103 #define RHINE_CR1_AUTOPOLL (1 << 3) /*< Disable autopoll */
104 #define RHINE_CR1_FDX (1 << 2) /*< Full duplex */
105 #define RIHNE_CR1_ACCUNI (1 << 1) /*< Disable accept unicast */
106 
107 /** Transmit queue wake register */
108 #define RHINE_TXQUEUE_WAKE 0x0a
109 
110 /** Interrupt service 0 */
111 #define RHINE_ISR0 0x0c
112 #define RHINE_ISR0_MIBOVFL (1 << 7)
113 #define RHINE_ISR0_PCIERR (1 << 6)
114 #define RHINE_ISR0_RXRINGERR (1 << 5)
115 #define RHINE_ISR0_TXRINGERR (1 << 4)
116 #define RHINE_ISR0_TXERR (1 << 3)
117 #define RHINE_ISR0_RXERR (1 << 2)
118 #define RHINE_ISR0_TXDONE (1 << 1)
119 #define RHINE_ISR0_RXDONE (1 << 0)
120 
121 /** Interrupt service 1 */
122 #define RHINE_ISR1 0x0d
123 #define RHINE_ISR1_GPI (1 << 7)
124 #define RHINE_ISR1_PORTSTATE (1 << 6)
125 #define RHINE_ISR1_TXABORT (1 << 5)
126 #define RHINE_ISR1_RXNOBUF (1 << 4)
127 #define RHINE_ISR1_RXFIFOOVFL (1 << 3)
128 #define RHINE_ISR1_RXFIFOUNFL (1 << 2)
129 #define RHINE_ISR1_TXFIFOUNFL (1 << 1)
130 #define RHINE_ISR1_EARLYRX (1 << 0)
131 
132 /** Interrupt enable mask register 0 */
133 #define RHINE_IMR0 0x0e
134 
135 /** Interrupt enable mask register 1 */
136 #define RHINE_IMR1 0x0f
137 
138 /** RX queue descriptor base address */
139 #define RHINE_RXQUEUE_BASE 0x18
140 
141 /** TX queue 0 descriptor base address */
142 #define RHINE_TXQUEUE_BASE 0x1c
143 
144 /** MII configuration */
145 #define RHINE_MII_CFG 0x6c
146 
147 /** MII status register */
148 #define RHINE_MII_SR 0x6d
149 #define RHINE_MII_SR_PHYRST (1 << 7) /*< PHY reset */
150 #define RHINE_MII_SR_LINKNWAY (1 << 4) /*< Link status after N-Way */
151 #define RHINE_MII_SR_PHYERR (1 << 3) /*< PHY device error */
152 #define RHINE_MII_SR_DUPLEX (1 << 2) /*< Duplex mode after N-Way */
153 #define RHINE_MII_SR_LINKPOLL (1 << 1) /*< Link status after poll */
154 #define RHINE_MII_SR_LINKSPD (1 << 0) /*< Link speed after N-Way */
155 
156 /** MII bus control 0 register */
157 #define RHINE_MII_BCR0 0x6e
158 
159 /** MII bus control 1 register */
160 #define RHINE_MII_BCR1 0x6f
161 
162 /** MII control register */
163 #define RHINE_MII_CR 0x70
164 #define RHINE_MII_CR_AUTOPOLL (1 << 7) /*< MII auto polling */
165 #define RHINE_MII_CR_RDEN (1 << 6) /*< PHY read enable */
166 #define RHINE_MII_CR_WREN (1 << 5) /*< PHY write enable */
167 #define RHINE_MII_CR_DIRECT (1 << 4) /*< Direct programming mode */
168 #define RHINE_MII_CR_MDIOOUT (1 << 3) /*< MDIO output enable */
169 
170 /** MII port address */
171 #define RHINE_MII_ADDR 0x71
172 #define RHINE_MII_ADDR_MSRCEN (1 << 6)
173 #define RHINE_MII_ADDR_MDONE (1 << 5)
174 
175 /** MII read/write data */
176 #define RHINE_MII_RDWR 0x72
177 
178 /** EERPOM control/status register */
179 #define RHINE_EEPROM_CTRL 0x74
180 #define RHINE_EEPROM_CTRL_STATUS (1 << 7) /*< EEPROM status */
181 #define RHINE_EEPROM_CTRL_RELOAD (1 << 5) /*< EEPROM reload */
182 
183 /** Chip configuration A */
184 #define RHINE_CHIPCFG_A 0x78
185 /* MMIO enable. Only valid for Rhine I. Reserved on later boards */
186 #define RHINE_CHIPCFG_A_MMIO (1 << 5)
187 
188 /** Chip configuration B */
189 #define RHINE_CHIPCFG_B 0x79
190 
191 /** Chip configuation C */
192 #define RHINE_CHIPCFG_C 0x7a
193 
194 /** Chip configuration D */
195 #define RHINE_CHIPCFG_D 0x7b
196 /* MMIO enable. Only valid on Rhine II and later. GPIOEN on Rhine I */
197 #define RHINE_CHIPCFG_D_MMIO (1 << 7)
198 
199 #define RHINE_REVISION_OLD 0x20
200 
201 /** A VIA Rhine descriptor ring */
202 struct rhine_ring {
203  /** Descriptors */
205  /** Producer index */
206  unsigned int prod;
207  /** Consumer index */
208  unsigned int cons;
209 
210  /** Number of descriptors */
211  unsigned int count;
212  /** Register address */
213  unsigned int reg;
214 };
215 
216 /**
217  * Initialise descriptor ring
218  *
219  * @v ring Descriptor ring
220  * @v count Number of descriptors (must be a power of 2)
221  * @v reg Register address
222  */
223 static inline __attribute__ (( always_inline)) void
224 rhine_init_ring ( struct rhine_ring *ring, unsigned int count,
225  unsigned int reg ) {
226  ring->count = count;
227  ring->reg = reg;
228 }
229 
230 /** A VIA Rhine network card */
231 struct rhine_nic {
232  /** I/O address (some PIO access is always required) */
233  unsigned long ioaddr;
234  /** Registers */
235  void *regs;
236  /** Cached value of CR1 (to avoid read-modify-write on fast path) */
238 
239  /** MII interface */
241  /** MII device */
242  struct mii_device mii;
243 
244  /** Transmit descriptor ring */
245  struct rhine_ring tx;
246  /** Receive descriptor ring */
247  struct rhine_ring rx;
248  /** Receive I/O buffers */
250 };
251 
252 #endif /* _RHINE_H */
unsigned long ioaddr
I/O address (some PIO access is always required)
Definition: rhine.h:233
unsigned int cons
Consumer index.
Definition: rhine.h:208
unsigned int reg
Register address.
Definition: rhine.h:213
struct rhine_ring __attribute__
FILE_LICENCE(GPL2_OR_LATER)
A VIA Rhine descriptor ring.
Definition: rhine.h:202
#define RHINE_RXDESC_NUM
Rhine descriptor rings sizes.
Definition: rhine.h:68
An MII device.
Definition: mii.h:49
struct mii_interface mdio
MII interface.
Definition: rhine.h:240
A VIA Rhine network card.
Definition: rhine.h:231
Rhine descriptor format.
Definition: rhine.h:19
struct mii_device mii
MII device.
Definition: rhine.h:242
uint32_t des1
Definition: rhine.h:21
uint32_t des0
Definition: rhine.h:20
struct io_buffer * rx_iobuf[RHINE_RXDESC_NUM]
Receive I/O buffers.
Definition: rhine.h:249
void * regs
Registers.
Definition: rhine.h:235
unsigned char uint8_t
Definition: stdint.h:10
uint32_t buffer
Definition: rhine.h:22
static unsigned int count
Definition: rhine.h:224
unsigned int uint32_t
Definition: stdint.h:12
struct rhine_ring rx
Receive descriptor ring.
Definition: rhine.h:247
unsigned int count
Number of descriptors.
Definition: rhine.h:211
An MII interface.
Definition: mii.h:43
uint32_t next
Definition: rhine.h:23
uint8_t cr1
Cached value of CR1 (to avoid read-modify-write on fast path)
Definition: rhine.h:237
struct rhine_descriptor * desc
Descriptors.
Definition: rhine.h:204
unsigned int prod
Producer index.
Definition: rhine.h:206
struct rhine_ring tx
Transmit descriptor ring.
Definition: rhine.h:245
static unsigned int unsigned int reg
Definition: rhine.h:225
A persistent I/O buffer.
Definition: iobuf.h:32