Go to the documentation of this file. 38 typedef unsigned char byte;
39 typedef unsigned short word;
40 typedef unsigned long int dword;
62 #define BANK_SELECT 14 67 #define TCR_ENABLE 0x0001 68 #define TCR_FDUPLX 0x0800 69 #define TCR_STP_SQET 0x1000 70 #define TCR_MON_CNS 0x0400 71 #define TCR_PAD_ENABLE 0x0080 75 #define TCR_NORMAL (TCR_ENABLE | TCR_PAD_ENABLE) 79 #define ES_LINK_OK 0x4000 82 #define RCR_SOFTRESET 0x8000 83 #define RCR_STRIP_CRC 0x200 84 #define RCR_ENABLE 0x100 86 #define RCR_PROMISC 0x2 89 #define RCR_NORMAL (RCR_STRIP_CRC | RCR_ENABLE) 99 #define RPC_REG 0x000A 100 #define RPC_SPEED 0x2000 // When 1 PHY is in 100Mbps mode. 101 #define RPC_DPLX 0x1000 // When 1 PHY is in Full-Duplex Mode 102 #define RPC_ANEG 0x0800 // When 1 PHY is in Auto-Negotiate Mode 103 #define RPC_LSXA_SHFT 5 // Bits to shift LS2A,LS1A,LS0A to lsb 104 #define RPC_LSXB_SHFT 2 // Bits to get LS2B,LS1B,LS0B to lsb 105 #define RPC_LED_100_10 (0x00) // LED = 100Mbps OR's with 10Mbps link detect 106 #define RPC_LED_RES (0x01) // LED = Reserved 107 #define RPC_LED_10 (0x02) // LED = 10Mbps link detect 108 #define RPC_LED_FD (0x03) // LED = Full Duplex Mode 109 #define RPC_LED_TX_RX (0x04) // LED = TX or RX packet occurred 110 #define RPC_LED_100 (0x05) // LED = 100Mbps link detect 111 #define RPC_LED_TX (0x06) // LED = TX packet occurred 112 #define RPC_LED_RX (0x07) // LED = RX packet occurred 113 #define RPC_DEFAULT (RPC_ANEG | (RPC_LED_100 << RPC_LSXA_SHFT) | (RPC_LED_FD << RPC_LSXB_SHFT) | RPC_SPEED | RPC_DPLX) 117 #define RPC_REG 0x000A 118 #define RPC_SPEED 0x2000 // When 1 PHY is in 100Mbps mode. 119 #define RPC_DPLX 0x1000 // When 1 PHY is in Full-Duplex Mode 120 #define RPC_ANEG 0x0800 // When 1 PHY is in Auto-Negotiate Mode 121 #define RPC_LSXA_SHFT 5 // Bits to shift LS2A,LS1A,LS0A to lsb 122 #define RPC_LSXB_SHFT 2 // Bits to get LS2B,LS1B,LS0B to lsb 123 #define RPC_LED_100_10 (0x00) // LED = 100Mbps OR's with 10Mbps link detect 124 #define RPC_LED_RES (0x01) // LED = Reserved 125 #define RPC_LED_10 (0x02) // LED = 10Mbps link detect 126 #define RPC_LED_FD (0x03) // LED = Full Duplex Mode 127 #define RPC_LED_TX_RX (0x04) // LED = TX or RX packet occurred 128 #define RPC_LED_100 (0x05) // LED = 100Mbps link detect 129 #define RPC_LED_TX (0x06) // LED = TX packet occurred 130 #define RPC_LED_RX (0x07) // LED = RX packet occurred 131 #define RPC_DEFAULT (RPC_ANEG | (RPC_LED_100 << RPC_LSXA_SHFT) | (RPC_LED_FD << RPC_LSXB_SHFT) | RPC_SPEED | RPC_DPLX) 135 #define CFG_AUI_SELECT 0x100 142 #define CTL_POWERDOWN 0x2000 143 #define CTL_LE_ENABLE 0x80 144 #define CTL_CR_ENABLE 0x40 145 #define CTL_TE_ENABLE 0x0020 146 #define CTL_AUTO_RELEASE 0x0800 147 #define CTL_EPROM_ACCESS 0x0003 153 #define MC_ALLOC 0x20 154 #define MC_RESET 0x40 155 #define MC_REMOVE 0x60 156 #define MC_RELEASE 0x80 157 #define MC_FREEPKT 0xA0 158 #define MC_ENQUEUE 0xC0 163 #define FP_RXEMPTY 0x8000 164 #define FP_TXEMPTY 0x80 167 #define PTR_READ 0x2000 168 #define PTR_RCV 0x8000 169 #define PTR_AUTOINC 0x4000 170 #define PTR_AUTO_INC 0x0040 177 #define IM_RCV_INT 0x1 178 #define IM_TX_INT 0x2 179 #define IM_TX_EMPTY_INT 0x4 180 #define IM_ALLOC_INT 0x8 181 #define IM_RX_OVRN_INT 0x10 182 #define IM_EPH_INT 0x20 183 #define IM_ERCV_INT 0x40 194 #define MII_REG 0x0008 195 #define MII_MSK_CRS100 0x4000 // Disables CRS100 detection during tx half dup 196 #define MII_MDOE 0x0008 // MII Output Enable 197 #define MII_MCLK 0x0004 // MII Clock, pin MDCLK 198 #define MII_MDI 0x0002 // MII Input, pin MDI 199 #define MII_MDO 0x0001 // MII Output, pin MDO 211 #define CHIP_91100FD 8 218 #define TS_SUCCESS 0x0001 219 #define TS_LOSTCAR 0x0400 220 #define TS_LATCOL 0x0200 221 #define TS_16COL 0x0010 226 #define RS_ALGNERR 0x8000 227 #define RS_BADCRC 0x2000 228 #define RS_ODDFRAME 0x1000 229 #define RS_TOOLONG 0x0800 230 #define RS_TOOSHORT 0x0400 231 #define RS_MULTICAST 0x0001 232 #define RS_ERRORS (RS_ALGNERR | RS_BADCRC | RS_TOOLONG | RS_TOOSHORT) 237 #define PHY_CNTL_REG 0x00 238 #define PHY_CNTL_RST 0x8000 // 1=PHY Reset 239 #define PHY_CNTL_LPBK 0x4000 // 1=PHY Loopback 240 #define PHY_CNTL_SPEED 0x2000 // 1=100Mbps, 0=10Mpbs 241 #define PHY_CNTL_ANEG_EN 0x1000 // 1=Enable Auto negotiation 242 #define PHY_CNTL_PDN 0x0800 // 1=PHY Power Down mode 243 #define PHY_CNTL_MII_DIS 0x0400 // 1=MII 4 bit interface disabled 244 #define PHY_CNTL_ANEG_RST 0x0200 // 1=Reset Auto negotiate 245 #define PHY_CNTL_DPLX 0x0100 // 1=Full Duplex, 0=Half Duplex 246 #define PHY_CNTL_COLTST 0x0080 // 1= MII Colision Test 249 #define PHY_STAT_REG 0x01 250 #define PHY_STAT_CAP_T4 0x8000 // 1=100Base-T4 capable 251 #define PHY_STAT_CAP_TXF 0x4000 // 1=100Base-X full duplex capable 252 #define PHY_STAT_CAP_TXH 0x2000 // 1=100Base-X half duplex capable 253 #define PHY_STAT_CAP_TF 0x1000 // 1=10Mbps full duplex capable 254 #define PHY_STAT_CAP_TH 0x0800 // 1=10Mbps half duplex capable 255 #define PHY_STAT_CAP_SUPR 0x0040 // 1=recv mgmt frames with not preamble 256 #define PHY_STAT_ANEG_ACK 0x0020 // 1=ANEG has completed 257 #define PHY_STAT_REM_FLT 0x0010 // 1=Remote Fault detected 258 #define PHY_STAT_CAP_ANEG 0x0008 // 1=Auto negotiate capable 259 #define PHY_STAT_LINK 0x0004 // 1=valid link 260 #define PHY_STAT_JAB 0x0002 // 1=10Mbps jabber condition 261 #define PHY_STAT_EXREG 0x0001 // 1=extended registers implemented 264 #define PHY_ID1_REG 0x02 // PHY Identifier 1 265 #define PHY_ID2_REG 0x03 // PHY Identifier 2 268 #define PHY_AD_REG 0x04 269 #define PHY_AD_NP 0x8000 // 1=PHY requests exchange of Next Page 270 #define PHY_AD_ACK 0x4000 // 1=got link code word from remote 271 #define PHY_AD_RF 0x2000 // 1=advertise remote fault 272 #define PHY_AD_T4 0x0200 // 1=PHY is capable of 100Base-T4 273 #define PHY_AD_TX_FDX 0x0100 // 1=PHY is capable of 100Base-TX FDPLX 274 #define PHY_AD_TX_HDX 0x0080 // 1=PHY is capable of 100Base-TX HDPLX 275 #define PHY_AD_10_FDX 0x0040 // 1=PHY is capable of 10Base-T FDPLX 276 #define PHY_AD_10_HDX 0x0020 // 1=PHY is capable of 10Base-T HDPLX 277 #define PHY_AD_CSMA 0x0001 // 1=PHY is capable of 802.3 CMSA 280 #define PHY_RMT_REG 0x05 284 #define PHY_CFG1_REG 0x10 285 #define PHY_CFG1_LNKDIS 0x8000 // 1=Rx Link Detect Function disabled 286 #define PHY_CFG1_XMTDIS 0x4000 // 1=TP Transmitter Disabled 287 #define PHY_CFG1_XMTPDN 0x2000 // 1=TP Transmitter Powered Down 288 #define PHY_CFG1_BYPSCR 0x0400 // 1=Bypass scrambler/descrambler 289 #define PHY_CFG1_UNSCDS 0x0200 // 1=Unscramble Idle Reception Disable 290 #define PHY_CFG1_EQLZR 0x0100 // 1=Rx Equalizer Disabled 291 #define PHY_CFG1_CABLE 0x0080 // 1=STP(150ohm), 0=UTP(100ohm) 292 #define PHY_CFG1_RLVL0 0x0040 // 1=Rx Squelch level reduced by 4.5db 293 #define PHY_CFG1_TLVL_SHIFT 2 // Transmit Output Level Adjust 294 #define PHY_CFG1_TLVL_MASK 0x003C 295 #define PHY_CFG1_TRF_MASK 0x0003 // Transmitter Rise/Fall time 299 #define PHY_CFG2_REG 0x11 300 #define PHY_CFG2_APOLDIS 0x0020 // 1=Auto Polarity Correction disabled 301 #define PHY_CFG2_JABDIS 0x0010 // 1=Jabber disabled 302 #define PHY_CFG2_MREG 0x0008 // 1=Multiple register access (MII mgt) 303 #define PHY_CFG2_INTMDIO 0x0004 // 1=Interrupt signaled with MDIO pulseo 306 #define PHY_INT_REG 0x12 // Status Output (Interrupt Status) 307 #define PHY_INT_INT 0x8000 // 1=bits have changed since last read 308 #define PHY_INT_LNKFAIL 0x4000 // 1=Link Not detected 309 #define PHY_INT_LOSSSYNC 0x2000 // 1=Descrambler has lost sync 310 #define PHY_INT_CWRD 0x1000 // 1=Invalid 4B5B code detected on rx 311 #define PHY_INT_SSD 0x0800 // 1=No Start Of Stream detected on rx 312 #define PHY_INT_ESD 0x0400 // 1=No End Of Stream detected on rx 313 #define PHY_INT_RPOL 0x0200 // 1=Reverse Polarity detected 314 #define PHY_INT_JAB 0x0100 // 1=Jabber detected 315 #define PHY_INT_SPDDET 0x0080 // 1=100Base-TX mode, 0=10Base-T mode 316 #define PHY_INT_DPLXDET 0x0040 // 1=Device in Full Duplex 319 #define PHY_MASK_REG 0x13 // Interrupt Mask 326 #define PHY_CNTL_REG 0x00 327 #define PHY_CNTL_RST 0x8000 // 1=PHY Reset 328 #define PHY_CNTL_LPBK 0x4000 // 1=PHY Loopback 329 #define PHY_CNTL_SPEED 0x2000 // 1=100Mbps, 0=10Mpbs 330 #define PHY_CNTL_ANEG_EN 0x1000 // 1=Enable Auto negotiation 331 #define PHY_CNTL_PDN 0x0800 // 1=PHY Power Down mode 332 #define PHY_CNTL_MII_DIS 0x0400 // 1=MII 4 bit interface disabled 333 #define PHY_CNTL_ANEG_RST 0x0200 // 1=Reset Auto negotiate 334 #define PHY_CNTL_DPLX 0x0100 // 1=Full Duplex, 0=Half Duplex 335 #define PHY_CNTL_COLTST 0x0080 // 1= MII Colision Test 338 #define PHY_STAT_REG 0x01 339 #define PHY_STAT_CAP_T4 0x8000 // 1=100Base-T4 capable 340 #define PHY_STAT_CAP_TXF 0x4000 // 1=100Base-X full duplex capable 341 #define PHY_STAT_CAP_TXH 0x2000 // 1=100Base-X half duplex capable 342 #define PHY_STAT_CAP_TF 0x1000 // 1=10Mbps full duplex capable 343 #define PHY_STAT_CAP_TH 0x0800 // 1=10Mbps half duplex capable 344 #define PHY_STAT_CAP_SUPR 0x0040 // 1=recv mgmt frames with not preamble 345 #define PHY_STAT_ANEG_ACK 0x0020 // 1=ANEG has completed 346 #define PHY_STAT_REM_FLT 0x0010 // 1=Remote Fault detected 347 #define PHY_STAT_CAP_ANEG 0x0008 // 1=Auto negotiate capable 348 #define PHY_STAT_LINK 0x0004 // 1=valid link 349 #define PHY_STAT_JAB 0x0002 // 1=10Mbps jabber condition 350 #define PHY_STAT_EXREG 0x0001 // 1=extended registers implemented 353 #define PHY_ID1_REG 0x02 // PHY Identifier 1 354 #define PHY_ID2_REG 0x03 // PHY Identifier 2 357 #define PHY_AD_REG 0x04 358 #define PHY_AD_NP 0x8000 // 1=PHY requests exchange of Next Page 359 #define PHY_AD_ACK 0x4000 // 1=got link code word from remote 360 #define PHY_AD_RF 0x2000 // 1=advertise remote fault 361 #define PHY_AD_T4 0x0200 // 1=PHY is capable of 100Base-T4 362 #define PHY_AD_TX_FDX 0x0100 // 1=PHY is capable of 100Base-TX FDPLX 363 #define PHY_AD_TX_HDX 0x0080 // 1=PHY is capable of 100Base-TX HDPLX 364 #define PHY_AD_10_FDX 0x0040 // 1=PHY is capable of 10Base-T FDPLX 365 #define PHY_AD_10_HDX 0x0020 // 1=PHY is capable of 10Base-T HDPLX 366 #define PHY_AD_CSMA 0x0001 // 1=PHY is capable of 802.3 CMSA 369 #define PHY_RMT_REG 0x05 373 #define PHY_CFG1_REG 0x10 374 #define PHY_CFG1_LNKDIS 0x8000 // 1=Rx Link Detect Function disabled 375 #define PHY_CFG1_XMTDIS 0x4000 // 1=TP Transmitter Disabled 376 #define PHY_CFG1_XMTPDN 0x2000 // 1=TP Transmitter Powered Down 377 #define PHY_CFG1_BYPSCR 0x0400 // 1=Bypass scrambler/descrambler 378 #define PHY_CFG1_UNSCDS 0x0200 // 1=Unscramble Idle Reception Disable 379 #define PHY_CFG1_EQLZR 0x0100 // 1=Rx Equalizer Disabled 380 #define PHY_CFG1_CABLE 0x0080 // 1=STP(150ohm), 0=UTP(100ohm) 381 #define PHY_CFG1_RLVL0 0x0040 // 1=Rx Squelch level reduced by 4.5db 382 #define PHY_CFG1_TLVL_SHIFT 2 // Transmit Output Level Adjust 383 #define PHY_CFG1_TLVL_MASK 0x003C 384 #define PHY_CFG1_TRF_MASK 0x0003 // Transmitter Rise/Fall time 388 #define PHY_CFG2_REG 0x11 389 #define PHY_CFG2_APOLDIS 0x0020 // 1=Auto Polarity Correction disabled 390 #define PHY_CFG2_JABDIS 0x0010 // 1=Jabber disabled 391 #define PHY_CFG2_MREG 0x0008 // 1=Multiple register access (MII mgt) 392 #define PHY_CFG2_INTMDIO 0x0004 // 1=Interrupt signaled with MDIO pulseo 395 #define PHY_INT_REG 0x12 // Status Output (Interrupt Status) 396 #define PHY_INT_INT 0x8000 // 1=bits have changed since last read 397 #define PHY_INT_LNKFAIL 0x4000 // 1=Link Not detected 398 #define PHY_INT_LOSSSYNC 0x2000 // 1=Descrambler has lost sync 399 #define PHY_INT_CWRD 0x1000 // 1=Invalid 4B5B code detected on rx 400 #define PHY_INT_SSD 0x0800 // 1=No Start Of Stream detected on rx 401 #define PHY_INT_ESD 0x0400 // 1=No End Of Stream detected on rx 402 #define PHY_INT_RPOL 0x0200 // 1=Reverse Polarity detected 403 #define PHY_INT_JAB 0x0100 // 1=Jabber detected 404 #define PHY_INT_SPDDET 0x0080 // 1=100Base-TX mode, 0=10Base-T mode 405 #define PHY_INT_DPLXDET 0x0040 // 1=Device in Full Duplex 408 #define PHY_MASK_REG 0x13 // Interrupt Mask 419 #define SMC_SELECT_BANK(x, y) { _outw( y, x + BANK_SELECT ); } 422 #define SMC_DELAY(x) { inw( x + RCR );\