Go to the source code of this file.
Macros | |
| #define | _SMC9000_H_ |
| #define | BANK_SELECT 14 |
| #define | TCR 0 /* transmit control register */ |
| #define | TCR_ENABLE 0x0001 /* if this is 1, we can transmit */ |
| #define | TCR_FDUPLX 0x0800 /* receive packets sent out */ |
| #define | TCR_STP_SQET 0x1000 /* stop transmitting if Signal quality error */ |
| #define | TCR_MON_CNS 0x0400 /* monitors the carrier status */ |
| #define | TCR_PAD_ENABLE 0x0080 /* pads short packets to 64 bytes */ |
| #define | TCR_CLEAR 0 /* do NOTHING */ |
| #define | TCR_NORMAL (TCR_ENABLE | TCR_PAD_ENABLE) |
| #define | EPH_STATUS 2 |
| #define | ES_LINK_OK 0x4000 /* is the link integrity ok ? */ |
| #define | RCR 4 |
| #define | RCR_SOFTRESET 0x8000 /* resets the chip */ |
| #define | RCR_STRIP_CRC 0x200 /* strips CRC */ |
| #define | RCR_ENABLE 0x100 /* IFF this is set, we can receive packets */ |
| #define | RCR_ALMUL 0x4 /* receive all multicast packets */ |
| #define | RCR_PROMISC 0x2 /* enable promiscuous mode */ |
| #define | RCR_NORMAL (RCR_STRIP_CRC | RCR_ENABLE) |
| #define | RCR_CLEAR 0x0 /* set it to a base state */ |
| #define | COUNTER 6 |
| #define | MIR 8 |
| #define | MCR 10 |
| #define | RPC_REG 0x000A |
| #define | RPC_SPEED 0x2000 |
| #define | RPC_DPLX 0x1000 |
| #define | RPC_ANEG 0x0800 |
| #define | RPC_LSXA_SHFT 5 |
| #define | RPC_LSXB_SHFT 2 |
| #define | RPC_LED_100_10 (0x00) |
| #define | RPC_LED_RES (0x01) |
| #define | RPC_LED_10 (0x02) |
| #define | RPC_LED_FD (0x03) |
| #define | RPC_LED_TX_RX (0x04) |
| #define | RPC_LED_100 (0x05) |
| #define | RPC_LED_TX (0x06) |
| #define | RPC_LED_RX (0x07) |
| #define | RPC_DEFAULT (RPC_ANEG | (RPC_LED_100 << RPC_LSXA_SHFT) | (RPC_LED_FD << RPC_LSXB_SHFT) | RPC_SPEED | RPC_DPLX) |
| #define | RPC_REG 0x000A |
| #define | RPC_SPEED 0x2000 |
| #define | RPC_DPLX 0x1000 |
| #define | RPC_ANEG 0x0800 |
| #define | RPC_LSXA_SHFT 5 |
| #define | RPC_LSXB_SHFT 2 |
| #define | RPC_LED_100_10 (0x00) |
| #define | RPC_LED_RES (0x01) |
| #define | RPC_LED_10 (0x02) |
| #define | RPC_LED_FD (0x03) |
| #define | RPC_LED_TX_RX (0x04) |
| #define | RPC_LED_100 (0x05) |
| #define | RPC_LED_TX (0x06) |
| #define | RPC_LED_RX (0x07) |
| #define | RPC_DEFAULT (RPC_ANEG | (RPC_LED_100 << RPC_LSXA_SHFT) | (RPC_LED_FD << RPC_LSXB_SHFT) | RPC_SPEED | RPC_DPLX) |
| #define | CFG 0 |
| #define | CFG_AUI_SELECT 0x100 |
| #define | BASE 2 |
| #define | ADDR0 4 |
| #define | ADDR1 6 |
| #define | ADDR2 8 |
| #define | GENERAL 10 |
| #define | CONTROL 12 |
| #define | CTL_POWERDOWN 0x2000 |
| #define | CTL_LE_ENABLE 0x80 |
| #define | CTL_CR_ENABLE 0x40 |
| #define | CTL_TE_ENABLE 0x0020 |
| #define | CTL_AUTO_RELEASE 0x0800 |
| #define | CTL_EPROM_ACCESS 0x0003 /* high if Eprom is being read */ |
| #define | MMU_CMD 0 |
| #define | MC_BUSY 1 /* only readable bit in the register */ |
| #define | MC_NOP 0 |
| #define | MC_ALLOC 0x20 /* or with number of 256 byte packets */ |
| #define | MC_RESET 0x40 |
| #define | MC_REMOVE 0x60 /* remove the current rx packet */ |
| #define | MC_RELEASE 0x80 /* remove and release the current rx packet */ |
| #define | MC_FREEPKT 0xA0 /* Release packet in PNR register */ |
| #define | MC_ENQUEUE 0xC0 /* Enqueue the packet for transmit */ |
| #define | PNR_ARR 2 |
| #define | FIFO_PORTS 4 |
| #define | FP_RXEMPTY 0x8000 |
| #define | FP_TXEMPTY 0x80 |
| #define | POINTER 6 |
| #define | PTR_READ 0x2000 |
| #define | PTR_RCV 0x8000 |
| #define | PTR_AUTOINC 0x4000 |
| #define | PTR_AUTO_INC 0x0040 |
| #define | DATA_1 8 |
| #define | DATA_2 10 |
| #define | INTERRUPT 12 |
| #define | INT_MASK 13 |
| #define | IM_RCV_INT 0x1 |
| #define | IM_TX_INT 0x2 |
| #define | IM_TX_EMPTY_INT 0x4 |
| #define | IM_ALLOC_INT 0x8 |
| #define | IM_RX_OVRN_INT 0x10 |
| #define | IM_EPH_INT 0x20 |
| #define | IM_ERCV_INT 0x40 /* not on SMC9192 */ |
| #define | MULTICAST1 0 |
| #define | MULTICAST2 2 |
| #define | MULTICAST3 4 |
| #define | MULTICAST4 6 |
| #define | MGMT 8 |
| #define | REVISION 10 /* ( hi: chip id low: rev # ) */ |
| #define | MII_REG 0x0008 |
| #define | MII_MSK_CRS100 0x4000 |
| #define | MII_MDOE 0x0008 |
| #define | MII_MCLK 0x0004 |
| #define | MII_MDI 0x0002 |
| #define | MII_MDO 0x0001 |
| #define | ERCV 12 |
| #define | CHIP_9190 3 |
| #define | CHIP_9194 4 |
| #define | CHIP_9195 5 |
| #define | CHIP_9196 4 |
| #define | CHIP_91100 7 |
| #define | CHIP_91100FD 8 |
| #define | REV_9196 6 |
| #define | TS_SUCCESS 0x0001 |
| #define | TS_LOSTCAR 0x0400 |
| #define | TS_LATCOL 0x0200 |
| #define | TS_16COL 0x0010 |
| #define | RS_ALGNERR 0x8000 |
| #define | RS_BADCRC 0x2000 |
| #define | RS_ODDFRAME 0x1000 |
| #define | RS_TOOLONG 0x0800 |
| #define | RS_TOOSHORT 0x0400 |
| #define | RS_MULTICAST 0x0001 |
| #define | RS_ERRORS (RS_ALGNERR | RS_BADCRC | RS_TOOLONG | RS_TOOSHORT) |
| #define | PHY_CNTL_REG 0x00 |
| #define | PHY_CNTL_RST 0x8000 |
| #define | PHY_CNTL_LPBK 0x4000 |
| #define | PHY_CNTL_SPEED 0x2000 |
| #define | PHY_CNTL_ANEG_EN 0x1000 |
| #define | PHY_CNTL_PDN 0x0800 |
| #define | PHY_CNTL_MII_DIS 0x0400 |
| #define | PHY_CNTL_ANEG_RST 0x0200 |
| #define | PHY_CNTL_DPLX 0x0100 |
| #define | PHY_CNTL_COLTST 0x0080 |
| #define | PHY_STAT_REG 0x01 |
| #define | PHY_STAT_CAP_T4 0x8000 |
| #define | PHY_STAT_CAP_TXF 0x4000 |
| #define | PHY_STAT_CAP_TXH 0x2000 |
| #define | PHY_STAT_CAP_TF 0x1000 |
| #define | PHY_STAT_CAP_TH 0x0800 |
| #define | PHY_STAT_CAP_SUPR 0x0040 |
| #define | PHY_STAT_ANEG_ACK 0x0020 |
| #define | PHY_STAT_REM_FLT 0x0010 |
| #define | PHY_STAT_CAP_ANEG 0x0008 |
| #define | PHY_STAT_LINK 0x0004 |
| #define | PHY_STAT_JAB 0x0002 |
| #define | PHY_STAT_EXREG 0x0001 |
| #define | PHY_ID1_REG 0x02 |
| #define | PHY_ID2_REG 0x03 |
| #define | PHY_AD_REG 0x04 |
| #define | PHY_AD_NP 0x8000 |
| #define | PHY_AD_ACK 0x4000 |
| #define | PHY_AD_RF 0x2000 |
| #define | PHY_AD_T4 0x0200 |
| #define | PHY_AD_TX_FDX 0x0100 |
| #define | PHY_AD_TX_HDX 0x0080 |
| #define | PHY_AD_10_FDX 0x0040 |
| #define | PHY_AD_10_HDX 0x0020 |
| #define | PHY_AD_CSMA 0x0001 |
| #define | PHY_RMT_REG 0x05 |
| #define | PHY_CFG1_REG 0x10 |
| #define | PHY_CFG1_LNKDIS 0x8000 |
| #define | PHY_CFG1_XMTDIS 0x4000 |
| #define | PHY_CFG1_XMTPDN 0x2000 |
| #define | PHY_CFG1_BYPSCR 0x0400 |
| #define | PHY_CFG1_UNSCDS 0x0200 |
| #define | PHY_CFG1_EQLZR 0x0100 |
| #define | PHY_CFG1_CABLE 0x0080 |
| #define | PHY_CFG1_RLVL0 0x0040 |
| #define | PHY_CFG1_TLVL_SHIFT 2 |
| #define | PHY_CFG1_TLVL_MASK 0x003C |
| #define | PHY_CFG1_TRF_MASK 0x0003 |
| #define | PHY_CFG2_REG 0x11 |
| #define | PHY_CFG2_APOLDIS 0x0020 |
| #define | PHY_CFG2_JABDIS 0x0010 |
| #define | PHY_CFG2_MREG 0x0008 |
| #define | PHY_CFG2_INTMDIO 0x0004 |
| #define | PHY_INT_REG 0x12 |
| #define | PHY_INT_INT 0x8000 |
| #define | PHY_INT_LNKFAIL 0x4000 |
| #define | PHY_INT_LOSSSYNC 0x2000 |
| #define | PHY_INT_CWRD 0x1000 |
| #define | PHY_INT_SSD 0x0800 |
| #define | PHY_INT_ESD 0x0400 |
| #define | PHY_INT_RPOL 0x0200 |
| #define | PHY_INT_JAB 0x0100 |
| #define | PHY_INT_SPDDET 0x0080 |
| #define | PHY_INT_DPLXDET 0x0040 |
| #define | PHY_MASK_REG 0x13 |
| #define | PHY_CNTL_REG 0x00 |
| #define | PHY_CNTL_RST 0x8000 |
| #define | PHY_CNTL_LPBK 0x4000 |
| #define | PHY_CNTL_SPEED 0x2000 |
| #define | PHY_CNTL_ANEG_EN 0x1000 |
| #define | PHY_CNTL_PDN 0x0800 |
| #define | PHY_CNTL_MII_DIS 0x0400 |
| #define | PHY_CNTL_ANEG_RST 0x0200 |
| #define | PHY_CNTL_DPLX 0x0100 |
| #define | PHY_CNTL_COLTST 0x0080 |
| #define | PHY_STAT_REG 0x01 |
| #define | PHY_STAT_CAP_T4 0x8000 |
| #define | PHY_STAT_CAP_TXF 0x4000 |
| #define | PHY_STAT_CAP_TXH 0x2000 |
| #define | PHY_STAT_CAP_TF 0x1000 |
| #define | PHY_STAT_CAP_TH 0x0800 |
| #define | PHY_STAT_CAP_SUPR 0x0040 |
| #define | PHY_STAT_ANEG_ACK 0x0020 |
| #define | PHY_STAT_REM_FLT 0x0010 |
| #define | PHY_STAT_CAP_ANEG 0x0008 |
| #define | PHY_STAT_LINK 0x0004 |
| #define | PHY_STAT_JAB 0x0002 |
| #define | PHY_STAT_EXREG 0x0001 |
| #define | PHY_ID1_REG 0x02 |
| #define | PHY_ID2_REG 0x03 |
| #define | PHY_AD_REG 0x04 |
| #define | PHY_AD_NP 0x8000 |
| #define | PHY_AD_ACK 0x4000 |
| #define | PHY_AD_RF 0x2000 |
| #define | PHY_AD_T4 0x0200 |
| #define | PHY_AD_TX_FDX 0x0100 |
| #define | PHY_AD_TX_HDX 0x0080 |
| #define | PHY_AD_10_FDX 0x0040 |
| #define | PHY_AD_10_HDX 0x0020 |
| #define | PHY_AD_CSMA 0x0001 |
| #define | PHY_RMT_REG 0x05 |
| #define | PHY_CFG1_REG 0x10 |
| #define | PHY_CFG1_LNKDIS 0x8000 |
| #define | PHY_CFG1_XMTDIS 0x4000 |
| #define | PHY_CFG1_XMTPDN 0x2000 |
| #define | PHY_CFG1_BYPSCR 0x0400 |
| #define | PHY_CFG1_UNSCDS 0x0200 |
| #define | PHY_CFG1_EQLZR 0x0100 |
| #define | PHY_CFG1_CABLE 0x0080 |
| #define | PHY_CFG1_RLVL0 0x0040 |
| #define | PHY_CFG1_TLVL_SHIFT 2 |
| #define | PHY_CFG1_TLVL_MASK 0x003C |
| #define | PHY_CFG1_TRF_MASK 0x0003 |
| #define | PHY_CFG2_REG 0x11 |
| #define | PHY_CFG2_APOLDIS 0x0020 |
| #define | PHY_CFG2_JABDIS 0x0010 |
| #define | PHY_CFG2_MREG 0x0008 |
| #define | PHY_CFG2_INTMDIO 0x0004 |
| #define | PHY_INT_REG 0x12 |
| #define | PHY_INT_INT 0x8000 |
| #define | PHY_INT_LNKFAIL 0x4000 |
| #define | PHY_INT_LOSSSYNC 0x2000 |
| #define | PHY_INT_CWRD 0x1000 |
| #define | PHY_INT_SSD 0x0800 |
| #define | PHY_INT_ESD 0x0400 |
| #define | PHY_INT_RPOL 0x0200 |
| #define | PHY_INT_JAB 0x0100 |
| #define | PHY_INT_SPDDET 0x0080 |
| #define | PHY_INT_DPLXDET 0x0040 |
| #define | PHY_MASK_REG 0x13 |
| #define | SMC_SELECT_BANK(x, y) |
| #define | SMC_DELAY(x) |
Typedefs | |
| typedef unsigned char | byte |
| typedef unsigned short | word |
| typedef unsigned long int | dword |
Functions | |
| FILE_LICENCE (GPL_ANY) | |
Macro Definition Documentation
◆ _SMC9000_H_
◆ BANK_SELECT
| #define BANK_SELECT 14 |
Definition at line 62 of file smc9000.h.
Referenced by smc9000_probe_addr(), smc_read_phy_register(), and smc_write_phy_register().
◆ TCR
| #define TCR 0 /* transmit control register */ |
Definition at line 66 of file smc9000.h.
Referenced by smc9000_disable(), smc9000_probe(), smc9000_transmit(), and smc_reset().
◆ TCR_ENABLE
| #define TCR_ENABLE 0x0001 /* if this is 1, we can transmit */ |
Definition at line 67 of file smc9000.h.
Referenced by smc9000_transmit().
◆ TCR_FDUPLX
◆ TCR_STP_SQET
◆ TCR_MON_CNS
| #define TCR_MON_CNS 0x0400 /* monitors the carrier status */ |
◆ TCR_PAD_ENABLE
| #define TCR_PAD_ENABLE 0x0080 /* pads short packets to 64 bytes */ |
◆ TCR_CLEAR
| #define TCR_CLEAR 0 /* do NOTHING */ |
Definition at line 73 of file smc9000.h.
Referenced by smc9000_disable(), and smc_reset().
◆ TCR_NORMAL
| #define TCR_NORMAL (TCR_ENABLE | TCR_PAD_ENABLE) |
Definition at line 75 of file smc9000.h.
Referenced by smc9000_probe().
◆ EPH_STATUS
◆ ES_LINK_OK
◆ RCR
| #define RCR 4 |
Definition at line 81 of file smc9000.h.
Referenced by smc9000_disable(), smc9000_probe(), and smc_reset().
◆ RCR_SOFTRESET
| #define RCR_SOFTRESET 0x8000 /* resets the chip */ |
Definition at line 82 of file smc9000.h.
Referenced by smc_reset().
◆ RCR_STRIP_CRC
◆ RCR_ENABLE
| #define RCR_ENABLE 0x100 /* IFF this is set, we can receive packets */ |
◆ RCR_ALMUL
◆ RCR_PROMISC
◆ RCR_NORMAL
| #define RCR_NORMAL (RCR_STRIP_CRC | RCR_ENABLE) |
Definition at line 89 of file smc9000.h.
Referenced by smc9000_probe().
◆ RCR_CLEAR
Definition at line 90 of file smc9000.h.
Referenced by smc9000_disable(), and smc_reset().
◆ COUNTER
◆ MIR
| #define MIR 8 |
Definition at line 93 of file smc9000.h.
Referenced by smc9000_probe().
◆ MCR
| #define MCR 10 |
Definition at line 94 of file smc9000.h.
Referenced by smc9000_probe().
◆ RPC_REG [1/2]
| #define RPC_REG 0x000A |
Definition at line 99 of file smc9000.h.
Referenced by smc_phy_configure().
◆ RPC_SPEED [1/2]
| #define RPC_SPEED 0x2000 |
Definition at line 100 of file smc9000.h.
Referenced by smc_phy_configure().
◆ RPC_DPLX [1/2]
| #define RPC_DPLX 0x1000 |
Definition at line 101 of file smc9000.h.
Referenced by smc_phy_configure().
◆ RPC_ANEG [1/2]
◆ RPC_LSXA_SHFT [1/2]
◆ RPC_LSXB_SHFT [1/2]
◆ RPC_LED_100_10 [1/2]
◆ RPC_LED_RES [1/2]
◆ RPC_LED_10 [1/2]
◆ RPC_LED_FD [1/2]
◆ RPC_LED_TX_RX [1/2]
◆ RPC_LED_100 [1/2]
◆ RPC_LED_TX [1/2]
◆ RPC_LED_RX [1/2]
◆ RPC_DEFAULT [1/2]
| #define RPC_DEFAULT (RPC_ANEG | (RPC_LED_100 << RPC_LSXA_SHFT) | (RPC_LED_FD << RPC_LSXB_SHFT) | RPC_SPEED | RPC_DPLX) |
Definition at line 113 of file smc9000.h.
Referenced by smc_phy_configure().
◆ RPC_REG [2/2]
◆ RPC_SPEED [2/2]
◆ RPC_DPLX [2/2]
◆ RPC_ANEG [2/2]
◆ RPC_LSXA_SHFT [2/2]
◆ RPC_LSXB_SHFT [2/2]
◆ RPC_LED_100_10 [2/2]
◆ RPC_LED_RES [2/2]
◆ RPC_LED_10 [2/2]
◆ RPC_LED_FD [2/2]
◆ RPC_LED_TX_RX [2/2]
◆ RPC_LED_100 [2/2]
◆ RPC_LED_TX [2/2]
◆ RPC_LED_RX [2/2]
◆ RPC_DEFAULT [2/2]
| #define RPC_DEFAULT (RPC_ANEG | (RPC_LED_100 << RPC_LSXA_SHFT) | (RPC_LED_FD << RPC_LSXB_SHFT) | RPC_SPEED | RPC_DPLX) |
◆ CFG
| #define CFG 0 |
Definition at line 134 of file smc9000.h.
Referenced by smc9000_probe().
◆ CFG_AUI_SELECT
| #define CFG_AUI_SELECT 0x100 |
Definition at line 135 of file smc9000.h.
Referenced by smc9000_probe().
◆ BASE
◆ ADDR0
| #define ADDR0 4 |
Definition at line 137 of file smc9000.h.
Referenced by smc9000_probe().
◆ ADDR1
◆ ADDR2
◆ GENERAL
◆ CONTROL
◆ CTL_POWERDOWN
◆ CTL_LE_ENABLE
◆ CTL_CR_ENABLE
◆ CTL_TE_ENABLE
◆ CTL_AUTO_RELEASE
◆ CTL_EPROM_ACCESS
◆ MMU_CMD
| #define MMU_CMD 0 |
Definition at line 150 of file smc9000.h.
Referenced by smc9000_poll(), smc9000_transmit(), and smc_reset().
◆ MC_BUSY
◆ MC_NOP
◆ MC_ALLOC
| #define MC_ALLOC 0x20 /* or with number of 256 byte packets */ |
Definition at line 153 of file smc9000.h.
Referenced by smc9000_transmit().
◆ MC_RESET
| #define MC_RESET 0x40 |
Definition at line 154 of file smc9000.h.
Referenced by smc9000_transmit(), and smc_reset().
◆ MC_REMOVE
◆ MC_RELEASE
Definition at line 156 of file smc9000.h.
Referenced by smc9000_poll().
◆ MC_FREEPKT
| #define MC_FREEPKT 0xA0 /* Release packet in PNR register */ |
Definition at line 157 of file smc9000.h.
Referenced by smc9000_transmit().
◆ MC_ENQUEUE
| #define MC_ENQUEUE 0xC0 /* Enqueue the packet for transmit */ |
Definition at line 158 of file smc9000.h.
Referenced by smc9000_transmit().
◆ PNR_ARR
| #define PNR_ARR 2 |
Definition at line 160 of file smc9000.h.
Referenced by smc9000_transmit().
◆ FIFO_PORTS
| #define FIFO_PORTS 4 |
Definition at line 161 of file smc9000.h.
Referenced by smc9000_poll(), and smc9000_transmit().
◆ FP_RXEMPTY
| #define FP_RXEMPTY 0x8000 |
Definition at line 163 of file smc9000.h.
Referenced by smc9000_poll().
◆ FP_TXEMPTY
◆ POINTER
| #define POINTER 6 |
Definition at line 166 of file smc9000.h.
Referenced by smc9000_poll(), and smc9000_transmit().
◆ PTR_READ
| #define PTR_READ 0x2000 |
Definition at line 167 of file smc9000.h.
Referenced by smc9000_poll(), and smc9000_transmit().
◆ PTR_RCV
| #define PTR_RCV 0x8000 |
Definition at line 168 of file smc9000.h.
Referenced by smc9000_poll().
◆ PTR_AUTOINC
| #define PTR_AUTOINC 0x4000 |
Definition at line 169 of file smc9000.h.
Referenced by smc9000_poll(), and smc9000_transmit().
◆ PTR_AUTO_INC
◆ DATA_1
| #define DATA_1 8 |
Definition at line 172 of file smc9000.h.
Referenced by smc9000_poll(), and smc9000_transmit().
◆ DATA_2
◆ INTERRUPT
| #define INTERRUPT 12 |
Definition at line 174 of file smc9000.h.
Referenced by smc9000_transmit().
◆ INT_MASK
| #define INT_MASK 13 |
Definition at line 176 of file smc9000.h.
Referenced by smc9000_disable(), and smc_reset().
◆ IM_RCV_INT
◆ IM_TX_INT
| #define IM_TX_INT 0x2 |
Definition at line 178 of file smc9000.h.
Referenced by smc9000_transmit().
◆ IM_TX_EMPTY_INT
◆ IM_ALLOC_INT
| #define IM_ALLOC_INT 0x8 |
Definition at line 180 of file smc9000.h.
Referenced by smc9000_transmit().
◆ IM_RX_OVRN_INT
◆ IM_EPH_INT
◆ IM_ERCV_INT
◆ MULTICAST1
◆ MULTICAST2
◆ MULTICAST3
◆ MULTICAST4
◆ MGMT
◆ REVISION
| #define REVISION 10 /* ( hi: chip id low: rev # ) */ |
Definition at line 191 of file smc9000.h.
Referenced by smc9000_probe(), and smc9000_probe_addr().
◆ MII_REG
| #define MII_REG 0x0008 |
Definition at line 194 of file smc9000.h.
Referenced by smc_read_phy_register(), and smc_write_phy_register().
◆ MII_MSK_CRS100
◆ MII_MDOE
| #define MII_MDOE 0x0008 |
Definition at line 196 of file smc9000.h.
Referenced by smc_read_phy_register(), and smc_write_phy_register().
◆ MII_MCLK
| #define MII_MCLK 0x0004 |
Definition at line 197 of file smc9000.h.
Referenced by smc_read_phy_register(), and smc_write_phy_register().
◆ MII_MDI
| #define MII_MDI 0x0002 |
Definition at line 198 of file smc9000.h.
Referenced by smc_read_phy_register(), and smc_write_phy_register().
◆ MII_MDO
| #define MII_MDO 0x0001 |
Definition at line 199 of file smc9000.h.
Referenced by smc_read_phy_register(), and smc_write_phy_register().
◆ ERCV
◆ CHIP_9190
◆ CHIP_9194
◆ CHIP_9195
◆ CHIP_9196
| #define CHIP_9196 4 |
Definition at line 209 of file smc9000.h.
Referenced by smc9000_probe().
◆ CHIP_91100
◆ CHIP_91100FD
◆ REV_9196
| #define REV_9196 6 |
Definition at line 213 of file smc9000.h.
Referenced by smc9000_probe().
◆ TS_SUCCESS
| #define TS_SUCCESS 0x0001 |
Definition at line 218 of file smc9000.h.
Referenced by smc9000_transmit().
◆ TS_LOSTCAR
◆ TS_LATCOL
◆ TS_16COL
◆ RS_ALGNERR
◆ RS_BADCRC
◆ RS_ODDFRAME
◆ RS_TOOLONG
◆ RS_TOOSHORT
◆ RS_MULTICAST
◆ RS_ERRORS
| #define RS_ERRORS (RS_ALGNERR | RS_BADCRC | RS_TOOLONG | RS_TOOSHORT) |
Definition at line 232 of file smc9000.h.
Referenced by smc9000_poll().
◆ PHY_CNTL_REG [1/2]
| #define PHY_CNTL_REG 0x00 |
Definition at line 237 of file smc9000.h.
Referenced by smc_phy_configure().
◆ PHY_CNTL_RST [1/2]
| #define PHY_CNTL_RST 0x8000 |
Definition at line 238 of file smc9000.h.
Referenced by smc_phy_configure().
◆ PHY_CNTL_LPBK [1/2]
◆ PHY_CNTL_SPEED [1/2]
| #define PHY_CNTL_SPEED 0x2000 |
Definition at line 240 of file smc9000.h.
Referenced by smc_phy_configure().
◆ PHY_CNTL_ANEG_EN [1/2]
| #define PHY_CNTL_ANEG_EN 0x1000 |
Definition at line 241 of file smc9000.h.
Referenced by smc_phy_configure().
◆ PHY_CNTL_PDN [1/2]
◆ PHY_CNTL_MII_DIS [1/2]
◆ PHY_CNTL_ANEG_RST [1/2]
| #define PHY_CNTL_ANEG_RST 0x0200 |
Definition at line 244 of file smc9000.h.
Referenced by smc_phy_configure().
◆ PHY_CNTL_DPLX [1/2]
| #define PHY_CNTL_DPLX 0x0100 |
Definition at line 245 of file smc9000.h.
Referenced by smc_phy_configure().
◆ PHY_CNTL_COLTST [1/2]
◆ PHY_STAT_REG [1/2]
| #define PHY_STAT_REG 0x01 |
Definition at line 249 of file smc9000.h.
Referenced by smc_phy_configure().
◆ PHY_STAT_CAP_T4 [1/2]
| #define PHY_STAT_CAP_T4 0x8000 |
Definition at line 250 of file smc9000.h.
Referenced by smc_phy_configure().
◆ PHY_STAT_CAP_TXF [1/2]
| #define PHY_STAT_CAP_TXF 0x4000 |
Definition at line 251 of file smc9000.h.
Referenced by smc_phy_configure().
◆ PHY_STAT_CAP_TXH [1/2]
| #define PHY_STAT_CAP_TXH 0x2000 |
Definition at line 252 of file smc9000.h.
Referenced by smc_phy_configure().
◆ PHY_STAT_CAP_TF [1/2]
| #define PHY_STAT_CAP_TF 0x1000 |
Definition at line 253 of file smc9000.h.
Referenced by smc_phy_configure().
◆ PHY_STAT_CAP_TH [1/2]
| #define PHY_STAT_CAP_TH 0x0800 |
Definition at line 254 of file smc9000.h.
Referenced by smc_phy_configure().
◆ PHY_STAT_CAP_SUPR [1/2]
◆ PHY_STAT_ANEG_ACK [1/2]
| #define PHY_STAT_ANEG_ACK 0x0020 |
Definition at line 256 of file smc9000.h.
Referenced by smc_phy_configure().
◆ PHY_STAT_REM_FLT [1/2]
| #define PHY_STAT_REM_FLT 0x0010 |
Definition at line 257 of file smc9000.h.
Referenced by smc_phy_configure().
◆ PHY_STAT_CAP_ANEG [1/2]
◆ PHY_STAT_LINK [1/2]
◆ PHY_STAT_JAB [1/2]
◆ PHY_STAT_EXREG [1/2]
◆ PHY_ID1_REG [1/2]
| #define PHY_ID1_REG 0x02 |
Definition at line 264 of file smc9000.h.
Referenced by smc_detect_phy().
◆ PHY_ID2_REG [1/2]
| #define PHY_ID2_REG 0x03 |
Definition at line 265 of file smc9000.h.
Referenced by smc_detect_phy().
◆ PHY_AD_REG [1/2]
| #define PHY_AD_REG 0x04 |
Definition at line 268 of file smc9000.h.
Referenced by smc_phy_configure().
◆ PHY_AD_NP [1/2]
◆ PHY_AD_ACK [1/2]
◆ PHY_AD_RF [1/2]
◆ PHY_AD_T4 [1/2]
| #define PHY_AD_T4 0x0200 |
Definition at line 272 of file smc9000.h.
Referenced by smc_phy_configure().
◆ PHY_AD_TX_FDX [1/2]
| #define PHY_AD_TX_FDX 0x0100 |
Definition at line 273 of file smc9000.h.
Referenced by smc_phy_configure().
◆ PHY_AD_TX_HDX [1/2]
| #define PHY_AD_TX_HDX 0x0080 |
Definition at line 274 of file smc9000.h.
Referenced by smc_phy_configure().
◆ PHY_AD_10_FDX [1/2]
| #define PHY_AD_10_FDX 0x0040 |
Definition at line 275 of file smc9000.h.
Referenced by smc_phy_configure().
◆ PHY_AD_10_HDX [1/2]
| #define PHY_AD_10_HDX 0x0020 |
Definition at line 276 of file smc9000.h.
Referenced by smc_phy_configure().
◆ PHY_AD_CSMA [1/2]
| #define PHY_AD_CSMA 0x0001 |
Definition at line 277 of file smc9000.h.
Referenced by smc_phy_configure().
◆ PHY_RMT_REG [1/2]
◆ PHY_CFG1_REG [1/2]
◆ PHY_CFG1_LNKDIS [1/2]
◆ PHY_CFG1_XMTDIS [1/2]
◆ PHY_CFG1_XMTPDN [1/2]
◆ PHY_CFG1_BYPSCR [1/2]
◆ PHY_CFG1_UNSCDS [1/2]
◆ PHY_CFG1_EQLZR [1/2]
◆ PHY_CFG1_CABLE [1/2]
◆ PHY_CFG1_RLVL0 [1/2]
◆ PHY_CFG1_TLVL_SHIFT [1/2]
◆ PHY_CFG1_TLVL_MASK [1/2]
◆ PHY_CFG1_TRF_MASK [1/2]
◆ PHY_CFG2_REG [1/2]
◆ PHY_CFG2_APOLDIS [1/2]
◆ PHY_CFG2_JABDIS [1/2]
◆ PHY_CFG2_MREG [1/2]
◆ PHY_CFG2_INTMDIO [1/2]
◆ PHY_INT_REG [1/2]
| #define PHY_INT_REG 0x12 |
Definition at line 306 of file smc9000.h.
Referenced by smc_phy_configure().
◆ PHY_INT_INT [1/2]
◆ PHY_INT_LNKFAIL [1/2]
◆ PHY_INT_LOSSSYNC [1/2]
| #define PHY_INT_LOSSSYNC 0x2000 |
Definition at line 309 of file smc9000.h.
Referenced by smc_phy_configure().
◆ PHY_INT_CWRD [1/2]
| #define PHY_INT_CWRD 0x1000 |
Definition at line 310 of file smc9000.h.
Referenced by smc_phy_configure().
◆ PHY_INT_SSD [1/2]
| #define PHY_INT_SSD 0x0800 |
Definition at line 311 of file smc9000.h.
Referenced by smc_phy_configure().
◆ PHY_INT_ESD [1/2]
| #define PHY_INT_ESD 0x0400 |
Definition at line 312 of file smc9000.h.
Referenced by smc_phy_configure().
◆ PHY_INT_RPOL [1/2]
| #define PHY_INT_RPOL 0x0200 |
Definition at line 313 of file smc9000.h.
Referenced by smc_phy_configure().
◆ PHY_INT_JAB [1/2]
| #define PHY_INT_JAB 0x0100 |
Definition at line 314 of file smc9000.h.
Referenced by smc_phy_configure().
◆ PHY_INT_SPDDET [1/2]
| #define PHY_INT_SPDDET 0x0080 |
Definition at line 315 of file smc9000.h.
Referenced by smc_phy_configure().
◆ PHY_INT_DPLXDET [1/2]
| #define PHY_INT_DPLXDET 0x0040 |
Definition at line 316 of file smc9000.h.
Referenced by smc_phy_configure().
◆ PHY_MASK_REG [1/2]
| #define PHY_MASK_REG 0x13 |
Definition at line 319 of file smc9000.h.
Referenced by smc_phy_configure().
◆ PHY_CNTL_REG [2/2]
◆ PHY_CNTL_RST [2/2]
◆ PHY_CNTL_LPBK [2/2]
◆ PHY_CNTL_SPEED [2/2]
◆ PHY_CNTL_ANEG_EN [2/2]
◆ PHY_CNTL_PDN [2/2]
◆ PHY_CNTL_MII_DIS [2/2]
◆ PHY_CNTL_ANEG_RST [2/2]
◆ PHY_CNTL_DPLX [2/2]
◆ PHY_CNTL_COLTST [2/2]
◆ PHY_STAT_REG [2/2]
◆ PHY_STAT_CAP_T4 [2/2]
◆ PHY_STAT_CAP_TXF [2/2]
◆ PHY_STAT_CAP_TXH [2/2]
◆ PHY_STAT_CAP_TF [2/2]
◆ PHY_STAT_CAP_TH [2/2]
◆ PHY_STAT_CAP_SUPR [2/2]
◆ PHY_STAT_ANEG_ACK [2/2]
◆ PHY_STAT_REM_FLT [2/2]
◆ PHY_STAT_CAP_ANEG [2/2]
◆ PHY_STAT_LINK [2/2]
◆ PHY_STAT_JAB [2/2]
◆ PHY_STAT_EXREG [2/2]
◆ PHY_ID1_REG [2/2]
◆ PHY_ID2_REG [2/2]
◆ PHY_AD_REG [2/2]
◆ PHY_AD_NP [2/2]
◆ PHY_AD_ACK [2/2]
◆ PHY_AD_RF [2/2]
◆ PHY_AD_T4 [2/2]
◆ PHY_AD_TX_FDX [2/2]
◆ PHY_AD_TX_HDX [2/2]
◆ PHY_AD_10_FDX [2/2]
◆ PHY_AD_10_HDX [2/2]
◆ PHY_AD_CSMA [2/2]
◆ PHY_RMT_REG [2/2]
◆ PHY_CFG1_REG [2/2]
◆ PHY_CFG1_LNKDIS [2/2]
◆ PHY_CFG1_XMTDIS [2/2]
◆ PHY_CFG1_XMTPDN [2/2]
◆ PHY_CFG1_BYPSCR [2/2]
◆ PHY_CFG1_UNSCDS [2/2]
◆ PHY_CFG1_EQLZR [2/2]
◆ PHY_CFG1_CABLE [2/2]
◆ PHY_CFG1_RLVL0 [2/2]
◆ PHY_CFG1_TLVL_SHIFT [2/2]
◆ PHY_CFG1_TLVL_MASK [2/2]
◆ PHY_CFG1_TRF_MASK [2/2]
◆ PHY_CFG2_REG [2/2]
◆ PHY_CFG2_APOLDIS [2/2]
◆ PHY_CFG2_JABDIS [2/2]
◆ PHY_CFG2_MREG [2/2]
◆ PHY_CFG2_INTMDIO [2/2]
◆ PHY_INT_REG [2/2]
◆ PHY_INT_INT [2/2]
◆ PHY_INT_LNKFAIL [2/2]
◆ PHY_INT_LOSSSYNC [2/2]
◆ PHY_INT_CWRD [2/2]
◆ PHY_INT_SSD [2/2]
◆ PHY_INT_ESD [2/2]
◆ PHY_INT_RPOL [2/2]
◆ PHY_INT_JAB [2/2]
◆ PHY_INT_SPDDET [2/2]
◆ PHY_INT_DPLXDET [2/2]
◆ PHY_MASK_REG [2/2]
◆ SMC_SELECT_BANK
Definition at line 419 of file smc9000.h.
Referenced by smc9000_disable(), smc9000_poll(), smc9000_probe(), smc9000_probe_addr(), smc9000_transmit(), smc_phy_configure(), smc_read_phy_register(), smc_reset(), and smc_write_phy_register().
◆ SMC_DELAY
| #define SMC_DELAY | ( | x | ) |
Typedef Documentation
◆ byte
◆ word
◆ dword
Function Documentation
◆ FILE_LICENCE()
| FILE_LICENCE | ( | GPL_ANY | ) |
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