Go to the source code of this file.
|
| typedef unsigned char | byte |
| |
| typedef unsigned short | word |
| |
| typedef unsigned long int | dword |
| |
◆ _SMC9000_H_
◆ BANK_SELECT
◆ TCR
| #define TCR 0 /* transmit control register */ |
◆ TCR_ENABLE
| #define TCR_ENABLE 0x0001 /* if this is 1, we can transmit */ |
◆ TCR_FDUPLX
| #define TCR_FDUPLX 0x0800 /* receive packets sent out */ |
◆ TCR_STP_SQET
| #define TCR_STP_SQET 0x1000 /* stop transmitting if Signal quality error */ |
◆ TCR_MON_CNS
| #define TCR_MON_CNS 0x0400 /* monitors the carrier status */ |
◆ TCR_PAD_ENABLE
| #define TCR_PAD_ENABLE 0x0080 /* pads short packets to 64 bytes */ |
◆ TCR_CLEAR
| #define TCR_CLEAR 0 /* do NOTHING */ |
◆ TCR_NORMAL
◆ EPH_STATUS
◆ ES_LINK_OK
| #define ES_LINK_OK 0x4000 /* is the link integrity ok ? */ |
◆ RCR
◆ RCR_SOFTRESET
| #define RCR_SOFTRESET 0x8000 /* resets the chip */ |
◆ RCR_STRIP_CRC
| #define RCR_STRIP_CRC 0x200 /* strips CRC */ |
◆ RCR_ENABLE
| #define RCR_ENABLE 0x100 /* IFF this is set, we can receive packets */ |
◆ RCR_ALMUL
| #define RCR_ALMUL 0x4 /* receive all multicast packets */ |
◆ RCR_PROMISC
| #define RCR_PROMISC 0x2 /* enable promiscuous mode */ |
◆ RCR_NORMAL
◆ RCR_CLEAR
| #define RCR_CLEAR 0x0 /* set it to a base state */ |
◆ COUNTER
◆ MIR
◆ MCR
◆ RPC_REG [1/2]
◆ RPC_SPEED [1/2]
◆ RPC_DPLX [1/2]
◆ RPC_ANEG [1/2]
◆ RPC_LSXA_SHFT [1/2]
◆ RPC_LSXB_SHFT [1/2]
◆ RPC_LED_100_10 [1/2]
| #define RPC_LED_100_10 (0x00) |
◆ RPC_LED_RES [1/2]
| #define RPC_LED_RES (0x01) |
◆ RPC_LED_10 [1/2]
| #define RPC_LED_10 (0x02) |
◆ RPC_LED_FD [1/2]
| #define RPC_LED_FD (0x03) |
◆ RPC_LED_TX_RX [1/2]
| #define RPC_LED_TX_RX (0x04) |
◆ RPC_LED_100 [1/2]
| #define RPC_LED_100 (0x05) |
◆ RPC_LED_TX [1/2]
| #define RPC_LED_TX (0x06) |
◆ RPC_LED_RX [1/2]
| #define RPC_LED_RX (0x07) |
◆ RPC_DEFAULT [1/2]
◆ RPC_REG [2/2]
◆ RPC_SPEED [2/2]
◆ RPC_DPLX [2/2]
◆ RPC_ANEG [2/2]
◆ RPC_LSXA_SHFT [2/2]
◆ RPC_LSXB_SHFT [2/2]
◆ RPC_LED_100_10 [2/2]
| #define RPC_LED_100_10 (0x00) |
◆ RPC_LED_RES [2/2]
| #define RPC_LED_RES (0x01) |
◆ RPC_LED_10 [2/2]
| #define RPC_LED_10 (0x02) |
◆ RPC_LED_FD [2/2]
| #define RPC_LED_FD (0x03) |
◆ RPC_LED_TX_RX [2/2]
| #define RPC_LED_TX_RX (0x04) |
◆ RPC_LED_100 [2/2]
| #define RPC_LED_100 (0x05) |
◆ RPC_LED_TX [2/2]
| #define RPC_LED_TX (0x06) |
◆ RPC_LED_RX [2/2]
| #define RPC_LED_RX (0x07) |
◆ RPC_DEFAULT [2/2]
◆ CFG
◆ CFG_AUI_SELECT
| #define CFG_AUI_SELECT 0x100 |
◆ BASE
◆ ADDR0
◆ ADDR1
◆ ADDR2
◆ GENERAL
◆ CONTROL
◆ CTL_POWERDOWN
| #define CTL_POWERDOWN 0x2000 |
◆ CTL_LE_ENABLE
| #define CTL_LE_ENABLE 0x80 |
◆ CTL_CR_ENABLE
| #define CTL_CR_ENABLE 0x40 |
◆ CTL_TE_ENABLE
| #define CTL_TE_ENABLE 0x0020 |
◆ CTL_AUTO_RELEASE
| #define CTL_AUTO_RELEASE 0x0800 |
◆ CTL_EPROM_ACCESS
| #define CTL_EPROM_ACCESS 0x0003 /* high if Eprom is being read */ |
◆ MMU_CMD
◆ MC_BUSY
| #define MC_BUSY 1 /* only readable bit in the register */ |
◆ MC_NOP
◆ MC_ALLOC
| #define MC_ALLOC 0x20 /* or with number of 256 byte packets */ |
◆ MC_RESET
◆ MC_REMOVE
| #define MC_REMOVE 0x60 /* remove the current rx packet */ |
◆ MC_RELEASE
| #define MC_RELEASE 0x80 /* remove and release the current rx packet */ |
◆ MC_FREEPKT
| #define MC_FREEPKT 0xA0 /* Release packet in PNR register */ |
◆ MC_ENQUEUE
| #define MC_ENQUEUE 0xC0 /* Enqueue the packet for transmit */ |
◆ PNR_ARR
◆ FIFO_PORTS
◆ FP_RXEMPTY
| #define FP_RXEMPTY 0x8000 |
◆ FP_TXEMPTY
◆ POINTER
◆ PTR_READ
◆ PTR_RCV
◆ PTR_AUTOINC
| #define PTR_AUTOINC 0x4000 |
◆ PTR_AUTO_INC
| #define PTR_AUTO_INC 0x0040 |
◆ DATA_1
◆ DATA_2
◆ INTERRUPT
◆ INT_MASK
◆ IM_RCV_INT
◆ IM_TX_INT
◆ IM_TX_EMPTY_INT
| #define IM_TX_EMPTY_INT 0x4 |
◆ IM_ALLOC_INT
◆ IM_RX_OVRN_INT
| #define IM_RX_OVRN_INT 0x10 |
◆ IM_EPH_INT
◆ IM_ERCV_INT
| #define IM_ERCV_INT 0x40 /* not on SMC9192 */ |
◆ MULTICAST1
◆ MULTICAST2
◆ MULTICAST3
◆ MULTICAST4
◆ MGMT
◆ REVISION
| #define REVISION 10 /* ( hi: chip id low: rev # ) */ |
◆ MII_REG
◆ MII_MSK_CRS100
| #define MII_MSK_CRS100 0x4000 |
◆ MII_MDOE
◆ MII_MCLK
◆ MII_MDI
◆ MII_MDO
◆ ERCV
◆ CHIP_9190
◆ CHIP_9194
◆ CHIP_9195
◆ CHIP_9196
◆ CHIP_91100
◆ CHIP_91100FD
◆ REV_9196
◆ TS_SUCCESS
| #define TS_SUCCESS 0x0001 |
◆ TS_LOSTCAR
| #define TS_LOSTCAR 0x0400 |
◆ TS_LATCOL
◆ TS_16COL
◆ RS_ALGNERR
| #define RS_ALGNERR 0x8000 |
◆ RS_BADCRC
◆ RS_ODDFRAME
| #define RS_ODDFRAME 0x1000 |
◆ RS_TOOLONG
| #define RS_TOOLONG 0x0800 |
◆ RS_TOOSHORT
| #define RS_TOOSHORT 0x0400 |
◆ RS_MULTICAST
| #define RS_MULTICAST 0x0001 |
◆ RS_ERRORS
◆ PHY_CNTL_REG [1/2]
| #define PHY_CNTL_REG 0x00 |
◆ PHY_CNTL_RST [1/2]
| #define PHY_CNTL_RST 0x8000 |
◆ PHY_CNTL_LPBK [1/2]
| #define PHY_CNTL_LPBK 0x4000 |
◆ PHY_CNTL_SPEED [1/2]
| #define PHY_CNTL_SPEED 0x2000 |
◆ PHY_CNTL_ANEG_EN [1/2]
| #define PHY_CNTL_ANEG_EN 0x1000 |
◆ PHY_CNTL_PDN [1/2]
| #define PHY_CNTL_PDN 0x0800 |
◆ PHY_CNTL_MII_DIS [1/2]
| #define PHY_CNTL_MII_DIS 0x0400 |
◆ PHY_CNTL_ANEG_RST [1/2]
| #define PHY_CNTL_ANEG_RST 0x0200 |
◆ PHY_CNTL_DPLX [1/2]
| #define PHY_CNTL_DPLX 0x0100 |
◆ PHY_CNTL_COLTST [1/2]
| #define PHY_CNTL_COLTST 0x0080 |
◆ PHY_STAT_REG [1/2]
| #define PHY_STAT_REG 0x01 |
◆ PHY_STAT_CAP_T4 [1/2]
| #define PHY_STAT_CAP_T4 0x8000 |
◆ PHY_STAT_CAP_TXF [1/2]
| #define PHY_STAT_CAP_TXF 0x4000 |
◆ PHY_STAT_CAP_TXH [1/2]
| #define PHY_STAT_CAP_TXH 0x2000 |
◆ PHY_STAT_CAP_TF [1/2]
| #define PHY_STAT_CAP_TF 0x1000 |
◆ PHY_STAT_CAP_TH [1/2]
| #define PHY_STAT_CAP_TH 0x0800 |
◆ PHY_STAT_CAP_SUPR [1/2]
| #define PHY_STAT_CAP_SUPR 0x0040 |
◆ PHY_STAT_ANEG_ACK [1/2]
| #define PHY_STAT_ANEG_ACK 0x0020 |
◆ PHY_STAT_REM_FLT [1/2]
| #define PHY_STAT_REM_FLT 0x0010 |
◆ PHY_STAT_CAP_ANEG [1/2]
| #define PHY_STAT_CAP_ANEG 0x0008 |
◆ PHY_STAT_LINK [1/2]
| #define PHY_STAT_LINK 0x0004 |
◆ PHY_STAT_JAB [1/2]
| #define PHY_STAT_JAB 0x0002 |
◆ PHY_STAT_EXREG [1/2]
| #define PHY_STAT_EXREG 0x0001 |
◆ PHY_ID1_REG [1/2]
◆ PHY_ID2_REG [1/2]
◆ PHY_AD_REG [1/2]
◆ PHY_AD_NP [1/2]
◆ PHY_AD_ACK [1/2]
| #define PHY_AD_ACK 0x4000 |
◆ PHY_AD_RF [1/2]
◆ PHY_AD_T4 [1/2]
◆ PHY_AD_TX_FDX [1/2]
| #define PHY_AD_TX_FDX 0x0100 |
◆ PHY_AD_TX_HDX [1/2]
| #define PHY_AD_TX_HDX 0x0080 |
◆ PHY_AD_10_FDX [1/2]
| #define PHY_AD_10_FDX 0x0040 |
◆ PHY_AD_10_HDX [1/2]
| #define PHY_AD_10_HDX 0x0020 |
◆ PHY_AD_CSMA [1/2]
| #define PHY_AD_CSMA 0x0001 |
◆ PHY_RMT_REG [1/2]
◆ PHY_CFG1_REG [1/2]
| #define PHY_CFG1_REG 0x10 |
◆ PHY_CFG1_LNKDIS [1/2]
| #define PHY_CFG1_LNKDIS 0x8000 |
◆ PHY_CFG1_XMTDIS [1/2]
| #define PHY_CFG1_XMTDIS 0x4000 |
◆ PHY_CFG1_XMTPDN [1/2]
| #define PHY_CFG1_XMTPDN 0x2000 |
◆ PHY_CFG1_BYPSCR [1/2]
| #define PHY_CFG1_BYPSCR 0x0400 |
◆ PHY_CFG1_UNSCDS [1/2]
| #define PHY_CFG1_UNSCDS 0x0200 |
◆ PHY_CFG1_EQLZR [1/2]
| #define PHY_CFG1_EQLZR 0x0100 |
◆ PHY_CFG1_CABLE [1/2]
| #define PHY_CFG1_CABLE 0x0080 |
◆ PHY_CFG1_RLVL0 [1/2]
| #define PHY_CFG1_RLVL0 0x0040 |
◆ PHY_CFG1_TLVL_SHIFT [1/2]
| #define PHY_CFG1_TLVL_SHIFT 2 |
◆ PHY_CFG1_TLVL_MASK [1/2]
| #define PHY_CFG1_TLVL_MASK 0x003C |
◆ PHY_CFG1_TRF_MASK [1/2]
| #define PHY_CFG1_TRF_MASK 0x0003 |
◆ PHY_CFG2_REG [1/2]
| #define PHY_CFG2_REG 0x11 |
◆ PHY_CFG2_APOLDIS [1/2]
| #define PHY_CFG2_APOLDIS 0x0020 |
◆ PHY_CFG2_JABDIS [1/2]
| #define PHY_CFG2_JABDIS 0x0010 |
◆ PHY_CFG2_MREG [1/2]
| #define PHY_CFG2_MREG 0x0008 |
◆ PHY_CFG2_INTMDIO [1/2]
| #define PHY_CFG2_INTMDIO 0x0004 |
◆ PHY_INT_REG [1/2]
◆ PHY_INT_INT [1/2]
| #define PHY_INT_INT 0x8000 |
◆ PHY_INT_LNKFAIL [1/2]
| #define PHY_INT_LNKFAIL 0x4000 |
◆ PHY_INT_LOSSSYNC [1/2]
| #define PHY_INT_LOSSSYNC 0x2000 |
◆ PHY_INT_CWRD [1/2]
| #define PHY_INT_CWRD 0x1000 |
◆ PHY_INT_SSD [1/2]
| #define PHY_INT_SSD 0x0800 |
◆ PHY_INT_ESD [1/2]
| #define PHY_INT_ESD 0x0400 |
◆ PHY_INT_RPOL [1/2]
| #define PHY_INT_RPOL 0x0200 |
◆ PHY_INT_JAB [1/2]
| #define PHY_INT_JAB 0x0100 |
◆ PHY_INT_SPDDET [1/2]
| #define PHY_INT_SPDDET 0x0080 |
◆ PHY_INT_DPLXDET [1/2]
| #define PHY_INT_DPLXDET 0x0040 |
◆ PHY_MASK_REG [1/2]
| #define PHY_MASK_REG 0x13 |
◆ PHY_CNTL_REG [2/2]
| #define PHY_CNTL_REG 0x00 |
◆ PHY_CNTL_RST [2/2]
| #define PHY_CNTL_RST 0x8000 |
◆ PHY_CNTL_LPBK [2/2]
| #define PHY_CNTL_LPBK 0x4000 |
◆ PHY_CNTL_SPEED [2/2]
| #define PHY_CNTL_SPEED 0x2000 |
◆ PHY_CNTL_ANEG_EN [2/2]
| #define PHY_CNTL_ANEG_EN 0x1000 |
◆ PHY_CNTL_PDN [2/2]
| #define PHY_CNTL_PDN 0x0800 |
◆ PHY_CNTL_MII_DIS [2/2]
| #define PHY_CNTL_MII_DIS 0x0400 |
◆ PHY_CNTL_ANEG_RST [2/2]
| #define PHY_CNTL_ANEG_RST 0x0200 |
◆ PHY_CNTL_DPLX [2/2]
| #define PHY_CNTL_DPLX 0x0100 |
◆ PHY_CNTL_COLTST [2/2]
| #define PHY_CNTL_COLTST 0x0080 |
◆ PHY_STAT_REG [2/2]
| #define PHY_STAT_REG 0x01 |
◆ PHY_STAT_CAP_T4 [2/2]
| #define PHY_STAT_CAP_T4 0x8000 |
◆ PHY_STAT_CAP_TXF [2/2]
| #define PHY_STAT_CAP_TXF 0x4000 |
◆ PHY_STAT_CAP_TXH [2/2]
| #define PHY_STAT_CAP_TXH 0x2000 |
◆ PHY_STAT_CAP_TF [2/2]
| #define PHY_STAT_CAP_TF 0x1000 |
◆ PHY_STAT_CAP_TH [2/2]
| #define PHY_STAT_CAP_TH 0x0800 |
◆ PHY_STAT_CAP_SUPR [2/2]
| #define PHY_STAT_CAP_SUPR 0x0040 |
◆ PHY_STAT_ANEG_ACK [2/2]
| #define PHY_STAT_ANEG_ACK 0x0020 |
◆ PHY_STAT_REM_FLT [2/2]
| #define PHY_STAT_REM_FLT 0x0010 |
◆ PHY_STAT_CAP_ANEG [2/2]
| #define PHY_STAT_CAP_ANEG 0x0008 |
◆ PHY_STAT_LINK [2/2]
| #define PHY_STAT_LINK 0x0004 |
◆ PHY_STAT_JAB [2/2]
| #define PHY_STAT_JAB 0x0002 |
◆ PHY_STAT_EXREG [2/2]
| #define PHY_STAT_EXREG 0x0001 |
◆ PHY_ID1_REG [2/2]
◆ PHY_ID2_REG [2/2]
◆ PHY_AD_REG [2/2]
◆ PHY_AD_NP [2/2]
◆ PHY_AD_ACK [2/2]
| #define PHY_AD_ACK 0x4000 |
◆ PHY_AD_RF [2/2]
◆ PHY_AD_T4 [2/2]
◆ PHY_AD_TX_FDX [2/2]
| #define PHY_AD_TX_FDX 0x0100 |
◆ PHY_AD_TX_HDX [2/2]
| #define PHY_AD_TX_HDX 0x0080 |
◆ PHY_AD_10_FDX [2/2]
| #define PHY_AD_10_FDX 0x0040 |
◆ PHY_AD_10_HDX [2/2]
| #define PHY_AD_10_HDX 0x0020 |
◆ PHY_AD_CSMA [2/2]
| #define PHY_AD_CSMA 0x0001 |
◆ PHY_RMT_REG [2/2]
◆ PHY_CFG1_REG [2/2]
| #define PHY_CFG1_REG 0x10 |
◆ PHY_CFG1_LNKDIS [2/2]
| #define PHY_CFG1_LNKDIS 0x8000 |
◆ PHY_CFG1_XMTDIS [2/2]
| #define PHY_CFG1_XMTDIS 0x4000 |
◆ PHY_CFG1_XMTPDN [2/2]
| #define PHY_CFG1_XMTPDN 0x2000 |
◆ PHY_CFG1_BYPSCR [2/2]
| #define PHY_CFG1_BYPSCR 0x0400 |
◆ PHY_CFG1_UNSCDS [2/2]
| #define PHY_CFG1_UNSCDS 0x0200 |
◆ PHY_CFG1_EQLZR [2/2]
| #define PHY_CFG1_EQLZR 0x0100 |
◆ PHY_CFG1_CABLE [2/2]
| #define PHY_CFG1_CABLE 0x0080 |
◆ PHY_CFG1_RLVL0 [2/2]
| #define PHY_CFG1_RLVL0 0x0040 |
◆ PHY_CFG1_TLVL_SHIFT [2/2]
| #define PHY_CFG1_TLVL_SHIFT 2 |
◆ PHY_CFG1_TLVL_MASK [2/2]
| #define PHY_CFG1_TLVL_MASK 0x003C |
◆ PHY_CFG1_TRF_MASK [2/2]
| #define PHY_CFG1_TRF_MASK 0x0003 |
◆ PHY_CFG2_REG [2/2]
| #define PHY_CFG2_REG 0x11 |
◆ PHY_CFG2_APOLDIS [2/2]
| #define PHY_CFG2_APOLDIS 0x0020 |
◆ PHY_CFG2_JABDIS [2/2]
| #define PHY_CFG2_JABDIS 0x0010 |
◆ PHY_CFG2_MREG [2/2]
| #define PHY_CFG2_MREG 0x0008 |
◆ PHY_CFG2_INTMDIO [2/2]
| #define PHY_CFG2_INTMDIO 0x0004 |
◆ PHY_INT_REG [2/2]
◆ PHY_INT_INT [2/2]
| #define PHY_INT_INT 0x8000 |
◆ PHY_INT_LNKFAIL [2/2]
| #define PHY_INT_LNKFAIL 0x4000 |
◆ PHY_INT_LOSSSYNC [2/2]
| #define PHY_INT_LOSSSYNC 0x2000 |
◆ PHY_INT_CWRD [2/2]
| #define PHY_INT_CWRD 0x1000 |
◆ PHY_INT_SSD [2/2]
| #define PHY_INT_SSD 0x0800 |
◆ PHY_INT_ESD [2/2]
| #define PHY_INT_ESD 0x0400 |
◆ PHY_INT_RPOL [2/2]
| #define PHY_INT_RPOL 0x0200 |
◆ PHY_INT_JAB [2/2]
| #define PHY_INT_JAB 0x0100 |
◆ PHY_INT_SPDDET [2/2]
| #define PHY_INT_SPDDET 0x0080 |
◆ PHY_INT_DPLXDET [2/2]
| #define PHY_INT_DPLXDET 0x0040 |
◆ PHY_MASK_REG [2/2]
| #define PHY_MASK_REG 0x13 |
◆ SMC_SELECT_BANK
◆ SMC_DELAY
Value:uint16_t inw(volatile uint16_t *io_addr)
Read 16-bit word from I/O-mapped device.
Definition at line 422 of file smc9000.h.
◆ byte
| typedef unsigned char byte |
◆ word
| typedef unsigned short word |
◆ dword
◆ FILE_LICENCE()
