CardBus Controller Configuration Space, Section 4.5.1, PC Card Standard. More...

#include <Pci22.h>

Data Fields
UINT32	CardBusSocketReg
	Cardbus Socket/ExCA Base. More...

UINT8	Cap_Ptr

UINT8	Reserved

UINT16	SecondaryStatus
	Secondary Status. More...

UINT8	PciBusNumber
	PCI Bus Number. More...

UINT8	CardBusBusNumber
	CardBus Bus Number. More...

UINT8	SubordinateBusNumber
	Subordinate Bus Number. More...

UINT8	CardBusLatencyTimer
	CardBus Latency Timer. More...

UINT32	MemoryBase0
	Memory Base Register 0. More...

UINT32	MemoryLimit0
	Memory Limit Register 0. More...

UINT32	MemoryBase1

UINT32	MemoryLimit1

UINT32	IoBase0

UINT32	IoLimit0
	I/O Base Register 0. More...

UINT32	IoBase1
	I/O Limit Register 0. More...

UINT32	IoLimit1

UINT8	InterruptLine
	Interrupt Line. More...

UINT8	InterruptPin
	Interrupt Pin. More...

UINT16	BridgeControl
	Bridge Control. More...

Detailed Description

CardBus Controller Configuration Space, Section 4.5.1, PC Card Standard.

8.0

Definition at line 119 of file Pci22.h.

Field Documentation

◆ CardBusSocketReg

UINT32 PCI_CARDBUS_CONTROL_REGISTER::CardBusSocketReg

Cardbus Socket/ExCA Base.

Definition at line 120 of file Pci22.h.

◆ Cap_Ptr

UINT8 PCI_CARDBUS_CONTROL_REGISTER::Cap_Ptr

Definition at line 121 of file Pci22.h.

◆ Reserved

UINT8 PCI_CARDBUS_CONTROL_REGISTER::Reserved

Definition at line 122 of file Pci22.h.

◆ SecondaryStatus

UINT16 PCI_CARDBUS_CONTROL_REGISTER::SecondaryStatus

Secondary Status.

Definition at line 123 of file Pci22.h.

◆ PciBusNumber

UINT8 PCI_CARDBUS_CONTROL_REGISTER::PciBusNumber

PCI Bus Number.

Definition at line 124 of file Pci22.h.

◆ CardBusBusNumber

UINT8 PCI_CARDBUS_CONTROL_REGISTER::CardBusBusNumber

CardBus Bus Number.

Definition at line 125 of file Pci22.h.

◆ SubordinateBusNumber

UINT8 PCI_CARDBUS_CONTROL_REGISTER::SubordinateBusNumber

Subordinate Bus Number.

Definition at line 126 of file Pci22.h.

◆ CardBusLatencyTimer

UINT8 PCI_CARDBUS_CONTROL_REGISTER::CardBusLatencyTimer

CardBus Latency Timer.

Definition at line 127 of file Pci22.h.

◆ MemoryBase0

UINT32 PCI_CARDBUS_CONTROL_REGISTER::MemoryBase0

Memory Base Register 0.

Definition at line 128 of file Pci22.h.

◆ MemoryLimit0

UINT32 PCI_CARDBUS_CONTROL_REGISTER::MemoryLimit0

Memory Limit Register 0.

Definition at line 129 of file Pci22.h.

◆ MemoryBase1

UINT32 PCI_CARDBUS_CONTROL_REGISTER::MemoryBase1

Definition at line 130 of file Pci22.h.

◆ MemoryLimit1

UINT32 PCI_CARDBUS_CONTROL_REGISTER::MemoryLimit1

Definition at line 131 of file Pci22.h.

◆ IoBase0

UINT32 PCI_CARDBUS_CONTROL_REGISTER::IoBase0

Definition at line 132 of file Pci22.h.

◆ IoLimit0

UINT32 PCI_CARDBUS_CONTROL_REGISTER::IoLimit0

I/O Base Register 0.

Definition at line 133 of file Pci22.h.

◆ IoBase1

UINT32 PCI_CARDBUS_CONTROL_REGISTER::IoBase1

I/O Limit Register 0.

Definition at line 134 of file Pci22.h.

◆ IoLimit1

UINT32 PCI_CARDBUS_CONTROL_REGISTER::IoLimit1

Definition at line 135 of file Pci22.h.

◆ InterruptLine

UINT8 PCI_CARDBUS_CONTROL_REGISTER::InterruptLine

Interrupt Line.

Definition at line 136 of file Pci22.h.

◆ InterruptPin

UINT8 PCI_CARDBUS_CONTROL_REGISTER::InterruptPin

Interrupt Pin.

Definition at line 137 of file Pci22.h.

◆ BridgeControl

UINT16 PCI_CARDBUS_CONTROL_REGISTER::BridgeControl

Bridge Control.

Definition at line 138 of file Pci22.h.

The documentation for this struct was generated from the following file:

include/ipxe/efi/IndustryStandard/Pci22.h

Data Fields