iPXE
velocity.h
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1 #ifndef _VELOCITY_H
2 #define _VELOCITY_H
3 
4 /** @file
5  *
6  * VIA Velocity network driver
7  *
8  */
9 
10 FILE_LICENCE ( GPL2_OR_LATER );
11 
12 /** Skeleton BAR size */
13 #define VELOCITY_BAR_SIZE 256
14 
15 /** Default timeout */
16 #define VELOCITY_TIMEOUT_US 10 * 1000
17 
18 struct velocity_frag {
21 } __attribute__ ((packed));
22 
23 /** Velocity descriptor format */
27  /* We only use the first fragment, the HW requires us to have 7 */
28  struct velocity_frag frags[7];
29 } __attribute__ ((packed));
30 
36 } __attribute__ ((packed));
37 
38 #define VELOCITY_DES0_RMBC(_n) (((_n) >> 16) & 0x1fff)
39 #define VELOCITY_DES0_OWN (1 << 31)
40 #define VELOCITY_DES0_TERR (1 << 15)
41 #define VELOCITY_DES0_RXOK (1 << 15)
42 #define VELOCITY_DES0_FDX (1 << 14)
43 #define VELOCITY_DES0_GMII (1 << 13)
44 #define VELOCITY_DES0_LNKFL (1 << 12)
45 #define VELOCITY_DES0_SHDN (1 << 10)
46 #define VELOCITY_DES0_CRS (1 << 9)
47 #define VELOCITY_DES0_CDH (1 << 8)
48 #define VELOCITY_DES0_ABT (1 << 7)
49 #define VELOCITY_DES0_OWT (1 << 6)
50 #define VELOCITY_DES0_OWC (1 << 5)
51 #define VELOCITY_DES0_COLS (1 << 4)
52 
53 #define VELOCITY_DES0_RXSHDN (1 << 30)
54 #define VELOCITY_DES0_RXER (1 << 5)
55 #define VELOCITY_DES0_RLE (1 << 4)
56 #define VELOCITY_DES0_CE (1 << 3)
57 #define VELOCITY_DES0_FAE (1 << 2)
58 #define VELOCITY_DES0_CRC (1 << 1)
59 #define VELOCITY_DES0_RX_ERR ( VELOCITY_DES0_RXER | \
60  VELOCITY_DES0_RLE | \
61  VELOCITY_DES0_CE | \
62  VELOCITY_DES0_FAE | \
63  VELOCITY_DES0_CRC )
64 
65 /** TX descriptor fragment number */
66 #define VELOCITY_DES1_FRAG(_n) (((_n + 1) & 0xf) << 28)
67 #define VELOCITY_DES1_TCPLS ((1 << 24) | (1 << 25))
68 #define VELOCITY_DES1_INTR (1 << 23)
69 #define VELOCITY_DES1_PIC (1 << 22)
70 #define VELOCITY_DES1_VETAG (1 << 21)
71 #define VELOCITY_DES1_IPCK (1 << 20)
72 #define VELOCITY_DES1_UDPCK (1 << 19)
73 #define VELOCITY_DES1_TCPCK (1 << 18)
74 #define VELOCITY_DES1_JMBO (1 << 17)
75 #define VELOCITY_DES1_CRC (1 << 16)
76 
77 #define VELOCITY_DES2_IC (1 << 31)
78 #define VELOCITY_DES2_SIZE(_n) (((_n) & 0x1fff) << 16)
79 
80 /** Number of receive descriptors
81  *
82  * Must be a multiple of 4 (hardware requirement).
83  */
84 #define VELOCITY_RXDESC_NUM 8
85 #define VELOCITY_RXDESC_SIZE \
86  ( VELOCITY_RXDESC_NUM * sizeof ( struct velocity_rx_descriptor ) )
87 
88 /** Number of transmit descriptors */
89 #define VELOCITY_TXDESC_NUM 8
90 #define VELOCITY_TXDESC_SIZE \
91  ( VELOCITY_TXDESC_NUM * sizeof ( struct velocity_tx_descriptor ) )
92 
93 /** Descriptor alignment */
94 #define VELOCITY_RING_ALIGN 64
95 
96 /** Receive buffer length */
97 #define VELOCITY_RX_MAX_LEN 1536
98 
99 /** MAC address registers */
100 #define VELOCITY_MAC0 0x00
101 #define VELOCITY_MAC1 0x01
102 #define VELOCITY_MAC2 0x02
103 #define VELOCITY_MAC3 0x03
104 #define VELOCITY_MAC4 0x04
105 #define VELOCITY_MAC5 0x05
106 
107 /** Receive control register */
108 #define VELOCITY_RCR 0x06
109 #define RHINE_RCR_SYMERR_ACCEPT (1 << 7) /*< Accept symbol error */
110 #define RHINE_RCR_FILTER_ACCEPT (1 << 6) /*< Accept based on filter */
111 #define RHINE_RCR_LONG_ACCEPT (1 << 5) /*< Accept long packets */
112 #define RHINE_RCR_PROMISC (1 << 4) /*< Promiscuous mode */
113 #define RHINE_RCR_BCAST_ACCEPT (1 << 3) /*< Accept broadcast */
114 #define RHINE_RCR_MCAST_ACCEPT (1 << 2) /*< Accept multicast */
115 #define RHINE_RCR_RUNT_ACCEPT (1 << 1) /*< Accept runt frames */
116 #define RHINE_RCR_ERR_ACCEPT (1 << 0) /*< Accept erroneous frames */
117 
118 /** Transmit control register */
119 #define VELOCITY_TCR 0x07
120 #define VELOCITY_TCR_LB0 (1 << 0) /*< Loopback control */
121 #define VELOCITY_TCR_LB1 (1 << 1) /*< Loopback control */
122 #define VELOCITY_TCR_COLTMC0 (1 << 2) /*< Collision retry control */
123 #define VELOCITY_TCR_COLTMC1 (1 << 3) /*< Collision retry control */
124 
125 /** Command register 0 (set) */
126 #define VELOCITY_CRS0 0x08
127 #define VELOCITY_CR0_TXON (1 << 3) /*< Transmit enable */
128 #define VELOCITY_CR0_RXON (1 << 2) /*< Receive enable */
129 #define VELOCITY_CR0_STOP (1 << 1) /*< Stop NIC */
130 #define VELOCITY_CR0_START (1 << 0) /*< Start NIC */
131 
132 /** Command register 1 (set) */
133 #define VELOCITY_CRS1 0x09
134 #define VELOCITY_CR1_SFRST (1 << 7) /*< Software reset */
135 #define VELOCITY_CR1_TM1EN (1 << 6) /*< Perioding software counting */
136 #define VELOCITY_CR1_TM0EN (1 << 5) /*< Single-shot software counting */
137 #define VELOCITY_CR1_DPOLL (1 << 3) /*< Disable auto polling */
138 #define VELOCITY_CR1_DISAU (1 << 0) /*< Unicast reception disable */
139 
140 /** Command register 2 (set) */
141 #define VELOCITY_CRS2 0x0A
142 #define VELOCITY_CR2_XONEN (1 << 7) /*< XON/XOFF mode enable */
143 #define VELOCITY_CR2_FDXTFCEN (1 << 6) /*< FDX flow control TX */
144 #define VELOCITY_CR2_FDXRFCEN (1 << 5)
145 #define VELOCITY_CR2_HDXFCEN (1 << 4)
146 
147 /** Command register 3 (set) */
148 #define VELOCITY_CRS3 0x0B
149 #define VELOCITY_CR3_FOSRST (1 << 6)
150 #define VELOCITY_CR3_FPHYRST (1 << 5)
151 #define VELOCITY_CR3_DIAG (1 << 4)
152 #define VELOCITY_CR3_INTPCTL (1 << 2)
153 #define VELOCITY_CR3_GINTMSK1 (1 << 1)
154 #define VELOCITY_CR3_SWPEND (1 << 0)
155 
156 /** Command register 0 (clear) */
157 #define VELOCITY_CRC0 0x0C
158 
159 /** Command register 1 (clear) */
160 #define VELOCITY_CRC1 0x0D
161 
162 /** Command register 2 (clear */
163 #define VELOCITY_CRC2 0x0E
164 
165 /** Command register 3 (clear */
166 #define VELOCITY_CRC3 0x0F
167 #define VELOCITY_CAM0 0x10
168 #define VELOCITY_CAM1 0x11
169 #define VELOCITY_CAM2 0x12
170 #define VELOCITY_CAM3 0x13
171 #define VELOCITY_CAM4 0x14
172 #define VELOCITY_CAM5 0x15
173 #define VELOCITY_CAM6 0x16
174 #define VELOCITY_CAM7 0x17
175 #define VELOCITY_TXDESC_HI 0x18 /* Hi part of 64bit txdesc base addr */
176 #define VELOCITY_DATABUF_HI 0x1D /* Hi part of 64bit data buffer addr */
177 #define VELOCITY_INTCTL0 0x20 /* interrupt control register */
178 #define VELOCITY_RXSUPPTHR 0x20
179 #define VELOCITY_TXSUPPTHR 0x20
180 #define VELOCITY_INTHOLDOFF 0x20
181 #define VELOCITY_INTCTL1 0x21 /* interrupt control register */
182 #define VELOCITY_TXHOSTERR 0x22 /* TX host error status */
183 #define VELOCITY_RXHOSTERR 0x23 /* RX host error status */
184 
185 /** Interrupt status register 0 */
186 #define VELOCITY_ISR0 0x24
187 #define VELOCITY_ISR0_PTX3 (1 << 7)
188 #define VELOCITY_ISR0_PTX2 (1 << 6)
189 #define VELOCITY_ISR0_PTX1 (1 << 5)
190 #define VELOCITY_ISR0_PTX0 (1 << 4)
191 #define VELOCITY_ISR0_PTXI (1 << 3)
192 #define VELOCITY_ISR0_PRXI (1 << 2)
193 #define VELOCITY_ISR0_PPTXI (1 << 1)
194 #define VELOCITY_ISR0_PPRXI (1 << 0)
195 
196 /** Interrupt status register 1 */
197 #define VELOCITY_ISR1 0x25
198 #define VELOCITY_ISR1_SRCI (1 << 7)
199 #define VELOCITY_ISR1_LSTPEI (1 << 6)
200 #define VELOCITY_ISR1_LSTEI (1 << 5)
201 #define VELOCITY_ISR1_OVFL (1 << 4)
202 #define VELOCITY_ISR1_FLONI (1 << 3)
203 #define VELOCITY_ISR1_RACEI (1 << 2)
204 
205 /** Interrupt status register 2 */
206 #define VELOCITY_ISR2 0x26
207 #define VELOCITY_ISR2_HFLD (1 << 7)
208 #define VELOCITY_ISR2_UDPI (1 << 6)
209 #define VELOCITY_ISR2_MIBFI (1 << 5)
210 #define VELOCITY_ISR2_SHDNII (1 << 4)
211 #define VELOCITY_ISR2_PHYI (1 << 3)
212 #define VELOCITY_ISR2_PWEI (1 << 2)
213 #define VELOCITY_ISR2_TMR1I (1 << 1)
214 #define VELOCITY_ISR2_TMR0I (1 << 0)
215 
216 /** Interrupt status register 3 */
217 #define VELOCITY_ISR3 0x27
218 
219 /** Interrupt mask register 0 */
220 #define VELOCITY_IMR0 0x28
221 
222 /** Interrupt mask register 1 */
223 #define VELOCITY_IMR1 0x29
224 
225 /** Interrupt mask register 2 */
226 #define VELOCITY_IMR2 0x2a
227 
228 /** Interrupt mask register 3 */
229 #define VELOCITY_IMR3 0x2b
230 
231 #define VELOCITY_TXSTS_PORT 0x2C /* Transmit status port (???) */
232 #define VELOCITY_TXQCSRS 0x30 /* TX queue ctl/status set */
233 
234 #define VELOCITY_TXQCSRS_DEAD3 (1 << 15)
235 #define VELOCITY_TXQCSRS_WAK3 (1 << 14)
236 #define VELOCITY_TXQCSRS_ACT3 (1 << 13)
237 #define VELOCITY_TXQCSRS_RUN3 (1 << 12)
238 #define VELOCITY_TXQCSRS_DEAD2 (1 << 11)
239 #define VELOCITY_TXQCSRS_WAK2 (1 << 10)
240 #define VELOCITY_TXQCSRS_ACT2 (1 << 9)
241 #define VELOCITY_TXQCSRS_RUN2 (1 << 8)
242 #define VELOCITY_TXQCSRS_DEAD1 (1 << 7)
243 #define VELOCITY_TXQCSRS_WAK1 (1 << 6)
244 #define VELOCITY_TXQCSRS_ACT1 (1 << 5)
245 #define VELOCITY_TXQCSRS_RUN1 (1 << 4)
246 #define VELOCITY_TXQCSRS_DEAD0 (1 << 3)
247 #define VELOCITY_TXQCSRS_WAK0 (1 << 2)
248 #define VELOCITY_TXQCSRS_ACT0 (1 << 1)
249 #define VELOCITY_TXQCSRS_RUN0 (1 << 0)
250 
251 #define VELOCITY_RXQCSRS 0x32 /* RX queue ctl/status set */
252 #define VELOCITY_RXQCSRC 0x36
253 
254 #define VELOCITY_RXQCSR_DEAD (1 << 3)
255 #define VELOCITY_RXQCSR_WAK (1 << 2)
256 #define VELOCITY_RXQCSR_ACT (1 << 1)
257 #define VELOCITY_RXQCSR_RUN (1 << 0)
258 
259 #define VELOCITY_TXQCSRC 0x34 /* TX queue ctl/status clear */
260 #define VELOCITY_RXQCSRC 0x36 /* RX queue ctl/status clear */
261 #define VELOCITY_RXDESC_ADDR_LO 0x38 /* RX desc base addr (lo 32 bits) */
262 #define VELOCITY_RXDESC_CONSIDX 0x3C /* Current RX descriptor index */
263 #define VELOCITY_TXQTIMER 0x3E /* TX queue timer pend register */
264 #define VELOCITY_RXQTIMER 0x3F /* RX queue timer pend register */
265 #define VELOCITY_TXDESC_ADDR_LO0 0x40 /* TX desc0 base addr (lo 32 bits) */
266 #define VELOCITY_TXDESC_ADDR_LO1 0x44 /* TX desc1 base addr (lo 32 bits) */
267 #define VELOCITY_TXDESC_ADDR_LO2 0x48 /* TX desc2 base addr (lo 32 bits) */
268 #define VELOCITY_TXDESC_ADDR_LO3 0x4C /* TX desc3 base addr (lo 32 bits) */
269 #define VELOCITY_RXDESCNUM 0x50 /* Size of RX desc ring */
270 #define VELOCITY_TXDESCNUM 0x52 /* Size of TX desc ring */
271 #define VELOCITY_TXDESC_CONSIDX0 0x54 /* Current TX descriptor index */
272 #define VELOCITY_TXDESC_CONSIDX1 0x56 /* Current TX descriptor index */
273 #define VELOCITY_TXDESC_CONSIDX2 0x58 /* Current TX descriptor index */
274 #define VELOCITY_TXDESC_CONSIDX3 0x5A /* Current TX descriptor index */
275 #define VELOCITY_TX_PAUSE_TIMER 0x5C /* TX pause frame timer */
276 #define VELOCITY_RXDESC_RESIDUECNT 0x5E /* RX descriptor residue count */
277 #define VELOCITY_FIFOTEST0 0x60 /* FIFO test register */
278 #define VELOCITY_FIFOTEST1 0x64 /* FIFO test register */
279 #define VELOCITY_CAMADDR 0x68 /* CAM address register */
280 #define VELOCITY_CAMCTL 0x69 /* CAM control register */
281 #define VELOCITY_MIICFG 0x6C /* MII port config register */
282 #define VELOCITY_MIISR 0x6D /* MII port status register */
283 #define VELOCITY_MIISR_IDLE (1 << 7)
284 #define VELOCITY_PHYSTS0 0x6E /* PHY status register */
285 #define VELOCITY_PHYSTS0_LINK (1 << 6)
286 #define VELOCITY_PHYSTS1 0x6F /* PHY status register */
287 #define VELOCITY_MIICR 0x70 /* MII command register */
288 #define VELOCITY_MIICR_MAUTO (1 << 7)
289 #define VELOCITY_MIICR_RCMD (1 << 6)
290 #define VELOCITY_MIICR_WCMD (1 << 5)
291 #define VELOCITY_MIICR_MDPM (1 << 4)
292 #define VELOCITY_MIICR_MOUT (1 << 3)
293 #define VELOCITY_MIICR_MDO (1 << 2)
294 #define VELOCITY_MIICR_MDI (1 << 1)
295 #define VELOCITY_MIICR_MDC (1 << 0)
296 
297 #define VELOCITY_MIIADDR 0x71 /* MII address register */
298 #define VELOCITY_MIIDATA 0x72 /* MII data register */
299 #define VELOCITY_SSTIMER 0x74 /* single-shot timer */
300 #define VELOCITY_PTIMER 0x76 /* periodic timer */
301 #define VELOCITY_DMACFG0 0x7C /* DMA config 0 */
302 #define VELOCITY_DMACFG1 0x7D /* DMA config 1 */
303 #define VELOCITY_RXCFG 0x7E /* MAC RX config */
304 #define VELOCITY_TXCFG 0x7F /* MAC TX config */
305 #define VELOCITY_SWEEDATA 0x85 /* EEPROM software loaded data */
306 
307 /** Chip Configuration Register A */
308 #define VELOCITY_CFGA 0x78
309 #define VELOCITY_CFGA_PACPI (1 << 0)
310 
311 /** Power Management Sticky Register */
312 #define VELOCITY_STICKY 0x83
313 #define VELOCITY_STICKY_DS0 (1 << 0)
314 #define VELOCITY_STICKY_DS1 (1 << 1)
315 
316 #define VELOCITY_EEWRDAT 0x8C /* EEPROM embedded write */
317 #define VELOCITY_EECSUM 0x92 /* EEPROM checksum */
318 #define VELOCITY_EECSR 0x93 /* EEPROM control/status */
319 #define VELOCITY_EECSR_RELOAD (1 << 5)
320 #define VELOCITY_EERDDAT 0x94 /* EEPROM embedded read */
321 #define VELOCITY_EEADDR 0x96 /* EEPROM address */
322 #define VELOCITY_EECMD 0x97 /* EEPROM embedded command */
323 
324 /** A Velocity network card */
325 struct velocity_nic {
326  /** Registers */
327  void *regs;
328  /** MII interface */
330  /** MII device */
331  struct mii_device mii;
332  /** Netdev */
334 
335  /** Receive descriptor ring */
337  /** Receive I/O buffers */
339  /** Receive producer index */
340  unsigned int rx_prod;
341  /** Receive consumer index */
342  unsigned int rx_cons;
343  /** Receive commit number
344  *
345  * Used to fullfill the hardware requirement of returning receive buffers
346  * to the hardware only in blocks of 4.
347  */
348  unsigned int rx_commit;
349 
350  /** Transmit descriptor ring */
352  /** Transmit producer index */
353  unsigned int tx_prod;
354  /** Transmit consumer index */
355  unsigned int tx_cons;
356 };
357 
358 #endif /* _VELOCITY_H */
struct velocity_tx_descriptor * tx_ring
Transmit descriptor ring.
Definition: velocity.h:351
struct velocity_rx_descriptor * rx_ring
Receive descriptor ring.
Definition: velocity.h:336
unsigned int rx_cons
Receive consumer index.
Definition: velocity.h:342
uint32_t des2
Definition: velocity.h:20
struct io_buffer * rx_buffs[VELOCITY_RXDESC_NUM]
Receive I/O buffers.
Definition: velocity.h:338
unsigned int rx_commit
Receive commit number.
Definition: velocity.h:348
FILE_LICENCE(GPL2_OR_LATER)
struct velocity_frag frags[7]
Definition: velocity.h:28
#define VELOCITY_RXDESC_NUM
Number of receive descriptors.
Definition: velocity.h:84
An MII device.
Definition: mii.h:49
unsigned int rx_prod
Receive producer index.
Definition: velocity.h:340
A Velocity network card.
Definition: velocity.h:325
unsigned int tx_prod
Transmit producer index.
Definition: velocity.h:353
A network device.
Definition: netdevice.h:348
struct velocity_nic __attribute__
Velocity descriptor format.
Definition: velocity.h:24
unsigned int uint32_t
Definition: stdint.h:12
unsigned int tx_cons
Transmit consumer index.
Definition: velocity.h:355
An MII interface.
Definition: mii.h:43
struct mii_device mii
MII device.
Definition: velocity.h:331
uint32_t addr
Definition: velocity.h:19
struct mii_interface mdio
MII interface.
Definition: velocity.h:329
struct net_device * netdev
Netdev.
Definition: velocity.h:333
void * regs
Registers.
Definition: velocity.h:327
A persistent I/O buffer.
Definition: iobuf.h:32