iPXE
atl1e.h
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00001 /*
00002  * Copyright(c) 2007 Atheros Corporation. All rights reserved.
00003  * Copyright(c) 2007 xiong huang <xiong.huang@atheros.com>
00004  *
00005  * Derived from Intel e1000 driver
00006  * Copyright(c) 1999 - 2005 Intel Corporation. All rights reserved.
00007  *
00008  * Modified for iPXE, October 2009 by Joshua Oreman <oremanj@rwcr.net>
00009  *
00010  * This program is free software; you can redistribute it and/or modify it
00011  * under the terms of the GNU General Public License as published by the Free
00012  * Software Foundation; either version 2 of the License, or (at your option)
00013  * any later version.
00014  *
00015  * This program is distributed in the hope that it will be useful, but WITHOUT
00016  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
00017  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
00018  * more details.
00019  *
00020  * You should have received a copy of the GNU General Public License along with
00021  * this program; if not, write to the Free Software Foundation, Inc., 51
00022  * Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
00023  */
00024 
00025 FILE_LICENCE ( GPL2_OR_LATER );
00026 
00027 #ifndef _ATL1E_H_
00028 #define _ATL1E_H_
00029 
00030 #include <mii.h>
00031 #include <stdlib.h>
00032 #include <string.h>
00033 #include <unistd.h>
00034 #include <byteswap.h>
00035 #include <errno.h>
00036 #include <ipxe/malloc.h>
00037 #include <ipxe/pci.h>
00038 #include <ipxe/pci_io.h>
00039 #include <ipxe/iobuf.h>
00040 #include <ipxe/netdevice.h>
00041 #include <ipxe/ethernet.h>
00042 #include <ipxe/if_ether.h>
00043 #include <ipxe/io.h>
00044 
00045 #define ETH_FCS_LEN     4
00046 #define VLAN_HLEN       4
00047 #define NET_IP_ALIGN    2
00048 
00049 #define SPEED_0            0xffff
00050 #define SPEED_10           10
00051 #define SPEED_100          100
00052 #define SPEED_1000         1000
00053 #define HALF_DUPLEX        1
00054 #define FULL_DUPLEX        2
00055 
00056 /* Error Codes */
00057 #define AT_ERR_EEPROM      1
00058 #define AT_ERR_PHY         2
00059 #define AT_ERR_CONFIG      3
00060 #define AT_ERR_PARAM       4
00061 #define AT_ERR_MAC_TYPE    5
00062 #define AT_ERR_PHY_TYPE    6
00063 #define AT_ERR_PHY_SPEED   7
00064 #define AT_ERR_PHY_RES     8
00065 #define AT_ERR_TIMEOUT     9
00066 
00067 #define AT_MAX_RECEIVE_QUEUE    4
00068 #define AT_PAGE_NUM_PER_QUEUE   2
00069 
00070 #define AT_TWSI_EEPROM_TIMEOUT  100
00071 #define AT_HW_MAX_IDLE_DELAY    10
00072 
00073 #define AT_REGS_LEN     75
00074 #define AT_EEPROM_LEN   512
00075 
00076 /* tpd word 2 */
00077 #define TPD_BUFLEN_MASK         0x3FFF
00078 #define TPD_BUFLEN_SHIFT        0
00079 
00080 /* tpd word 3 bits 0:4 */
00081 #define TPD_EOP_MASK            0x0001
00082 #define TPD_EOP_SHIFT           0
00083 
00084 struct atl1e_tpd_desc {
00085         u64 buffer_addr;
00086         u32 word2;
00087         u32 word3;
00088 };
00089 
00090 #define MAX_TX_BUF_LEN      0x2000
00091 #define MAX_TX_BUF_SHIFT    13
00092 
00093 /* rrs word 1 bit 0:31 */
00094 #define RRS_RX_CSUM_MASK        0xFFFF
00095 #define RRS_RX_CSUM_SHIFT       0
00096 #define RRS_PKT_SIZE_MASK       0x3FFF
00097 #define RRS_PKT_SIZE_SHIFT      16
00098 #define RRS_CPU_NUM_MASK        0x0003
00099 #define RRS_CPU_NUM_SHIFT       30
00100 
00101 #define RRS_IS_RSS_IPV4         0x0001
00102 #define RRS_IS_RSS_IPV4_TCP     0x0002
00103 #define RRS_IS_RSS_IPV6         0x0004
00104 #define RRS_IS_RSS_IPV6_TCP     0x0008
00105 #define RRS_IS_IPV6             0x0010
00106 #define RRS_IS_IP_FRAG          0x0020
00107 #define RRS_IS_IP_DF            0x0040
00108 #define RRS_IS_802_3            0x0080
00109 #define RRS_IS_VLAN_TAG         0x0100
00110 #define RRS_IS_ERR_FRAME        0x0200
00111 #define RRS_IS_IPV4             0x0400
00112 #define RRS_IS_UDP              0x0800
00113 #define RRS_IS_TCP              0x1000
00114 #define RRS_IS_BCAST            0x2000
00115 #define RRS_IS_MCAST            0x4000
00116 #define RRS_IS_PAUSE            0x8000
00117 
00118 #define RRS_ERR_BAD_CRC         0x0001
00119 #define RRS_ERR_CODE            0x0002
00120 #define RRS_ERR_DRIBBLE         0x0004
00121 #define RRS_ERR_RUNT            0x0008
00122 #define RRS_ERR_RX_OVERFLOW     0x0010
00123 #define RRS_ERR_TRUNC           0x0020
00124 #define RRS_ERR_IP_CSUM         0x0040
00125 #define RRS_ERR_L4_CSUM         0x0080
00126 #define RRS_ERR_LENGTH          0x0100
00127 #define RRS_ERR_DES_ADDR        0x0200
00128 
00129 struct atl1e_recv_ret_status {
00130         u16 seq_num;
00131         u16 hash_lo;
00132         u32 word1;
00133         u16 pkt_flag;
00134         u16 err_flag;
00135         u16 hash_hi;
00136         u16 vtag;
00137 };
00138 
00139 enum atl1e_dma_req_block {
00140         atl1e_dma_req_128 = 0,
00141         atl1e_dma_req_256 = 1,
00142         atl1e_dma_req_512 = 2,
00143         atl1e_dma_req_1024 = 3,
00144         atl1e_dma_req_2048 = 4,
00145         atl1e_dma_req_4096 = 5
00146 };
00147 
00148 enum atl1e_nic_type {
00149         athr_l1e = 0,
00150         athr_l2e_revA = 1,
00151         athr_l2e_revB = 2
00152 };
00153 
00154 struct atl1e_hw {
00155         u8 *hw_addr;            /* inner register address */
00156         struct atl1e_adapter *adapter;
00157         enum atl1e_nic_type  nic_type;
00158         u8 mac_addr[ETH_ALEN];
00159         u8 perm_mac_addr[ETH_ALEN];
00160 
00161         u16 mii_autoneg_adv_reg;
00162         u16 mii_1000t_ctrl_reg;
00163 
00164         enum atl1e_dma_req_block dmar_block;
00165         enum atl1e_dma_req_block dmaw_block;
00166 
00167         int phy_configured;
00168         int re_autoneg;
00169         int emi_ca;
00170 };
00171 
00172 /*
00173  * wrapper around a pointer to a socket buffer,
00174  * so a DMA handle can be stored along with the buffer
00175  */
00176 struct atl1e_tx_buffer {
00177         struct io_buffer *iob;
00178         u16 length;
00179         u32 dma;
00180 };
00181 
00182 struct atl1e_rx_page {
00183         u32             dma;    /* receive rage DMA address */
00184         u8              *addr;   /* receive rage virtual address */
00185         u32             write_offset_dma;  /* the DMA address which contain the
00186                                               receive data offset in the page */
00187         u32             *write_offset_addr; /* the virtaul address which contain
00188                                              the receive data offset in the page */
00189         u32             read_offset;       /* the offset where we have read */
00190 };
00191 
00192 struct atl1e_rx_page_desc {
00193         struct atl1e_rx_page   rx_page[AT_PAGE_NUM_PER_QUEUE];
00194         u8  rx_using;
00195         u16 rx_nxseq;
00196 };
00197 
00198 /* transmit packet descriptor (tpd) ring */
00199 struct atl1e_tx_ring {
00200         struct atl1e_tpd_desc *desc;  /* descriptor ring virtual address  */
00201         u32                dma;    /* descriptor ring physical address */
00202         u16                count;  /* the count of transmit rings  */
00203         u16                next_to_use;
00204         u16                next_to_clean;
00205         struct atl1e_tx_buffer *tx_buffer;
00206         u32                cmb_dma;
00207         u32                *cmb;
00208 };
00209 
00210 /* receive packet descriptor ring */
00211 struct atl1e_rx_ring {
00212         void            *desc;
00213         u32             dma;
00214         int             size;
00215         u32             page_size; /* bytes length of rxf page */
00216         u32             real_page_size; /* real_page_size = page_size + jumbo + aliagn */
00217         struct atl1e_rx_page_desc rx_page_desc;
00218 };
00219 
00220 /* board specific private data structure */
00221 struct atl1e_adapter {
00222         struct net_device   *netdev;
00223         struct pci_device   *pdev;
00224         struct mii_if_info  mii;    /* MII interface info */
00225         struct atl1e_hw        hw;
00226 
00227         u16 link_speed;
00228         u16 link_duplex;
00229 
00230         /* All Descriptor memory */
00231         u32             ring_dma;
00232         void            *ring_vir_addr;
00233         u32             ring_size;
00234 
00235         struct atl1e_tx_ring tx_ring;
00236         struct atl1e_rx_ring rx_ring;
00237 
00238         int bd_number;     /* board number;*/
00239 };
00240 
00241 #define AT_WRITE_REG(a, reg, value) \
00242                 writel((value), ((a)->hw_addr + reg))
00243 
00244 #define AT_WRITE_FLUSH(a) \
00245                 readl((a)->hw_addr)
00246 
00247 #define AT_READ_REG(a, reg) \
00248                 readl((a)->hw_addr + reg)
00249 
00250 #define AT_WRITE_REGB(a, reg, value) \
00251                 writeb((value), ((a)->hw_addr + reg))
00252 
00253 #define AT_READ_REGB(a, reg) \
00254                 readb((a)->hw_addr + reg)
00255 
00256 #define AT_WRITE_REGW(a, reg, value) \
00257                 writew((value), ((a)->hw_addr + reg))
00258 
00259 #define AT_READ_REGW(a, reg) \
00260                 readw((a)->hw_addr + reg)
00261 
00262 #define AT_WRITE_REG_ARRAY(a, reg, offset, value) \
00263                 writel((value), (((a)->hw_addr + reg) + ((offset) << 2)))
00264 
00265 #define AT_READ_REG_ARRAY(a, reg, offset) \
00266                 readl(((a)->hw_addr + reg) + ((offset) << 2))
00267 
00268 extern int atl1e_up(struct atl1e_adapter *adapter);
00269 extern void atl1e_down(struct atl1e_adapter *adapter);
00270 extern s32 atl1e_reset_hw(struct atl1e_hw *hw);
00271 
00272 /********** Hardware-level functionality: **********/
00273 
00274 /* function prototype */
00275 s32 atl1e_reset_hw(struct atl1e_hw *hw);
00276 s32 atl1e_read_mac_addr(struct atl1e_hw *hw);
00277 s32 atl1e_init_hw(struct atl1e_hw *hw);
00278 s32 atl1e_phy_commit(struct atl1e_hw *hw);
00279 s32 atl1e_get_speed_and_duplex(struct atl1e_hw *hw, u16 *speed, u16 *duplex);
00280 u32 atl1e_auto_get_fc(struct atl1e_adapter *adapter, u16 duplex);
00281 s32 atl1e_read_phy_reg(struct atl1e_hw *hw, u16 reg_addr, u16 *phy_data);
00282 s32 atl1e_write_phy_reg(struct atl1e_hw *hw, u32 reg_addr, u16 phy_data);
00283 s32 atl1e_validate_mdi_setting(struct atl1e_hw *hw);
00284 void atl1e_hw_set_mac_addr(struct atl1e_hw *hw);
00285 s32 atl1e_phy_enter_power_saving(struct atl1e_hw *hw);
00286 s32 atl1e_phy_leave_power_saving(struct atl1e_hw *hw);
00287 s32 atl1e_phy_init(struct atl1e_hw *hw);
00288 int atl1e_check_eeprom_exist(struct atl1e_hw *hw);
00289 void atl1e_force_ps(struct atl1e_hw *hw);
00290 s32 atl1e_restart_autoneg(struct atl1e_hw *hw);
00291 
00292 /* register definition */
00293 #define REG_PM_CTRLSTAT             0x44
00294 
00295 #define REG_PCIE_CAP_LIST           0x58
00296 
00297 #define REG_DEVICE_CAP              0x5C
00298 #define     DEVICE_CAP_MAX_PAYLOAD_MASK     0x7
00299 #define     DEVICE_CAP_MAX_PAYLOAD_SHIFT    0
00300 
00301 #define REG_DEVICE_CTRL             0x60
00302 #define     DEVICE_CTRL_MAX_PAYLOAD_MASK    0x7
00303 #define     DEVICE_CTRL_MAX_PAYLOAD_SHIFT   5
00304 #define     DEVICE_CTRL_MAX_RREQ_SZ_MASK    0x7
00305 #define     DEVICE_CTRL_MAX_RREQ_SZ_SHIFT   12
00306 
00307 #define REG_VPD_CAP                 0x6C
00308 #define     VPD_CAP_ID_MASK                 0xff
00309 #define     VPD_CAP_ID_SHIFT                0
00310 #define     VPD_CAP_NEXT_PTR_MASK           0xFF
00311 #define     VPD_CAP_NEXT_PTR_SHIFT          8
00312 #define     VPD_CAP_VPD_ADDR_MASK           0x7FFF
00313 #define     VPD_CAP_VPD_ADDR_SHIFT          16
00314 #define     VPD_CAP_VPD_FLAG                0x80000000
00315 
00316 #define REG_VPD_DATA                0x70
00317 
00318 #define REG_SPI_FLASH_CTRL          0x200
00319 #define     SPI_FLASH_CTRL_STS_NON_RDY      0x1
00320 #define     SPI_FLASH_CTRL_STS_WEN          0x2
00321 #define     SPI_FLASH_CTRL_STS_WPEN         0x80
00322 #define     SPI_FLASH_CTRL_DEV_STS_MASK     0xFF
00323 #define     SPI_FLASH_CTRL_DEV_STS_SHIFT    0
00324 #define     SPI_FLASH_CTRL_INS_MASK         0x7
00325 #define     SPI_FLASH_CTRL_INS_SHIFT        8
00326 #define     SPI_FLASH_CTRL_START            0x800
00327 #define     SPI_FLASH_CTRL_EN_VPD           0x2000
00328 #define     SPI_FLASH_CTRL_LDSTART          0x8000
00329 #define     SPI_FLASH_CTRL_CS_HI_MASK       0x3
00330 #define     SPI_FLASH_CTRL_CS_HI_SHIFT      16
00331 #define     SPI_FLASH_CTRL_CS_HOLD_MASK     0x3
00332 #define     SPI_FLASH_CTRL_CS_HOLD_SHIFT    18
00333 #define     SPI_FLASH_CTRL_CLK_LO_MASK      0x3
00334 #define     SPI_FLASH_CTRL_CLK_LO_SHIFT     20
00335 #define     SPI_FLASH_CTRL_CLK_HI_MASK      0x3
00336 #define     SPI_FLASH_CTRL_CLK_HI_SHIFT     22
00337 #define     SPI_FLASH_CTRL_CS_SETUP_MASK    0x3
00338 #define     SPI_FLASH_CTRL_CS_SETUP_SHIFT   24
00339 #define     SPI_FLASH_CTRL_EROM_PGSZ_MASK   0x3
00340 #define     SPI_FLASH_CTRL_EROM_PGSZ_SHIFT  26
00341 #define     SPI_FLASH_CTRL_WAIT_READY       0x10000000
00342 
00343 #define REG_SPI_ADDR                0x204
00344 
00345 #define REG_SPI_DATA                0x208
00346 
00347 #define REG_SPI_FLASH_CONFIG        0x20C
00348 #define     SPI_FLASH_CONFIG_LD_ADDR_MASK   0xFFFFFF
00349 #define     SPI_FLASH_CONFIG_LD_ADDR_SHIFT  0
00350 #define     SPI_FLASH_CONFIG_VPD_ADDR_MASK  0x3
00351 #define     SPI_FLASH_CONFIG_VPD_ADDR_SHIFT 24
00352 #define     SPI_FLASH_CONFIG_LD_EXIST       0x4000000
00353 
00354 
00355 #define REG_SPI_FLASH_OP_PROGRAM    0x210
00356 #define REG_SPI_FLASH_OP_SC_ERASE   0x211
00357 #define REG_SPI_FLASH_OP_CHIP_ERASE 0x212
00358 #define REG_SPI_FLASH_OP_RDID       0x213
00359 #define REG_SPI_FLASH_OP_WREN       0x214
00360 #define REG_SPI_FLASH_OP_RDSR       0x215
00361 #define REG_SPI_FLASH_OP_WRSR       0x216
00362 #define REG_SPI_FLASH_OP_READ       0x217
00363 
00364 #define REG_TWSI_CTRL               0x218
00365 #define     TWSI_CTRL_LD_OFFSET_MASK        0xFF
00366 #define     TWSI_CTRL_LD_OFFSET_SHIFT       0
00367 #define     TWSI_CTRL_LD_SLV_ADDR_MASK      0x7
00368 #define     TWSI_CTRL_LD_SLV_ADDR_SHIFT     8
00369 #define     TWSI_CTRL_SW_LDSTART            0x800
00370 #define     TWSI_CTRL_HW_LDSTART            0x1000
00371 #define     TWSI_CTRL_SMB_SLV_ADDR_MASK     0x0x7F
00372 #define     TWSI_CTRL_SMB_SLV_ADDR_SHIFT    15
00373 #define     TWSI_CTRL_LD_EXIST              0x400000
00374 #define     TWSI_CTRL_READ_FREQ_SEL_MASK    0x3
00375 #define     TWSI_CTRL_READ_FREQ_SEL_SHIFT   23
00376 #define     TWSI_CTRL_FREQ_SEL_100K         0
00377 #define     TWSI_CTRL_FREQ_SEL_200K         1
00378 #define     TWSI_CTRL_FREQ_SEL_300K         2
00379 #define     TWSI_CTRL_FREQ_SEL_400K         3
00380 #define     TWSI_CTRL_SMB_SLV_ADDR
00381 #define     TWSI_CTRL_WRITE_FREQ_SEL_MASK   0x3
00382 #define     TWSI_CTRL_WRITE_FREQ_SEL_SHIFT  24
00383 
00384 
00385 #define REG_PCIE_DEV_MISC_CTRL      0x21C
00386 #define     PCIE_DEV_MISC_CTRL_EXT_PIPE     0x2
00387 #define     PCIE_DEV_MISC_CTRL_RETRY_BUFDIS 0x1
00388 #define     PCIE_DEV_MISC_CTRL_SPIROM_EXIST 0x4
00389 #define     PCIE_DEV_MISC_CTRL_SERDES_ENDIAN    0x8
00390 #define     PCIE_DEV_MISC_CTRL_SERDES_SEL_DIN   0x10
00391 
00392 #define REG_PCIE_PHYMISC            0x1000
00393 #define PCIE_PHYMISC_FORCE_RCV_DET      0x4
00394 
00395 #define REG_LTSSM_TEST_MODE         0x12FC
00396 #define         LTSSM_TEST_MODE_DEF     0xE000
00397 
00398 /* Selene Master Control Register */
00399 #define REG_MASTER_CTRL             0x1400
00400 #define     MASTER_CTRL_SOFT_RST            0x1
00401 #define     MASTER_CTRL_MTIMER_EN           0x2
00402 #define     MASTER_CTRL_ITIMER_EN           0x4
00403 #define     MASTER_CTRL_MANUAL_INT          0x8
00404 #define     MASTER_CTRL_ITIMER2_EN          0x20
00405 #define     MASTER_CTRL_INT_RDCLR           0x40
00406 #define     MASTER_CTRL_LED_MODE            0x200
00407 #define     MASTER_CTRL_REV_NUM_SHIFT       16
00408 #define     MASTER_CTRL_REV_NUM_MASK        0xff
00409 #define     MASTER_CTRL_DEV_ID_SHIFT        24
00410 #define     MASTER_CTRL_DEV_ID_MASK         0xff
00411 
00412 /* Timer Initial Value Register */
00413 #define REG_MANUAL_TIMER_INIT       0x1404
00414 
00415 
00416 /* IRQ ModeratorTimer Initial Value Register */
00417 #define REG_IRQ_MODU_TIMER_INIT     0x1408   /* w */
00418 #define REG_IRQ_MODU_TIMER2_INIT    0x140A   /* w */
00419 
00420 
00421 #define REG_GPHY_CTRL               0x140C
00422 #define     GPHY_CTRL_EXT_RESET         1
00423 #define     GPHY_CTRL_PIPE_MOD          2
00424 #define     GPHY_CTRL_TEST_MODE_MASK    3
00425 #define     GPHY_CTRL_TEST_MODE_SHIFT   2
00426 #define     GPHY_CTRL_BERT_START        0x10
00427 #define     GPHY_CTRL_GATE_25M_EN       0x20
00428 #define     GPHY_CTRL_LPW_EXIT          0x40
00429 #define     GPHY_CTRL_PHY_IDDQ          0x80
00430 #define     GPHY_CTRL_PHY_IDDQ_DIS      0x100
00431 #define     GPHY_CTRL_PCLK_SEL_DIS      0x200
00432 #define     GPHY_CTRL_HIB_EN            0x400
00433 #define     GPHY_CTRL_HIB_PULSE         0x800
00434 #define     GPHY_CTRL_SEL_ANA_RST       0x1000
00435 #define     GPHY_CTRL_PHY_PLL_ON        0x2000
00436 #define     GPHY_CTRL_PWDOWN_HW         0x4000
00437 #define     GPHY_CTRL_DEFAULT (\
00438                 GPHY_CTRL_PHY_PLL_ON    |\
00439                 GPHY_CTRL_SEL_ANA_RST   |\
00440                 GPHY_CTRL_HIB_PULSE     |\
00441                 GPHY_CTRL_HIB_EN)
00442 
00443 #define     GPHY_CTRL_PW_WOL_DIS (\
00444                 GPHY_CTRL_PHY_PLL_ON    |\
00445                 GPHY_CTRL_SEL_ANA_RST   |\
00446                 GPHY_CTRL_HIB_PULSE     |\
00447                 GPHY_CTRL_HIB_EN        |\
00448                 GPHY_CTRL_PWDOWN_HW     |\
00449                 GPHY_CTRL_PCLK_SEL_DIS  |\
00450                 GPHY_CTRL_PHY_IDDQ)
00451 
00452 /* IRQ Anti-Lost Timer Initial Value Register */
00453 #define REG_CMBDISDMA_TIMER         0x140E
00454 
00455 
00456 /* Block IDLE Status Register */
00457 #define REG_IDLE_STATUS         0x1410
00458 #define     IDLE_STATUS_RXMAC       1    /* 1: RXMAC state machine is in non-IDLE state. 0: RXMAC is idling */
00459 #define     IDLE_STATUS_TXMAC       2    /* 1: TXMAC state machine is in non-IDLE state. 0: TXMAC is idling */
00460 #define     IDLE_STATUS_RXQ         4    /* 1: RXQ state machine is in non-IDLE state.   0: RXQ is idling   */
00461 #define     IDLE_STATUS_TXQ         8    /* 1: TXQ state machine is in non-IDLE state.   0: TXQ is idling   */
00462 #define     IDLE_STATUS_DMAR        0x10 /* 1: DMAR state machine is in non-IDLE state.  0: DMAR is idling  */
00463 #define     IDLE_STATUS_DMAW        0x20 /* 1: DMAW state machine is in non-IDLE state.  0: DMAW is idling  */
00464 #define     IDLE_STATUS_SMB         0x40 /* 1: SMB state machine is in non-IDLE state.   0: SMB is idling   */
00465 #define     IDLE_STATUS_CMB         0x80 /* 1: CMB state machine is in non-IDLE state.   0: CMB is idling   */
00466 
00467 /* MDIO Control Register */
00468 #define REG_MDIO_CTRL           0x1414
00469 #define     MDIO_DATA_MASK          0xffff  /* On MDIO write, the 16-bit control data to write to PHY MII management register */
00470 #define     MDIO_DATA_SHIFT         0       /* On MDIO read, the 16-bit status data that was read from the PHY MII management register*/
00471 #define     MDIO_REG_ADDR_MASK      0x1f    /* MDIO register address */
00472 #define     MDIO_REG_ADDR_SHIFT     16
00473 #define     MDIO_RW                 0x200000      /* 1: read, 0: write */
00474 #define     MDIO_SUP_PREAMBLE       0x400000      /* Suppress preamble */
00475 #define     MDIO_START              0x800000      /* Write 1 to initiate the MDIO master. And this bit is self cleared after one cycle*/
00476 #define     MDIO_CLK_SEL_SHIFT      24
00477 #define     MDIO_CLK_25_4           0
00478 #define     MDIO_CLK_25_6           2
00479 #define     MDIO_CLK_25_8           3
00480 #define     MDIO_CLK_25_10          4
00481 #define     MDIO_CLK_25_14          5
00482 #define     MDIO_CLK_25_20          6
00483 #define     MDIO_CLK_25_28          7
00484 #define     MDIO_BUSY               0x8000000
00485 #define     MDIO_AP_EN              0x10000000
00486 #define MDIO_WAIT_TIMES         10
00487 
00488 /* MII PHY Status Register */
00489 #define REG_PHY_STATUS           0x1418
00490 #define     PHY_STATUS_100M           0x20000
00491 #define     PHY_STATUS_EMI_CA         0x40000
00492 
00493 /* BIST Control and Status Register0 (for the Packet Memory) */
00494 #define REG_BIST0_CTRL              0x141c
00495 #define     BIST0_NOW                   0x1 /* 1: To trigger BIST0 logic. This bit stays high during the */
00496 /* BIST process and reset to zero when BIST is done */
00497 #define     BIST0_SRAM_FAIL             0x2 /* 1: The SRAM failure is un-repairable because it has address */
00498 /* decoder failure or more than 1 cell stuck-to-x failure */
00499 #define     BIST0_FUSE_FLAG             0x4 /* 1: Indicating one cell has been fixed */
00500 
00501 /* BIST Control and Status Register1(for the retry buffer of PCI Express) */
00502 #define REG_BIST1_CTRL              0x1420
00503 #define     BIST1_NOW                   0x1 /* 1: To trigger BIST0 logic. This bit stays high during the */
00504 /* BIST process and reset to zero when BIST is done */
00505 #define     BIST1_SRAM_FAIL             0x2 /* 1: The SRAM failure is un-repairable because it has address */
00506 /* decoder failure or more than 1 cell stuck-to-x failure.*/
00507 #define     BIST1_FUSE_FLAG             0x4
00508 
00509 /* SerDes Lock Detect Control and Status Register */
00510 #define REG_SERDES_LOCK             0x1424
00511 #define     SERDES_LOCK_DETECT          1  /* 1: SerDes lock detected . This signal comes from Analog SerDes */
00512 #define     SERDES_LOCK_DETECT_EN       2  /* 1: Enable SerDes Lock detect function */
00513 
00514 /* MAC Control Register  */
00515 #define REG_MAC_CTRL                0x1480
00516 #define     MAC_CTRL_TX_EN              1  /* 1: Transmit Enable */
00517 #define     MAC_CTRL_RX_EN              2  /* 1: Receive Enable */
00518 #define     MAC_CTRL_TX_FLOW            4  /* 1: Transmit Flow Control Enable */
00519 #define     MAC_CTRL_RX_FLOW            8  /* 1: Receive Flow Control Enable */
00520 #define     MAC_CTRL_LOOPBACK           0x10      /* 1: Loop back at G/MII Interface */
00521 #define     MAC_CTRL_DUPLX              0x20      /* 1: Full-duplex mode  0: Half-duplex mode */
00522 #define     MAC_CTRL_ADD_CRC            0x40      /* 1: Instruct MAC to attach CRC on all egress Ethernet frames */
00523 #define     MAC_CTRL_PAD                0x80      /* 1: Instruct MAC to pad short frames to 60-bytes, and then attach CRC. This bit has higher priority over CRC_EN */
00524 #define     MAC_CTRL_LENCHK             0x100     /* 1: Instruct MAC to check if length field matches the real packet length */
00525 #define     MAC_CTRL_HUGE_EN            0x200     /* 1: receive Jumbo frame enable */
00526 #define     MAC_CTRL_PRMLEN_SHIFT       10        /* Preamble length */
00527 #define     MAC_CTRL_PRMLEN_MASK        0xf
00528 #define     MAC_CTRL_RMV_VLAN           0x4000    /* 1: to remove VLAN Tag automatically from all receive packets */
00529 #define     MAC_CTRL_PROMIS_EN          0x8000    /* 1: Promiscuous Mode Enable */
00530 #define     MAC_CTRL_TX_PAUSE           0x10000   /* 1: transmit test pause */
00531 #define     MAC_CTRL_SCNT               0x20000   /* 1: shortcut slot time counter */
00532 #define     MAC_CTRL_SRST_TX            0x40000   /* 1: synchronized reset Transmit MAC module */
00533 #define     MAC_CTRL_TX_SIMURST         0x80000   /* 1: transmit simulation reset */
00534 #define     MAC_CTRL_SPEED_SHIFT        20        /* 10: gigabit 01:10M/100M */
00535 #define     MAC_CTRL_SPEED_MASK         0x300000
00536 #define     MAC_CTRL_SPEED_1000         2
00537 #define     MAC_CTRL_SPEED_10_100       1
00538 #define     MAC_CTRL_DBG_TX_BKPRESURE   0x400000  /* 1: transmit maximum backoff (half-duplex test bit) */
00539 #define     MAC_CTRL_TX_HUGE            0x800000  /* 1: transmit huge enable */
00540 #define     MAC_CTRL_RX_CHKSUM_EN       0x1000000 /* 1: RX checksum enable */
00541 #define     MAC_CTRL_MC_ALL_EN          0x2000000 /* 1: upload all multicast frame without error to system */
00542 #define     MAC_CTRL_BC_EN              0x4000000 /* 1: upload all broadcast frame without error to system */
00543 #define     MAC_CTRL_DBG                0x8000000 /* 1: upload all received frame to system (Debug Mode) */
00544 
00545 /* MAC IPG/IFG Control Register  */
00546 #define REG_MAC_IPG_IFG             0x1484
00547 #define     MAC_IPG_IFG_IPGT_SHIFT      0     /* Desired back to back inter-packet gap. The default is 96-bit time */
00548 #define     MAC_IPG_IFG_IPGT_MASK       0x7f
00549 #define     MAC_IPG_IFG_MIFG_SHIFT      8     /* Minimum number of IFG to enforce in between RX frames */
00550 #define     MAC_IPG_IFG_MIFG_MASK       0xff  /* Frame gap below such IFP is dropped */
00551 #define     MAC_IPG_IFG_IPGR1_SHIFT     16    /* 64bit Carrier-Sense window */
00552 #define     MAC_IPG_IFG_IPGR1_MASK      0x7f
00553 #define     MAC_IPG_IFG_IPGR2_SHIFT     24    /* 96-bit IPG window */
00554 #define     MAC_IPG_IFG_IPGR2_MASK      0x7f
00555 
00556 /* MAC STATION ADDRESS  */
00557 #define REG_MAC_STA_ADDR            0x1488
00558 
00559 /* Hash table for multicast address */
00560 #define REG_RX_HASH_TABLE           0x1490
00561 
00562 
00563 /* MAC Half-Duplex Control Register */
00564 #define REG_MAC_HALF_DUPLX_CTRL     0x1498
00565 #define     MAC_HALF_DUPLX_CTRL_LCOL_SHIFT   0      /* Collision Window */
00566 #define     MAC_HALF_DUPLX_CTRL_LCOL_MASK    0x3ff
00567 #define     MAC_HALF_DUPLX_CTRL_RETRY_SHIFT  12     /* Retransmission maximum, afterwards the packet will be discarded */
00568 #define     MAC_HALF_DUPLX_CTRL_RETRY_MASK   0xf
00569 #define     MAC_HALF_DUPLX_CTRL_EXC_DEF_EN   0x10000 /* 1: Allow the transmission of a packet which has been excessively deferred */
00570 #define     MAC_HALF_DUPLX_CTRL_NO_BACK_C    0x20000 /* 1: No back-off on collision, immediately start the retransmission */
00571 #define     MAC_HALF_DUPLX_CTRL_NO_BACK_P    0x40000 /* 1: No back-off on backpressure, immediately start the transmission after back pressure */
00572 #define     MAC_HALF_DUPLX_CTRL_ABEBE        0x80000 /* 1: Alternative Binary Exponential Back-off Enabled */
00573 #define     MAC_HALF_DUPLX_CTRL_ABEBT_SHIFT  20      /* Maximum binary exponential number */
00574 #define     MAC_HALF_DUPLX_CTRL_ABEBT_MASK   0xf
00575 #define     MAC_HALF_DUPLX_CTRL_JAMIPG_SHIFT 24      /* IPG to start JAM for collision based flow control in half-duplex */
00576 #define     MAC_HALF_DUPLX_CTRL_JAMIPG_MASK  0xf     /* mode. In unit of 8-bit time */
00577 
00578 /* Maximum Frame Length Control Register   */
00579 #define REG_MTU                     0x149c
00580 
00581 /* Wake-On-Lan control register */
00582 #define REG_WOL_CTRL                0x14a0
00583 #define     WOL_PATTERN_EN                  0x00000001
00584 #define     WOL_PATTERN_PME_EN              0x00000002
00585 #define     WOL_MAGIC_EN                    0x00000004
00586 #define     WOL_MAGIC_PME_EN                0x00000008
00587 #define     WOL_LINK_CHG_EN                 0x00000010
00588 #define     WOL_LINK_CHG_PME_EN             0x00000020
00589 #define     WOL_PATTERN_ST                  0x00000100
00590 #define     WOL_MAGIC_ST                    0x00000200
00591 #define     WOL_LINKCHG_ST                  0x00000400
00592 #define     WOL_CLK_SWITCH_EN               0x00008000
00593 #define     WOL_PT0_EN                      0x00010000
00594 #define     WOL_PT1_EN                      0x00020000
00595 #define     WOL_PT2_EN                      0x00040000
00596 #define     WOL_PT3_EN                      0x00080000
00597 #define     WOL_PT4_EN                      0x00100000
00598 #define     WOL_PT5_EN                      0x00200000
00599 #define     WOL_PT6_EN                      0x00400000
00600 /* WOL Length ( 2 DWORD ) */
00601 #define REG_WOL_PATTERN_LEN         0x14a4
00602 #define     WOL_PT_LEN_MASK                 0x7f
00603 #define     WOL_PT0_LEN_SHIFT               0
00604 #define     WOL_PT1_LEN_SHIFT               8
00605 #define     WOL_PT2_LEN_SHIFT               16
00606 #define     WOL_PT3_LEN_SHIFT               24
00607 #define     WOL_PT4_LEN_SHIFT               0
00608 #define     WOL_PT5_LEN_SHIFT               8
00609 #define     WOL_PT6_LEN_SHIFT               16
00610 
00611 /* Internal SRAM Partition Register */
00612 #define REG_SRAM_TRD_ADDR           0x1518
00613 #define REG_SRAM_TRD_LEN            0x151C
00614 #define REG_SRAM_RXF_ADDR           0x1520
00615 #define REG_SRAM_RXF_LEN            0x1524
00616 #define REG_SRAM_TXF_ADDR           0x1528
00617 #define REG_SRAM_TXF_LEN            0x152C
00618 #define REG_SRAM_TCPH_ADDR          0x1530
00619 #define REG_SRAM_PKTH_ADDR          0x1532
00620 
00621 /* Load Ptr Register */
00622 #define REG_LOAD_PTR                0x1534  /* Software sets this bit after the initialization of the head and tail */
00623 
00624 /*
00625  * addresses of all descriptors, as well as the following descriptor
00626  * control register, which triggers each function block to load the head
00627  * pointer to prepare for the operation. This bit is then self-cleared
00628  * after one cycle.
00629  */
00630 
00631 /* Descriptor Control register  */
00632 #define REG_RXF3_BASE_ADDR_HI           0x153C
00633 #define REG_DESC_BASE_ADDR_HI           0x1540
00634 #define REG_RXF0_BASE_ADDR_HI           0x1540 /* share with DESC BASE ADDR HI */
00635 #define REG_HOST_RXF0_PAGE0_LO          0x1544
00636 #define REG_HOST_RXF0_PAGE1_LO          0x1548
00637 #define REG_TPD_BASE_ADDR_LO            0x154C
00638 #define REG_RXF1_BASE_ADDR_HI           0x1550
00639 #define REG_RXF2_BASE_ADDR_HI           0x1554
00640 #define REG_HOST_RXFPAGE_SIZE           0x1558
00641 #define REG_TPD_RING_SIZE               0x155C
00642 /* RSS about */
00643 #define REG_RSS_KEY0                    0x14B0
00644 #define REG_RSS_KEY1                    0x14B4
00645 #define REG_RSS_KEY2                    0x14B8
00646 #define REG_RSS_KEY3                    0x14BC
00647 #define REG_RSS_KEY4                    0x14C0
00648 #define REG_RSS_KEY5                    0x14C4
00649 #define REG_RSS_KEY6                    0x14C8
00650 #define REG_RSS_KEY7                    0x14CC
00651 #define REG_RSS_KEY8                    0x14D0
00652 #define REG_RSS_KEY9                    0x14D4
00653 #define REG_IDT_TABLE4                  0x14E0
00654 #define REG_IDT_TABLE5                  0x14E4
00655 #define REG_IDT_TABLE6                  0x14E8
00656 #define REG_IDT_TABLE7                  0x14EC
00657 #define REG_IDT_TABLE0                  0x1560
00658 #define REG_IDT_TABLE1                  0x1564
00659 #define REG_IDT_TABLE2                  0x1568
00660 #define REG_IDT_TABLE3                  0x156C
00661 #define REG_IDT_TABLE                   REG_IDT_TABLE0
00662 #define REG_RSS_HASH_VALUE              0x1570
00663 #define REG_RSS_HASH_FLAG               0x1574
00664 #define REG_BASE_CPU_NUMBER             0x157C
00665 
00666 
00667 /* TXQ Control Register */
00668 #define REG_TXQ_CTRL                0x1580
00669 #define     TXQ_CTRL_NUM_TPD_BURST_MASK     0xF
00670 #define     TXQ_CTRL_NUM_TPD_BURST_SHIFT    0
00671 #define     TXQ_CTRL_EN                     0x20  /* 1: Enable TXQ */
00672 #define     TXQ_CTRL_ENH_MODE               0x40  /* Performance enhancement mode, in which up to two back-to-back DMA read commands might be dispatched. */
00673 #define     TXQ_CTRL_TXF_BURST_NUM_SHIFT    16    /* Number of data byte to read in a cache-aligned burst. Each SRAM entry is 8-byte in length. */
00674 #define     TXQ_CTRL_TXF_BURST_NUM_MASK     0xffff
00675 
00676 /* Jumbo packet Threshold for task offload */
00677 #define REG_TX_EARLY_TH                     0x1584 /* Jumbo frame threshold in QWORD unit. Packet greater than */
00678 /* JUMBO_TASK_OFFLOAD_THRESHOLD will not be task offloaded. */
00679 #define     TX_TX_EARLY_TH_MASK             0x7ff
00680 #define     TX_TX_EARLY_TH_SHIFT            0
00681 
00682 
00683 /* RXQ Control Register */
00684 #define REG_RXQ_CTRL                0x15A0
00685 #define         RXQ_CTRL_PBA_ALIGN_32                   0   /* rx-packet alignment */
00686 #define         RXQ_CTRL_PBA_ALIGN_64                   1
00687 #define         RXQ_CTRL_PBA_ALIGN_128                  2
00688 #define         RXQ_CTRL_PBA_ALIGN_256                  3
00689 #define         RXQ_CTRL_Q1_EN                          0x10
00690 #define         RXQ_CTRL_Q2_EN                          0x20
00691 #define         RXQ_CTRL_Q3_EN                          0x40
00692 #define         RXQ_CTRL_IPV6_XSUM_VERIFY_EN            0x80
00693 #define         RXQ_CTRL_HASH_TLEN_SHIFT                8
00694 #define         RXQ_CTRL_HASH_TLEN_MASK                 0xFF
00695 #define         RXQ_CTRL_HASH_TYPE_IPV4                 0x10000
00696 #define         RXQ_CTRL_HASH_TYPE_IPV4_TCP             0x20000
00697 #define         RXQ_CTRL_HASH_TYPE_IPV6                 0x40000
00698 #define         RXQ_CTRL_HASH_TYPE_IPV6_TCP             0x80000
00699 #define         RXQ_CTRL_RSS_MODE_DISABLE               0
00700 #define         RXQ_CTRL_RSS_MODE_SQSINT                0x4000000
00701 #define         RXQ_CTRL_RSS_MODE_MQUESINT              0x8000000
00702 #define         RXQ_CTRL_RSS_MODE_MQUEMINT              0xC000000
00703 #define         RXQ_CTRL_NIP_QUEUE_SEL_TBL              0x10000000
00704 #define         RXQ_CTRL_HASH_ENABLE                    0x20000000
00705 #define         RXQ_CTRL_CUT_THRU_EN                    0x40000000
00706 #define         RXQ_CTRL_EN                             0x80000000
00707 
00708 /* Rx jumbo packet threshold and rrd  retirement timer  */
00709 #define REG_RXQ_JMBOSZ_RRDTIM       0x15A4
00710 /*
00711  * Jumbo packet threshold for non-VLAN packet, in QWORD (64-bit) unit.
00712  * When the packet length greater than or equal to this value, RXQ
00713  * shall start cut-through forwarding of the received packet.
00714  */
00715 #define         RXQ_JMBOSZ_TH_MASK      0x7ff
00716 #define         RXQ_JMBOSZ_TH_SHIFT         0  /* RRD retirement timer. Decrement by 1 after every 512ns passes*/
00717 #define         RXQ_JMBO_LKAH_MASK          0xf
00718 #define         RXQ_JMBO_LKAH_SHIFT         11
00719 
00720 /* RXF flow control register */
00721 #define REG_RXQ_RXF_PAUSE_THRESH    0x15A8
00722 #define     RXQ_RXF_PAUSE_TH_HI_SHIFT       0
00723 #define     RXQ_RXF_PAUSE_TH_HI_MASK        0xfff
00724 #define     RXQ_RXF_PAUSE_TH_LO_SHIFT       16
00725 #define     RXQ_RXF_PAUSE_TH_LO_MASK        0xfff
00726 
00727 
00728 /* DMA Engine Control Register */
00729 #define REG_DMA_CTRL                0x15C0
00730 #define     DMA_CTRL_DMAR_IN_ORDER          0x1
00731 #define     DMA_CTRL_DMAR_ENH_ORDER         0x2
00732 #define     DMA_CTRL_DMAR_OUT_ORDER         0x4
00733 #define     DMA_CTRL_RCB_VALUE              0x8
00734 #define     DMA_CTRL_DMAR_BURST_LEN_SHIFT   4
00735 #define     DMA_CTRL_DMAR_BURST_LEN_MASK    7
00736 #define     DMA_CTRL_DMAW_BURST_LEN_SHIFT   7
00737 #define     DMA_CTRL_DMAW_BURST_LEN_MASK    7
00738 #define     DMA_CTRL_DMAR_REQ_PRI           0x400
00739 #define     DMA_CTRL_DMAR_DLY_CNT_MASK      0x1F
00740 #define     DMA_CTRL_DMAR_DLY_CNT_SHIFT     11
00741 #define     DMA_CTRL_DMAW_DLY_CNT_MASK      0xF
00742 #define     DMA_CTRL_DMAW_DLY_CNT_SHIFT     16
00743 #define     DMA_CTRL_TXCMB_EN               0x100000
00744 #define     DMA_CTRL_RXCMB_EN                           0x200000
00745 
00746 
00747 /* CMB/SMB Control Register */
00748 #define REG_SMB_STAT_TIMER                      0x15C4
00749 #define REG_TRIG_RRD_THRESH                     0x15CA
00750 #define REG_TRIG_TPD_THRESH                     0x15C8
00751 #define REG_TRIG_TXTIMER                        0x15CC
00752 #define REG_TRIG_RXTIMER                        0x15CE
00753 
00754 /* HOST RXF Page 1,2,3 address */
00755 #define REG_HOST_RXF1_PAGE0_LO                  0x15D0
00756 #define REG_HOST_RXF1_PAGE1_LO                  0x15D4
00757 #define REG_HOST_RXF2_PAGE0_LO                  0x15D8
00758 #define REG_HOST_RXF2_PAGE1_LO                  0x15DC
00759 #define REG_HOST_RXF3_PAGE0_LO                  0x15E0
00760 #define REG_HOST_RXF3_PAGE1_LO                  0x15E4
00761 
00762 /* Mail box */
00763 #define REG_MB_RXF1_RADDR                       0x15B4
00764 #define REG_MB_RXF2_RADDR                       0x15B8
00765 #define REG_MB_RXF3_RADDR                       0x15BC
00766 #define REG_MB_TPD_PROD_IDX                     0x15F0
00767 
00768 /* RXF-Page 0-3  PageNo & Valid bit */
00769 #define REG_HOST_RXF0_PAGE0_VLD     0x15F4
00770 #define     HOST_RXF_VALID              1
00771 #define     HOST_RXF_PAGENO_SHIFT       1
00772 #define     HOST_RXF_PAGENO_MASK        0x7F
00773 #define REG_HOST_RXF0_PAGE1_VLD     0x15F5
00774 #define REG_HOST_RXF1_PAGE0_VLD     0x15F6
00775 #define REG_HOST_RXF1_PAGE1_VLD     0x15F7
00776 #define REG_HOST_RXF2_PAGE0_VLD     0x15F8
00777 #define REG_HOST_RXF2_PAGE1_VLD     0x15F9
00778 #define REG_HOST_RXF3_PAGE0_VLD     0x15FA
00779 #define REG_HOST_RXF3_PAGE1_VLD     0x15FB
00780 
00781 /* Interrupt Status Register */
00782 #define REG_ISR    0x1600
00783 #define  ISR_SMB                1
00784 #define  ISR_TIMER              2       /* Interrupt when Timer is counted down to zero */
00785 /*
00786  * Software manual interrupt, for debug. Set when SW_MAN_INT_EN is set
00787  * in Table 51 Selene Master Control Register (Offset 0x1400).
00788  */
00789 #define  ISR_MANUAL             4
00790 #define  ISR_HW_RXF_OV          8        /* RXF overflow interrupt */
00791 #define  ISR_HOST_RXF0_OV       0x10
00792 #define  ISR_HOST_RXF1_OV       0x20
00793 #define  ISR_HOST_RXF2_OV       0x40
00794 #define  ISR_HOST_RXF3_OV       0x80
00795 #define  ISR_TXF_UN             0x100
00796 #define  ISR_RX0_PAGE_FULL      0x200
00797 #define  ISR_DMAR_TO_RST        0x400
00798 #define  ISR_DMAW_TO_RST        0x800
00799 #define  ISR_GPHY               0x1000
00800 #define  ISR_TX_CREDIT          0x2000
00801 #define  ISR_GPHY_LPW           0x4000    /* GPHY low power state interrupt */
00802 #define  ISR_RX_PKT             0x10000   /* One packet received, triggered by RFD */
00803 #define  ISR_TX_PKT             0x20000   /* One packet transmitted, triggered by TPD */
00804 #define  ISR_TX_DMA             0x40000
00805 #define  ISR_RX_PKT_1           0x80000
00806 #define  ISR_RX_PKT_2           0x100000
00807 #define  ISR_RX_PKT_3           0x200000
00808 #define  ISR_MAC_RX             0x400000
00809 #define  ISR_MAC_TX             0x800000
00810 #define  ISR_UR_DETECTED        0x1000000
00811 #define  ISR_FERR_DETECTED      0x2000000
00812 #define  ISR_NFERR_DETECTED     0x4000000
00813 #define  ISR_CERR_DETECTED      0x8000000
00814 #define  ISR_PHY_LINKDOWN       0x10000000
00815 #define  ISR_DIS_INT            0x80000000
00816 
00817 
00818 /* Interrupt Mask Register */
00819 #define REG_IMR 0x1604
00820 
00821 
00822 #define IMR_NORMAL_MASK (\
00823                 ISR_SMB         |\
00824                 ISR_TXF_UN      |\
00825                 ISR_HW_RXF_OV   |\
00826                 ISR_HOST_RXF0_OV|\
00827                 ISR_MANUAL      |\
00828                 ISR_GPHY        |\
00829                 ISR_GPHY_LPW    |\
00830                 ISR_DMAR_TO_RST |\
00831                 ISR_DMAW_TO_RST |\
00832                 ISR_PHY_LINKDOWN|\
00833                 ISR_RX_PKT      |\
00834                 ISR_TX_PKT)
00835 
00836 #define ISR_TX_EVENT (ISR_TXF_UN | ISR_TX_PKT)
00837 #define ISR_RX_EVENT (ISR_HOST_RXF0_OV | ISR_HW_RXF_OV | ISR_RX_PKT)
00838 
00839 #define REG_MAC_RX_STATUS_BIN 0x1700
00840 #define REG_MAC_RX_STATUS_END 0x175c
00841 #define REG_MAC_TX_STATUS_BIN 0x1760
00842 #define REG_MAC_TX_STATUS_END 0x17c0
00843 
00844 /* Hardware Offset Register */
00845 #define REG_HOST_RXF0_PAGEOFF 0x1800
00846 #define REG_TPD_CONS_IDX      0x1804
00847 #define REG_HOST_RXF1_PAGEOFF 0x1808
00848 #define REG_HOST_RXF2_PAGEOFF 0x180C
00849 #define REG_HOST_RXF3_PAGEOFF 0x1810
00850 
00851 /* RXF-Page 0-3 Offset DMA Address */
00852 #define REG_HOST_RXF0_MB0_LO  0x1820
00853 #define REG_HOST_RXF0_MB1_LO  0x1824
00854 #define REG_HOST_RXF1_MB0_LO  0x1828
00855 #define REG_HOST_RXF1_MB1_LO  0x182C
00856 #define REG_HOST_RXF2_MB0_LO  0x1830
00857 #define REG_HOST_RXF2_MB1_LO  0x1834
00858 #define REG_HOST_RXF3_MB0_LO  0x1838
00859 #define REG_HOST_RXF3_MB1_LO  0x183C
00860 
00861 /* Tpd CMB DMA Address */
00862 #define REG_HOST_TX_CMB_LO    0x1840
00863 #define REG_HOST_SMB_ADDR_LO  0x1844
00864 
00865 /* DEBUG ADDR */
00866 #define REG_DEBUG_DATA0 0x1900
00867 #define REG_DEBUG_DATA1 0x1904
00868 
00869 /***************************** MII definition ***************************************/
00870 /* PHY Common Register */
00871 #define MII_BMCR                        0x00
00872 #define MII_BMSR                        0x01
00873 #define MII_PHYSID1                     0x02
00874 #define MII_PHYSID2                     0x03
00875 #define MII_ADVERTISE                   0x04
00876 #define MII_LPA                         0x05
00877 #define MII_EXPANSION                   0x06
00878 #define MII_AT001_CR                    0x09
00879 #define MII_AT001_SR                    0x0A
00880 #define MII_AT001_ESR                   0x0F
00881 #define MII_AT001_PSCR                  0x10
00882 #define MII_AT001_PSSR                  0x11
00883 #define MII_INT_CTRL                    0x12
00884 #define MII_INT_STATUS                  0x13
00885 #define MII_SMARTSPEED                  0x14
00886 #define MII_RERRCOUNTER                 0x15
00887 #define MII_SREVISION                   0x16
00888 #define MII_RESV1                       0x17
00889 #define MII_LBRERROR                    0x18
00890 #define MII_PHYADDR                     0x19
00891 #define MII_RESV2                       0x1a
00892 #define MII_TPISTATUS                   0x1b
00893 #define MII_NCONFIG                     0x1c
00894 
00895 #define MII_DBG_ADDR                    0x1D
00896 #define MII_DBG_DATA                    0x1E
00897 
00898 
00899 /* PHY Control Register */
00900 #define MII_CR_SPEED_SELECT_MSB                  0x0040  /* bits 6,13: 10=1000, 01=100, 00=10 */
00901 #define MII_CR_COLL_TEST_ENABLE                  0x0080  /* Collision test enable */
00902 #define MII_CR_FULL_DUPLEX                       0x0100  /* FDX =1, half duplex =0 */
00903 #define MII_CR_RESTART_AUTO_NEG                  0x0200  /* Restart auto negotiation */
00904 #define MII_CR_ISOLATE                           0x0400  /* Isolate PHY from MII */
00905 #define MII_CR_POWER_DOWN                        0x0800  /* Power down */
00906 #define MII_CR_AUTO_NEG_EN                       0x1000  /* Auto Neg Enable */
00907 #define MII_CR_SPEED_SELECT_LSB                  0x2000  /* bits 6,13: 10=1000, 01=100, 00=10 */
00908 #define MII_CR_LOOPBACK                          0x4000  /* 0 = normal, 1 = loopback */
00909 #define MII_CR_RESET                             0x8000  /* 0 = normal, 1 = PHY reset */
00910 #define MII_CR_SPEED_MASK                        0x2040
00911 #define MII_CR_SPEED_1000                        0x0040
00912 #define MII_CR_SPEED_100                         0x2000
00913 #define MII_CR_SPEED_10                          0x0000
00914 
00915 
00916 /* PHY Status Register */
00917 #define MII_SR_EXTENDED_CAPS                     0x0001  /* Extended register capabilities */
00918 #define MII_SR_JABBER_DETECT                     0x0002  /* Jabber Detected */
00919 #define MII_SR_LINK_STATUS                       0x0004  /* Link Status 1 = link */
00920 #define MII_SR_AUTONEG_CAPS                      0x0008  /* Auto Neg Capable */
00921 #define MII_SR_REMOTE_FAULT                      0x0010  /* Remote Fault Detect */
00922 #define MII_SR_AUTONEG_COMPLETE                  0x0020  /* Auto Neg Complete */
00923 #define MII_SR_PREAMBLE_SUPPRESS                 0x0040  /* Preamble may be suppressed */
00924 #define MII_SR_EXTENDED_STATUS                   0x0100  /* Ext. status info in Reg 0x0F */
00925 #define MII_SR_100T2_HD_CAPS                     0x0200  /* 100T2 Half Duplex Capable */
00926 #define MII_SR_100T2_FD_CAPS                     0x0400  /* 100T2 Full Duplex Capable */
00927 #define MII_SR_10T_HD_CAPS                       0x0800  /* 10T   Half Duplex Capable */
00928 #define MII_SR_10T_FD_CAPS                       0x1000  /* 10T   Full Duplex Capable */
00929 #define MII_SR_100X_HD_CAPS                      0x2000  /* 100X  Half Duplex Capable */
00930 #define MII_SR_100X_FD_CAPS                      0x4000  /* 100X  Full Duplex Capable */
00931 #define MII_SR_100T4_CAPS                        0x8000  /* 100T4 Capable */
00932 
00933 /* Link partner ability register. */
00934 #define MII_LPA_SLCT                             0x001f  /* Same as advertise selector  */
00935 #define MII_LPA_10HALF                           0x0020  /* Can do 10mbps half-duplex   */
00936 #define MII_LPA_10FULL                           0x0040  /* Can do 10mbps full-duplex   */
00937 #define MII_LPA_100HALF                          0x0080  /* Can do 100mbps half-duplex  */
00938 #define MII_LPA_100FULL                          0x0100  /* Can do 100mbps full-duplex  */
00939 #define MII_LPA_100BASE4                         0x0200  /* 100BASE-T4  */
00940 #define MII_LPA_PAUSE                            0x0400  /* PAUSE */
00941 #define MII_LPA_ASYPAUSE                         0x0800  /* Asymmetrical PAUSE */
00942 #define MII_LPA_RFAULT                           0x2000  /* Link partner faulted        */
00943 #define MII_LPA_LPACK                            0x4000  /* Link partner acked us       */
00944 #define MII_LPA_NPAGE                            0x8000  /* Next page bit               */
00945 
00946 /* Autoneg Advertisement Register */
00947 #define MII_AR_SELECTOR_FIELD                   0x0001  /* indicates IEEE 802.3 CSMA/CD */
00948 #define MII_AR_10T_HD_CAPS                      0x0020  /* 10T   Half Duplex Capable */
00949 #define MII_AR_10T_FD_CAPS                      0x0040  /* 10T   Full Duplex Capable */
00950 #define MII_AR_100TX_HD_CAPS                    0x0080  /* 100TX Half Duplex Capable */
00951 #define MII_AR_100TX_FD_CAPS                    0x0100  /* 100TX Full Duplex Capable */
00952 #define MII_AR_100T4_CAPS                       0x0200  /* 100T4 Capable */
00953 #define MII_AR_PAUSE                            0x0400  /* Pause operation desired */
00954 #define MII_AR_ASM_DIR                          0x0800  /* Asymmetric Pause Direction bit */
00955 #define MII_AR_REMOTE_FAULT                     0x2000  /* Remote Fault detected */
00956 #define MII_AR_NEXT_PAGE                        0x8000  /* Next Page ability supported */
00957 #define MII_AR_SPEED_MASK                       0x01E0
00958 #define MII_AR_DEFAULT_CAP_MASK                 0x0DE0
00959 
00960 /* 1000BASE-T Control Register */
00961 #define MII_AT001_CR_1000T_HD_CAPS              0x0100  /* Advertise 1000T HD capability */
00962 #define MII_AT001_CR_1000T_FD_CAPS              0x0200  /* Advertise 1000T FD capability  */
00963 #define MII_AT001_CR_1000T_REPEATER_DTE         0x0400  /* 1=Repeater/switch device port */
00964 /* 0=DTE device */
00965 #define MII_AT001_CR_1000T_MS_VALUE             0x0800  /* 1=Configure PHY as Master */
00966 /* 0=Configure PHY as Slave */
00967 #define MII_AT001_CR_1000T_MS_ENABLE            0x1000  /* 1=Master/Slave manual config value */
00968 /* 0=Automatic Master/Slave config */
00969 #define MII_AT001_CR_1000T_TEST_MODE_NORMAL     0x0000  /* Normal Operation */
00970 #define MII_AT001_CR_1000T_TEST_MODE_1          0x2000  /* Transmit Waveform test */
00971 #define MII_AT001_CR_1000T_TEST_MODE_2          0x4000  /* Master Transmit Jitter test */
00972 #define MII_AT001_CR_1000T_TEST_MODE_3          0x6000  /* Slave Transmit Jitter test */
00973 #define MII_AT001_CR_1000T_TEST_MODE_4          0x8000  /* Transmitter Distortion test */
00974 #define MII_AT001_CR_1000T_SPEED_MASK           0x0300
00975 #define MII_AT001_CR_1000T_DEFAULT_CAP_MASK     0x0300
00976 
00977 /* 1000BASE-T Status Register */
00978 #define MII_AT001_SR_1000T_LP_HD_CAPS           0x0400  /* LP is 1000T HD capable */
00979 #define MII_AT001_SR_1000T_LP_FD_CAPS           0x0800  /* LP is 1000T FD capable */
00980 #define MII_AT001_SR_1000T_REMOTE_RX_STATUS     0x1000  /* Remote receiver OK */
00981 #define MII_AT001_SR_1000T_LOCAL_RX_STATUS      0x2000  /* Local receiver OK */
00982 #define MII_AT001_SR_1000T_MS_CONFIG_RES        0x4000  /* 1=Local TX is Master, 0=Slave */
00983 #define MII_AT001_SR_1000T_MS_CONFIG_FAULT      0x8000  /* Master/Slave config fault */
00984 #define MII_AT001_SR_1000T_REMOTE_RX_STATUS_SHIFT   12
00985 #define MII_AT001_SR_1000T_LOCAL_RX_STATUS_SHIFT    13
00986 
00987 /* Extended Status Register */
00988 #define MII_AT001_ESR_1000T_HD_CAPS             0x1000  /* 1000T HD capable */
00989 #define MII_AT001_ESR_1000T_FD_CAPS             0x2000  /* 1000T FD capable */
00990 #define MII_AT001_ESR_1000X_HD_CAPS             0x4000  /* 1000X HD capable */
00991 #define MII_AT001_ESR_1000X_FD_CAPS             0x8000  /* 1000X FD capable */
00992 
00993 /* AT001 PHY Specific Control Register */
00994 #define MII_AT001_PSCR_JABBER_DISABLE           0x0001  /* 1=Jabber Function disabled */
00995 #define MII_AT001_PSCR_POLARITY_REVERSAL        0x0002  /* 1=Polarity Reversal enabled */
00996 #define MII_AT001_PSCR_SQE_TEST                 0x0004  /* 1=SQE Test enabled */
00997 #define MII_AT001_PSCR_MAC_POWERDOWN            0x0008
00998 #define MII_AT001_PSCR_CLK125_DISABLE           0x0010  /* 1=CLK125 low,
00999                                                          * 0=CLK125 toggling
01000                                                          */
01001 #define MII_AT001_PSCR_MDI_MANUAL_MODE          0x0000  /* MDI Crossover Mode bits 6:5 */
01002 /* Manual MDI configuration */
01003 #define MII_AT001_PSCR_MDIX_MANUAL_MODE         0x0020  /* Manual MDIX configuration */
01004 #define MII_AT001_PSCR_AUTO_X_1000T             0x0040  /* 1000BASE-T: Auto crossover,
01005                                                          *  100BASE-TX/10BASE-T:
01006                                                          *  MDI Mode
01007                                                          */
01008 #define MII_AT001_PSCR_AUTO_X_MODE              0x0060  /* Auto crossover enabled
01009                                                          * all speeds.
01010                                                          */
01011 #define MII_AT001_PSCR_10BT_EXT_DIST_ENABLE     0x0080
01012 /* 1=Enable Extended 10BASE-T distance
01013  * (Lower 10BASE-T RX Threshold)
01014  * 0=Normal 10BASE-T RX Threshold */
01015 #define MII_AT001_PSCR_MII_5BIT_ENABLE          0x0100
01016 /* 1=5-Bit interface in 100BASE-TX
01017  * 0=MII interface in 100BASE-TX */
01018 #define MII_AT001_PSCR_SCRAMBLER_DISABLE        0x0200  /* 1=Scrambler disable */
01019 #define MII_AT001_PSCR_FORCE_LINK_GOOD          0x0400  /* 1=Force link good */
01020 #define MII_AT001_PSCR_ASSERT_CRS_ON_TX         0x0800  /* 1=Assert CRS on Transmit */
01021 #define MII_AT001_PSCR_POLARITY_REVERSAL_SHIFT    1
01022 #define MII_AT001_PSCR_AUTO_X_MODE_SHIFT          5
01023 #define MII_AT001_PSCR_10BT_EXT_DIST_ENABLE_SHIFT 7
01024 /* AT001 PHY Specific Status Register */
01025 #define MII_AT001_PSSR_SPD_DPLX_RESOLVED        0x0800  /* 1=Speed & Duplex resolved */
01026 #define MII_AT001_PSSR_DPLX                     0x2000  /* 1=Duplex 0=Half Duplex */
01027 #define MII_AT001_PSSR_SPEED                    0xC000  /* Speed, bits 14:15 */
01028 #define MII_AT001_PSSR_10MBS                    0x0000  /* 00=10Mbs */
01029 #define MII_AT001_PSSR_100MBS                   0x4000  /* 01=100Mbs */
01030 #define MII_AT001_PSSR_1000MBS                  0x8000  /* 10=1000Mbs */
01031 
01032 
01033 #endif /* _ATL1_E_H_ */