iPXE
atl1e.c
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00001 /*
00002  * Copyright(c) 2007 Atheros Corporation. All rights reserved.
00003  *
00004  * Derived from Intel e1000 driver
00005  * Copyright(c) 1999 - 2005 Intel Corporation. All rights reserved.
00006  *
00007  * Modified for iPXE, October 2009 by Joshua Oreman <oremanj@rwcr.net>.
00008  *
00009  * This program is free software; you can redistribute it and/or modify it
00010  * under the terms of the GNU General Public License as published by the Free
00011  * Software Foundation; either version 2 of the License, or (at your option)
00012  * any later version.
00013  *
00014  * This program is distributed in the hope that it will be useful, but WITHOUT
00015  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
00016  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
00017  * more details.
00018  *
00019  * You should have received a copy of the GNU General Public License along with
00020  * this program; if not, write to the Free Software Foundation, Inc., 51
00021  * Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
00022  */
00023 
00024 FILE_LICENCE ( GPL2_OR_LATER );
00025 
00026 #include "atl1e.h"
00027 
00028 /* User-tweakable parameters: */
00029 #define TX_DESC_COUNT   32      /* TX descriptors, minimum 32 */
00030 #define RX_MEM_SIZE     8192    /* RX area size, minimum 8kb */
00031 #define MAX_FRAME_SIZE  1500    /* Maximum MTU supported, minimum 1500 */
00032 
00033 /* Arcane parameters: */
00034 #define PREAMBLE_LEN    7
00035 #define RX_JUMBO_THRESH ((MAX_FRAME_SIZE + ETH_HLEN + \
00036                           VLAN_HLEN + ETH_FCS_LEN + 7) >> 3)
00037 #define IMT_VAL         100     /* interrupt moderator timer, us */
00038 #define ICT_VAL         50000   /* interrupt clear timer, us */
00039 #define SMB_TIMER       200000
00040 #define RRD_THRESH      1       /* packets to queue before interrupt */
00041 #define TPD_BURST       5
00042 #define TPD_THRESH      (TX_DESC_COUNT / 2)
00043 #define RX_COUNT_DOWN   4
00044 #define TX_COUNT_DOWN   (IMT_VAL * 4 / 3)
00045 #define DMAR_DLY_CNT    15
00046 #define DMAW_DLY_CNT    4
00047 
00048 #define PCI_DEVICE_ID_ATTANSIC_L1E      0x1026
00049 
00050 /*
00051  * atl1e_pci_tbl - PCI Device ID Table
00052  *
00053  * Wildcard entries (PCI_ANY_ID) should come last
00054  * Last entry must be all 0s
00055  *
00056  * { Vendor ID, Device ID, SubVendor ID, SubDevice ID,
00057  *   Class, Class Mask, private data (not used) }
00058  */
00059 static struct pci_device_id atl1e_pci_tbl[] = {
00060         PCI_ROM(0x1969, 0x1026, "atl1e_26", "Attansic L1E 0x1026", 0),
00061         PCI_ROM(0x1969, 0x1066, "atl1e_66", "Attansic L1E 0x1066", 0),
00062 };
00063 
00064 static void atl1e_setup_mac_ctrl(struct atl1e_adapter *adapter);
00065 
00066 static const u16
00067 atl1e_rx_page_vld_regs[AT_PAGE_NUM_PER_QUEUE] =
00068 {
00069         REG_HOST_RXF0_PAGE0_VLD, REG_HOST_RXF0_PAGE1_VLD
00070 };
00071 
00072 static const u16
00073 atl1e_rx_page_lo_addr_regs[AT_PAGE_NUM_PER_QUEUE] =
00074 {
00075         REG_HOST_RXF0_PAGE0_LO, REG_HOST_RXF0_PAGE1_LO
00076 };
00077 
00078 static const u16
00079 atl1e_rx_page_write_offset_regs[AT_PAGE_NUM_PER_QUEUE] =
00080 {
00081         REG_HOST_RXF0_MB0_LO,  REG_HOST_RXF0_MB1_LO
00082 };
00083 
00084 static const u16 atl1e_pay_load_size[] = {
00085         128, 256, 512, 1024, 2048, 4096,
00086 };
00087 
00088 /*
00089  * atl1e_irq_enable - Enable default interrupt generation settings
00090  * @adapter: board private structure
00091  */
00092 static inline void atl1e_irq_enable(struct atl1e_adapter *adapter)
00093 {
00094         AT_WRITE_REG(&adapter->hw, REG_ISR, 0);
00095         AT_WRITE_REG(&adapter->hw, REG_IMR, IMR_NORMAL_MASK);
00096         AT_WRITE_FLUSH(&adapter->hw);
00097 }
00098 
00099 /*
00100  * atl1e_irq_disable - Mask off interrupt generation on the NIC
00101  * @adapter: board private structure
00102  */
00103 static inline void atl1e_irq_disable(struct atl1e_adapter *adapter)
00104 {
00105         AT_WRITE_REG(&adapter->hw, REG_IMR, 0);
00106         AT_WRITE_FLUSH(&adapter->hw);
00107 }
00108 
00109 /*
00110  * atl1e_irq_reset - reset interrupt confiure on the NIC
00111  * @adapter: board private structure
00112  */
00113 static inline void atl1e_irq_reset(struct atl1e_adapter *adapter)
00114 {
00115         AT_WRITE_REG(&adapter->hw, REG_ISR, 0);
00116         AT_WRITE_REG(&adapter->hw, REG_IMR, 0);
00117         AT_WRITE_FLUSH(&adapter->hw);
00118 }
00119 
00120 static void atl1e_reset(struct atl1e_adapter *adapter)
00121 {
00122         atl1e_down(adapter);
00123         atl1e_up(adapter);
00124 }
00125 
00126 static int atl1e_check_link(struct atl1e_adapter *adapter)
00127 {
00128         struct atl1e_hw *hw = &adapter->hw;
00129         struct net_device *netdev = adapter->netdev;
00130         int err = 0;
00131         u16 speed, duplex, phy_data;
00132 
00133         /* MII_BMSR must read twise */
00134         atl1e_read_phy_reg(hw, MII_BMSR, &phy_data);
00135         atl1e_read_phy_reg(hw, MII_BMSR, &phy_data);
00136 
00137         if ((phy_data & BMSR_LSTATUS) == 0) {
00138                 /* link down */
00139                 if (netdev_link_ok(netdev)) { /* old link state: Up */
00140                         u32 value;
00141                         /* disable rx */
00142                         value = AT_READ_REG(hw, REG_MAC_CTRL);
00143                         value &= ~MAC_CTRL_RX_EN;
00144                         AT_WRITE_REG(hw, REG_MAC_CTRL, value);
00145                         adapter->link_speed = SPEED_0;
00146 
00147                         DBG("atl1e: %s link is down\n", netdev->name);
00148                         netdev_link_down(netdev);
00149                 }
00150         } else {
00151                 /* Link Up */
00152                 err = atl1e_get_speed_and_duplex(hw, &speed, &duplex);
00153                 if (err)
00154                         return err;
00155 
00156                 /* link result is our setting */
00157                 if (adapter->link_speed != speed ||
00158                     adapter->link_duplex != duplex) {
00159                         adapter->link_speed  = speed;
00160                         adapter->link_duplex = duplex;
00161                         atl1e_setup_mac_ctrl(adapter);
00162 
00163                         DBG("atl1e: %s link is up, %d Mbps, %s duplex\n",
00164                             netdev->name, adapter->link_speed,
00165                             adapter->link_duplex == FULL_DUPLEX ?
00166                             "full" : "half");
00167                         netdev_link_up(netdev);
00168                 }
00169         }
00170         return 0;
00171 }
00172 
00173 static int atl1e_mdio_read(struct net_device *netdev, int phy_id __unused,
00174                            int reg_num)
00175 {
00176         struct atl1e_adapter *adapter = netdev_priv(netdev);
00177         u16 result;
00178 
00179         atl1e_read_phy_reg(&adapter->hw, reg_num & MDIO_REG_ADDR_MASK, &result);
00180         return result;
00181 }
00182 
00183 static void atl1e_mdio_write(struct net_device *netdev, int phy_id __unused,
00184                              int reg_num, int val)
00185 {
00186         struct atl1e_adapter *adapter = netdev_priv(netdev);
00187 
00188         atl1e_write_phy_reg(&adapter->hw, reg_num & MDIO_REG_ADDR_MASK, val);
00189 }
00190 
00191 static void atl1e_setup_pcicmd(struct pci_device *pdev)
00192 {
00193         u16 cmd;
00194 
00195         pci_read_config_word(pdev, PCI_COMMAND, &cmd);
00196         cmd |=  (PCI_COMMAND_MEM | PCI_COMMAND_MASTER);
00197         pci_write_config_word(pdev, PCI_COMMAND, cmd);
00198 
00199         /*
00200          * some motherboards BIOS(PXE/EFI) driver may set PME
00201          * while they transfer control to OS (Windows/Linux)
00202          * so we should clear this bit before NIC work normally
00203          */
00204         pci_write_config_dword(pdev, REG_PM_CTRLSTAT, 0);
00205         mdelay(1);
00206 }
00207 
00208 /*
00209  * atl1e_sw_init - Initialize general software structures (struct atl1e_adapter)
00210  * @adapter: board private structure to initialize
00211  *
00212  * atl1e_sw_init initializes the Adapter private data structure.
00213  * Fields are initialized based on PCI device information and
00214  * OS network device settings (MTU size).
00215  */
00216 static int atl1e_sw_init(struct atl1e_adapter *adapter)
00217 {
00218         struct atl1e_hw *hw = &adapter->hw;
00219         struct pci_device *pdev = adapter->pdev;
00220         u32 phy_status_data = 0;
00221         u8 rev_id = 0;
00222 
00223         adapter->link_speed = SPEED_0;   /* hardware init */
00224         adapter->link_duplex = FULL_DUPLEX;
00225 
00226         /* PCI config space info */
00227         pci_read_config_byte(pdev, PCI_REVISION, &rev_id);
00228 
00229         phy_status_data = AT_READ_REG(hw, REG_PHY_STATUS);
00230         /* nic type */
00231         if (rev_id >= 0xF0) {
00232                 hw->nic_type = athr_l2e_revB;
00233         } else {
00234                 if (phy_status_data & PHY_STATUS_100M)
00235                         hw->nic_type = athr_l1e;
00236                 else
00237                         hw->nic_type = athr_l2e_revA;
00238         }
00239 
00240         phy_status_data = AT_READ_REG(hw, REG_PHY_STATUS);
00241 
00242         hw->emi_ca = !!(phy_status_data & PHY_STATUS_EMI_CA);
00243 
00244         hw->phy_configured = 0;
00245 
00246         /* need confirm */
00247 
00248         hw->dmar_block = atl1e_dma_req_1024;
00249         hw->dmaw_block = atl1e_dma_req_1024;
00250 
00251         return 0;
00252 }
00253 
00254 /*
00255  * atl1e_clean_tx_ring - free all Tx buffers for device close
00256  * @adapter: board private structure
00257  */
00258 static void atl1e_clean_tx_ring(struct atl1e_adapter *adapter)
00259 {
00260         struct atl1e_tx_ring *tx_ring = (struct atl1e_tx_ring *)
00261                                 &adapter->tx_ring;
00262         struct atl1e_tx_buffer *tx_buffer = NULL;
00263         u16 index, ring_count = tx_ring->count;
00264 
00265         if (tx_ring->desc == NULL || tx_ring->tx_buffer == NULL)
00266                 return;
00267 
00268         for (index = 0; index < ring_count; index++) {
00269                 tx_buffer = &tx_ring->tx_buffer[index];
00270                 if (tx_buffer->iob) {
00271                         netdev_tx_complete(adapter->netdev, tx_buffer->iob);
00272                         tx_buffer->dma = 0;
00273                         tx_buffer->iob = NULL;
00274                 }
00275         }
00276 
00277         /* Zero out Tx-buffers */
00278         memset(tx_ring->desc, 0, sizeof(struct atl1e_tpd_desc) *
00279                ring_count);
00280         memset(tx_ring->tx_buffer, 0, sizeof(struct atl1e_tx_buffer) *
00281                ring_count);
00282 }
00283 
00284 /*
00285  * atl1e_clean_rx_ring - Free rx-reservation iobs
00286  * @adapter: board private structure
00287  */
00288 static void atl1e_clean_rx_ring(struct atl1e_adapter *adapter)
00289 {
00290         struct atl1e_rx_ring *rx_ring =
00291                 (struct atl1e_rx_ring *)&adapter->rx_ring;
00292         struct atl1e_rx_page_desc *rx_page_desc = &rx_ring->rx_page_desc;
00293         u16 j;
00294 
00295         if (adapter->ring_vir_addr == NULL)
00296                 return;
00297 
00298         /* Zero out the descriptor ring */
00299         for (j = 0; j < AT_PAGE_NUM_PER_QUEUE; j++) {
00300                 if (rx_page_desc->rx_page[j].addr != NULL) {
00301                         memset(rx_page_desc->rx_page[j].addr, 0,
00302                                rx_ring->real_page_size);
00303                 }
00304         }
00305 }
00306 
00307 static void atl1e_cal_ring_size(struct atl1e_adapter *adapter, u32 *ring_size)
00308 {
00309         *ring_size = ((u32)(adapter->tx_ring.count *
00310                      sizeof(struct atl1e_tpd_desc) + 7
00311                         /* tx ring, qword align */
00312                      + adapter->rx_ring.real_page_size * AT_PAGE_NUM_PER_QUEUE
00313                      + 31
00314                         /* rx ring,  32 bytes align */
00315                      + (1 + AT_PAGE_NUM_PER_QUEUE) *
00316                         sizeof(u32) + 3));
00317                         /* tx, rx cmd, dword align   */
00318 }
00319 
00320 static void atl1e_init_ring_resources(struct atl1e_adapter *adapter)
00321 {
00322         struct atl1e_rx_ring *rx_ring = &adapter->rx_ring;
00323 
00324         rx_ring->real_page_size = adapter->rx_ring.page_size
00325                                  + MAX_FRAME_SIZE
00326                                  + ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN;
00327         rx_ring->real_page_size = (rx_ring->real_page_size + 31) & ~31;
00328         atl1e_cal_ring_size(adapter, &adapter->ring_size);
00329 
00330         adapter->ring_vir_addr = NULL;
00331         adapter->rx_ring.desc = NULL;
00332 
00333         return;
00334 }
00335 
00336 /*
00337  * Read / Write Ptr Initialize:
00338  */
00339 static void atl1e_init_ring_ptrs(struct atl1e_adapter *adapter)
00340 {
00341         struct atl1e_tx_ring *tx_ring = NULL;
00342         struct atl1e_rx_ring *rx_ring = NULL;
00343         struct atl1e_rx_page_desc *rx_page_desc = NULL;
00344         int j;
00345 
00346         tx_ring = &adapter->tx_ring;
00347         rx_ring = &adapter->rx_ring;
00348         rx_page_desc = &rx_ring->rx_page_desc;
00349 
00350         tx_ring->next_to_use = 0;
00351         tx_ring->next_to_clean = 0;
00352 
00353         rx_page_desc->rx_using  = 0;
00354         rx_page_desc->rx_nxseq = 0;
00355         for (j = 0; j < AT_PAGE_NUM_PER_QUEUE; j++) {
00356                 *rx_page_desc->rx_page[j].write_offset_addr = 0;
00357                 rx_page_desc->rx_page[j].read_offset = 0;
00358         }
00359 }
00360 
00361 /*
00362  * atl1e_free_ring_resources - Free Tx / RX descriptor Resources
00363  * @adapter: board private structure
00364  *
00365  * Free all transmit software resources
00366  */
00367 static void atl1e_free_ring_resources(struct atl1e_adapter *adapter)
00368 {
00369         atl1e_clean_tx_ring(adapter);
00370         atl1e_clean_rx_ring(adapter);
00371 
00372         if (adapter->ring_vir_addr) {
00373                 free_dma(adapter->ring_vir_addr, adapter->ring_size);
00374                 adapter->ring_vir_addr = NULL;
00375                 adapter->ring_dma = 0;
00376         }
00377 
00378         if (adapter->tx_ring.tx_buffer) {
00379                 free(adapter->tx_ring.tx_buffer);
00380                 adapter->tx_ring.tx_buffer = NULL;
00381         }
00382 }
00383 
00384 /*
00385  * atl1e_setup_mem_resources - allocate Tx / RX descriptor resources
00386  * @adapter: board private structure
00387  *
00388  * Return 0 on success, negative on failure
00389  */
00390 static int atl1e_setup_ring_resources(struct atl1e_adapter *adapter)
00391 {
00392         struct atl1e_tx_ring *tx_ring;
00393         struct atl1e_rx_ring *rx_ring;
00394         struct atl1e_rx_page_desc  *rx_page_desc;
00395         int size, j;
00396         u32 offset = 0;
00397         int err = 0;
00398 
00399         if (adapter->ring_vir_addr != NULL)
00400                 return 0; /* alloced already */
00401 
00402         tx_ring = &adapter->tx_ring;
00403         rx_ring = &adapter->rx_ring;
00404 
00405         /* real ring DMA buffer */
00406 
00407         size = adapter->ring_size;
00408         adapter->ring_vir_addr = malloc_dma(adapter->ring_size, 32);
00409 
00410         if (adapter->ring_vir_addr == NULL) {
00411                 DBG("atl1e: out of memory allocating %d bytes for %s ring\n",
00412                     adapter->ring_size, adapter->netdev->name);
00413                 return -ENOMEM;
00414         }
00415 
00416         adapter->ring_dma = virt_to_bus(adapter->ring_vir_addr);
00417         memset(adapter->ring_vir_addr, 0, adapter->ring_size);
00418 
00419         rx_page_desc = &rx_ring->rx_page_desc;
00420 
00421         /* Init TPD Ring */
00422         tx_ring->dma = (adapter->ring_dma + 7) & ~7;
00423         offset = tx_ring->dma - adapter->ring_dma;
00424         tx_ring->desc = (struct atl1e_tpd_desc *)
00425                         (adapter->ring_vir_addr + offset);
00426         size = sizeof(struct atl1e_tx_buffer) * (tx_ring->count);
00427         tx_ring->tx_buffer = zalloc(size);
00428         if (tx_ring->tx_buffer == NULL) {
00429                 DBG("atl1e: out of memory allocating %d bytes for %s txbuf\n",
00430                     size, adapter->netdev->name);
00431                 err = -ENOMEM;
00432                 goto failed;
00433         }
00434 
00435         /* Init RXF-Pages */
00436         offset += (sizeof(struct atl1e_tpd_desc) * tx_ring->count);
00437         offset = (offset + 31) & ~31;
00438 
00439         for (j = 0; j < AT_PAGE_NUM_PER_QUEUE; j++) {
00440                 rx_page_desc->rx_page[j].dma =
00441                         adapter->ring_dma + offset;
00442                 rx_page_desc->rx_page[j].addr =
00443                         adapter->ring_vir_addr + offset;
00444                 offset += rx_ring->real_page_size;
00445         }
00446 
00447         /* Init CMB dma address */
00448         tx_ring->cmb_dma = adapter->ring_dma + offset;
00449         tx_ring->cmb     = (u32 *)(adapter->ring_vir_addr + offset);
00450         offset += sizeof(u32);
00451 
00452         for (j = 0; j < AT_PAGE_NUM_PER_QUEUE; j++) {
00453                 rx_page_desc->rx_page[j].write_offset_dma =
00454                         adapter->ring_dma + offset;
00455                 rx_page_desc->rx_page[j].write_offset_addr =
00456                         adapter->ring_vir_addr + offset;
00457                 offset += sizeof(u32);
00458         }
00459 
00460         if (offset > adapter->ring_size) {
00461                 DBG("atl1e: ring miscalculation! need %d > %d bytes\n",
00462                     offset, adapter->ring_size);
00463                 err = -EINVAL;
00464                 goto failed;
00465         }
00466 
00467         return 0;
00468 failed:
00469         atl1e_free_ring_resources(adapter);
00470         return err;
00471 }
00472 
00473 static inline void atl1e_configure_des_ring(const struct atl1e_adapter *adapter)
00474 {
00475 
00476         struct atl1e_hw *hw = (struct atl1e_hw *)&adapter->hw;
00477         struct atl1e_rx_ring *rx_ring =
00478                         (struct atl1e_rx_ring *)&adapter->rx_ring;
00479         struct atl1e_tx_ring *tx_ring =
00480                         (struct atl1e_tx_ring *)&adapter->tx_ring;
00481         struct atl1e_rx_page_desc *rx_page_desc = NULL;
00482         int j;
00483 
00484         AT_WRITE_REG(hw, REG_DESC_BASE_ADDR_HI, 0);
00485         AT_WRITE_REG(hw, REG_TPD_BASE_ADDR_LO, tx_ring->dma);
00486         AT_WRITE_REG(hw, REG_TPD_RING_SIZE, (u16)(tx_ring->count));
00487         AT_WRITE_REG(hw, REG_HOST_TX_CMB_LO, tx_ring->cmb_dma);
00488 
00489         rx_page_desc = &rx_ring->rx_page_desc;
00490 
00491         /* RXF Page Physical address / Page Length */
00492         AT_WRITE_REG(hw, REG_RXF0_BASE_ADDR_HI, 0);
00493 
00494         for (j = 0; j < AT_PAGE_NUM_PER_QUEUE; j++) {
00495                 u32 page_phy_addr;
00496                 u32 offset_phy_addr;
00497 
00498                 page_phy_addr = rx_page_desc->rx_page[j].dma;
00499                 offset_phy_addr = rx_page_desc->rx_page[j].write_offset_dma;
00500 
00501                 AT_WRITE_REG(hw, atl1e_rx_page_lo_addr_regs[j], page_phy_addr);
00502                 AT_WRITE_REG(hw, atl1e_rx_page_write_offset_regs[j],
00503                              offset_phy_addr);
00504                 AT_WRITE_REGB(hw, atl1e_rx_page_vld_regs[j], 1);
00505         }
00506 
00507         /* Page Length */
00508         AT_WRITE_REG(hw, REG_HOST_RXFPAGE_SIZE, rx_ring->page_size);
00509         /* Load all of base address above */
00510         AT_WRITE_REG(hw, REG_LOAD_PTR, 1);
00511 
00512         return;
00513 }
00514 
00515 static inline void atl1e_configure_tx(struct atl1e_adapter *adapter)
00516 {
00517         struct atl1e_hw *hw = (struct atl1e_hw *)&adapter->hw;
00518         u32 dev_ctrl_data = 0;
00519         u32 max_pay_load = 0;
00520         u32 jumbo_thresh = 0;
00521         u32 extra_size = 0;     /* Jumbo frame threshold in QWORD unit */
00522 
00523         /* configure TXQ param */
00524         if (hw->nic_type != athr_l2e_revB) {
00525                 extra_size = ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN;
00526                 jumbo_thresh = MAX_FRAME_SIZE + extra_size;
00527                 AT_WRITE_REG(hw, REG_TX_EARLY_TH, (jumbo_thresh + 7) >> 3);
00528         }
00529 
00530         dev_ctrl_data = AT_READ_REG(hw, REG_DEVICE_CTRL);
00531 
00532         max_pay_load  = ((dev_ctrl_data >> DEVICE_CTRL_MAX_PAYLOAD_SHIFT)) &
00533                         DEVICE_CTRL_MAX_PAYLOAD_MASK;
00534         if (max_pay_load < hw->dmaw_block)
00535                 hw->dmaw_block = max_pay_load;
00536 
00537         max_pay_load  = ((dev_ctrl_data >> DEVICE_CTRL_MAX_RREQ_SZ_SHIFT)) &
00538                         DEVICE_CTRL_MAX_RREQ_SZ_MASK;
00539         if (max_pay_load < hw->dmar_block)
00540                 hw->dmar_block = max_pay_load;
00541 
00542         if (hw->nic_type != athr_l2e_revB)
00543                 AT_WRITE_REGW(hw, REG_TXQ_CTRL + 2,
00544                               atl1e_pay_load_size[hw->dmar_block]);
00545         /* enable TXQ */
00546         AT_WRITE_REGW(hw, REG_TXQ_CTRL,
00547                         ((TPD_BURST & TXQ_CTRL_NUM_TPD_BURST_MASK)
00548                          << TXQ_CTRL_NUM_TPD_BURST_SHIFT)
00549                         | TXQ_CTRL_ENH_MODE | TXQ_CTRL_EN);
00550         return;
00551 }
00552 
00553 static inline void atl1e_configure_rx(struct atl1e_adapter *adapter)
00554 {
00555         struct atl1e_hw *hw = (struct atl1e_hw *)&adapter->hw;
00556         u32 rxf_len  = 0;
00557         u32 rxf_low  = 0;
00558         u32 rxf_high = 0;
00559         u32 rxf_thresh_data = 0;
00560         u32 rxq_ctrl_data = 0;
00561 
00562         if (hw->nic_type != athr_l2e_revB) {
00563                 AT_WRITE_REGW(hw, REG_RXQ_JMBOSZ_RRDTIM,
00564                               (u16)((RX_JUMBO_THRESH & RXQ_JMBOSZ_TH_MASK) <<
00565                               RXQ_JMBOSZ_TH_SHIFT |
00566                               (1 & RXQ_JMBO_LKAH_MASK) <<
00567                               RXQ_JMBO_LKAH_SHIFT));
00568 
00569                 rxf_len  = AT_READ_REG(hw, REG_SRAM_RXF_LEN);
00570                 rxf_high = rxf_len * 4 / 5;
00571                 rxf_low  = rxf_len / 5;
00572                 rxf_thresh_data = ((rxf_high  & RXQ_RXF_PAUSE_TH_HI_MASK)
00573                                   << RXQ_RXF_PAUSE_TH_HI_SHIFT) |
00574                                   ((rxf_low & RXQ_RXF_PAUSE_TH_LO_MASK)
00575                                   << RXQ_RXF_PAUSE_TH_LO_SHIFT);
00576 
00577                 AT_WRITE_REG(hw, REG_RXQ_RXF_PAUSE_THRESH, rxf_thresh_data);
00578         }
00579 
00580         /* RRS */
00581         AT_WRITE_REG(hw, REG_IDT_TABLE, 0);
00582         AT_WRITE_REG(hw, REG_BASE_CPU_NUMBER, 0);
00583 
00584         rxq_ctrl_data |= RXQ_CTRL_PBA_ALIGN_32 |
00585                          RXQ_CTRL_CUT_THRU_EN | RXQ_CTRL_EN;
00586 
00587         AT_WRITE_REG(hw, REG_RXQ_CTRL, rxq_ctrl_data);
00588         return;
00589 }
00590 
00591 static inline void atl1e_configure_dma(struct atl1e_adapter *adapter)
00592 {
00593         struct atl1e_hw *hw = &adapter->hw;
00594         u32 dma_ctrl_data = 0;
00595 
00596         dma_ctrl_data = DMA_CTRL_RXCMB_EN;
00597         dma_ctrl_data |= (((u32)hw->dmar_block) & DMA_CTRL_DMAR_BURST_LEN_MASK)
00598                 << DMA_CTRL_DMAR_BURST_LEN_SHIFT;
00599         dma_ctrl_data |= (((u32)hw->dmaw_block) & DMA_CTRL_DMAW_BURST_LEN_MASK)
00600                 << DMA_CTRL_DMAW_BURST_LEN_SHIFT;
00601         dma_ctrl_data |= DMA_CTRL_DMAR_REQ_PRI | DMA_CTRL_DMAR_OUT_ORDER;
00602         dma_ctrl_data |= (DMAR_DLY_CNT & DMA_CTRL_DMAR_DLY_CNT_MASK)
00603                 << DMA_CTRL_DMAR_DLY_CNT_SHIFT;
00604         dma_ctrl_data |= (DMAW_DLY_CNT & DMA_CTRL_DMAW_DLY_CNT_MASK)
00605                 << DMA_CTRL_DMAW_DLY_CNT_SHIFT;
00606 
00607         AT_WRITE_REG(hw, REG_DMA_CTRL, dma_ctrl_data);
00608         return;
00609 }
00610 
00611 static void atl1e_setup_mac_ctrl(struct atl1e_adapter *adapter)
00612 {
00613         u32 value;
00614         struct atl1e_hw *hw = &adapter->hw;
00615 
00616         /* Config MAC CTRL Register */
00617         value = MAC_CTRL_TX_EN |
00618                 MAC_CTRL_RX_EN ;
00619 
00620         if (FULL_DUPLEX == adapter->link_duplex)
00621                 value |= MAC_CTRL_DUPLX;
00622 
00623         value |= ((u32)((SPEED_1000 == adapter->link_speed) ?
00624                           MAC_CTRL_SPEED_1000 : MAC_CTRL_SPEED_10_100) <<
00625                           MAC_CTRL_SPEED_SHIFT);
00626         value |= (MAC_CTRL_TX_FLOW | MAC_CTRL_RX_FLOW);
00627 
00628         value |= (MAC_CTRL_ADD_CRC | MAC_CTRL_PAD);
00629         value |= ((PREAMBLE_LEN & MAC_CTRL_PRMLEN_MASK) << MAC_CTRL_PRMLEN_SHIFT);
00630 
00631         value |= MAC_CTRL_BC_EN;
00632         value |= MAC_CTRL_MC_ALL_EN;
00633 
00634         AT_WRITE_REG(hw, REG_MAC_CTRL, value);
00635 }
00636 
00637 /*
00638  * atl1e_configure - Configure Transmit&Receive Unit after Reset
00639  * @adapter: board private structure
00640  *
00641  * Configure the Tx /Rx unit of the MAC after a reset.
00642  */
00643 static int atl1e_configure(struct atl1e_adapter *adapter)
00644 {
00645         struct atl1e_hw *hw = &adapter->hw;
00646         u32 intr_status_data = 0;
00647 
00648         /* clear interrupt status */
00649         AT_WRITE_REG(hw, REG_ISR, ~0);
00650 
00651         /* 1. set MAC Address */
00652         atl1e_hw_set_mac_addr(hw);
00653 
00654         /* 2. Init the Multicast HASH table (clear) */
00655         AT_WRITE_REG(hw, REG_RX_HASH_TABLE, 0);
00656         AT_WRITE_REG_ARRAY(hw, REG_RX_HASH_TABLE, 1, 0);
00657 
00658         /* 3. Clear any WOL status */
00659         AT_WRITE_REG(hw, REG_WOL_CTRL, 0);
00660 
00661         /* 4. Descripter Ring BaseMem/Length/Read ptr/Write ptr
00662          *    TPD Ring/SMB/RXF0 Page CMBs, they use the same
00663          *    High 32bits memory */
00664         atl1e_configure_des_ring(adapter);
00665 
00666         /* 5. set Interrupt Moderator Timer */
00667         AT_WRITE_REGW(hw, REG_IRQ_MODU_TIMER_INIT, IMT_VAL);
00668         AT_WRITE_REGW(hw, REG_IRQ_MODU_TIMER2_INIT, IMT_VAL);
00669         AT_WRITE_REG(hw, REG_MASTER_CTRL, MASTER_CTRL_LED_MODE |
00670                         MASTER_CTRL_ITIMER_EN | MASTER_CTRL_ITIMER2_EN);
00671 
00672         /* 6. rx/tx threshold to trig interrupt */
00673         AT_WRITE_REGW(hw, REG_TRIG_RRD_THRESH, RRD_THRESH);
00674         AT_WRITE_REGW(hw, REG_TRIG_TPD_THRESH, TPD_THRESH);
00675         AT_WRITE_REGW(hw, REG_TRIG_RXTIMER, RX_COUNT_DOWN);
00676         AT_WRITE_REGW(hw, REG_TRIG_TXTIMER, TX_COUNT_DOWN);
00677 
00678         /* 7. set Interrupt Clear Timer */
00679         AT_WRITE_REGW(hw, REG_CMBDISDMA_TIMER, ICT_VAL);
00680 
00681         /* 8. set MTU */
00682         AT_WRITE_REG(hw, REG_MTU, MAX_FRAME_SIZE + ETH_HLEN +
00683                         VLAN_HLEN + ETH_FCS_LEN);
00684 
00685         /* 9. config TXQ early tx threshold */
00686         atl1e_configure_tx(adapter);
00687 
00688         /* 10. config RXQ */
00689         atl1e_configure_rx(adapter);
00690 
00691         /* 11. config  DMA Engine */
00692         atl1e_configure_dma(adapter);
00693 
00694         /* 12. smb timer to trig interrupt */
00695         AT_WRITE_REG(hw, REG_SMB_STAT_TIMER, SMB_TIMER);
00696 
00697         intr_status_data = AT_READ_REG(hw, REG_ISR);
00698         if ((intr_status_data & ISR_PHY_LINKDOWN) != 0) {
00699                 DBG("atl1e: configure failed, PCIE phy link down\n");
00700                 return -1;
00701         }
00702 
00703         AT_WRITE_REG(hw, REG_ISR, 0x7fffffff);
00704         return 0;
00705 }
00706 
00707 static inline void atl1e_clear_phy_int(struct atl1e_adapter *adapter)
00708 {
00709         u16 phy_data;
00710 
00711         atl1e_read_phy_reg(&adapter->hw, MII_INT_STATUS, &phy_data);
00712 }
00713 
00714 static int atl1e_clean_tx_irq(struct atl1e_adapter *adapter)
00715 {
00716         struct atl1e_tx_ring *tx_ring = (struct atl1e_tx_ring *)
00717                                         &adapter->tx_ring;
00718         struct atl1e_tx_buffer *tx_buffer = NULL;
00719         u16 hw_next_to_clean = AT_READ_REGW(&adapter->hw, REG_TPD_CONS_IDX);
00720         u16 next_to_clean = tx_ring->next_to_clean;
00721 
00722         while (next_to_clean != hw_next_to_clean) {
00723                 tx_buffer = &tx_ring->tx_buffer[next_to_clean];
00724 
00725                 tx_buffer->dma = 0;
00726                 if (tx_buffer->iob) {
00727                         netdev_tx_complete(adapter->netdev, tx_buffer->iob);
00728                         tx_buffer->iob = NULL;
00729                 }
00730 
00731                 if (++next_to_clean == tx_ring->count)
00732                         next_to_clean = 0;
00733         }
00734 
00735         tx_ring->next_to_clean = next_to_clean;
00736 
00737         return 1;
00738 }
00739 
00740 static struct atl1e_rx_page *atl1e_get_rx_page(struct atl1e_adapter *adapter)
00741 {
00742         struct atl1e_rx_page_desc *rx_page_desc =
00743                 (struct atl1e_rx_page_desc *) &adapter->rx_ring.rx_page_desc;
00744         u8 rx_using = rx_page_desc->rx_using;
00745 
00746         return (struct atl1e_rx_page *)&(rx_page_desc->rx_page[rx_using]);
00747 }
00748 
00749 static void atl1e_clean_rx_irq(struct atl1e_adapter *adapter)
00750 {
00751         struct net_device *netdev  = adapter->netdev;
00752         struct atl1e_rx_ring *rx_ring = (struct atl1e_rx_ring *)
00753                                          &adapter->rx_ring;
00754         struct atl1e_rx_page_desc *rx_page_desc =
00755                 (struct atl1e_rx_page_desc *) &rx_ring->rx_page_desc;
00756         struct io_buffer *iob = NULL;
00757         struct atl1e_rx_page *rx_page = atl1e_get_rx_page(adapter);
00758         u32 packet_size, write_offset;
00759         struct atl1e_recv_ret_status *prrs;
00760 
00761         write_offset = *(rx_page->write_offset_addr);
00762         if (rx_page->read_offset >= write_offset)
00763                 return;
00764 
00765         do {
00766                 /* get new packet's  rrs */
00767                 prrs = (struct atl1e_recv_ret_status *) (rx_page->addr +
00768                                                          rx_page->read_offset);
00769                 /* check sequence number */
00770                 if (prrs->seq_num != rx_page_desc->rx_nxseq) {
00771                         DBG("atl1e %s: RX sequence number error (%d != %d)\n",
00772                             netdev->name, prrs->seq_num,
00773                             rx_page_desc->rx_nxseq);
00774                         rx_page_desc->rx_nxseq++;
00775                         goto fatal_err;
00776                 }
00777 
00778                 rx_page_desc->rx_nxseq++;
00779 
00780                 /* error packet */
00781                 if (prrs->pkt_flag & RRS_IS_ERR_FRAME) {
00782                         if (prrs->err_flag & (RRS_ERR_BAD_CRC |
00783                                               RRS_ERR_DRIBBLE | RRS_ERR_CODE |
00784                                               RRS_ERR_TRUNC)) {
00785                                 /* hardware error, discard this
00786                                    packet */
00787                                 netdev_rx_err(netdev, NULL, EIO);
00788                                 goto skip_pkt;
00789                         }
00790                 }
00791 
00792                 packet_size = ((prrs->word1 >> RRS_PKT_SIZE_SHIFT) &
00793                                RRS_PKT_SIZE_MASK) - ETH_FCS_LEN;
00794                 iob = alloc_iob(packet_size + NET_IP_ALIGN);
00795                 if (iob == NULL) {
00796                         DBG("atl1e %s: dropping packet under memory pressure\n",
00797                             netdev->name);
00798                         goto skip_pkt;
00799                 }
00800                 iob_reserve(iob, NET_IP_ALIGN);
00801                 memcpy(iob->data, (u8 *)(prrs + 1), packet_size);
00802                 iob_put(iob, packet_size);
00803 
00804                 netdev_rx(netdev, iob);
00805 
00806 skip_pkt:
00807                 /* skip current packet whether it's ok or not. */
00808                 rx_page->read_offset +=
00809                         (((u32)((prrs->word1 >> RRS_PKT_SIZE_SHIFT) &
00810                                 RRS_PKT_SIZE_MASK) +
00811                           sizeof(struct atl1e_recv_ret_status) + 31) &
00812                          0xFFFFFFE0);
00813 
00814                 if (rx_page->read_offset >= rx_ring->page_size) {
00815                         /* mark this page clean */
00816                         u16 reg_addr;
00817                         u8  rx_using;
00818 
00819                         rx_page->read_offset =
00820                                 *(rx_page->write_offset_addr) = 0;
00821                         rx_using = rx_page_desc->rx_using;
00822                         reg_addr =
00823                                 atl1e_rx_page_vld_regs[rx_using];
00824                         AT_WRITE_REGB(&adapter->hw, reg_addr, 1);
00825                         rx_page_desc->rx_using ^= 1;
00826                         rx_page = atl1e_get_rx_page(adapter);
00827                 }
00828                 write_offset = *(rx_page->write_offset_addr);
00829         } while (rx_page->read_offset < write_offset);
00830 
00831         return;
00832 
00833 fatal_err:
00834         if (!netdev_link_ok(adapter->netdev))
00835                 atl1e_reset(adapter);
00836 }
00837 
00838 /*
00839  * atl1e_poll - poll for completed transmissions and received packets
00840  * @netdev: network device
00841  */
00842 static void atl1e_poll(struct net_device *netdev)
00843 {
00844         struct atl1e_adapter *adapter = netdev_priv(netdev);
00845         struct atl1e_hw *hw = &adapter->hw;
00846         int max_ints = 64;
00847         u32 status;
00848 
00849         do {
00850                 status = AT_READ_REG(hw, REG_ISR);
00851                 if ((status & IMR_NORMAL_MASK) == 0)
00852                         break;
00853 
00854                 /* link event */
00855                 if (status & ISR_GPHY)
00856                         atl1e_clear_phy_int(adapter);
00857                 /* Ack ISR */
00858                 AT_WRITE_REG(hw, REG_ISR, status | ISR_DIS_INT);
00859 
00860                 /* check if PCIE PHY Link down */
00861                 if (status & ISR_PHY_LINKDOWN) {
00862                         DBG("atl1e: PCI-E PHY link down: %x\n", status);
00863                         if (netdev_link_ok(adapter->netdev)) {
00864                                 /* reset MAC */
00865                                 atl1e_irq_reset(adapter);
00866                                 atl1e_reset(adapter);
00867                                 break;
00868                         }
00869                 }
00870 
00871                 /* check if DMA read/write error */
00872                 if (status & (ISR_DMAR_TO_RST | ISR_DMAW_TO_RST)) {
00873                         DBG("atl1e: PCI-E DMA RW error: %x\n", status);
00874                         atl1e_irq_reset(adapter);
00875                         atl1e_reset(adapter);
00876                         break;
00877                 }
00878 
00879                 /* link event */
00880                 if (status & (ISR_GPHY | ISR_MANUAL)) {
00881                         atl1e_check_link(adapter);
00882                         break;
00883                 }
00884 
00885                 /* transmit event */
00886                 if (status & ISR_TX_EVENT)
00887                         atl1e_clean_tx_irq(adapter);
00888 
00889                 if (status & ISR_RX_EVENT)
00890                         atl1e_clean_rx_irq(adapter);
00891         } while (--max_ints > 0);
00892 
00893         /* re-enable Interrupt*/
00894         AT_WRITE_REG(&adapter->hw, REG_ISR, 0);
00895 
00896         return;
00897 }
00898 
00899 static inline u16 atl1e_tpd_avail(struct atl1e_adapter *adapter)
00900 {
00901         struct atl1e_tx_ring *tx_ring = &adapter->tx_ring;
00902         u16 next_to_use = 0;
00903         u16 next_to_clean = 0;
00904 
00905         next_to_clean = tx_ring->next_to_clean;
00906         next_to_use   = tx_ring->next_to_use;
00907 
00908         return (u16)(next_to_clean > next_to_use) ?
00909                 (next_to_clean - next_to_use - 1) :
00910                 (tx_ring->count + next_to_clean - next_to_use - 1);
00911 }
00912 
00913 /*
00914  * get next usable tpd
00915  * Note: should call atl1e_tdp_avail to make sure
00916  * there is enough tpd to use
00917  */
00918 static struct atl1e_tpd_desc *atl1e_get_tpd(struct atl1e_adapter *adapter)
00919 {
00920         struct atl1e_tx_ring *tx_ring = &adapter->tx_ring;
00921         u16 next_to_use = 0;
00922 
00923         next_to_use = tx_ring->next_to_use;
00924         if (++tx_ring->next_to_use == tx_ring->count)
00925                 tx_ring->next_to_use = 0;
00926 
00927         memset(&tx_ring->desc[next_to_use], 0, sizeof(struct atl1e_tpd_desc));
00928         return (struct atl1e_tpd_desc *)&tx_ring->desc[next_to_use];
00929 }
00930 
00931 static struct atl1e_tx_buffer *
00932 atl1e_get_tx_buffer(struct atl1e_adapter *adapter, struct atl1e_tpd_desc *tpd)
00933 {
00934         struct atl1e_tx_ring *tx_ring = &adapter->tx_ring;
00935 
00936         return &tx_ring->tx_buffer[tpd - tx_ring->desc];
00937 }
00938 
00939 static void atl1e_tx_map(struct atl1e_adapter *adapter,
00940                       struct io_buffer *iob, struct atl1e_tpd_desc *tpd)
00941 {
00942         struct atl1e_tx_buffer *tx_buffer = NULL;
00943         u16 buf_len = iob_len(iob);
00944 
00945         tx_buffer = atl1e_get_tx_buffer(adapter, tpd);
00946         tx_buffer->iob = iob;
00947         tx_buffer->length = buf_len;
00948         tx_buffer->dma = virt_to_bus(iob->data);
00949         tpd->buffer_addr = cpu_to_le64(tx_buffer->dma);
00950         tpd->word2 = ((tpd->word2 & ~TPD_BUFLEN_MASK) |
00951                       ((cpu_to_le32(buf_len) & TPD_BUFLEN_MASK) <<
00952                        TPD_BUFLEN_SHIFT));
00953         tpd->word3 |= 1 << TPD_EOP_SHIFT;
00954 }
00955 
00956 static void atl1e_tx_queue(struct atl1e_adapter *adapter, u16 count __unused,
00957                            struct atl1e_tpd_desc *tpd __unused)
00958 {
00959         struct atl1e_tx_ring *tx_ring = &adapter->tx_ring;
00960         wmb();
00961         AT_WRITE_REG(&adapter->hw, REG_MB_TPD_PROD_IDX, tx_ring->next_to_use);
00962 }
00963 
00964 static int atl1e_xmit_frame(struct net_device *netdev, struct io_buffer *iob)
00965 {
00966         struct atl1e_adapter *adapter = netdev_priv(netdev);
00967         u16 tpd_req = 1;
00968         struct atl1e_tpd_desc *tpd;
00969 
00970         if (!netdev_link_ok(netdev)) {
00971                 return -EINVAL;
00972         }
00973 
00974         if (atl1e_tpd_avail(adapter) < tpd_req) {
00975                 return -EBUSY;
00976         }
00977 
00978         tpd = atl1e_get_tpd(adapter);
00979 
00980         atl1e_tx_map(adapter, iob, tpd);
00981         atl1e_tx_queue(adapter, tpd_req, tpd);
00982 
00983         return 0;
00984 }
00985 
00986 int atl1e_up(struct atl1e_adapter *adapter)
00987 {
00988         struct net_device *netdev = adapter->netdev;
00989         int err = 0;
00990         u32 val;
00991 
00992         /* hardware has been reset, we need to reload some things */
00993         err = atl1e_init_hw(&adapter->hw);
00994         if (err) {
00995                 return -EIO;
00996         }
00997         atl1e_init_ring_ptrs(adapter);
00998 
00999         memcpy(adapter->hw.mac_addr, netdev->ll_addr, ETH_ALEN);
01000 
01001         if (atl1e_configure(adapter) != 0) {
01002                 return -EIO;
01003         }
01004 
01005         atl1e_irq_disable(adapter);
01006 
01007         val = AT_READ_REG(&adapter->hw, REG_MASTER_CTRL);
01008         AT_WRITE_REG(&adapter->hw, REG_MASTER_CTRL,
01009                       val | MASTER_CTRL_MANUAL_INT);
01010 
01011         return err;
01012 }
01013 
01014 void atl1e_irq(struct net_device *netdev, int enable)
01015 {
01016         struct atl1e_adapter *adapter = netdev_priv(netdev);
01017 
01018         if (enable)
01019                 atl1e_irq_enable(adapter);
01020         else
01021                 atl1e_irq_disable(adapter);
01022 }
01023 
01024 void atl1e_down(struct atl1e_adapter *adapter)
01025 {
01026         struct net_device *netdev = adapter->netdev;
01027 
01028         /* reset MAC to disable all RX/TX */
01029         atl1e_reset_hw(&adapter->hw);
01030         mdelay(1);
01031 
01032         netdev_link_down(netdev);
01033         adapter->link_speed = SPEED_0;
01034         adapter->link_duplex = -1;
01035 
01036         atl1e_clean_tx_ring(adapter);
01037         atl1e_clean_rx_ring(adapter);
01038 }
01039 
01040 /*
01041  * atl1e_open - Called when a network interface is made active
01042  * @netdev: network interface device structure
01043  *
01044  * Returns 0 on success, negative value on failure
01045  *
01046  * The open entry point is called when a network interface is made
01047  * active by the system (IFF_UP).  At this point all resources needed
01048  * for transmit and receive operations are allocated, the interrupt
01049  * handler is registered with the OS, the watchdog timer is started,
01050  * and the stack is notified that the interface is ready.
01051  */
01052 static int atl1e_open(struct net_device *netdev)
01053 {
01054         struct atl1e_adapter *adapter = netdev_priv(netdev);
01055         int err;
01056 
01057         /* allocate rx/tx dma buffer & descriptors */
01058         atl1e_init_ring_resources(adapter);
01059         err = atl1e_setup_ring_resources(adapter);
01060         if (err)
01061                 return err;
01062 
01063         err = atl1e_up(adapter);
01064         if (err)
01065                 goto err_up;
01066 
01067         return 0;
01068 
01069 err_up:
01070         atl1e_free_ring_resources(adapter);
01071         atl1e_reset_hw(&adapter->hw);
01072 
01073         return err;
01074 }
01075 
01076 /*
01077  * atl1e_close - Disables a network interface
01078  * @netdev: network interface device structure
01079  *
01080  * Returns 0, this is not allowed to fail
01081  *
01082  * The close entry point is called when an interface is de-activated
01083  * by the OS.  The hardware is still under the drivers control, but
01084  * needs to be disabled.  A global MAC reset is issued to stop the
01085  * hardware, and all transmit and receive resources are freed.
01086  */
01087 static void atl1e_close(struct net_device *netdev)
01088 {
01089         struct atl1e_adapter *adapter = netdev_priv(netdev);
01090 
01091         atl1e_down(adapter);
01092         atl1e_free_ring_resources(adapter);
01093 }
01094 
01095 static struct net_device_operations atl1e_netdev_ops = {
01096         .open           = atl1e_open,
01097         .close          = atl1e_close,
01098         .transmit       = atl1e_xmit_frame,
01099         .poll           = atl1e_poll,
01100         .irq            = atl1e_irq,
01101 };
01102 
01103 static void atl1e_init_netdev(struct net_device *netdev, struct pci_device *pdev)
01104 {
01105         netdev_init(netdev, &atl1e_netdev_ops);
01106 
01107         netdev->dev = &pdev->dev;
01108         pci_set_drvdata(pdev, netdev);
01109 }
01110 
01111 /*
01112  * atl1e_probe - Device Initialization Routine
01113  * @pdev: PCI device information struct
01114  * @ent: entry in atl1e_pci_tbl
01115  *
01116  * Returns 0 on success, negative on failure
01117  *
01118  * atl1e_probe initializes an adapter identified by a pci_device structure.
01119  * The OS initialization, configuring of the adapter private structure,
01120  * and a hardware reset occur.
01121  */
01122 static int atl1e_probe(struct pci_device *pdev)
01123 {
01124         struct net_device *netdev;
01125         struct atl1e_adapter *adapter = NULL;
01126         static int cards_found;
01127 
01128         int err = 0;
01129 
01130         adjust_pci_device(pdev);
01131 
01132         netdev = alloc_etherdev(sizeof(struct atl1e_adapter));
01133         if (netdev == NULL) {
01134                 err = -ENOMEM;
01135                 DBG("atl1e: out of memory allocating net_device\n");
01136                 goto err;
01137         }
01138 
01139         atl1e_init_netdev(netdev, pdev);
01140 
01141         adapter = netdev_priv(netdev);
01142         adapter->bd_number = cards_found;
01143         adapter->netdev = netdev;
01144         adapter->pdev = pdev;
01145         adapter->hw.adapter = adapter;
01146         if (!pdev->membase) {
01147                 err = -EIO;
01148                 DBG("atl1e: cannot map device registers\n");
01149                 goto err_free_netdev;
01150         }
01151         adapter->hw.hw_addr = bus_to_virt(pdev->membase);
01152 
01153         /* init mii data */
01154         adapter->mii.dev = netdev;
01155         adapter->mii.mdio_read  = atl1e_mdio_read;
01156         adapter->mii.mdio_write = atl1e_mdio_write;
01157         adapter->mii.phy_id_mask = 0x1f;
01158         adapter->mii.reg_num_mask = MDIO_REG_ADDR_MASK;
01159 
01160         /* get user settings */
01161         adapter->tx_ring.count = TX_DESC_COUNT;
01162         adapter->rx_ring.page_size = RX_MEM_SIZE;
01163 
01164         atl1e_setup_pcicmd(pdev);
01165 
01166         /* setup the private structure */
01167         err = atl1e_sw_init(adapter);
01168         if (err) {
01169                 DBG("atl1e: private data init failed\n");
01170                 goto err_free_netdev;
01171         }
01172 
01173         /* Init GPHY as early as possible due to power saving issue  */
01174         atl1e_phy_init(&adapter->hw);
01175 
01176         /* reset the controller to
01177          * put the device in a known good starting state */
01178         err = atl1e_reset_hw(&adapter->hw);
01179         if (err) {
01180                 err = -EIO;
01181                 goto err_free_netdev;
01182         }
01183 
01184         /* This may have been run by a zero-wait timer around
01185            now... unclear. */
01186         atl1e_restart_autoneg(&adapter->hw);
01187 
01188         if (atl1e_read_mac_addr(&adapter->hw) != 0) {
01189                 DBG("atl1e: cannot read MAC address from EEPROM\n");
01190                 err = -EIO;
01191                 goto err_free_netdev;
01192         }
01193 
01194         memcpy(netdev->hw_addr, adapter->hw.perm_mac_addr, ETH_ALEN);
01195         memcpy(netdev->ll_addr, adapter->hw.mac_addr, ETH_ALEN);
01196         DBG("atl1e: Attansic L1E Ethernet controller on %s, "
01197             "%02x:%02x:%02x:%02x:%02x:%02x\n", adapter->netdev->name,
01198             adapter->hw.mac_addr[0], adapter->hw.mac_addr[1],
01199             adapter->hw.mac_addr[2], adapter->hw.mac_addr[3],
01200             adapter->hw.mac_addr[4], adapter->hw.mac_addr[5]);
01201 
01202         err = register_netdev(netdev);
01203         if (err) {
01204                 DBG("atl1e: cannot register network device\n");
01205                 goto err_free_netdev;
01206         }
01207 
01208         cards_found++;
01209         return 0;
01210 
01211 err_free_netdev:
01212         netdev_nullify(netdev);
01213         netdev_put(netdev);
01214 err:
01215         return err;
01216 }
01217 
01218 /*
01219  * atl1e_remove - Device Removal Routine
01220  * @pdev: PCI device information struct
01221  *
01222  * atl1e_remove is called by the PCI subsystem to alert the driver
01223  * that it should release a PCI device.  The could be caused by a
01224  * Hot-Plug event, or because the driver is going to be removed from
01225  * memory.
01226  */
01227 static void atl1e_remove(struct pci_device *pdev)
01228 {
01229         struct net_device *netdev = pci_get_drvdata(pdev);
01230         struct atl1e_adapter *adapter = netdev_priv(netdev);
01231 
01232         unregister_netdev(netdev);
01233         atl1e_free_ring_resources(adapter);
01234         atl1e_force_ps(&adapter->hw);
01235         netdev_nullify(netdev);
01236         netdev_put(netdev);
01237 }
01238 
01239 struct pci_driver atl1e_driver __pci_driver = {
01240         .ids      = atl1e_pci_tbl,
01241         .id_count = (sizeof(atl1e_pci_tbl) / sizeof(atl1e_pci_tbl[0])),
01242         .probe    = atl1e_probe,
01243         .remove   = atl1e_remove,
01244 };
01245 
01246 /********** Hardware-level functions: **********/
01247 
01248 /*
01249  * check_eeprom_exist
01250  * return 0 if eeprom exist
01251  */
01252 int atl1e_check_eeprom_exist(struct atl1e_hw *hw)
01253 {
01254         u32 value;
01255 
01256         value = AT_READ_REG(hw, REG_SPI_FLASH_CTRL);
01257         if (value & SPI_FLASH_CTRL_EN_VPD) {
01258                 value &= ~SPI_FLASH_CTRL_EN_VPD;
01259                 AT_WRITE_REG(hw, REG_SPI_FLASH_CTRL, value);
01260         }
01261         value = AT_READ_REGW(hw, REG_PCIE_CAP_LIST);
01262         return ((value & 0xFF00) == 0x6C00) ? 0 : 1;
01263 }
01264 
01265 void atl1e_hw_set_mac_addr(struct atl1e_hw *hw)
01266 {
01267         u32 value;
01268         /*
01269          * 00-0B-6A-F6-00-DC
01270          * 0:  6AF600DC 1: 000B
01271          * low dword
01272          */
01273         value = (((u32)hw->mac_addr[2]) << 24) |
01274                 (((u32)hw->mac_addr[3]) << 16) |
01275                 (((u32)hw->mac_addr[4]) << 8)  |
01276                 (((u32)hw->mac_addr[5])) ;
01277         AT_WRITE_REG_ARRAY(hw, REG_MAC_STA_ADDR, 0, value);
01278         /* hight dword */
01279         value = (((u32)hw->mac_addr[0]) << 8) |
01280                 (((u32)hw->mac_addr[1])) ;
01281         AT_WRITE_REG_ARRAY(hw, REG_MAC_STA_ADDR, 1, value);
01282 }
01283 
01284 /*
01285  * atl1e_get_permanent_address
01286  * return 0 if get valid mac address,
01287  */
01288 static int atl1e_get_permanent_address(struct atl1e_hw *hw)
01289 {
01290         union {
01291                 u32 dword[2];
01292                 u8 byte[8];
01293         } hw_addr;
01294         u32 i;
01295         u32 twsi_ctrl_data;
01296         u8  eth_addr[ETH_ALEN];
01297 
01298         if (!atl1e_check_eeprom_exist(hw)) {
01299                 /* eeprom exist */
01300                 twsi_ctrl_data = AT_READ_REG(hw, REG_TWSI_CTRL);
01301                 twsi_ctrl_data |= TWSI_CTRL_SW_LDSTART;
01302                 AT_WRITE_REG(hw, REG_TWSI_CTRL, twsi_ctrl_data);
01303                 for (i = 0; i < AT_TWSI_EEPROM_TIMEOUT; i++) {
01304                         mdelay(10);
01305                         twsi_ctrl_data = AT_READ_REG(hw, REG_TWSI_CTRL);
01306                         if ((twsi_ctrl_data & TWSI_CTRL_SW_LDSTART) == 0)
01307                                 break;
01308                 }
01309                 if (i >= AT_TWSI_EEPROM_TIMEOUT)
01310                         return AT_ERR_TIMEOUT;
01311         }
01312 
01313         /* maybe MAC-address is from BIOS */
01314         hw_addr.dword[0] = AT_READ_REG(hw, REG_MAC_STA_ADDR);
01315         hw_addr.dword[1] = AT_READ_REG(hw, REG_MAC_STA_ADDR + 4);
01316         for (i = 0; i < ETH_ALEN; i++) {
01317                 eth_addr[ETH_ALEN - i - 1] = hw_addr.byte[i];
01318         }
01319 
01320         memcpy(hw->perm_mac_addr, eth_addr, ETH_ALEN);
01321         return 0;
01322 }
01323 
01324 void atl1e_force_ps(struct atl1e_hw *hw)
01325 {
01326         AT_WRITE_REGW(hw, REG_GPHY_CTRL,
01327                         GPHY_CTRL_PW_WOL_DIS | GPHY_CTRL_EXT_RESET);
01328 }
01329 
01330 /*
01331  * Reads the adapter's MAC address from the EEPROM
01332  *
01333  * hw - Struct containing variables accessed by shared code
01334  */
01335 int atl1e_read_mac_addr(struct atl1e_hw *hw)
01336 {
01337         int err = 0;
01338 
01339         err = atl1e_get_permanent_address(hw);
01340         if (err)
01341                 return AT_ERR_EEPROM;
01342         memcpy(hw->mac_addr, hw->perm_mac_addr, sizeof(hw->perm_mac_addr));
01343         return 0;
01344 }
01345 
01346 /*
01347  * Reads the value from a PHY register
01348  * hw - Struct containing variables accessed by shared code
01349  * reg_addr - address of the PHY register to read
01350  */
01351 int atl1e_read_phy_reg(struct atl1e_hw *hw, u16 reg_addr, u16 *phy_data)
01352 {
01353         u32 val;
01354         int i;
01355 
01356         val = ((u32)(reg_addr & MDIO_REG_ADDR_MASK)) << MDIO_REG_ADDR_SHIFT |
01357                 MDIO_START | MDIO_SUP_PREAMBLE | MDIO_RW |
01358                 MDIO_CLK_25_4 << MDIO_CLK_SEL_SHIFT;
01359 
01360         AT_WRITE_REG(hw, REG_MDIO_CTRL, val);
01361 
01362         wmb();
01363 
01364         for (i = 0; i < MDIO_WAIT_TIMES; i++) {
01365                 udelay(2);
01366                 val = AT_READ_REG(hw, REG_MDIO_CTRL);
01367                 if (!(val & (MDIO_START | MDIO_BUSY)))
01368                         break;
01369                 wmb();
01370         }
01371         if (!(val & (MDIO_START | MDIO_BUSY))) {
01372                 *phy_data = (u16)val;
01373                 return 0;
01374         }
01375 
01376         return AT_ERR_PHY;
01377 }
01378 
01379 /*
01380  * Writes a value to a PHY register
01381  * hw - Struct containing variables accessed by shared code
01382  * reg_addr - address of the PHY register to write
01383  * data - data to write to the PHY
01384  */
01385 int atl1e_write_phy_reg(struct atl1e_hw *hw, u32 reg_addr, u16 phy_data)
01386 {
01387         int i;
01388         u32 val;
01389 
01390         val = ((u32)(phy_data & MDIO_DATA_MASK)) << MDIO_DATA_SHIFT |
01391                (reg_addr&MDIO_REG_ADDR_MASK) << MDIO_REG_ADDR_SHIFT |
01392                MDIO_SUP_PREAMBLE |
01393                MDIO_START |
01394                MDIO_CLK_25_4 << MDIO_CLK_SEL_SHIFT;
01395 
01396         AT_WRITE_REG(hw, REG_MDIO_CTRL, val);
01397         wmb();
01398 
01399         for (i = 0; i < MDIO_WAIT_TIMES; i++) {
01400                 udelay(2);
01401                 val = AT_READ_REG(hw, REG_MDIO_CTRL);
01402                 if (!(val & (MDIO_START | MDIO_BUSY)))
01403                         break;
01404                 wmb();
01405         }
01406 
01407         if (!(val & (MDIO_START | MDIO_BUSY)))
01408                 return 0;
01409 
01410         return AT_ERR_PHY;
01411 }
01412 
01413 /*
01414  * atl1e_init_pcie - init PCIE module
01415  */
01416 static void atl1e_init_pcie(struct atl1e_hw *hw)
01417 {
01418         u32 value;
01419         /* comment 2lines below to save more power when sususpend
01420            value = LTSSM_TEST_MODE_DEF;
01421            AT_WRITE_REG(hw, REG_LTSSM_TEST_MODE, value);
01422          */
01423 
01424         /* pcie flow control mode change */
01425         value = AT_READ_REG(hw, 0x1008);
01426         value |= 0x8000;
01427         AT_WRITE_REG(hw, 0x1008, value);
01428 }
01429 /*
01430  * Configures PHY autoneg and flow control advertisement settings
01431  *
01432  * hw - Struct containing variables accessed by shared code
01433  */
01434 static int atl1e_phy_setup_autoneg_adv(struct atl1e_hw *hw)
01435 {
01436         s32 ret_val;
01437         u16 mii_autoneg_adv_reg;
01438         u16 mii_1000t_ctrl_reg;
01439 
01440         if (0 != hw->mii_autoneg_adv_reg)
01441                 return 0;
01442         /* Read the MII Auto-Neg Advertisement Register (Address 4/9). */
01443         mii_autoneg_adv_reg = MII_AR_DEFAULT_CAP_MASK;
01444         mii_1000t_ctrl_reg  = MII_AT001_CR_1000T_DEFAULT_CAP_MASK;
01445 
01446         /*
01447          * First we clear all the 10/100 mb speed bits in the Auto-Neg
01448          * Advertisement Register (Address 4) and the 1000 mb speed bits in
01449          * the  1000Base-T control Register (Address 9).
01450          */
01451         mii_autoneg_adv_reg &= ~MII_AR_SPEED_MASK;
01452         mii_1000t_ctrl_reg  &= ~MII_AT001_CR_1000T_SPEED_MASK;
01453 
01454         /* Assume auto-detect media type */
01455         mii_autoneg_adv_reg |= (MII_AR_10T_HD_CAPS   |
01456                                 MII_AR_10T_FD_CAPS   |
01457                                 MII_AR_100TX_HD_CAPS |
01458                                 MII_AR_100TX_FD_CAPS);
01459         if (hw->nic_type == athr_l1e) {
01460                 mii_1000t_ctrl_reg |= MII_AT001_CR_1000T_FD_CAPS;
01461         }
01462 
01463         /* flow control fixed to enable all */
01464         mii_autoneg_adv_reg |= (MII_AR_ASM_DIR | MII_AR_PAUSE);
01465 
01466         hw->mii_autoneg_adv_reg = mii_autoneg_adv_reg;
01467         hw->mii_1000t_ctrl_reg  = mii_1000t_ctrl_reg;
01468 
01469         ret_val = atl1e_write_phy_reg(hw, MII_ADVERTISE, mii_autoneg_adv_reg);
01470         if (ret_val)
01471                 return ret_val;
01472 
01473         if (hw->nic_type == athr_l1e || hw->nic_type == athr_l2e_revA) {
01474                 ret_val = atl1e_write_phy_reg(hw, MII_AT001_CR,
01475                                            mii_1000t_ctrl_reg);
01476                 if (ret_val)
01477                         return ret_val;
01478         }
01479 
01480         return 0;
01481 }
01482 
01483 
01484 /*
01485  * Resets the PHY and make all config validate
01486  *
01487  * hw - Struct containing variables accessed by shared code
01488  *
01489  * Sets bit 15 and 12 of the MII control regiser (for F001 bug)
01490  */
01491 int atl1e_phy_commit(struct atl1e_hw *hw)
01492 {
01493         int ret_val;
01494         u16 phy_data;
01495 
01496         phy_data = MII_CR_RESET | MII_CR_AUTO_NEG_EN | MII_CR_RESTART_AUTO_NEG;
01497 
01498         ret_val = atl1e_write_phy_reg(hw, MII_BMCR, phy_data);
01499         if (ret_val) {
01500                 u32 val;
01501                 int i;
01502                 /**************************************
01503                  * pcie serdes link may be down !
01504                  **************************************/
01505                 for (i = 0; i < 25; i++) {
01506                         mdelay(1);
01507                         val = AT_READ_REG(hw, REG_MDIO_CTRL);
01508                         if (!(val & (MDIO_START | MDIO_BUSY)))
01509                                 break;
01510                 }
01511 
01512                 if (0 != (val & (MDIO_START | MDIO_BUSY))) {
01513                         DBG("atl1e: PCI-E link down for at least 25ms\n");
01514                         return ret_val;
01515                 }
01516 
01517                 DBG("atl1e: PCI-E link up after %d ms\n", i);
01518         }
01519         return 0;
01520 }
01521 
01522 int atl1e_phy_init(struct atl1e_hw *hw)
01523 {
01524         s32 ret_val;
01525         u16 phy_val;
01526 
01527         if (hw->phy_configured) {
01528                 if (hw->re_autoneg) {
01529                         hw->re_autoneg = 0;
01530                         return atl1e_restart_autoneg(hw);
01531                 }
01532                 return 0;
01533         }
01534 
01535         /* RESET GPHY Core */
01536         AT_WRITE_REGW(hw, REG_GPHY_CTRL, GPHY_CTRL_DEFAULT);
01537         mdelay(2);
01538         AT_WRITE_REGW(hw, REG_GPHY_CTRL, GPHY_CTRL_DEFAULT |
01539                       GPHY_CTRL_EXT_RESET);
01540         mdelay(2);
01541 
01542         /* patches */
01543         /* p1. eable hibernation mode */
01544         ret_val = atl1e_write_phy_reg(hw, MII_DBG_ADDR, 0xB);
01545         if (ret_val)
01546                 return ret_val;
01547         ret_val = atl1e_write_phy_reg(hw, MII_DBG_DATA, 0xBC00);
01548         if (ret_val)
01549                 return ret_val;
01550         /* p2. set Class A/B for all modes */
01551         ret_val = atl1e_write_phy_reg(hw, MII_DBG_ADDR, 0);
01552         if (ret_val)
01553                 return ret_val;
01554         phy_val = 0x02ef;
01555         /* remove Class AB */
01556         /* phy_val = hw->emi_ca ? 0x02ef : 0x02df; */
01557         ret_val = atl1e_write_phy_reg(hw, MII_DBG_DATA, phy_val);
01558         if (ret_val)
01559                 return ret_val;
01560         /* p3. 10B ??? */
01561         ret_val = atl1e_write_phy_reg(hw, MII_DBG_ADDR, 0x12);
01562         if (ret_val)
01563                 return ret_val;
01564         ret_val = atl1e_write_phy_reg(hw, MII_DBG_DATA, 0x4C04);
01565         if (ret_val)
01566                 return ret_val;
01567         /* p4. 1000T power */
01568         ret_val = atl1e_write_phy_reg(hw, MII_DBG_ADDR, 0x4);
01569         if (ret_val)
01570                 return ret_val;
01571         ret_val = atl1e_write_phy_reg(hw, MII_DBG_DATA, 0x8BBB);
01572         if (ret_val)
01573                 return ret_val;
01574 
01575         ret_val = atl1e_write_phy_reg(hw, MII_DBG_ADDR, 0x5);
01576         if (ret_val)
01577                 return ret_val;
01578         ret_val = atl1e_write_phy_reg(hw, MII_DBG_DATA, 0x2C46);
01579         if (ret_val)
01580                 return ret_val;
01581 
01582         mdelay(1);
01583 
01584         /*Enable PHY LinkChange Interrupt */
01585         ret_val = atl1e_write_phy_reg(hw, MII_INT_CTRL, 0xC00);
01586         if (ret_val) {
01587                 DBG("atl1e: Error enable PHY linkChange Interrupt\n");
01588                 return ret_val;
01589         }
01590         /* setup AutoNeg parameters */
01591         ret_val = atl1e_phy_setup_autoneg_adv(hw);
01592         if (ret_val) {
01593                 DBG("atl1e: Error Setting up Auto-Negotiation\n");
01594                 return ret_val;
01595         }
01596         /* SW.Reset & En-Auto-Neg to restart Auto-Neg*/
01597         DBG("atl1e: Restarting Auto-Neg");
01598         ret_val = atl1e_phy_commit(hw);
01599         if (ret_val) {
01600                 DBG("atl1e: Error Resetting the phy");
01601                 return ret_val;
01602         }
01603 
01604         hw->phy_configured = 1;
01605 
01606         return 0;
01607 }
01608 
01609 /*
01610  * Reset the transmit and receive units; mask and clear all interrupts.
01611  * hw - Struct containing variables accessed by shared code
01612  * return : 0  or  idle status (if error)
01613  */
01614 int atl1e_reset_hw(struct atl1e_hw *hw)
01615 {
01616         struct atl1e_adapter *adapter = hw->adapter;
01617         struct pci_device *pdev = adapter->pdev;
01618         int timeout = 0;
01619         u32 idle_status_data = 0;
01620         u16 pci_cfg_cmd_word = 0;
01621 
01622         /* Workaround for PCI problem when BIOS sets MMRBC incorrectly. */
01623         pci_read_config_word(pdev, PCI_COMMAND, &pci_cfg_cmd_word);
01624         if ((pci_cfg_cmd_word & (PCI_COMMAND_IO | PCI_COMMAND_MEM |
01625                                  PCI_COMMAND_MASTER))
01626                         != (PCI_COMMAND_IO | PCI_COMMAND_MEM |
01627                             PCI_COMMAND_MASTER)) {
01628                 pci_cfg_cmd_word |= (PCI_COMMAND_IO | PCI_COMMAND_MEM |
01629                                      PCI_COMMAND_MASTER);
01630                 pci_write_config_word(pdev, PCI_COMMAND, pci_cfg_cmd_word);
01631         }
01632 
01633         /*
01634          * Issue Soft Reset to the MAC.  This will reset the chip's
01635          * transmit, receive, DMA.  It will not effect
01636          * the current PCI configuration.  The global reset bit is self-
01637          * clearing, and should clear within a microsecond.
01638          */
01639         AT_WRITE_REG(hw, REG_MASTER_CTRL,
01640                         MASTER_CTRL_LED_MODE | MASTER_CTRL_SOFT_RST);
01641         wmb();
01642         mdelay(1);
01643 
01644         /* Wait at least 10ms for All module to be Idle */
01645         for (timeout = 0; timeout < AT_HW_MAX_IDLE_DELAY; timeout++) {
01646                 idle_status_data = AT_READ_REG(hw, REG_IDLE_STATUS);
01647                 if (idle_status_data == 0)
01648                         break;
01649                 mdelay(1);
01650         }
01651 
01652         if (timeout >= AT_HW_MAX_IDLE_DELAY) {
01653                 DBG("atl1e: MAC reset timeout\n");
01654                 return AT_ERR_TIMEOUT;
01655         }
01656 
01657         return 0;
01658 }
01659 
01660 
01661 /*
01662  * Performs basic configuration of the adapter.
01663  *
01664  * hw - Struct containing variables accessed by shared code
01665  * Assumes that the controller has previously been reset and is in a
01666  * post-reset uninitialized state. Initializes multicast table,
01667  * and  Calls routines to setup link
01668  * Leaves the transmit and receive units disabled and uninitialized.
01669  */
01670 int atl1e_init_hw(struct atl1e_hw *hw)
01671 {
01672         s32 ret_val = 0;
01673 
01674         atl1e_init_pcie(hw);
01675 
01676         /* Zero out the Multicast HASH table */
01677         /* clear the old settings from the multicast hash table */
01678         AT_WRITE_REG(hw, REG_RX_HASH_TABLE, 0);
01679         AT_WRITE_REG_ARRAY(hw, REG_RX_HASH_TABLE, 1, 0);
01680 
01681         ret_val = atl1e_phy_init(hw);
01682 
01683         return ret_val;
01684 }
01685 
01686 /*
01687  * Detects the current speed and duplex settings of the hardware.
01688  *
01689  * hw - Struct containing variables accessed by shared code
01690  * speed - Speed of the connection
01691  * duplex - Duplex setting of the connection
01692  */
01693 int atl1e_get_speed_and_duplex(struct atl1e_hw *hw, u16 *speed, u16 *duplex)
01694 {
01695         int err;
01696         u16 phy_data;
01697 
01698         /* Read   PHY Specific Status Register (17) */
01699         err = atl1e_read_phy_reg(hw, MII_AT001_PSSR, &phy_data);
01700         if (err)
01701                 return err;
01702 
01703         if (!(phy_data & MII_AT001_PSSR_SPD_DPLX_RESOLVED))
01704                 return AT_ERR_PHY_RES;
01705 
01706         switch (phy_data & MII_AT001_PSSR_SPEED) {
01707         case MII_AT001_PSSR_1000MBS:
01708                 *speed = SPEED_1000;
01709                 break;
01710         case MII_AT001_PSSR_100MBS:
01711                 *speed = SPEED_100;
01712                 break;
01713         case MII_AT001_PSSR_10MBS:
01714                 *speed = SPEED_10;
01715                 break;
01716         default:
01717                 return AT_ERR_PHY_SPEED;
01718                 break;
01719         }
01720 
01721         if (phy_data & MII_AT001_PSSR_DPLX)
01722                 *duplex = FULL_DUPLEX;
01723         else
01724                 *duplex = HALF_DUPLEX;
01725 
01726         return 0;
01727 }
01728 
01729 int atl1e_restart_autoneg(struct atl1e_hw *hw)
01730 {
01731         int err = 0;
01732 
01733         err = atl1e_write_phy_reg(hw, MII_ADVERTISE, hw->mii_autoneg_adv_reg);
01734         if (err)
01735                 return err;
01736 
01737         if (hw->nic_type == athr_l1e || hw->nic_type == athr_l2e_revA) {
01738                 err = atl1e_write_phy_reg(hw, MII_AT001_CR,
01739                                        hw->mii_1000t_ctrl_reg);
01740                 if (err)
01741                         return err;
01742         }
01743 
01744         err = atl1e_write_phy_reg(hw, MII_BMCR,
01745                         MII_CR_RESET | MII_CR_AUTO_NEG_EN |
01746                         MII_CR_RESTART_AUTO_NEG);
01747         return err;
01748 }
01749