iPXE
b44.h
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00001 /*
00002  * Copyright (c) 2008 Stefan Hajnoczi <stefanha@gmail.com>
00003  * Copyright (c) 2008 Pantelis Koukousoulas <pktoss@gmail.com>
00004  *
00005  * This program is free software; you can redistribute it and/or
00006  * modify it under the terms of the GNU General Public License as
00007  * published by the Free Software Foundation; either version 2 of the
00008  * License, or any later version.
00009  *
00010  * This program is distributed in the hope that it will be useful, but
00011  * WITHOUT ANY WARRANTY; without even the implied warranty of
00012  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
00013  * General Public License for more details.
00014  *
00015  * You should have received a copy of the GNU General Public License
00016  * along with this program; if not, write to the Free Software
00017  * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
00018  * 02110-1301, USA.
00019  *
00020  * This driver is a port of the b44 linux driver version 1.01
00021  *
00022  * Copyright (c) 2002 David S. Miller <davem@redhat.com>
00023  * Copyright (c) Pekka Pietikainen <pp@ee.oulu.fi>
00024  * Copyright (C) 2006 Broadcom Corporation.
00025  *
00026  * Some ssb bits copied from version 2.0 of the b44 driver
00027  * Copyright (c) Michael Buesch
00028  *
00029  * Copyright (c) a lot of people too. Please respect their work.
00030  */
00031 
00032 FILE_LICENCE ( GPL2_OR_LATER );
00033 
00034 #ifndef _B44_H
00035 #define _B44_H
00036 
00037 /* BCM44xx Register layout */
00038 #define B44_DEVCTRL             0x0000UL /* Device Control */
00039 #define  DEVCTRL_MPM            0x00000040 /* MP PME Enable (B0 only) */
00040 #define  DEVCTRL_PFE            0x00000080 /* Pattern Filtering Enable */
00041 #define  DEVCTRL_IPP            0x00000400 /* Internal EPHY Present */
00042 #define  DEVCTRL_EPR            0x00008000 /* EPHY Reset */
00043 #define  DEVCTRL_PME            0x00001000 /* PHY Mode Enable */
00044 #define  DEVCTRL_PMCE           0x00002000 /* PHY Mode Clocks Enable */
00045 #define  DEVCTRL_PADDR          0x0007c000 /* PHY Address */
00046 #define  DEVCTRL_PADDR_SHIFT    18
00047 #define B44_BIST_STAT           0x000CUL /* Built-In Self-Test Status */
00048 #define B44_WKUP_LEN            0x0010UL /* Wakeup Length */
00049 #define  WKUP_LEN_P0_MASK       0x0000007f /* Pattern 0 */
00050 #define  WKUP_LEN_D0            0x00000080
00051 #define  WKUP_LEN_P1_MASK       0x00007f00 /* Pattern 1 */
00052 #define  WKUP_LEN_P1_SHIFT      8
00053 #define  WKUP_LEN_D1            0x00008000
00054 #define  WKUP_LEN_P2_MASK       0x007f0000 /* Pattern 2 */
00055 #define  WKUP_LEN_P2_SHIFT      16
00056 #define  WKUP_LEN_D2            0x00000000
00057 #define  WKUP_LEN_P3_MASK       0x7f000000 /* Pattern 3 */
00058 #define  WKUP_LEN_P3_SHIFT      24
00059 #define  WKUP_LEN_D3            0x80000000
00060 #define  WKUP_LEN_DISABLE       0x80808080
00061 #define  WKUP_LEN_ENABLE_TWO    0x80800000
00062 #define  WKUP_LEN_ENABLE_THREE  0x80000000
00063 #define B44_ISTAT               0x0020UL /* Interrupt Status */
00064 #define  ISTAT_LS               0x00000020 /* Link Change (B0 only) */
00065 #define  ISTAT_PME              0x00000040 /* Power Management Event */
00066 #define  ISTAT_TO               0x00000080 /* General Purpose Timeout */
00067 #define  ISTAT_DSCE             0x00000400 /* Descriptor Error */
00068 #define  ISTAT_DATAE            0x00000800 /* Data Error */
00069 #define  ISTAT_DPE              0x00001000 /* Descr. Protocol Error */
00070 #define  ISTAT_RDU              0x00002000 /* Receive Descr. Underflow */
00071 #define  ISTAT_RFO              0x00004000 /* Receive FIFO Overflow */
00072 #define  ISTAT_TFU              0x00008000 /* Transmit FIFO Underflow */
00073 #define  ISTAT_RX               0x00010000 /* RX Interrupt */
00074 #define  ISTAT_TX               0x01000000 /* TX Interrupt */
00075 #define  ISTAT_EMAC             0x04000000 /* EMAC Interrupt */
00076 #define  ISTAT_MII_WRITE        0x08000000 /* MII Write Interrupt */
00077 #define  ISTAT_MII_READ         0x10000000 /* MII Read Interrupt */
00078 #define  ISTAT_ERRORS           (ISTAT_DSCE|ISTAT_DATAE|ISTAT_DPE|\
00079                                  ISTAT_RDU|ISTAT_RFO|ISTAT_TFU)
00080 #define B44_IMASK               0x0024UL /* Interrupt Mask */
00081 #define  IMASK_DEF              (ISTAT_ERRORS | ISTAT_RX | ISTAT_TX)
00082 #define  IMASK_DISABLE          0
00083 #define B44_GPTIMER             0x0028UL /* General Purpose Timer */
00084 #define B44_ADDR_LO             0x0088UL /* ENET Address Lo (B0 only) */
00085 #define B44_ADDR_HI             0x008CUL /* ENET Address Hi (B0 only) */
00086 #define B44_FILT_ADDR           0x0090UL /* ENET Filter Address */
00087 #define B44_FILT_DATA           0x0094UL /* ENET Filter Data */
00088 #define B44_TXBURST             0x00A0UL /* TX Max Burst Length */
00089 #define B44_RXBURST             0x00A4UL /* RX Max Burst Length */
00090 #define B44_MAC_CTRL            0x00A8UL /* MAC Control */
00091 #define  MAC_CTRL_CRC32_ENAB    0x00000001 /* CRC32 Generation Enable */
00092 #define  MAC_CTRL_PHY_PDOWN     0x00000004 /* Onchip EPHY Powerdown */
00093 #define  MAC_CTRL_PHY_EDET      0x00000008 /* Onchip EPHY Energy Detected*/
00094 #define  MAC_CTRL_PHY_LEDCTRL   0x000000e0 /* Onchip EPHY LED Control */
00095 #define  MAC_CTRL_PHY_LEDCTRL_SHIFT 5
00096 #define B44_MAC_FLOW            0x00ACUL /* MAC Flow Control */
00097 #define  MAC_FLOW_RX_HI_WATER   0x000000ff /* Receive FIFO HI Water Mark */
00098 #define  MAC_FLOW_PAUSE_ENAB    0x00008000 /* Enbl Pause Frm Generation */
00099 #define B44_RCV_LAZY            0x0100UL /* Lazy Interrupt Control */
00100 #define  RCV_LAZY_TO_MASK       0x00ffffff /* Timeout */
00101 #define  RCV_LAZY_FC_MASK       0xff000000 /* Frame Count */
00102 #define  RCV_LAZY_FC_SHIFT      24
00103 #define B44_DMATX_CTRL          0x0200UL /* DMA TX Control */
00104 #define  DMATX_CTRL_ENABLE      0x00000001 /* Enable */
00105 #define  DMATX_CTRL_SUSPEND     0x00000002 /* Suepend Request */
00106 #define  DMATX_CTRL_LPBACK      0x00000004 /* Loopback Enable */
00107 #define  DMATX_CTRL_FAIRPRIOR   0x00000008 /* Fair Priority */
00108 #define  DMATX_CTRL_FLUSH       0x00000010 /* Flush Request */
00109 #define B44_DMATX_ADDR          0x0204UL /* DMA TX Descriptor Ring Addr */
00110 #define B44_DMATX_PTR           0x0208UL /* DMA TX Last Posted Desc. */
00111 #define B44_DMATX_STAT          0x020CUL /* DMA TX Cur Actve Desc. + Sts */
00112 #define  DMATX_STAT_CDMASK      0x00000fff /* Current Descriptor Mask */
00113 #define  DMATX_STAT_SMASK       0x0000f000 /* State Mask */
00114 #define  DMATX_STAT_SDISABLED   0x00000000 /* State Disabled */
00115 #define  DMATX_STAT_SACTIVE     0x00001000 /* State Active */
00116 #define  DMATX_STAT_SIDLE       0x00002000 /* State Idle Wait */
00117 #define  DMATX_STAT_SSTOPPED    0x00003000 /* State Stopped */
00118 #define  DMATX_STAT_SSUSP       0x00004000 /* State Suspend Pending */
00119 #define  DMATX_STAT_EMASK       0x000f0000 /* Error Mask */
00120 #define  DMATX_STAT_ENONE       0x00000000 /* Error None */
00121 #define  DMATX_STAT_EDPE        0x00010000 /* Error Desc. Protocol Error */
00122 #define  DMATX_STAT_EDFU        0x00020000 /* Error Data FIFO Underrun */
00123 #define  DMATX_STAT_EBEBR       0x00030000 /* Bus Error on Buffer Read */
00124 #define  DMATX_STAT_EBEDA       0x00040000 /* Bus Error on Desc. Access */
00125 #define  DMATX_STAT_FLUSHED     0x00100000 /* Flushed */
00126 #define B44_DMARX_CTRL          0x0210UL /* DMA RX Control */
00127 #define  DMARX_CTRL_ENABLE      0x00000001 /* Enable */
00128 #define  DMARX_CTRL_ROMASK      0x000000fe /* Receive Offset Mask */
00129 #define  DMARX_CTRL_ROSHIFT     1          /* Receive Offset Shift */
00130 #define B44_DMARX_ADDR          0x0214UL /* DMA RX Descriptor Ring Addr */
00131 #define B44_DMARX_PTR           0x0218UL /* DMA RX Last Posted Desc */
00132 #define B44_DMARX_STAT          0x021CUL /* Cur Active Desc. + Status */
00133 #define  DMARX_STAT_CDMASK      0x00000fff /* Current Descriptor Mask */
00134 #define  DMARX_STAT_SMASK       0x0000f000 /* State Mask */
00135 #define  DMARX_STAT_SDISABLED   0x00000000 /* State Disbaled */
00136 #define  DMARX_STAT_SACTIVE     0x00001000 /* State Active */
00137 #define  DMARX_STAT_SIDLE       0x00002000 /* State Idle Wait */
00138 #define  DMARX_STAT_SSTOPPED    0x00003000 /* State Stopped */
00139 #define  DMARX_STAT_EMASK       0x000f0000 /* Error Mask */
00140 #define  DMARX_STAT_ENONE       0x00000000 /* Error None */
00141 #define  DMARX_STAT_EDPE        0x00010000 /* Error Desc. Protocol Error */
00142 #define  DMARX_STAT_EDFO        0x00020000 /* Error Data FIFO Overflow */
00143 #define  DMARX_STAT_EBEBW       0x00030000 /* Error on Buffer Write */
00144 #define  DMARX_STAT_EBEDA       0x00040000 /* Bus Error on Desc. Access */
00145 #define B44_DMAFIFO_AD          0x0220UL /* DMA FIFO Diag Address */
00146 #define  DMAFIFO_AD_OMASK       0x0000ffff /* Offset Mask */
00147 #define  DMAFIFO_AD_SMASK       0x000f0000 /* Select Mask */
00148 #define  DMAFIFO_AD_SXDD        0x00000000 /* Select Transmit DMA Data */
00149 #define  DMAFIFO_AD_SXDP        0x00010000 /* Sel Transmit DMA Pointers */
00150 #define  DMAFIFO_AD_SRDD        0x00040000 /* Select Receive DMA Data */
00151 #define  DMAFIFO_AD_SRDP        0x00050000 /* Sel Receive DMA Pointers */
00152 #define  DMAFIFO_AD_SXFD        0x00080000 /* Select Transmit FIFO Data */
00153 #define  DMAFIFO_AD_SXFP        0x00090000 /* Sel Transmit FIFO Pointers */
00154 #define  DMAFIFO_AD_SRFD        0x000c0000 /* Select Receive FIFO Data */
00155 #define  DMAFIFO_AD_SRFP        0x000c0000 /* Sel Receive FIFO Pointers */
00156 #define B44_DMAFIFO_LO          0x0224UL /* DMA FIFO Diag Low Data */
00157 #define B44_DMAFIFO_HI          0x0228UL /* DMA FIFO Diag High Data */
00158 #define B44_RXCONFIG            0x0400UL /* EMAC RX Config */
00159 #define  RXCONFIG_DBCAST        0x00000001 /* Disable Broadcast */
00160 #define  RXCONFIG_ALLMULTI      0x00000002 /* Accept All Multicast */
00161 #define  RXCONFIG_NORX_WHILE_TX 0x00000004 /* Rcv Disble While TX */
00162 #define  RXCONFIG_PROMISC       0x00000008 /* Promiscuous Enable */
00163 #define  RXCONFIG_LPBACK        0x00000010 /* Loopback Enable */
00164 #define  RXCONFIG_FLOW          0x00000020 /* Flow Control Enable */
00165 #define  RXCONFIG_FLOW_ACCEPT   0x00000040 /* Accept UFC Frame */
00166 #define  RXCONFIG_RFILT         0x00000080 /* Reject Filter */
00167 #define B44_RXMAXLEN            0x0404UL /* EMAC RX Max Packet Length */
00168 #define B44_TXMAXLEN            0x0408UL /* EMAC TX Max Packet Length */
00169 #define B44_MDIO_CTRL           0x0410UL /* EMAC MDIO Control */
00170 #define  MDIO_CTRL_MAXF_MASK    0x0000007f /* MDC Frequency */
00171 #define  MDIO_CTRL_PREAMBLE     0x00000080 /* MII Preamble Enable */
00172 #define B44_MDIO_DATA           0x0414UL /* EMAC MDIO Data */
00173 #define  MDIO_DATA_DATA         0x0000ffff /* R/W Data */
00174 #define  MDIO_DATA_TA_MASK      0x00030000 /* Turnaround Value */
00175 #define  MDIO_DATA_TA_SHIFT     16
00176 #define  MDIO_TA_VALID          2
00177 #define  MDIO_DATA_RA_MASK      0x007c0000 /* Register Address */
00178 #define  MDIO_DATA_RA_SHIFT     18
00179 #define  MDIO_DATA_PMD_MASK     0x0f800000 /* Physical Media Device */
00180 #define  MDIO_DATA_PMD_SHIFT    23
00181 #define  MDIO_DATA_OP_MASK      0x30000000 /* Opcode */
00182 #define  MDIO_DATA_OP_SHIFT     28
00183 #define  MDIO_OP_WRITE          1
00184 #define  MDIO_OP_READ           2
00185 #define  MDIO_DATA_SB_MASK      0xc0000000 /* Start Bits */
00186 #define  MDIO_DATA_SB_SHIFT     30
00187 #define  MDIO_DATA_SB_START     0x40000000 /* Start Of Frame */
00188 #define B44_EMAC_IMASK          0x0418UL /* EMAC Interrupt Mask */
00189 #define B44_EMAC_ISTAT          0x041CUL /* EMAC Interrupt Status */
00190 #define  EMAC_INT_MII           0x00000001 /* MII MDIO Interrupt */
00191 #define  EMAC_INT_MIB           0x00000002 /* MIB Interrupt */
00192 #define  EMAC_INT_FLOW          0x00000003 /* Flow Control Interrupt */
00193 #define B44_CAM_DATA_LO         0x0420UL /* EMAC CAM Data Low */
00194 #define B44_CAM_DATA_HI         0x0424UL /* EMAC CAM Data High */
00195 #define  CAM_DATA_HI_VALID      0x00010000 /* Valid Bit */
00196 #define B44_CAM_CTRL            0x0428UL /* EMAC CAM Control */
00197 #define  CAM_CTRL_ENABLE        0x00000001 /* CAM Enable */
00198 #define  CAM_CTRL_MSEL          0x00000002 /* Mask Select */
00199 #define  CAM_CTRL_READ          0x00000004 /* Read */
00200 #define  CAM_CTRL_WRITE         0x00000008 /* Read */
00201 #define  CAM_CTRL_INDEX_MASK    0x003f0000 /* Index Mask */
00202 #define  CAM_CTRL_INDEX_SHIFT   16
00203 #define  CAM_CTRL_BUSY          0x80000000 /* CAM Busy */
00204 #define B44_ENET_CTRL           0x042CUL /* EMAC ENET Control */
00205 #define  ENET_CTRL_ENABLE       0x00000001 /* EMAC Enable */
00206 #define  ENET_CTRL_DISABLE      0x00000002 /* EMAC Disable */
00207 #define  ENET_CTRL_SRST         0x00000004 /* EMAC Soft Reset */
00208 #define  ENET_CTRL_EPSEL        0x00000008 /* External PHY Select */
00209 #define B44_TX_CTRL             0x0430UL /* EMAC TX Control */
00210 #define  TX_CTRL_DUPLEX         0x00000001 /* Full Duplex */
00211 #define  TX_CTRL_FMODE          0x00000002 /* Flow Mode */
00212 #define  TX_CTRL_SBENAB         0x00000004 /* Single Backoff Enable */
00213 #define  TX_CTRL_SMALL_SLOT     0x00000008 /* Small Slottime */
00214 #define B44_TX_HIWMARK          0x0434UL /* EMAC TX High Watermark */
00215 #define  TX_HIWMARK_DEFLT       56  /* Default used in all drivers */
00216 #define B44_MIB_CTRL            0x0438UL /* EMAC MIB Control */
00217 #define  MIB_CTRL_CLR_ON_READ   0x00000001 /* Autoclear on Read */
00218 #define B44_TX_GOOD_O           0x0500UL /* MIB TX Good Octets */
00219 #define B44_TX_GOOD_P           0x0504UL /* MIB TX Good Packets */
00220 #define B44_TX_O                0x0508UL /* MIB TX Octets */
00221 #define B44_TX_P                0x050CUL /* MIB TX Packets */
00222 #define B44_TX_BCAST            0x0510UL /* MIB TX Broadcast Packets */
00223 #define B44_TX_MCAST            0x0514UL /* MIB TX Multicast Packets */
00224 #define B44_TX_64               0x0518UL /* MIB TX <= 64 byte Packets */
00225 #define B44_TX_65_127           0x051CUL /* MIB TX 65 to 127 byte Pkts */
00226 #define B44_TX_128_255          0x0520UL /* MIB TX 128 to 255 byte Pkts */
00227 #define B44_TX_256_511          0x0524UL /* MIB TX 256 to 511 byte Pkts */
00228 #define B44_TX_512_1023         0x0528UL /* MIB TX 512 to 1023 byte Pkts */
00229 #define B44_TX_1024_MAX         0x052CUL /* MIB TX 1024 to max byte Pkts */
00230 #define B44_TX_JABBER           0x0530UL /* MIB TX Jabber Packets */
00231 #define B44_TX_OSIZE            0x0534UL /* MIB TX Oversize Packets */
00232 #define B44_TX_FRAG             0x0538UL /* MIB TX Fragment Packets */
00233 #define B44_TX_URUNS            0x053CUL /* MIB TX Underruns */
00234 #define B44_TX_TCOLS            0x0540UL /* MIB TX Total Collisions */
00235 #define B44_TX_SCOLS            0x0544UL /* MIB TX Single Collisions */
00236 #define B44_TX_MCOLS            0x0548UL /* MIB TX Multiple Collisions */
00237 #define B44_TX_ECOLS            0x054CUL /* MIB TX Excessive Collisions */
00238 #define B44_TX_LCOLS            0x0550UL /* MIB TX Late Collisions */
00239 #define B44_TX_DEFERED          0x0554UL /* MIB TX Defered Packets */
00240 #define B44_TX_CLOST            0x0558UL /* MIB TX Carrier Lost */
00241 #define B44_TX_PAUSE            0x055CUL /* MIB TX Pause Packets */
00242 #define B44_RX_GOOD_O           0x0580UL /* MIB RX Good Octets */
00243 #define B44_RX_GOOD_P           0x0584UL /* MIB RX Good Packets */
00244 #define B44_RX_O                0x0588UL /* MIB RX Octets */
00245 #define B44_RX_P                0x058CUL /* MIB RX Packets */
00246 #define B44_RX_BCAST            0x0590UL /* MIB RX Broadcast Packets */
00247 #define B44_RX_MCAST            0x0594UL /* MIB RX Multicast Packets */
00248 #define B44_RX_64               0x0598UL /* MIB RX <= 64 byte Packets */
00249 #define B44_RX_65_127           0x059CUL /* MIB RX 65 to 127 byte Pkts */
00250 #define B44_RX_128_255          0x05A0UL /* MIB RX 128 to 255 byte Pkts */
00251 #define B44_RX_256_511          0x05A4UL /* MIB RX 256 to 511 byte Pkts */
00252 #define B44_RX_512_1023         0x05A8UL /* MIB RX 512 to 1023 byte Pkts */
00253 #define B44_RX_1024_MAX         0x05ACUL /* MIB RX 1024 to max byte Pkts */
00254 #define B44_RX_JABBER           0x05B0UL /* MIB RX Jabber Packets */
00255 #define B44_RX_OSIZE            0x05B4UL /* MIB RX Oversize Packets */
00256 #define B44_RX_FRAG             0x05B8UL /* MIB RX Fragment Packets */
00257 #define B44_RX_MISS             0x05BCUL /* MIB RX Missed Packets */
00258 #define B44_RX_CRCA             0x05C0UL /* MIB RX CRC Align Errors */
00259 #define B44_RX_USIZE            0x05C4UL /* MIB RX Undersize Packets */
00260 #define B44_RX_CRC              0x05C8UL /* MIB RX CRC Errors */
00261 #define B44_RX_ALIGN            0x05CCUL /* MIB RX Align Errors */
00262 #define B44_RX_SYM              0x05D0UL /* MIB RX Symbol Errors */
00263 #define B44_RX_PAUSE            0x05D4UL /* MIB RX Pause Packets */
00264 #define B44_RX_NPAUSE           0x05D8UL /* MIB RX Non-Pause Packets */
00265 
00266 /* Sonics Silicon backplane register definitions */
00267 #define B44_SBIMSTATE           0x0F90UL /* SB Initiator Agent State */
00268 #define  SBIMSTATE_PC           0x0000000f /* Pipe Count */
00269 #define  SBIMSTATE_AP_MASK      0x00000030 /* Arbitration Priority */
00270 #define  SBIMSTATE_AP_BOTH      0x00000000 /* both timeslices and token */
00271 #define  SBIMSTATE_AP_TS        0x00000010 /* Use timeslices only */
00272 #define  SBIMSTATE_AP_TK        0x00000020 /* Use token only */
00273 #define  SBIMSTATE_AP_RSV       0x00000030 /* Reserved */
00274 #define  SBIMSTATE_IBE          0x00020000 /* In Band Error */
00275 #define  SBIMSTATE_TO           0x00040000 /* Timeout */
00276 #define  SBIMSTATE_BAD      ( SBIMSTATE_IBE | SBIMSTATE_TO )
00277 #define B44_SBINTVEC            0x0F94UL /* SB Interrupt Mask */
00278 #define  SBINTVEC_PCI           0x00000001 /* Enable interrupts for PCI */
00279 #define  SBINTVEC_ENET0         0x00000002 /* Enable ints for enet 0 */
00280 #define  SBINTVEC_ILINE20       0x00000004 /* Enable ints for iline20 */
00281 #define  SBINTVEC_CODEC         0x00000008 /* Enable ints for v90 codec */
00282 #define  SBINTVEC_USB           0x00000010 /* Enable intts for usb */
00283 #define  SBINTVEC_EXTIF         0x00000020 /* Enable ints for ext i/f */
00284 #define  SBINTVEC_ENET1         0x00000040 /* Enable ints for enet 1 */
00285 #define B44_SBTMSLOW            0x0F98UL /* SB Target State Low */
00286 #define  SBTMSLOW_RESET         0x00000001 /* Reset */
00287 #define  SBTMSLOW_REJECT        0x00000002 /* Reject */
00288 #define  SBTMSLOW_CLOCK         0x00010000 /* Clock Enable */
00289 #define  SBTMSLOW_FGC           0x00020000 /* Force Gated Clocks On */
00290 #define  SBTMSLOW_PE            0x40000000 /* Power Management Enable */
00291 #define  SBTMSLOW_BE            0x80000000 /* BIST Enable */
00292 #define B44_SBTMSHIGH           0x0F9CUL /* SB Target State High */
00293 #define  SBTMSHIGH_SERR         0x00000001 /* S-error */
00294 #define  SBTMSHIGH_INT          0x00000002 /* Interrupt */
00295 #define  SBTMSHIGH_BUSY         0x00000004 /* Busy */
00296 #define  SBTMSHIGH_GCR          0x20000000 /* Gated Clock Request */
00297 #define  SBTMSHIGH_BISTF        0x40000000 /* BIST Failed */
00298 #define  SBTMSHIGH_BISTD        0x80000000 /* BIST Done */
00299 #define B44_SBIDHIGH            0x0FFCUL /* SB Identification High */
00300 #define  SBIDHIGH_RC_MASK       0x0000000f /* Revision Code */
00301 #define  SBIDHIGH_CC_MASK       0x0000fff0 /* Core Code */
00302 #define  SBIDHIGH_CC_SHIFT      4
00303 #define  SBIDHIGH_VC_MASK       0xffff0000 /* Vendor Code */
00304 #define  SBIDHIGH_VC_SHIFT      16
00305 
00306 /* SSB PCI config space registers.  */
00307 #define SSB_PMCSR               0x44
00308 #define  SSB_PE                 0x100
00309 #define SSB_BAR0_WIN            0x80
00310 #define SSB_BAR1_WIN            0x84
00311 #define SSB_SPROM_CONTROL       0x88
00312 #define SSB_BAR1_CONTROL        0x8c
00313 
00314 /* SSB core and host control registers.  */
00315 #define SSB_CONTROL             0x0000UL
00316 #define SSB_ARBCONTROL          0x0010UL
00317 #define SSB_ISTAT               0x0020UL
00318 #define SSB_IMASK               0x0024UL
00319 #define SSB_MBOX                0x0028UL
00320 #define SSB_BCAST_ADDR          0x0050UL
00321 #define SSB_BCAST_DATA          0x0054UL
00322 #define SSB_PCI_TRANS_0         0x0100UL
00323 #define SSB_PCI_TRANS_1         0x0104UL
00324 #define SSB_PCI_TRANS_2         0x0108UL
00325 #define SSB_SPROM               0x0800UL
00326 
00327 #define SSB_PCI_MEM             0x00000000
00328 #define SSB_PCI_IO              0x00000001
00329 #define SSB_PCI_CFG0            0x00000002
00330 #define SSB_PCI_CFG1            0x00000003
00331 #define SSB_PCI_PREF            0x00000004
00332 #define SSB_PCI_BURST           0x00000008
00333 #define SSB_PCI_MASK0           0xfc000000
00334 #define SSB_PCI_MASK1           0xfc000000
00335 #define SSB_PCI_MASK2           0xc0000000
00336 
00337 /* 4400 PHY registers */
00338 #define B44_MII_AUXCTRL         24      /* Auxiliary Control */
00339 #define  MII_AUXCTRL_DUPLEX     0x0001  /* Full Duplex */
00340 #define  MII_AUXCTRL_SPEED      0x0002  /* 1=100Mbps, 0=10Mbps */
00341 #define  MII_AUXCTRL_FORCED     0x0004  /* Forced 10/100 */
00342 #define B44_MII_ALEDCTRL        26      /* Activity LED */
00343 #define  MII_ALEDCTRL_ALLMSK    0x7fff
00344 #define B44_MII_TLEDCTRL        27      /* Traffic Meter LED */
00345 #define  MII_TLEDCTRL_ENABLE    0x0040
00346 
00347 /* RX/TX descriptor */
00348 struct dma_desc {
00349         u32 ctrl; /* length of data and flags */
00350         u32 addr; /* address of data */
00351 };
00352 
00353 /* There are only 12 bits in the DMA engine for descriptor offsetting
00354  * so the table must be aligned on a boundary of this.
00355  */
00356 #define B44_DMA_ALIGNMENT       4096
00357 
00358 /* The DMA engine can only address the first gigabyte of address space
00359  */
00360 #define B44_30BIT_DMA_MASK      0x3fffffff
00361 
00362 #define DESC_CTRL_LEN           0x00001fff
00363 #define DESC_CTRL_CMASK         0x0ff00000 /* Core specific bits */
00364 #define DESC_CTRL_EOT           0x10000000 /* End of Table */
00365 #define DESC_CTRL_IOC           0x20000000 /* Interrupt On Completion */
00366 #define DESC_CTRL_EOF           0x40000000 /* End of Frame */
00367 #define DESC_CTRL_SOF           0x80000000 /* Start of Frame */
00368 
00369 struct rx_header {
00370         u16 len;
00371         u16 flags;
00372         u16 pad[12];
00373 };
00374 #define RX_HEADER_LEN   28
00375 
00376 #define RX_FLAG_OFIFO   0x00000001 /* FIFO Overflow */
00377 #define RX_FLAG_CRCERR  0x00000002 /* CRC Error */
00378 #define RX_FLAG_SERR    0x00000004 /* Receive Symbol Error */
00379 #define RX_FLAG_ODD     0x00000008 /* Frame has odd number of nibbles */
00380 #define RX_FLAG_LARGE   0x00000010 /* Frame is > RX MAX Length */
00381 #define RX_FLAG_MCAST   0x00000020 /* Dest is Multicast Address */
00382 #define RX_FLAG_BCAST   0x00000040 /* Dest is Broadcast Address */
00383 #define RX_FLAG_MISS    0x00000080 /* Received due to promisc mode */
00384 #define RX_FLAG_LAST    0x00000800 /* Last buffer in frame */
00385 #define RX_FLAG_ERRORS  (RX_FLAG_ODD | RX_FLAG_SERR |\
00386                          RX_FLAG_CRCERR | RX_FLAG_OFIFO)
00387 
00388 /* Client Mode PCI memory access space (1 GB) */
00389 #define SB_PCI_DMA              0x40000000
00390 
00391  /* Address of PCI core on BCM4400 cards */
00392 #define BCM4400_PCI_CORE_ADDR   0x18002000
00393 
00394 /* Hardware minimum and maximum for a single frame's data payload */
00395 #define B44_MIN_MTU             60
00396 #define B44_MAX_MTU             1500
00397 
00398 #define B44_RING_SIZE           8
00399 #define B44_RING_LAST           ( B44_RING_SIZE - 1 )
00400 
00401 #define B44_RX_RING_LEN_BYTES   ( sizeof bp->rx[0] * B44_RING_SIZE )
00402 #define B44_TX_RING_LEN_BYTES   ( sizeof bp->tx[0] * B44_RING_SIZE )
00403 
00404 #define RX_PKT_OFFSET           30
00405 #define RX_PKT_BUF_SZ           (1536 + RX_PKT_OFFSET + 64)
00406 
00407 #define B44_FULL_RESET          1
00408 #define B44_FULL_RESET_SKIP_PHY 2
00409 #define B44_PARTIAL_RESET       3
00410 #define B44_CHIP_RESET_FULL     4
00411 #define B44_CHIP_RESET_PARTIAL  5
00412 
00413 #define SSB_CORE_DOWN           ( SBTMSLOW_RESET | SBTMSLOW_REJECT )
00414 
00415 #define B44_REGS_SIZE           8192
00416 
00417 /** Driver private state */
00418 struct b44_private {
00419         struct net_device *netdev;
00420         struct pci_device *pci;
00421         u8 *regs; /* memory-mapped registers */
00422         u8 phy_addr;
00423 
00424         struct dma_desc *tx;
00425         struct io_buffer *tx_iobuf[B44_RING_SIZE];
00426         u32 tx_cur; /* next available descriptor */
00427         u32 tx_dirty; /* oldest pending descriptor */
00428 
00429         struct dma_desc *rx;
00430         struct io_buffer *rx_iobuf[B44_RING_SIZE];
00431         u32 rx_cur; /* next descriptor to read */
00432 };
00433 
00434 
00435 static void ssb_core_reset ( struct b44_private *bp );
00436 static void ssb_core_disable ( struct b44_private *bp );
00437 static u32 ssb_pci_setup ( struct b44_private *bp, u32 cores );
00438 
00439 static void b44_chip_reset ( struct b44_private *bp, int reset_kind );
00440 static void b44_init_hw ( struct b44_private *bp, int reset_kind );
00441 static void b44_cam_write ( struct b44_private *bp, u8 *data, int index );
00442 static void b44_set_mac_addr ( struct b44_private *bp );
00443 static void b44_set_rx_mode ( struct net_device *netdev );
00444 static void b44_halt(struct b44_private *);
00445 
00446 static int b44_phy_reset ( struct b44_private *bp );
00447 static int b44_phy_write ( struct b44_private *bp, int reg, u32 val );
00448 static int b44_phy_read ( struct b44_private *bp, int reg, u32 *val );
00449 
00450 static int b44_init_tx_ring ( struct b44_private *bp );
00451 static void b44_free_tx_ring ( struct b44_private *bp );
00452 static int b44_init_rx_ring ( struct b44_private *bp );
00453 static void b44_free_rx_ring ( struct b44_private *bp );
00454 static void b44_rx_refill ( struct b44_private *bp, u32 pending );
00455 static void b44_populate_rx_descriptor (struct b44_private *bp, u32 index);
00456 
00457 static int b44_probe ( struct pci_device *pci );
00458 static void b44_remove ( struct pci_device *pci );
00459 
00460 static int b44_open ( struct net_device *netdev );
00461 static void b44_close ( struct net_device *netdev );
00462 static void b44_irq ( struct net_device *netdev, int enable );
00463 static void b44_poll ( struct net_device *netdev );
00464 static void b44_process_rx_packets ( struct b44_private *bp );
00465 static int b44_transmit ( struct net_device *netdev,
00466                           struct io_buffer *iobuf );
00467 
00468 static struct net_device_operations b44_operations;
00469 
00470 #endif /* _B44_H */