iPXE
bnx2.h
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00001 /* bnx2.h: Broadcom NX2 network driver.
00002  *
00003  * Copyright (c) 2004, 2005, 2006 Broadcom Corporation
00004  *
00005  * This program is free software; you can redistribute it and/or modify
00006  * it under the terms of the GNU General Public License as published by
00007  * the Free Software Foundation.
00008  *
00009  * Written by: Michael Chan  (mchan@broadcom.com)
00010  */
00011 
00012 FILE_LICENCE ( GPL_ANY );
00013 
00014 #ifndef BNX2_H
00015 #define BNX2_H
00016 
00017 #define L1_CACHE_BYTES 128 /* Rough approximaition of the cache line size */
00018 #define L1_CACHE_ALIGN(X) (((X) + L1_CACHE_BYTES-1)&~(L1_CACHE_BYTES -1))
00019 
00020 typedef unsigned long dma_addr_t;
00021 
00022 /* From pci.h */
00023 typedef int pci_power_t;
00024 
00025 #define PCI_D0          ((pci_power_t) 0)
00026 #define PCI_D1          ((pci_power_t) 1)
00027 #define PCI_D2          ((pci_power_t) 2)
00028 #define PCI_D3hot       ((pci_power_t) 3)
00029 #define PCI_D3cold      ((pci_power_t) 4)
00030 #define PCI_UNKNOWN     ((pci_power_t) 5)
00031 #define PCI_POWER_ERROR ((pci_power_t) -1)
00032 
00033 /* From pci_regs.h */
00034 
00035 #define  PCI_CAP_ID_PCIX        0x07    /* PCI-X */
00036 #define  PCI_X_CMD              2       /* Modes & Features */
00037 #define  PCI_X_CMD_ERO          0x0002  /* Enable Relaxed Ordering */
00038 
00039 /* From mii.h */
00040 
00041 /* Indicates what features are advertised by the interface. */
00042 #define ADVERTISED_10baseT_Half         (1 << 0)
00043 #define ADVERTISED_10baseT_Full         (1 << 1)
00044 #define ADVERTISED_100baseT_Half        (1 << 2)
00045 #define ADVERTISED_100baseT_Full        (1 << 3)
00046 #define ADVERTISED_1000baseT_Half       (1 << 4)
00047 #define ADVERTISED_1000baseT_Full       (1 << 5)
00048 #define ADVERTISED_Autoneg              (1 << 6)
00049 #define ADVERTISED_TP                   (1 << 7)
00050 #define ADVERTISED_AUI                  (1 << 8)
00051 #define ADVERTISED_MII                  (1 << 9)
00052 #define ADVERTISED_FIBRE                (1 << 10)
00053 #define ADVERTISED_BNC                  (1 << 11)
00054 
00055 /* The following are all involved in forcing a particular link
00056  * mode for the device for setting things.  When getting the
00057  * devices settings, these indicate the current mode and whether
00058  * it was foced up into this mode or autonegotiated.
00059  */
00060 
00061 /* Duplex, half or full. */
00062 #define DUPLEX_HALF             0x00
00063 #define DUPLEX_FULL             0x01
00064 #define DUPLEX_INVALID          0x02
00065 
00066 /* Which connector port. */
00067 #define PORT_TP                 0x00
00068 #define PORT_AUI                0x01
00069 #define PORT_MII                0x02
00070 #define PORT_FIBRE              0x03
00071 #define PORT_BNC                0x04
00072 
00073 /* Which tranceiver to use. */
00074 #define XCVR_INTERNAL           0x00
00075 #define XCVR_EXTERNAL           0x01
00076 #define XCVR_DUMMY1             0x02
00077 #define XCVR_DUMMY2             0x03
00078 #define XCVR_DUMMY3             0x04
00079 
00080 /* Enable or disable autonegotiation.  If this is set to enable,
00081  * the forced link modes above are completely ignored.
00082  */
00083 #define AUTONEG_DISABLE         0x00
00084 #define AUTONEG_ENABLE          0x01
00085 
00086 /* Wake-On-Lan options. */
00087 #define WAKE_PHY                (1 << 0)
00088 #define WAKE_UCAST              (1 << 1)
00089 #define WAKE_MCAST              (1 << 2)
00090 #define WAKE_BCAST              (1 << 3)
00091 #define WAKE_ARP                (1 << 4)
00092 #define WAKE_MAGIC              (1 << 5)
00093 #define WAKE_MAGICSECURE        (1 << 6) /* only meaningful if WAKE_MAGIC */
00094 
00095 /* The following are all involved in forcing a particular link
00096  *  * mode for the device for setting things.  When getting the
00097  *   * devices settings, these indicate the current mode and whether
00098  *    * it was foced up into this mode or autonegotiated.
00099  *     */
00100 
00101 /* The forced speed, 10Mb, 100Mb, gigabit. */
00102 #define SPEED_10                10
00103 #define SPEED_100               100
00104 #define SPEED_1000              1000
00105 #define SPEED_2500              2500
00106 #define SPEED_INVALID           0 /* XXX was 3 */
00107 
00108 
00109 /* Duplex, half or full. */
00110 #define DUPLEX_HALF             0x00
00111 #define DUPLEX_FULL             0x01
00112 #define DUPLEX_INVALID          0x02
00113 
00114 /* Which connector port. */
00115 #define PORT_TP                 0x00
00116 #define PORT_AUI                0x01
00117 #define PORT_MII                0x02
00118 #define PORT_FIBRE              0x03
00119 #define PORT_BNC                0x04
00120 
00121 /* Which tranceiver to use. */
00122 #define XCVR_INTERNAL           0x00
00123 #define XCVR_EXTERNAL           0x01
00124 #define XCVR_DUMMY1             0x02
00125 #define XCVR_DUMMY2             0x03
00126 #define XCVR_DUMMY3             0x04
00127 
00128 /* Enable or disable autonegotiation.  If this is set to enable,
00129  *  * the forced link modes above are completely ignored.
00130  *   */
00131 #define AUTONEG_DISABLE         0x00
00132 #define AUTONEG_ENABLE          0x01
00133 
00134 /* Wake-On-Lan options. */
00135 #define WAKE_PHY                (1 << 0)
00136 #define WAKE_UCAST              (1 << 1)
00137 #define WAKE_MCAST              (1 << 2)
00138 #define WAKE_BCAST              (1 << 3)
00139 #define WAKE_ARP                (1 << 4)
00140 #define WAKE_MAGIC              (1 << 5)
00141 #define WAKE_MAGICSECURE        (1 << 6) /* only meaningful if WAKE_MAGIC */
00142 
00143 /* Hardware data structures and register definitions automatically
00144  * generated from RTL code. Do not modify.
00145  */
00146 
00147 /*
00148  *  tx_bd definition
00149  */
00150 struct tx_bd {
00151         u32 tx_bd_haddr_hi;
00152         u32 tx_bd_haddr_lo;                                   
00153         u32 tx_bd_mss_nbytes;                                     
00154         u32 tx_bd_vlan_tag_flags;                                      
00155                 #define TX_BD_FLAGS_CONN_FAULT          (1<<0)
00156                 #define TX_BD_FLAGS_TCP_UDP_CKSUM       (1<<1)
00157                 #define TX_BD_FLAGS_IP_CKSUM            (1<<2)
00158                 #define TX_BD_FLAGS_VLAN_TAG            (1<<3)
00159                 #define TX_BD_FLAGS_COAL_NOW            (1<<4)
00160                 #define TX_BD_FLAGS_DONT_GEN_CRC        (1<<5)
00161                 #define TX_BD_FLAGS_END                 (1<<6)
00162                 #define TX_BD_FLAGS_START               (1<<7)
00163                 #define TX_BD_FLAGS_SW_OPTION_WORD      (0x1f<<8)
00164                 #define TX_BD_FLAGS_SW_FLAGS            (1<<13)
00165                 #define TX_BD_FLAGS_SW_SNAP             (1<<14)
00166                 #define TX_BD_FLAGS_SW_LSO              (1<<15)
00167 
00168 };
00169 
00170 
00171 /*
00172  *  rx_bd definition
00173  */
00174 struct rx_bd {
00175         u32 rx_bd_haddr_hi;
00176         u32 rx_bd_haddr_lo;
00177         u32 rx_bd_len;
00178         u32 rx_bd_flags;
00179                 #define RX_BD_FLAGS_NOPUSH              (1<<0)
00180                 #define RX_BD_FLAGS_DUMMY               (1<<1)
00181                 #define RX_BD_FLAGS_END                 (1<<2)
00182                 #define RX_BD_FLAGS_START               (1<<3)
00183 
00184 };
00185 
00186 
00187 /*
00188  *  status_block definition
00189  */
00190 struct status_block {
00191         u32 status_attn_bits;
00192                 #define STATUS_ATTN_BITS_LINK_STATE             (1L<<0)
00193                 #define STATUS_ATTN_BITS_TX_SCHEDULER_ABORT     (1L<<1)
00194                 #define STATUS_ATTN_BITS_TX_BD_READ_ABORT       (1L<<2)
00195                 #define STATUS_ATTN_BITS_TX_BD_CACHE_ABORT      (1L<<3)
00196                 #define STATUS_ATTN_BITS_TX_PROCESSOR_ABORT     (1L<<4)
00197                 #define STATUS_ATTN_BITS_TX_DMA_ABORT           (1L<<5)
00198                 #define STATUS_ATTN_BITS_TX_PATCHUP_ABORT       (1L<<6)
00199                 #define STATUS_ATTN_BITS_TX_ASSEMBLER_ABORT     (1L<<7)
00200                 #define STATUS_ATTN_BITS_RX_PARSER_MAC_ABORT    (1L<<8)
00201                 #define STATUS_ATTN_BITS_RX_PARSER_CATCHUP_ABORT        (1L<<9)
00202                 #define STATUS_ATTN_BITS_RX_MBUF_ABORT          (1L<<10)
00203                 #define STATUS_ATTN_BITS_RX_LOOKUP_ABORT        (1L<<11)
00204                 #define STATUS_ATTN_BITS_RX_PROCESSOR_ABORT     (1L<<12)
00205                 #define STATUS_ATTN_BITS_RX_V2P_ABORT           (1L<<13)
00206                 #define STATUS_ATTN_BITS_RX_BD_CACHE_ABORT      (1L<<14)
00207                 #define STATUS_ATTN_BITS_RX_DMA_ABORT           (1L<<15)
00208                 #define STATUS_ATTN_BITS_COMPLETION_ABORT       (1L<<16)
00209                 #define STATUS_ATTN_BITS_HOST_COALESCE_ABORT    (1L<<17)
00210                 #define STATUS_ATTN_BITS_MAILBOX_QUEUE_ABORT    (1L<<18)
00211                 #define STATUS_ATTN_BITS_CONTEXT_ABORT          (1L<<19)
00212                 #define STATUS_ATTN_BITS_CMD_SCHEDULER_ABORT    (1L<<20)
00213                 #define STATUS_ATTN_BITS_CMD_PROCESSOR_ABORT    (1L<<21)
00214                 #define STATUS_ATTN_BITS_MGMT_PROCESSOR_ABORT   (1L<<22)
00215                 #define STATUS_ATTN_BITS_MAC_ABORT              (1L<<23)
00216                 #define STATUS_ATTN_BITS_TIMER_ABORT            (1L<<24)
00217                 #define STATUS_ATTN_BITS_DMAE_ABORT             (1L<<25)
00218                 #define STATUS_ATTN_BITS_FLSH_ABORT             (1L<<26)
00219                 #define STATUS_ATTN_BITS_GRC_ABORT              (1L<<27)
00220                 #define STATUS_ATTN_BITS_PARITY_ERROR           (1L<<31)
00221 
00222         u32 status_attn_bits_ack;
00223 #if __BYTE_ORDER == __BIG_ENDIAN
00224         u16 status_tx_quick_consumer_index0;
00225         u16 status_tx_quick_consumer_index1;
00226         u16 status_tx_quick_consumer_index2;
00227         u16 status_tx_quick_consumer_index3;
00228         u16 status_rx_quick_consumer_index0;
00229         u16 status_rx_quick_consumer_index1;
00230         u16 status_rx_quick_consumer_index2;
00231         u16 status_rx_quick_consumer_index3;
00232         u16 status_rx_quick_consumer_index4;
00233         u16 status_rx_quick_consumer_index5;
00234         u16 status_rx_quick_consumer_index6;
00235         u16 status_rx_quick_consumer_index7;
00236         u16 status_rx_quick_consumer_index8;
00237         u16 status_rx_quick_consumer_index9;
00238         u16 status_rx_quick_consumer_index10;
00239         u16 status_rx_quick_consumer_index11;
00240         u16 status_rx_quick_consumer_index12;
00241         u16 status_rx_quick_consumer_index13;
00242         u16 status_rx_quick_consumer_index14;
00243         u16 status_rx_quick_consumer_index15;
00244         u16 status_completion_producer_index;
00245         u16 status_cmd_consumer_index;
00246         u16 status_idx;
00247         u16 status_unused;
00248 #elif __BYTE_ORDER == __LITTLE_ENDIAN
00249         u16 status_tx_quick_consumer_index1;
00250         u16 status_tx_quick_consumer_index0;
00251         u16 status_tx_quick_consumer_index3;
00252         u16 status_tx_quick_consumer_index2;
00253         u16 status_rx_quick_consumer_index1;
00254         u16 status_rx_quick_consumer_index0;
00255         u16 status_rx_quick_consumer_index3;
00256         u16 status_rx_quick_consumer_index2;
00257         u16 status_rx_quick_consumer_index5;
00258         u16 status_rx_quick_consumer_index4;
00259         u16 status_rx_quick_consumer_index7;
00260         u16 status_rx_quick_consumer_index6;
00261         u16 status_rx_quick_consumer_index9;
00262         u16 status_rx_quick_consumer_index8;
00263         u16 status_rx_quick_consumer_index11;
00264         u16 status_rx_quick_consumer_index10;
00265         u16 status_rx_quick_consumer_index13;
00266         u16 status_rx_quick_consumer_index12;
00267         u16 status_rx_quick_consumer_index15;
00268         u16 status_rx_quick_consumer_index14;
00269         u16 status_cmd_consumer_index;
00270         u16 status_completion_producer_index;
00271         u16 status_unused;
00272         u16 status_idx;
00273 #endif
00274 };
00275 
00276 
00277 /*
00278  *  statistics_block definition
00279  */
00280 struct statistics_block {
00281         u32 stat_IfHCInOctets_hi;
00282         u32 stat_IfHCInOctets_lo;
00283         u32 stat_IfHCInBadOctets_hi;
00284         u32 stat_IfHCInBadOctets_lo;
00285         u32 stat_IfHCOutOctets_hi;
00286         u32 stat_IfHCOutOctets_lo;
00287         u32 stat_IfHCOutBadOctets_hi;
00288         u32 stat_IfHCOutBadOctets_lo;
00289         u32 stat_IfHCInUcastPkts_hi;
00290         u32 stat_IfHCInUcastPkts_lo;
00291         u32 stat_IfHCInMulticastPkts_hi;
00292         u32 stat_IfHCInMulticastPkts_lo;
00293         u32 stat_IfHCInBroadcastPkts_hi;
00294         u32 stat_IfHCInBroadcastPkts_lo;
00295         u32 stat_IfHCOutUcastPkts_hi;
00296         u32 stat_IfHCOutUcastPkts_lo;
00297         u32 stat_IfHCOutMulticastPkts_hi;
00298         u32 stat_IfHCOutMulticastPkts_lo;
00299         u32 stat_IfHCOutBroadcastPkts_hi;
00300         u32 stat_IfHCOutBroadcastPkts_lo;
00301         u32 stat_emac_tx_stat_dot3statsinternalmactransmiterrors;
00302         u32 stat_Dot3StatsCarrierSenseErrors;
00303         u32 stat_Dot3StatsFCSErrors;
00304         u32 stat_Dot3StatsAlignmentErrors;
00305         u32 stat_Dot3StatsSingleCollisionFrames;
00306         u32 stat_Dot3StatsMultipleCollisionFrames;
00307         u32 stat_Dot3StatsDeferredTransmissions;
00308         u32 stat_Dot3StatsExcessiveCollisions;
00309         u32 stat_Dot3StatsLateCollisions;
00310         u32 stat_EtherStatsCollisions;
00311         u32 stat_EtherStatsFragments;
00312         u32 stat_EtherStatsJabbers;
00313         u32 stat_EtherStatsUndersizePkts;
00314         u32 stat_EtherStatsOverrsizePkts;
00315         u32 stat_EtherStatsPktsRx64Octets;
00316         u32 stat_EtherStatsPktsRx65Octetsto127Octets;
00317         u32 stat_EtherStatsPktsRx128Octetsto255Octets;
00318         u32 stat_EtherStatsPktsRx256Octetsto511Octets;
00319         u32 stat_EtherStatsPktsRx512Octetsto1023Octets;
00320         u32 stat_EtherStatsPktsRx1024Octetsto1522Octets;
00321         u32 stat_EtherStatsPktsRx1523Octetsto9022Octets;
00322         u32 stat_EtherStatsPktsTx64Octets;
00323         u32 stat_EtherStatsPktsTx65Octetsto127Octets;
00324         u32 stat_EtherStatsPktsTx128Octetsto255Octets;
00325         u32 stat_EtherStatsPktsTx256Octetsto511Octets;
00326         u32 stat_EtherStatsPktsTx512Octetsto1023Octets;
00327         u32 stat_EtherStatsPktsTx1024Octetsto1522Octets;
00328         u32 stat_EtherStatsPktsTx1523Octetsto9022Octets;
00329         u32 stat_XonPauseFramesReceived;
00330         u32 stat_XoffPauseFramesReceived;
00331         u32 stat_OutXonSent;
00332         u32 stat_OutXoffSent;
00333         u32 stat_FlowControlDone;
00334         u32 stat_MacControlFramesReceived;
00335         u32 stat_XoffStateEntered;
00336         u32 stat_IfInFramesL2FilterDiscards;
00337         u32 stat_IfInRuleCheckerDiscards;
00338         u32 stat_IfInFTQDiscards;
00339         u32 stat_IfInMBUFDiscards;
00340         u32 stat_IfInRuleCheckerP4Hit;
00341         u32 stat_CatchupInRuleCheckerDiscards;
00342         u32 stat_CatchupInFTQDiscards;
00343         u32 stat_CatchupInMBUFDiscards;
00344         u32 stat_CatchupInRuleCheckerP4Hit;
00345         u32 stat_GenStat00;
00346         u32 stat_GenStat01;
00347         u32 stat_GenStat02;
00348         u32 stat_GenStat03;
00349         u32 stat_GenStat04;
00350         u32 stat_GenStat05;
00351         u32 stat_GenStat06;
00352         u32 stat_GenStat07;
00353         u32 stat_GenStat08;
00354         u32 stat_GenStat09;
00355         u32 stat_GenStat10;
00356         u32 stat_GenStat11;
00357         u32 stat_GenStat12;
00358         u32 stat_GenStat13;
00359         u32 stat_GenStat14;
00360         u32 stat_GenStat15;
00361 };
00362 
00363 
00364 /*
00365  *  l2_fhdr definition
00366  */
00367 struct l2_fhdr {
00368         u32 l2_fhdr_status;
00369                 #define L2_FHDR_STATUS_RULE_CLASS       (0x7<<0)
00370                 #define L2_FHDR_STATUS_RULE_P2          (1<<3)
00371                 #define L2_FHDR_STATUS_RULE_P3          (1<<4)
00372                 #define L2_FHDR_STATUS_RULE_P4          (1<<5)
00373                 #define L2_FHDR_STATUS_L2_VLAN_TAG      (1<<6)
00374                 #define L2_FHDR_STATUS_L2_LLC_SNAP      (1<<7)
00375                 #define L2_FHDR_STATUS_RSS_HASH         (1<<8)
00376                 #define L2_FHDR_STATUS_IP_DATAGRAM      (1<<13)
00377                 #define L2_FHDR_STATUS_TCP_SEGMENT      (1<<14)
00378                 #define L2_FHDR_STATUS_UDP_DATAGRAM     (1<<15)
00379 
00380                 #define L2_FHDR_ERRORS_BAD_CRC          (1<<17)
00381                 #define L2_FHDR_ERRORS_PHY_DECODE       (1<<18)
00382                 #define L2_FHDR_ERRORS_ALIGNMENT        (1<<19)
00383                 #define L2_FHDR_ERRORS_TOO_SHORT        (1<<20)
00384                 #define L2_FHDR_ERRORS_GIANT_FRAME      (1<<21)
00385                 #define L2_FHDR_ERRORS_TCP_XSUM         (1<<28)
00386                 #define L2_FHDR_ERRORS_UDP_XSUM         (1<<31)
00387 
00388         u32 l2_fhdr_hash;
00389 #if __BYTE_ORDER == __BIG_ENDIAN
00390         u16 l2_fhdr_pkt_len;
00391         u16 l2_fhdr_vlan_tag;
00392         u16 l2_fhdr_ip_xsum;
00393         u16 l2_fhdr_tcp_udp_xsum;
00394 #elif __BYTE_ORDER == __LITTLE_ENDIAN
00395         u16 l2_fhdr_vlan_tag;
00396         u16 l2_fhdr_pkt_len;
00397         u16 l2_fhdr_tcp_udp_xsum;
00398         u16 l2_fhdr_ip_xsum;
00399 #endif
00400 };
00401 
00402 
00403 /*
00404  *  l2_context definition
00405  */
00406 #define BNX2_L2CTX_TYPE                                 0x00000000
00407 #define BNX2_L2CTX_TYPE_SIZE_L2                          ((0xc0/0x20)<<16)
00408 #define BNX2_L2CTX_TYPE_TYPE                             (0xf<<28)
00409 #define BNX2_L2CTX_TYPE_TYPE_EMPTY                       (0<<28)
00410 #define BNX2_L2CTX_TYPE_TYPE_L2                          (1<<28)
00411 
00412 #define BNX2_L2CTX_TX_HOST_BIDX                         0x00000088
00413 #define BNX2_L2CTX_EST_NBD                              0x00000088
00414 #define BNX2_L2CTX_CMD_TYPE                             0x00000088
00415 #define BNX2_L2CTX_CMD_TYPE_TYPE                         (0xf<<24)
00416 #define BNX2_L2CTX_CMD_TYPE_TYPE_L2                      (0<<24)
00417 #define BNX2_L2CTX_CMD_TYPE_TYPE_TCP                     (1<<24)
00418 
00419 #define BNX2_L2CTX_TX_HOST_BSEQ                         0x00000090
00420 #define BNX2_L2CTX_TSCH_BSEQ                            0x00000094
00421 #define BNX2_L2CTX_TBDR_BSEQ                            0x00000098
00422 #define BNX2_L2CTX_TBDR_BOFF                            0x0000009c
00423 #define BNX2_L2CTX_TBDR_BIDX                            0x0000009c
00424 #define BNX2_L2CTX_TBDR_BHADDR_HI                       0x000000a0
00425 #define BNX2_L2CTX_TBDR_BHADDR_LO                       0x000000a4
00426 #define BNX2_L2CTX_TXP_BOFF                             0x000000a8
00427 #define BNX2_L2CTX_TXP_BIDX                             0x000000a8
00428 #define BNX2_L2CTX_TXP_BSEQ                             0x000000ac
00429 
00430 
00431 /*
00432  *  l2_bd_chain_context definition
00433  */
00434 #define BNX2_L2CTX_BD_PRE_READ                          0x00000000
00435 #define BNX2_L2CTX_CTX_SIZE                             0x00000000
00436 #define BNX2_L2CTX_CTX_TYPE                             0x00000000
00437 #define BNX2_L2CTX_CTX_TYPE_SIZE_L2                      ((0x20/20)<<16)
00438 #define BNX2_L2CTX_CTX_TYPE_CTX_BD_CHN_TYPE              (0xf<<28)
00439 #define BNX2_L2CTX_CTX_TYPE_CTX_BD_CHN_TYPE_UNDEFINED    (0<<28)
00440 #define BNX2_L2CTX_CTX_TYPE_CTX_BD_CHN_TYPE_VALUE        (1<<28)
00441 
00442 #define BNX2_L2CTX_HOST_BDIDX                           0x00000004
00443 #define BNX2_L2CTX_HOST_BSEQ                            0x00000008
00444 #define BNX2_L2CTX_NX_BSEQ                              0x0000000c
00445 #define BNX2_L2CTX_NX_BDHADDR_HI                        0x00000010
00446 #define BNX2_L2CTX_NX_BDHADDR_LO                        0x00000014
00447 #define BNX2_L2CTX_NX_BDIDX                             0x00000018
00448 
00449 
00450 /*
00451  *  pci_config_l definition
00452  *  offset: 0000
00453  */
00454 #define BNX2_PCICFG_MISC_CONFIG                         0x00000068
00455 #define BNX2_PCICFG_MISC_CONFIG_TARGET_BYTE_SWAP         (1L<<2)
00456 #define BNX2_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP      (1L<<3)
00457 #define BNX2_PCICFG_MISC_CONFIG_CLOCK_CTL_ENA            (1L<<5)
00458 #define BNX2_PCICFG_MISC_CONFIG_TARGET_GRC_WORD_SWAP     (1L<<6)
00459 #define BNX2_PCICFG_MISC_CONFIG_REG_WINDOW_ENA           (1L<<7)
00460 #define BNX2_PCICFG_MISC_CONFIG_CORE_RST_REQ             (1L<<8)
00461 #define BNX2_PCICFG_MISC_CONFIG_CORE_RST_BSY             (1L<<9)
00462 #define BNX2_PCICFG_MISC_CONFIG_ASIC_METAL_REV           (0xffL<<16)
00463 #define BNX2_PCICFG_MISC_CONFIG_ASIC_BASE_REV            (0xfL<<24)
00464 #define BNX2_PCICFG_MISC_CONFIG_ASIC_ID                  (0xfL<<28)
00465 
00466 #define BNX2_PCICFG_MISC_STATUS                         0x0000006c
00467 #define BNX2_PCICFG_MISC_STATUS_INTA_VALUE               (1L<<0)
00468 #define BNX2_PCICFG_MISC_STATUS_32BIT_DET                (1L<<1)
00469 #define BNX2_PCICFG_MISC_STATUS_M66EN                    (1L<<2)
00470 #define BNX2_PCICFG_MISC_STATUS_PCIX_DET                 (1L<<3)
00471 #define BNX2_PCICFG_MISC_STATUS_PCIX_SPEED               (0x3L<<4)
00472 #define BNX2_PCICFG_MISC_STATUS_PCIX_SPEED_66            (0L<<4)
00473 #define BNX2_PCICFG_MISC_STATUS_PCIX_SPEED_100           (1L<<4)
00474 #define BNX2_PCICFG_MISC_STATUS_PCIX_SPEED_133           (2L<<4)
00475 #define BNX2_PCICFG_MISC_STATUS_PCIX_SPEED_PCI_MODE      (3L<<4)
00476 
00477 #define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS              0x00000070
00478 #define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET       (0xfL<<0)
00479 #define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_32MHZ         (0L<<0)
00480 #define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_38MHZ         (1L<<0)
00481 #define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_48MHZ         (2L<<0)
00482 #define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_55MHZ         (3L<<0)
00483 #define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_66MHZ         (4L<<0)
00484 #define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_80MHZ         (5L<<0)
00485 #define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_95MHZ         (6L<<0)
00486 #define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_133MHZ        (7L<<0)
00487 #define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_LOW   (0xfL<<0)
00488 #define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_DISABLE      (1L<<6)
00489 #define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_ALT  (1L<<7)
00490 #define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_ALT_SRC      (0x7L<<8)
00491 #define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_ALT_SRC_UNDEF        (0L<<8)
00492 #define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_ALT_SRC_12   (1L<<8)
00493 #define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_ALT_SRC_6    (2L<<8)
00494 #define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_ALT_SRC_62   (4L<<8)
00495 #define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PLAY_DEAD     (1L<<11)
00496 #define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED    (0xfL<<12)
00497 #define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_100        (0L<<12)
00498 #define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_80         (1L<<12)
00499 #define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_50         (2L<<12)
00500 #define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_40         (4L<<12)
00501 #define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_25         (8L<<12)
00502 #define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_PLL_STOP     (1L<<16)
00503 #define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_PLL_STOP  (1L<<17)
00504 #define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_RESERVED_18   (1L<<18)
00505 #define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_USE_SPD_DET   (1L<<19)
00506 #define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_RESERVED      (0xfffL<<20)
00507 
00508 #define BNX2_PCICFG_REG_WINDOW_ADDRESS                  0x00000078
00509 #define BNX2_PCICFG_REG_WINDOW                          0x00000080
00510 #define BNX2_PCICFG_INT_ACK_CMD                         0x00000084
00511 #define BNX2_PCICFG_INT_ACK_CMD_INDEX                    (0xffffL<<0)
00512 #define BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID              (1L<<16)
00513 #define BNX2_PCICFG_INT_ACK_CMD_USE_INT_HC_PARAM         (1L<<17)
00514 #define BNX2_PCICFG_INT_ACK_CMD_MASK_INT                 (1L<<18)
00515 
00516 #define BNX2_PCICFG_STATUS_BIT_SET_CMD                  0x00000088
00517 #define BNX2_PCICFG_STATUS_BIT_CLEAR_CMD                0x0000008c
00518 #define BNX2_PCICFG_MAILBOX_QUEUE_ADDR                  0x00000090
00519 #define BNX2_PCICFG_MAILBOX_QUEUE_DATA                  0x00000094
00520 
00521 
00522 /*
00523  *  pci_reg definition
00524  *  offset: 0x400
00525  */
00526 #define BNX2_PCI_GRC_WINDOW_ADDR                        0x00000400
00527 #define BNX2_PCI_GRC_WINDOW_ADDR_PCI_GRC_WINDOW_ADDR_VALUE       (0x3ffffL<<8)
00528 
00529 #define BNX2_PCI_CONFIG_1                               0x00000404
00530 #define BNX2_PCI_CONFIG_1_READ_BOUNDARY                  (0x7L<<8)
00531 #define BNX2_PCI_CONFIG_1_READ_BOUNDARY_OFF              (0L<<8)
00532 #define BNX2_PCI_CONFIG_1_READ_BOUNDARY_16               (1L<<8)
00533 #define BNX2_PCI_CONFIG_1_READ_BOUNDARY_32               (2L<<8)
00534 #define BNX2_PCI_CONFIG_1_READ_BOUNDARY_64               (3L<<8)
00535 #define BNX2_PCI_CONFIG_1_READ_BOUNDARY_128              (4L<<8)
00536 #define BNX2_PCI_CONFIG_1_READ_BOUNDARY_256              (5L<<8)
00537 #define BNX2_PCI_CONFIG_1_READ_BOUNDARY_512              (6L<<8)
00538 #define BNX2_PCI_CONFIG_1_READ_BOUNDARY_1024             (7L<<8)
00539 #define BNX2_PCI_CONFIG_1_WRITE_BOUNDARY                 (0x7L<<11)
00540 #define BNX2_PCI_CONFIG_1_WRITE_BOUNDARY_OFF             (0L<<11)
00541 #define BNX2_PCI_CONFIG_1_WRITE_BOUNDARY_16              (1L<<11)
00542 #define BNX2_PCI_CONFIG_1_WRITE_BOUNDARY_32              (2L<<11)
00543 #define BNX2_PCI_CONFIG_1_WRITE_BOUNDARY_64              (3L<<11)
00544 #define BNX2_PCI_CONFIG_1_WRITE_BOUNDARY_128             (4L<<11)
00545 #define BNX2_PCI_CONFIG_1_WRITE_BOUNDARY_256             (5L<<11)
00546 #define BNX2_PCI_CONFIG_1_WRITE_BOUNDARY_512             (6L<<11)
00547 #define BNX2_PCI_CONFIG_1_WRITE_BOUNDARY_1024            (7L<<11)
00548 
00549 #define BNX2_PCI_CONFIG_2                               0x00000408
00550 #define BNX2_PCI_CONFIG_2_BAR1_SIZE                      (0xfL<<0)
00551 #define BNX2_PCI_CONFIG_2_BAR1_SIZE_DISABLED             (0L<<0)
00552 #define BNX2_PCI_CONFIG_2_BAR1_SIZE_64K                  (1L<<0)
00553 #define BNX2_PCI_CONFIG_2_BAR1_SIZE_128K                 (2L<<0)
00554 #define BNX2_PCI_CONFIG_2_BAR1_SIZE_256K                 (3L<<0)
00555 #define BNX2_PCI_CONFIG_2_BAR1_SIZE_512K                 (4L<<0)
00556 #define BNX2_PCI_CONFIG_2_BAR1_SIZE_1M                   (5L<<0)
00557 #define BNX2_PCI_CONFIG_2_BAR1_SIZE_2M                   (6L<<0)
00558 #define BNX2_PCI_CONFIG_2_BAR1_SIZE_4M                   (7L<<0)
00559 #define BNX2_PCI_CONFIG_2_BAR1_SIZE_8M                   (8L<<0)
00560 #define BNX2_PCI_CONFIG_2_BAR1_SIZE_16M                  (9L<<0)
00561 #define BNX2_PCI_CONFIG_2_BAR1_SIZE_32M                  (10L<<0)
00562 #define BNX2_PCI_CONFIG_2_BAR1_SIZE_64M                  (11L<<0)
00563 #define BNX2_PCI_CONFIG_2_BAR1_SIZE_128M                 (12L<<0)
00564 #define BNX2_PCI_CONFIG_2_BAR1_SIZE_256M                 (13L<<0)
00565 #define BNX2_PCI_CONFIG_2_BAR1_SIZE_512M                 (14L<<0)
00566 #define BNX2_PCI_CONFIG_2_BAR1_SIZE_1G                   (15L<<0)
00567 #define BNX2_PCI_CONFIG_2_BAR1_64ENA                     (1L<<4)
00568 #define BNX2_PCI_CONFIG_2_EXP_ROM_RETRY                  (1L<<5)
00569 #define BNX2_PCI_CONFIG_2_CFG_CYCLE_RETRY                (1L<<6)
00570 #define BNX2_PCI_CONFIG_2_FIRST_CFG_DONE                 (1L<<7)
00571 #define BNX2_PCI_CONFIG_2_EXP_ROM_SIZE                   (0xffL<<8)
00572 #define BNX2_PCI_CONFIG_2_EXP_ROM_SIZE_DISABLED          (0L<<8)
00573 #define BNX2_PCI_CONFIG_2_EXP_ROM_SIZE_1K                (1L<<8)
00574 #define BNX2_PCI_CONFIG_2_EXP_ROM_SIZE_2K                (2L<<8)
00575 #define BNX2_PCI_CONFIG_2_EXP_ROM_SIZE_4K                (3L<<8)
00576 #define BNX2_PCI_CONFIG_2_EXP_ROM_SIZE_8K                (4L<<8)
00577 #define BNX2_PCI_CONFIG_2_EXP_ROM_SIZE_16K               (5L<<8)
00578 #define BNX2_PCI_CONFIG_2_EXP_ROM_SIZE_32K               (6L<<8)
00579 #define BNX2_PCI_CONFIG_2_EXP_ROM_SIZE_64K               (7L<<8)
00580 #define BNX2_PCI_CONFIG_2_EXP_ROM_SIZE_128K              (8L<<8)
00581 #define BNX2_PCI_CONFIG_2_EXP_ROM_SIZE_256K              (9L<<8)
00582 #define BNX2_PCI_CONFIG_2_EXP_ROM_SIZE_512K              (10L<<8)
00583 #define BNX2_PCI_CONFIG_2_EXP_ROM_SIZE_1M                (11L<<8)
00584 #define BNX2_PCI_CONFIG_2_EXP_ROM_SIZE_2M                (12L<<8)
00585 #define BNX2_PCI_CONFIG_2_EXP_ROM_SIZE_4M                (13L<<8)
00586 #define BNX2_PCI_CONFIG_2_EXP_ROM_SIZE_8M                (14L<<8)
00587 #define BNX2_PCI_CONFIG_2_EXP_ROM_SIZE_16M               (15L<<8)
00588 #define BNX2_PCI_CONFIG_2_MAX_SPLIT_LIMIT                (0x1fL<<16)
00589 #define BNX2_PCI_CONFIG_2_MAX_READ_LIMIT                 (0x3L<<21)
00590 #define BNX2_PCI_CONFIG_2_MAX_READ_LIMIT_512             (0L<<21)
00591 #define BNX2_PCI_CONFIG_2_MAX_READ_LIMIT_1K              (1L<<21)
00592 #define BNX2_PCI_CONFIG_2_MAX_READ_LIMIT_2K              (2L<<21)
00593 #define BNX2_PCI_CONFIG_2_MAX_READ_LIMIT_4K              (3L<<21)
00594 #define BNX2_PCI_CONFIG_2_FORCE_32_BIT_MSTR              (1L<<23)
00595 #define BNX2_PCI_CONFIG_2_FORCE_32_BIT_TGT               (1L<<24)
00596 #define BNX2_PCI_CONFIG_2_KEEP_REQ_ASSERT                (1L<<25)
00597 
00598 #define BNX2_PCI_CONFIG_3                               0x0000040c
00599 #define BNX2_PCI_CONFIG_3_STICKY_BYTE                    (0xffL<<0)
00600 #define BNX2_PCI_CONFIG_3_FORCE_PME                      (1L<<24)
00601 #define BNX2_PCI_CONFIG_3_PME_STATUS                     (1L<<25)
00602 #define BNX2_PCI_CONFIG_3_PME_ENABLE                     (1L<<26)
00603 #define BNX2_PCI_CONFIG_3_PM_STATE                       (0x3L<<27)
00604 #define BNX2_PCI_CONFIG_3_VAUX_PRESET                    (1L<<30)
00605 #define BNX2_PCI_CONFIG_3_PCI_POWER                      (1L<<31)
00606 
00607 #define BNX2_PCI_PM_DATA_A                              0x00000410
00608 #define BNX2_PCI_PM_DATA_A_PM_DATA_0_PRG                 (0xffL<<0)
00609 #define BNX2_PCI_PM_DATA_A_PM_DATA_1_PRG                 (0xffL<<8)
00610 #define BNX2_PCI_PM_DATA_A_PM_DATA_2_PRG                 (0xffL<<16)
00611 #define BNX2_PCI_PM_DATA_A_PM_DATA_3_PRG                 (0xffL<<24)
00612 
00613 #define BNX2_PCI_PM_DATA_B                              0x00000414
00614 #define BNX2_PCI_PM_DATA_B_PM_DATA_4_PRG                 (0xffL<<0)
00615 #define BNX2_PCI_PM_DATA_B_PM_DATA_5_PRG                 (0xffL<<8)
00616 #define BNX2_PCI_PM_DATA_B_PM_DATA_6_PRG                 (0xffL<<16)
00617 #define BNX2_PCI_PM_DATA_B_PM_DATA_7_PRG                 (0xffL<<24)
00618 
00619 #define BNX2_PCI_SWAP_DIAG0                             0x00000418
00620 #define BNX2_PCI_SWAP_DIAG1                             0x0000041c
00621 #define BNX2_PCI_EXP_ROM_ADDR                           0x00000420
00622 #define BNX2_PCI_EXP_ROM_ADDR_ADDRESS                    (0x3fffffL<<2)
00623 #define BNX2_PCI_EXP_ROM_ADDR_REQ                        (1L<<31)
00624 
00625 #define BNX2_PCI_EXP_ROM_DATA                           0x00000424
00626 #define BNX2_PCI_VPD_INTF                               0x00000428
00627 #define BNX2_PCI_VPD_INTF_INTF_REQ                       (1L<<0)
00628 
00629 #define BNX2_PCI_VPD_ADDR_FLAG                          0x0000042c
00630 #define BNX2_PCI_VPD_ADDR_FLAG_ADDRESS                   (0x1fff<<2)
00631 #define BNX2_PCI_VPD_ADDR_FLAG_WR                        (1<<15)
00632 
00633 #define BNX2_PCI_VPD_DATA                               0x00000430
00634 #define BNX2_PCI_ID_VAL1                                0x00000434
00635 #define BNX2_PCI_ID_VAL1_DEVICE_ID                       (0xffffL<<0)
00636 #define BNX2_PCI_ID_VAL1_VENDOR_ID                       (0xffffL<<16)
00637 
00638 #define BNX2_PCI_ID_VAL2                                0x00000438
00639 #define BNX2_PCI_ID_VAL2_SUBSYSTEM_VENDOR_ID             (0xffffL<<0)
00640 #define BNX2_PCI_ID_VAL2_SUBSYSTEM_ID                    (0xffffL<<16)
00641 
00642 #define BNX2_PCI_ID_VAL3                                0x0000043c
00643 #define BNX2_PCI_ID_VAL3_CLASS_CODE                      (0xffffffL<<0)
00644 #define BNX2_PCI_ID_VAL3_REVISION_ID                     (0xffL<<24)
00645 
00646 #define BNX2_PCI_ID_VAL4                                0x00000440
00647 #define BNX2_PCI_ID_VAL4_CAP_ENA                         (0xfL<<0)
00648 #define BNX2_PCI_ID_VAL4_CAP_ENA_0                       (0L<<0)
00649 #define BNX2_PCI_ID_VAL4_CAP_ENA_1                       (1L<<0)
00650 #define BNX2_PCI_ID_VAL4_CAP_ENA_2                       (2L<<0)
00651 #define BNX2_PCI_ID_VAL4_CAP_ENA_3                       (3L<<0)
00652 #define BNX2_PCI_ID_VAL4_CAP_ENA_4                       (4L<<0)
00653 #define BNX2_PCI_ID_VAL4_CAP_ENA_5                       (5L<<0)
00654 #define BNX2_PCI_ID_VAL4_CAP_ENA_6                       (6L<<0)
00655 #define BNX2_PCI_ID_VAL4_CAP_ENA_7                       (7L<<0)
00656 #define BNX2_PCI_ID_VAL4_CAP_ENA_8                       (8L<<0)
00657 #define BNX2_PCI_ID_VAL4_CAP_ENA_9                       (9L<<0)
00658 #define BNX2_PCI_ID_VAL4_CAP_ENA_10                      (10L<<0)
00659 #define BNX2_PCI_ID_VAL4_CAP_ENA_11                      (11L<<0)
00660 #define BNX2_PCI_ID_VAL4_CAP_ENA_12                      (12L<<0)
00661 #define BNX2_PCI_ID_VAL4_CAP_ENA_13                      (13L<<0)
00662 #define BNX2_PCI_ID_VAL4_CAP_ENA_14                      (14L<<0)
00663 #define BNX2_PCI_ID_VAL4_CAP_ENA_15                      (15L<<0)
00664 #define BNX2_PCI_ID_VAL4_PM_SCALE_PRG                    (0x3L<<6)
00665 #define BNX2_PCI_ID_VAL4_PM_SCALE_PRG_0                  (0L<<6)
00666 #define BNX2_PCI_ID_VAL4_PM_SCALE_PRG_1                  (1L<<6)
00667 #define BNX2_PCI_ID_VAL4_PM_SCALE_PRG_2                  (2L<<6)
00668 #define BNX2_PCI_ID_VAL4_PM_SCALE_PRG_3                  (3L<<6)
00669 #define BNX2_PCI_ID_VAL4_MSI_LIMIT                       (0x7L<<9)
00670 #define BNX2_PCI_ID_VAL4_MSI_ADVERTIZE                   (0x7L<<12)
00671 #define BNX2_PCI_ID_VAL4_MSI_ENABLE                      (1L<<15)
00672 #define BNX2_PCI_ID_VAL4_MAX_64_ADVERTIZE                (1L<<16)
00673 #define BNX2_PCI_ID_VAL4_MAX_133_ADVERTIZE               (1L<<17)
00674 #define BNX2_PCI_ID_VAL4_MAX_MEM_READ_SIZE               (0x3L<<21)
00675 #define BNX2_PCI_ID_VAL4_MAX_SPLIT_SIZE                  (0x7L<<23)
00676 #define BNX2_PCI_ID_VAL4_MAX_CUMULATIVE_SIZE             (0x7L<<26)
00677 
00678 #define BNX2_PCI_ID_VAL5                                0x00000444
00679 #define BNX2_PCI_ID_VAL5_D1_SUPPORT                      (1L<<0)
00680 #define BNX2_PCI_ID_VAL5_D2_SUPPORT                      (1L<<1)
00681 #define BNX2_PCI_ID_VAL5_PME_IN_D0                       (1L<<2)
00682 #define BNX2_PCI_ID_VAL5_PME_IN_D1                       (1L<<3)
00683 #define BNX2_PCI_ID_VAL5_PME_IN_D2                       (1L<<4)
00684 #define BNX2_PCI_ID_VAL5_PME_IN_D3_HOT                   (1L<<5)
00685 
00686 #define BNX2_PCI_PCIX_EXTENDED_STATUS                   0x00000448
00687 #define BNX2_PCI_PCIX_EXTENDED_STATUS_NO_SNOOP           (1L<<8)
00688 #define BNX2_PCI_PCIX_EXTENDED_STATUS_LONG_BURST         (1L<<9)
00689 #define BNX2_PCI_PCIX_EXTENDED_STATUS_SPLIT_COMP_MSG_CLASS       (0xfL<<16)
00690 #define BNX2_PCI_PCIX_EXTENDED_STATUS_SPLIT_COMP_MSG_IDX         (0xffL<<24)
00691 
00692 #define BNX2_PCI_ID_VAL6                                0x0000044c
00693 #define BNX2_PCI_ID_VAL6_MAX_LAT                         (0xffL<<0)
00694 #define BNX2_PCI_ID_VAL6_MIN_GNT                         (0xffL<<8)
00695 #define BNX2_PCI_ID_VAL6_BIST                            (0xffL<<16)
00696 
00697 #define BNX2_PCI_MSI_DATA                               0x00000450
00698 #define BNX2_PCI_MSI_DATA_PCI_MSI_DATA                   (0xffffL<<0)
00699 
00700 #define BNX2_PCI_MSI_ADDR_H                             0x00000454
00701 #define BNX2_PCI_MSI_ADDR_L                             0x00000458
00702 
00703 
00704 /*
00705  *  misc_reg definition
00706  *  offset: 0x800
00707  */
00708 #define BNX2_MISC_COMMAND                               0x00000800
00709 #define BNX2_MISC_COMMAND_ENABLE_ALL                     (1L<<0)
00710 #define BNX2_MISC_COMMAND_DISABLE_ALL                    (1L<<1)
00711 #define BNX2_MISC_COMMAND_CORE_RESET                     (1L<<4)
00712 #define BNX2_MISC_COMMAND_HARD_RESET                     (1L<<5)
00713 #define BNX2_MISC_COMMAND_PAR_ERROR                      (1L<<8)
00714 #define BNX2_MISC_COMMAND_PAR_ERR_RAM                    (0x7fL<<16)
00715 
00716 #define BNX2_MISC_CFG                                   0x00000804
00717 #define BNX2_MISC_CFG_PCI_GRC_TMOUT                      (1L<<0)
00718 #define BNX2_MISC_CFG_NVM_WR_EN                          (0x3L<<1)
00719 #define BNX2_MISC_CFG_NVM_WR_EN_PROTECT                  (0L<<1)
00720 #define BNX2_MISC_CFG_NVM_WR_EN_PCI                      (1L<<1)
00721 #define BNX2_MISC_CFG_NVM_WR_EN_ALLOW                    (2L<<1)
00722 #define BNX2_MISC_CFG_NVM_WR_EN_ALLOW2                   (3L<<1)
00723 #define BNX2_MISC_CFG_BIST_EN                            (1L<<3)
00724 #define BNX2_MISC_CFG_CK25_OUT_ALT_SRC                   (1L<<4)
00725 #define BNX2_MISC_CFG_BYPASS_BSCAN                       (1L<<5)
00726 #define BNX2_MISC_CFG_BYPASS_EJTAG                       (1L<<6)
00727 #define BNX2_MISC_CFG_CLK_CTL_OVERRIDE                   (1L<<7)
00728 #define BNX2_MISC_CFG_LEDMODE                            (0x3L<<8)
00729 #define BNX2_MISC_CFG_LEDMODE_MAC                        (0L<<8)
00730 #define BNX2_MISC_CFG_LEDMODE_GPHY1                      (1L<<8)
00731 #define BNX2_MISC_CFG_LEDMODE_GPHY2                      (2L<<8)
00732 
00733 #define BNX2_MISC_ID                                    0x00000808
00734 #define BNX2_MISC_ID_BOND_ID                             (0xfL<<0)
00735 #define BNX2_MISC_ID_CHIP_METAL                          (0xffL<<4)
00736 #define BNX2_MISC_ID_CHIP_REV                            (0xfL<<12)
00737 #define BNX2_MISC_ID_CHIP_NUM                            (0xffffL<<16)
00738 
00739 #define BNX2_MISC_ENABLE_STATUS_BITS                    0x0000080c
00740 #define BNX2_MISC_ENABLE_STATUS_BITS_TX_SCHEDULER_ENABLE         (1L<<0)
00741 #define BNX2_MISC_ENABLE_STATUS_BITS_TX_BD_READ_ENABLE   (1L<<1)
00742 #define BNX2_MISC_ENABLE_STATUS_BITS_TX_BD_CACHE_ENABLE  (1L<<2)
00743 #define BNX2_MISC_ENABLE_STATUS_BITS_TX_PROCESSOR_ENABLE         (1L<<3)
00744 #define BNX2_MISC_ENABLE_STATUS_BITS_TX_DMA_ENABLE       (1L<<4)
00745 #define BNX2_MISC_ENABLE_STATUS_BITS_TX_PATCHUP_ENABLE   (1L<<5)
00746 #define BNX2_MISC_ENABLE_STATUS_BITS_TX_PAYLOAD_Q_ENABLE         (1L<<6)
00747 #define BNX2_MISC_ENABLE_STATUS_BITS_TX_HEADER_Q_ENABLE  (1L<<7)
00748 #define BNX2_MISC_ENABLE_STATUS_BITS_TX_ASSEMBLER_ENABLE         (1L<<8)
00749 #define BNX2_MISC_ENABLE_STATUS_BITS_EMAC_ENABLE         (1L<<9)
00750 #define BNX2_MISC_ENABLE_STATUS_BITS_RX_PARSER_MAC_ENABLE        (1L<<10)
00751 #define BNX2_MISC_ENABLE_STATUS_BITS_RX_PARSER_CATCHUP_ENABLE    (1L<<11)
00752 #define BNX2_MISC_ENABLE_STATUS_BITS_RX_MBUF_ENABLE      (1L<<12)
00753 #define BNX2_MISC_ENABLE_STATUS_BITS_RX_LOOKUP_ENABLE    (1L<<13)
00754 #define BNX2_MISC_ENABLE_STATUS_BITS_RX_PROCESSOR_ENABLE         (1L<<14)
00755 #define BNX2_MISC_ENABLE_STATUS_BITS_RX_V2P_ENABLE       (1L<<15)
00756 #define BNX2_MISC_ENABLE_STATUS_BITS_RX_BD_CACHE_ENABLE  (1L<<16)
00757 #define BNX2_MISC_ENABLE_STATUS_BITS_RX_DMA_ENABLE       (1L<<17)
00758 #define BNX2_MISC_ENABLE_STATUS_BITS_COMPLETION_ENABLE   (1L<<18)
00759 #define BNX2_MISC_ENABLE_STATUS_BITS_HOST_COALESCE_ENABLE        (1L<<19)
00760 #define BNX2_MISC_ENABLE_STATUS_BITS_MAILBOX_QUEUE_ENABLE        (1L<<20)
00761 #define BNX2_MISC_ENABLE_STATUS_BITS_CONTEXT_ENABLE      (1L<<21)
00762 #define BNX2_MISC_ENABLE_STATUS_BITS_CMD_SCHEDULER_ENABLE        (1L<<22)
00763 #define BNX2_MISC_ENABLE_STATUS_BITS_CMD_PROCESSOR_ENABLE        (1L<<23)
00764 #define BNX2_MISC_ENABLE_STATUS_BITS_MGMT_PROCESSOR_ENABLE       (1L<<24)
00765 #define BNX2_MISC_ENABLE_STATUS_BITS_TIMER_ENABLE        (1L<<25)
00766 #define BNX2_MISC_ENABLE_STATUS_BITS_DMA_ENGINE_ENABLE   (1L<<26)
00767 #define BNX2_MISC_ENABLE_STATUS_BITS_UMP_ENABLE          (1L<<27)
00768 
00769 #define BNX2_MISC_ENABLE_SET_BITS                       0x00000810
00770 #define BNX2_MISC_ENABLE_SET_BITS_TX_SCHEDULER_ENABLE    (1L<<0)
00771 #define BNX2_MISC_ENABLE_SET_BITS_TX_BD_READ_ENABLE      (1L<<1)
00772 #define BNX2_MISC_ENABLE_SET_BITS_TX_BD_CACHE_ENABLE     (1L<<2)
00773 #define BNX2_MISC_ENABLE_SET_BITS_TX_PROCESSOR_ENABLE    (1L<<3)
00774 #define BNX2_MISC_ENABLE_SET_BITS_TX_DMA_ENABLE          (1L<<4)
00775 #define BNX2_MISC_ENABLE_SET_BITS_TX_PATCHUP_ENABLE      (1L<<5)
00776 #define BNX2_MISC_ENABLE_SET_BITS_TX_PAYLOAD_Q_ENABLE    (1L<<6)
00777 #define BNX2_MISC_ENABLE_SET_BITS_TX_HEADER_Q_ENABLE     (1L<<7)
00778 #define BNX2_MISC_ENABLE_SET_BITS_TX_ASSEMBLER_ENABLE    (1L<<8)
00779 #define BNX2_MISC_ENABLE_SET_BITS_EMAC_ENABLE            (1L<<9)
00780 #define BNX2_MISC_ENABLE_SET_BITS_RX_PARSER_MAC_ENABLE   (1L<<10)
00781 #define BNX2_MISC_ENABLE_SET_BITS_RX_PARSER_CATCHUP_ENABLE       (1L<<11)
00782 #define BNX2_MISC_ENABLE_SET_BITS_RX_MBUF_ENABLE         (1L<<12)
00783 #define BNX2_MISC_ENABLE_SET_BITS_RX_LOOKUP_ENABLE       (1L<<13)
00784 #define BNX2_MISC_ENABLE_SET_BITS_RX_PROCESSOR_ENABLE    (1L<<14)
00785 #define BNX2_MISC_ENABLE_SET_BITS_RX_V2P_ENABLE          (1L<<15)
00786 #define BNX2_MISC_ENABLE_SET_BITS_RX_BD_CACHE_ENABLE     (1L<<16)
00787 #define BNX2_MISC_ENABLE_SET_BITS_RX_DMA_ENABLE          (1L<<17)
00788 #define BNX2_MISC_ENABLE_SET_BITS_COMPLETION_ENABLE      (1L<<18)
00789 #define BNX2_MISC_ENABLE_SET_BITS_HOST_COALESCE_ENABLE   (1L<<19)
00790 #define BNX2_MISC_ENABLE_SET_BITS_MAILBOX_QUEUE_ENABLE   (1L<<20)
00791 #define BNX2_MISC_ENABLE_SET_BITS_CONTEXT_ENABLE         (1L<<21)
00792 #define BNX2_MISC_ENABLE_SET_BITS_CMD_SCHEDULER_ENABLE   (1L<<22)
00793 #define BNX2_MISC_ENABLE_SET_BITS_CMD_PROCESSOR_ENABLE   (1L<<23)
00794 #define BNX2_MISC_ENABLE_SET_BITS_MGMT_PROCESSOR_ENABLE  (1L<<24)
00795 #define BNX2_MISC_ENABLE_SET_BITS_TIMER_ENABLE           (1L<<25)
00796 #define BNX2_MISC_ENABLE_SET_BITS_DMA_ENGINE_ENABLE      (1L<<26)
00797 #define BNX2_MISC_ENABLE_SET_BITS_UMP_ENABLE             (1L<<27)
00798 
00799 #define BNX2_MISC_ENABLE_CLR_BITS                       0x00000814
00800 #define BNX2_MISC_ENABLE_CLR_BITS_TX_SCHEDULER_ENABLE    (1L<<0)
00801 #define BNX2_MISC_ENABLE_CLR_BITS_TX_BD_READ_ENABLE      (1L<<1)
00802 #define BNX2_MISC_ENABLE_CLR_BITS_TX_BD_CACHE_ENABLE     (1L<<2)
00803 #define BNX2_MISC_ENABLE_CLR_BITS_TX_PROCESSOR_ENABLE    (1L<<3)
00804 #define BNX2_MISC_ENABLE_CLR_BITS_TX_DMA_ENABLE          (1L<<4)
00805 #define BNX2_MISC_ENABLE_CLR_BITS_TX_PATCHUP_ENABLE      (1L<<5)
00806 #define BNX2_MISC_ENABLE_CLR_BITS_TX_PAYLOAD_Q_ENABLE    (1L<<6)
00807 #define BNX2_MISC_ENABLE_CLR_BITS_TX_HEADER_Q_ENABLE     (1L<<7)
00808 #define BNX2_MISC_ENABLE_CLR_BITS_TX_ASSEMBLER_ENABLE    (1L<<8)
00809 #define BNX2_MISC_ENABLE_CLR_BITS_EMAC_ENABLE            (1L<<9)
00810 #define BNX2_MISC_ENABLE_CLR_BITS_RX_PARSER_MAC_ENABLE   (1L<<10)
00811 #define BNX2_MISC_ENABLE_CLR_BITS_RX_PARSER_CATCHUP_ENABLE       (1L<<11)
00812 #define BNX2_MISC_ENABLE_CLR_BITS_RX_MBUF_ENABLE         (1L<<12)
00813 #define BNX2_MISC_ENABLE_CLR_BITS_RX_LOOKUP_ENABLE       (1L<<13)
00814 #define BNX2_MISC_ENABLE_CLR_BITS_RX_PROCESSOR_ENABLE    (1L<<14)
00815 #define BNX2_MISC_ENABLE_CLR_BITS_RX_V2P_ENABLE          (1L<<15)
00816 #define BNX2_MISC_ENABLE_CLR_BITS_RX_BD_CACHE_ENABLE     (1L<<16)
00817 #define BNX2_MISC_ENABLE_CLR_BITS_RX_DMA_ENABLE          (1L<<17)
00818 #define BNX2_MISC_ENABLE_CLR_BITS_COMPLETION_ENABLE      (1L<<18)
00819 #define BNX2_MISC_ENABLE_CLR_BITS_HOST_COALESCE_ENABLE   (1L<<19)
00820 #define BNX2_MISC_ENABLE_CLR_BITS_MAILBOX_QUEUE_ENABLE   (1L<<20)
00821 #define BNX2_MISC_ENABLE_CLR_BITS_CONTEXT_ENABLE         (1L<<21)
00822 #define BNX2_MISC_ENABLE_CLR_BITS_CMD_SCHEDULER_ENABLE   (1L<<22)
00823 #define BNX2_MISC_ENABLE_CLR_BITS_CMD_PROCESSOR_ENABLE   (1L<<23)
00824 #define BNX2_MISC_ENABLE_CLR_BITS_MGMT_PROCESSOR_ENABLE  (1L<<24)
00825 #define BNX2_MISC_ENABLE_CLR_BITS_TIMER_ENABLE           (1L<<25)
00826 #define BNX2_MISC_ENABLE_CLR_BITS_DMA_ENGINE_ENABLE      (1L<<26)
00827 #define BNX2_MISC_ENABLE_CLR_BITS_UMP_ENABLE             (1L<<27)
00828 
00829 #define BNX2_MISC_CLOCK_CONTROL_BITS                    0x00000818
00830 #define BNX2_MISC_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET     (0xfL<<0)
00831 #define BNX2_MISC_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_32MHZ       (0L<<0)
00832 #define BNX2_MISC_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_38MHZ       (1L<<0)
00833 #define BNX2_MISC_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_48MHZ       (2L<<0)
00834 #define BNX2_MISC_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_55MHZ       (3L<<0)
00835 #define BNX2_MISC_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_66MHZ       (4L<<0)
00836 #define BNX2_MISC_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_80MHZ       (5L<<0)
00837 #define BNX2_MISC_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_95MHZ       (6L<<0)
00838 #define BNX2_MISC_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_133MHZ      (7L<<0)
00839 #define BNX2_MISC_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_LOW         (0xfL<<0)
00840 #define BNX2_MISC_CLOCK_CONTROL_BITS_CORE_CLK_DISABLE    (1L<<6)
00841 #define BNX2_MISC_CLOCK_CONTROL_BITS_CORE_CLK_ALT        (1L<<7)
00842 #define BNX2_MISC_CLOCK_CONTROL_BITS_CORE_CLK_ALT_SRC    (0x7L<<8)
00843 #define BNX2_MISC_CLOCK_CONTROL_BITS_CORE_CLK_ALT_SRC_UNDEF      (0L<<8)
00844 #define BNX2_MISC_CLOCK_CONTROL_BITS_CORE_CLK_ALT_SRC_12         (1L<<8)
00845 #define BNX2_MISC_CLOCK_CONTROL_BITS_CORE_CLK_ALT_SRC_6  (2L<<8)
00846 #define BNX2_MISC_CLOCK_CONTROL_BITS_CORE_CLK_ALT_SRC_62         (4L<<8)
00847 #define BNX2_MISC_CLOCK_CONTROL_BITS_PLAY_DEAD           (1L<<11)
00848 #define BNX2_MISC_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED  (0xfL<<12)
00849 #define BNX2_MISC_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_100      (0L<<12)
00850 #define BNX2_MISC_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_80       (1L<<12)
00851 #define BNX2_MISC_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_50       (2L<<12)
00852 #define BNX2_MISC_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_40       (4L<<12)
00853 #define BNX2_MISC_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_25       (8L<<12)
00854 #define BNX2_MISC_CLOCK_CONTROL_BITS_CORE_CLK_PLL_STOP   (1L<<16)
00855 #define BNX2_MISC_CLOCK_CONTROL_BITS_PCI_PLL_STOP        (1L<<17)
00856 #define BNX2_MISC_CLOCK_CONTROL_BITS_RESERVED_18         (1L<<18)
00857 #define BNX2_MISC_CLOCK_CONTROL_BITS_USE_SPD_DET         (1L<<19)
00858 #define BNX2_MISC_CLOCK_CONTROL_BITS_RESERVED            (0xfffL<<20)
00859 
00860 #define BNX2_MISC_GPIO                                  0x0000081c
00861 #define BNX2_MISC_GPIO_VALUE                             (0xffL<<0)
00862 #define BNX2_MISC_GPIO_SET                               (0xffL<<8)
00863 #define BNX2_MISC_GPIO_CLR                               (0xffL<<16)
00864 #define BNX2_MISC_GPIO_FLOAT                             (0xffL<<24)
00865 
00866 #define BNX2_MISC_GPIO_INT                              0x00000820
00867 #define BNX2_MISC_GPIO_INT_INT_STATE                     (0xfL<<0)
00868 #define BNX2_MISC_GPIO_INT_OLD_VALUE                     (0xfL<<8)
00869 #define BNX2_MISC_GPIO_INT_OLD_SET                       (0xfL<<16)
00870 #define BNX2_MISC_GPIO_INT_OLD_CLR                       (0xfL<<24)
00871 
00872 #define BNX2_MISC_CONFIG_LFSR                           0x00000824
00873 #define BNX2_MISC_CONFIG_LFSR_DIV                        (0xffffL<<0)
00874 
00875 #define BNX2_MISC_LFSR_MASK_BITS                        0x00000828
00876 #define BNX2_MISC_LFSR_MASK_BITS_TX_SCHEDULER_ENABLE     (1L<<0)
00877 #define BNX2_MISC_LFSR_MASK_BITS_TX_BD_READ_ENABLE       (1L<<1)
00878 #define BNX2_MISC_LFSR_MASK_BITS_TX_BD_CACHE_ENABLE      (1L<<2)
00879 #define BNX2_MISC_LFSR_MASK_BITS_TX_PROCESSOR_ENABLE     (1L<<3)
00880 #define BNX2_MISC_LFSR_MASK_BITS_TX_DMA_ENABLE           (1L<<4)
00881 #define BNX2_MISC_LFSR_MASK_BITS_TX_PATCHUP_ENABLE       (1L<<5)
00882 #define BNX2_MISC_LFSR_MASK_BITS_TX_PAYLOAD_Q_ENABLE     (1L<<6)
00883 #define BNX2_MISC_LFSR_MASK_BITS_TX_HEADER_Q_ENABLE      (1L<<7)
00884 #define BNX2_MISC_LFSR_MASK_BITS_TX_ASSEMBLER_ENABLE     (1L<<8)
00885 #define BNX2_MISC_LFSR_MASK_BITS_EMAC_ENABLE             (1L<<9)
00886 #define BNX2_MISC_LFSR_MASK_BITS_RX_PARSER_MAC_ENABLE    (1L<<10)
00887 #define BNX2_MISC_LFSR_MASK_BITS_RX_PARSER_CATCHUP_ENABLE        (1L<<11)
00888 #define BNX2_MISC_LFSR_MASK_BITS_RX_MBUF_ENABLE          (1L<<12)
00889 #define BNX2_MISC_LFSR_MASK_BITS_RX_LOOKUP_ENABLE        (1L<<13)
00890 #define BNX2_MISC_LFSR_MASK_BITS_RX_PROCESSOR_ENABLE     (1L<<14)
00891 #define BNX2_MISC_LFSR_MASK_BITS_RX_V2P_ENABLE           (1L<<15)
00892 #define BNX2_MISC_LFSR_MASK_BITS_RX_BD_CACHE_ENABLE      (1L<<16)
00893 #define BNX2_MISC_LFSR_MASK_BITS_RX_DMA_ENABLE           (1L<<17)
00894 #define BNX2_MISC_LFSR_MASK_BITS_COMPLETION_ENABLE       (1L<<18)
00895 #define BNX2_MISC_LFSR_MASK_BITS_HOST_COALESCE_ENABLE    (1L<<19)
00896 #define BNX2_MISC_LFSR_MASK_BITS_MAILBOX_QUEUE_ENABLE    (1L<<20)
00897 #define BNX2_MISC_LFSR_MASK_BITS_CONTEXT_ENABLE          (1L<<21)
00898 #define BNX2_MISC_LFSR_MASK_BITS_CMD_SCHEDULER_ENABLE    (1L<<22)
00899 #define BNX2_MISC_LFSR_MASK_BITS_CMD_PROCESSOR_ENABLE    (1L<<23)
00900 #define BNX2_MISC_LFSR_MASK_BITS_MGMT_PROCESSOR_ENABLE   (1L<<24)
00901 #define BNX2_MISC_LFSR_MASK_BITS_TIMER_ENABLE            (1L<<25)
00902 #define BNX2_MISC_LFSR_MASK_BITS_DMA_ENGINE_ENABLE       (1L<<26)
00903 #define BNX2_MISC_LFSR_MASK_BITS_UMP_ENABLE              (1L<<27)
00904 
00905 #define BNX2_MISC_ARB_REQ0                              0x0000082c
00906 #define BNX2_MISC_ARB_REQ1                              0x00000830
00907 #define BNX2_MISC_ARB_REQ2                              0x00000834
00908 #define BNX2_MISC_ARB_REQ3                              0x00000838
00909 #define BNX2_MISC_ARB_REQ4                              0x0000083c
00910 #define BNX2_MISC_ARB_FREE0                             0x00000840
00911 #define BNX2_MISC_ARB_FREE1                             0x00000844
00912 #define BNX2_MISC_ARB_FREE2                             0x00000848
00913 #define BNX2_MISC_ARB_FREE3                             0x0000084c
00914 #define BNX2_MISC_ARB_FREE4                             0x00000850
00915 #define BNX2_MISC_ARB_REQ_STATUS0                       0x00000854
00916 #define BNX2_MISC_ARB_REQ_STATUS1                       0x00000858
00917 #define BNX2_MISC_ARB_REQ_STATUS2                       0x0000085c
00918 #define BNX2_MISC_ARB_REQ_STATUS3                       0x00000860
00919 #define BNX2_MISC_ARB_REQ_STATUS4                       0x00000864
00920 #define BNX2_MISC_ARB_GNT0                              0x00000868
00921 #define BNX2_MISC_ARB_GNT0_0                             (0x7L<<0)
00922 #define BNX2_MISC_ARB_GNT0_1                             (0x7L<<4)
00923 #define BNX2_MISC_ARB_GNT0_2                             (0x7L<<8)
00924 #define BNX2_MISC_ARB_GNT0_3                             (0x7L<<12)
00925 #define BNX2_MISC_ARB_GNT0_4                             (0x7L<<16)
00926 #define BNX2_MISC_ARB_GNT0_5                             (0x7L<<20)
00927 #define BNX2_MISC_ARB_GNT0_6                             (0x7L<<24)
00928 #define BNX2_MISC_ARB_GNT0_7                             (0x7L<<28)
00929 
00930 #define BNX2_MISC_ARB_GNT1                              0x0000086c
00931 #define BNX2_MISC_ARB_GNT1_8                             (0x7L<<0)
00932 #define BNX2_MISC_ARB_GNT1_9                             (0x7L<<4)
00933 #define BNX2_MISC_ARB_GNT1_10                            (0x7L<<8)
00934 #define BNX2_MISC_ARB_GNT1_11                            (0x7L<<12)
00935 #define BNX2_MISC_ARB_GNT1_12                            (0x7L<<16)
00936 #define BNX2_MISC_ARB_GNT1_13                            (0x7L<<20)
00937 #define BNX2_MISC_ARB_GNT1_14                            (0x7L<<24)
00938 #define BNX2_MISC_ARB_GNT1_15                            (0x7L<<28)
00939 
00940 #define BNX2_MISC_ARB_GNT2                              0x00000870
00941 #define BNX2_MISC_ARB_GNT2_16                            (0x7L<<0)
00942 #define BNX2_MISC_ARB_GNT2_17                            (0x7L<<4)
00943 #define BNX2_MISC_ARB_GNT2_18                            (0x7L<<8)
00944 #define BNX2_MISC_ARB_GNT2_19                            (0x7L<<12)
00945 #define BNX2_MISC_ARB_GNT2_20                            (0x7L<<16)
00946 #define BNX2_MISC_ARB_GNT2_21                            (0x7L<<20)
00947 #define BNX2_MISC_ARB_GNT2_22                            (0x7L<<24)
00948 #define BNX2_MISC_ARB_GNT2_23                            (0x7L<<28)
00949 
00950 #define BNX2_MISC_ARB_GNT3                              0x00000874
00951 #define BNX2_MISC_ARB_GNT3_24                            (0x7L<<0)
00952 #define BNX2_MISC_ARB_GNT3_25                            (0x7L<<4)
00953 #define BNX2_MISC_ARB_GNT3_26                            (0x7L<<8)
00954 #define BNX2_MISC_ARB_GNT3_27                            (0x7L<<12)
00955 #define BNX2_MISC_ARB_GNT3_28                            (0x7L<<16)
00956 #define BNX2_MISC_ARB_GNT3_29                            (0x7L<<20)
00957 #define BNX2_MISC_ARB_GNT3_30                            (0x7L<<24)
00958 #define BNX2_MISC_ARB_GNT3_31                            (0x7L<<28)
00959 
00960 #define BNX2_MISC_PRBS_CONTROL                          0x00000878
00961 #define BNX2_MISC_PRBS_CONTROL_EN                        (1L<<0)
00962 #define BNX2_MISC_PRBS_CONTROL_RSTB                      (1L<<1)
00963 #define BNX2_MISC_PRBS_CONTROL_INV                       (1L<<2)
00964 #define BNX2_MISC_PRBS_CONTROL_ERR_CLR                   (1L<<3)
00965 #define BNX2_MISC_PRBS_CONTROL_ORDER                     (0x3L<<4)
00966 #define BNX2_MISC_PRBS_CONTROL_ORDER_7TH                 (0L<<4)
00967 #define BNX2_MISC_PRBS_CONTROL_ORDER_15TH                (1L<<4)
00968 #define BNX2_MISC_PRBS_CONTROL_ORDER_23RD                (2L<<4)
00969 #define BNX2_MISC_PRBS_CONTROL_ORDER_31ST                (3L<<4)
00970 
00971 #define BNX2_MISC_PRBS_STATUS                           0x0000087c
00972 #define BNX2_MISC_PRBS_STATUS_LOCK                       (1L<<0)
00973 #define BNX2_MISC_PRBS_STATUS_STKY                       (1L<<1)
00974 #define BNX2_MISC_PRBS_STATUS_ERRORS                     (0x3fffL<<2)
00975 #define BNX2_MISC_PRBS_STATUS_STATE                      (0xfL<<16)
00976 
00977 #define BNX2_MISC_SM_ASF_CONTROL                        0x00000880
00978 #define BNX2_MISC_SM_ASF_CONTROL_ASF_RST                 (1L<<0)
00979 #define BNX2_MISC_SM_ASF_CONTROL_TSC_EN                  (1L<<1)
00980 #define BNX2_MISC_SM_ASF_CONTROL_WG_TO                   (1L<<2)
00981 #define BNX2_MISC_SM_ASF_CONTROL_HB_TO                   (1L<<3)
00982 #define BNX2_MISC_SM_ASF_CONTROL_PA_TO                   (1L<<4)
00983 #define BNX2_MISC_SM_ASF_CONTROL_PL_TO                   (1L<<5)
00984 #define BNX2_MISC_SM_ASF_CONTROL_RT_TO                   (1L<<6)
00985 #define BNX2_MISC_SM_ASF_CONTROL_SMB_EVENT               (1L<<7)
00986 #define BNX2_MISC_SM_ASF_CONTROL_RES                     (0xfL<<8)
00987 #define BNX2_MISC_SM_ASF_CONTROL_SMB_EN                  (1L<<12)
00988 #define BNX2_MISC_SM_ASF_CONTROL_SMB_BB_EN               (1L<<13)
00989 #define BNX2_MISC_SM_ASF_CONTROL_SMB_NO_ADDR_FILT        (1L<<14)
00990 #define BNX2_MISC_SM_ASF_CONTROL_SMB_AUTOREAD            (1L<<15)
00991 #define BNX2_MISC_SM_ASF_CONTROL_NIC_SMB_ADDR1           (0x3fL<<16)
00992 #define BNX2_MISC_SM_ASF_CONTROL_NIC_SMB_ADDR2           (0x3fL<<24)
00993 #define BNX2_MISC_SM_ASF_CONTROL_EN_NIC_SMB_ADDR_0       (1L<<30)
00994 #define BNX2_MISC_SM_ASF_CONTROL_SMB_EARLY_ATTN          (1L<<31)
00995 
00996 #define BNX2_MISC_SMB_IN                                0x00000884
00997 #define BNX2_MISC_SMB_IN_DAT_IN                          (0xffL<<0)
00998 #define BNX2_MISC_SMB_IN_RDY                             (1L<<8)
00999 #define BNX2_MISC_SMB_IN_DONE                            (1L<<9)
01000 #define BNX2_MISC_SMB_IN_FIRSTBYTE                       (1L<<10)
01001 #define BNX2_MISC_SMB_IN_STATUS                          (0x7L<<11)
01002 #define BNX2_MISC_SMB_IN_STATUS_OK                       (0x0L<<11)
01003 #define BNX2_MISC_SMB_IN_STATUS_PEC                      (0x1L<<11)
01004 #define BNX2_MISC_SMB_IN_STATUS_OFLOW                    (0x2L<<11)
01005 #define BNX2_MISC_SMB_IN_STATUS_STOP                     (0x3L<<11)
01006 #define BNX2_MISC_SMB_IN_STATUS_TIMEOUT                  (0x4L<<11)
01007 
01008 #define BNX2_MISC_SMB_OUT                               0x00000888
01009 #define BNX2_MISC_SMB_OUT_DAT_OUT                        (0xffL<<0)
01010 #define BNX2_MISC_SMB_OUT_RDY                            (1L<<8)
01011 #define BNX2_MISC_SMB_OUT_START                          (1L<<9)
01012 #define BNX2_MISC_SMB_OUT_LAST                           (1L<<10)
01013 #define BNX2_MISC_SMB_OUT_ACC_TYPE                       (1L<<11)
01014 #define BNX2_MISC_SMB_OUT_ENB_PEC                        (1L<<12)
01015 #define BNX2_MISC_SMB_OUT_GET_RX_LEN                     (1L<<13)
01016 #define BNX2_MISC_SMB_OUT_SMB_READ_LEN                   (0x3fL<<14)
01017 #define BNX2_MISC_SMB_OUT_SMB_OUT_STATUS                 (0xfL<<20)
01018 #define BNX2_MISC_SMB_OUT_SMB_OUT_STATUS_OK              (0L<<20)
01019 #define BNX2_MISC_SMB_OUT_SMB_OUT_STATUS_FIRST_NACK      (1L<<20)
01020 #define BNX2_MISC_SMB_OUT_SMB_OUT_STATUS_SUB_NACK        (9L<<20)
01021 #define BNX2_MISC_SMB_OUT_SMB_OUT_STATUS_UFLOW           (2L<<20)
01022 #define BNX2_MISC_SMB_OUT_SMB_OUT_STATUS_STOP            (3L<<20)
01023 #define BNX2_MISC_SMB_OUT_SMB_OUT_STATUS_TIMEOUT         (4L<<20)
01024 #define BNX2_MISC_SMB_OUT_SMB_OUT_STATUS_FIRST_LOST      (5L<<20)
01025 #define BNX2_MISC_SMB_OUT_SMB_OUT_STATUS_SUB_LOST        (0xdL<<20)
01026 #define BNX2_MISC_SMB_OUT_SMB_OUT_STATUS_BADACK          (0x6L<<20)
01027 #define BNX2_MISC_SMB_OUT_SMB_OUT_SLAVEMODE              (1L<<24)
01028 #define BNX2_MISC_SMB_OUT_SMB_OUT_DAT_EN                 (1L<<25)
01029 #define BNX2_MISC_SMB_OUT_SMB_OUT_DAT_IN                 (1L<<26)
01030 #define BNX2_MISC_SMB_OUT_SMB_OUT_CLK_EN                 (1L<<27)
01031 #define BNX2_MISC_SMB_OUT_SMB_OUT_CLK_IN                 (1L<<28)
01032 
01033 #define BNX2_MISC_SMB_WATCHDOG                          0x0000088c
01034 #define BNX2_MISC_SMB_WATCHDOG_WATCHDOG                  (0xffffL<<0)
01035 
01036 #define BNX2_MISC_SMB_HEARTBEAT                         0x00000890
01037 #define BNX2_MISC_SMB_HEARTBEAT_HEARTBEAT                (0xffffL<<0)
01038 
01039 #define BNX2_MISC_SMB_POLL_ASF                          0x00000894
01040 #define BNX2_MISC_SMB_POLL_ASF_POLL_ASF                  (0xffffL<<0)
01041 
01042 #define BNX2_MISC_SMB_POLL_LEGACY                       0x00000898
01043 #define BNX2_MISC_SMB_POLL_LEGACY_POLL_LEGACY            (0xffffL<<0)
01044 
01045 #define BNX2_MISC_SMB_RETRAN                            0x0000089c
01046 #define BNX2_MISC_SMB_RETRAN_RETRAN                      (0xffL<<0)
01047 
01048 #define BNX2_MISC_SMB_TIMESTAMP                         0x000008a0
01049 #define BNX2_MISC_SMB_TIMESTAMP_TIMESTAMP                (0xffffffffL<<0)
01050 
01051 #define BNX2_MISC_PERR_ENA0                             0x000008a4
01052 #define BNX2_MISC_PERR_ENA0_COM_MISC_CTXC                (1L<<0)
01053 #define BNX2_MISC_PERR_ENA0_COM_MISC_REGF                (1L<<1)
01054 #define BNX2_MISC_PERR_ENA0_COM_MISC_SCPAD               (1L<<2)
01055 #define BNX2_MISC_PERR_ENA0_CP_MISC_CTXC                 (1L<<3)
01056 #define BNX2_MISC_PERR_ENA0_CP_MISC_REGF                 (1L<<4)
01057 #define BNX2_MISC_PERR_ENA0_CP_MISC_SCPAD                (1L<<5)
01058 #define BNX2_MISC_PERR_ENA0_CS_MISC_TMEM                 (1L<<6)
01059 #define BNX2_MISC_PERR_ENA0_CTX_MISC_ACCM0               (1L<<7)
01060 #define BNX2_MISC_PERR_ENA0_CTX_MISC_ACCM1               (1L<<8)
01061 #define BNX2_MISC_PERR_ENA0_CTX_MISC_ACCM2               (1L<<9)
01062 #define BNX2_MISC_PERR_ENA0_CTX_MISC_ACCM3               (1L<<10)
01063 #define BNX2_MISC_PERR_ENA0_CTX_MISC_ACCM4               (1L<<11)
01064 #define BNX2_MISC_PERR_ENA0_CTX_MISC_ACCM5               (1L<<12)
01065 #define BNX2_MISC_PERR_ENA0_CTX_MISC_PGTBL               (1L<<13)
01066 #define BNX2_MISC_PERR_ENA0_DMAE_MISC_DR0                (1L<<14)
01067 #define BNX2_MISC_PERR_ENA0_DMAE_MISC_DR1                (1L<<15)
01068 #define BNX2_MISC_PERR_ENA0_DMAE_MISC_DR2                (1L<<16)
01069 #define BNX2_MISC_PERR_ENA0_DMAE_MISC_DR3                (1L<<17)
01070 #define BNX2_MISC_PERR_ENA0_DMAE_MISC_DR4                (1L<<18)
01071 #define BNX2_MISC_PERR_ENA0_DMAE_MISC_DW0                (1L<<19)
01072 #define BNX2_MISC_PERR_ENA0_DMAE_MISC_DW1                (1L<<20)
01073 #define BNX2_MISC_PERR_ENA0_DMAE_MISC_DW2                (1L<<21)
01074 #define BNX2_MISC_PERR_ENA0_HC_MISC_DMA                  (1L<<22)
01075 #define BNX2_MISC_PERR_ENA0_MCP_MISC_REGF                (1L<<23)
01076 #define BNX2_MISC_PERR_ENA0_MCP_MISC_SCPAD               (1L<<24)
01077 #define BNX2_MISC_PERR_ENA0_MQ_MISC_CTX                  (1L<<25)
01078 #define BNX2_MISC_PERR_ENA0_RBDC_MISC                    (1L<<26)
01079 #define BNX2_MISC_PERR_ENA0_RBUF_MISC_MB                 (1L<<27)
01080 #define BNX2_MISC_PERR_ENA0_RBUF_MISC_PTR                (1L<<28)
01081 #define BNX2_MISC_PERR_ENA0_RDE_MISC_RPC                 (1L<<29)
01082 #define BNX2_MISC_PERR_ENA0_RDE_MISC_RPM                 (1L<<30)
01083 #define BNX2_MISC_PERR_ENA0_RV2P_MISC_CB0REGS            (1L<<31)
01084 
01085 #define BNX2_MISC_PERR_ENA1                             0x000008a8
01086 #define BNX2_MISC_PERR_ENA1_RV2P_MISC_CB1REGS            (1L<<0)
01087 #define BNX2_MISC_PERR_ENA1_RV2P_MISC_P1IRAM             (1L<<1)
01088 #define BNX2_MISC_PERR_ENA1_RV2P_MISC_P2IRAM             (1L<<2)
01089 #define BNX2_MISC_PERR_ENA1_RXP_MISC_CTXC                (1L<<3)
01090 #define BNX2_MISC_PERR_ENA1_RXP_MISC_REGF                (1L<<4)
01091 #define BNX2_MISC_PERR_ENA1_RXP_MISC_SCPAD               (1L<<5)
01092 #define BNX2_MISC_PERR_ENA1_RXP_MISC_RBUFC               (1L<<6)
01093 #define BNX2_MISC_PERR_ENA1_TBDC_MISC                    (1L<<7)
01094 #define BNX2_MISC_PERR_ENA1_TDMA_MISC                    (1L<<8)
01095 #define BNX2_MISC_PERR_ENA1_THBUF_MISC_MB0               (1L<<9)
01096 #define BNX2_MISC_PERR_ENA1_THBUF_MISC_MB1               (1L<<10)
01097 #define BNX2_MISC_PERR_ENA1_TPAT_MISC_REGF               (1L<<11)
01098 #define BNX2_MISC_PERR_ENA1_TPAT_MISC_SCPAD              (1L<<12)
01099 #define BNX2_MISC_PERR_ENA1_TPBUF_MISC_MB                (1L<<13)
01100 #define BNX2_MISC_PERR_ENA1_TSCH_MISC_LR                 (1L<<14)
01101 #define BNX2_MISC_PERR_ENA1_TXP_MISC_CTXC                (1L<<15)
01102 #define BNX2_MISC_PERR_ENA1_TXP_MISC_REGF                (1L<<16)
01103 #define BNX2_MISC_PERR_ENA1_TXP_MISC_SCPAD               (1L<<17)
01104 #define BNX2_MISC_PERR_ENA1_UMP_MISC_FIORX               (1L<<18)
01105 #define BNX2_MISC_PERR_ENA1_UMP_MISC_FIOTX               (1L<<19)
01106 #define BNX2_MISC_PERR_ENA1_UMP_MISC_RX                  (1L<<20)
01107 #define BNX2_MISC_PERR_ENA1_UMP_MISC_TX                  (1L<<21)
01108 #define BNX2_MISC_PERR_ENA1_RDMAQ_MISC                   (1L<<22)
01109 #define BNX2_MISC_PERR_ENA1_CSQ_MISC                     (1L<<23)
01110 #define BNX2_MISC_PERR_ENA1_CPQ_MISC                     (1L<<24)
01111 #define BNX2_MISC_PERR_ENA1_MCPQ_MISC                    (1L<<25)
01112 #define BNX2_MISC_PERR_ENA1_RV2PMQ_MISC                  (1L<<26)
01113 #define BNX2_MISC_PERR_ENA1_RV2PPQ_MISC                  (1L<<27)
01114 #define BNX2_MISC_PERR_ENA1_RV2PTQ_MISC                  (1L<<28)
01115 #define BNX2_MISC_PERR_ENA1_RXPQ_MISC                    (1L<<29)
01116 #define BNX2_MISC_PERR_ENA1_RXPCQ_MISC                   (1L<<30)
01117 #define BNX2_MISC_PERR_ENA1_RLUPQ_MISC                   (1L<<31)
01118 
01119 #define BNX2_MISC_PERR_ENA2                             0x000008ac
01120 #define BNX2_MISC_PERR_ENA2_COMQ_MISC                    (1L<<0)
01121 #define BNX2_MISC_PERR_ENA2_COMXQ_MISC                   (1L<<1)
01122 #define BNX2_MISC_PERR_ENA2_COMTQ_MISC                   (1L<<2)
01123 #define BNX2_MISC_PERR_ENA2_TSCHQ_MISC                   (1L<<3)
01124 #define BNX2_MISC_PERR_ENA2_TBDRQ_MISC                   (1L<<4)
01125 #define BNX2_MISC_PERR_ENA2_TXPQ_MISC                    (1L<<5)
01126 #define BNX2_MISC_PERR_ENA2_TDMAQ_MISC                   (1L<<6)
01127 #define BNX2_MISC_PERR_ENA2_TPATQ_MISC                   (1L<<7)
01128 #define BNX2_MISC_PERR_ENA2_TASQ_MISC                    (1L<<8)
01129 
01130 #define BNX2_MISC_DEBUG_VECTOR_SEL                      0x000008b0
01131 #define BNX2_MISC_DEBUG_VECTOR_SEL_0                     (0xfffL<<0)
01132 #define BNX2_MISC_DEBUG_VECTOR_SEL_1                     (0xfffL<<12)
01133 
01134 #define BNX2_MISC_VREG_CONTROL                          0x000008b4
01135 #define BNX2_MISC_VREG_CONTROL_1_2                       (0xfL<<0)
01136 #define BNX2_MISC_VREG_CONTROL_2_5                       (0xfL<<4)
01137 
01138 #define BNX2_MISC_FINAL_CLK_CTL_VAL                     0x000008b8
01139 #define BNX2_MISC_FINAL_CLK_CTL_VAL_MISC_FINAL_CLK_CTL_VAL       (0x3ffffffL<<6)
01140 
01141 #define BNX2_MISC_UNUSED0                               0x000008bc
01142 
01143 
01144 /*
01145  *  nvm_reg definition
01146  *  offset: 0x6400
01147  */
01148 #define BNX2_NVM_COMMAND                                0x00006400
01149 #define BNX2_NVM_COMMAND_RST                             (1L<<0)
01150 #define BNX2_NVM_COMMAND_DONE                            (1L<<3)
01151 #define BNX2_NVM_COMMAND_DOIT                            (1L<<4)
01152 #define BNX2_NVM_COMMAND_WR                              (1L<<5)
01153 #define BNX2_NVM_COMMAND_ERASE                           (1L<<6)
01154 #define BNX2_NVM_COMMAND_FIRST                           (1L<<7)
01155 #define BNX2_NVM_COMMAND_LAST                            (1L<<8)
01156 #define BNX2_NVM_COMMAND_WREN                            (1L<<16)
01157 #define BNX2_NVM_COMMAND_WRDI                            (1L<<17)
01158 #define BNX2_NVM_COMMAND_EWSR                            (1L<<18)
01159 #define BNX2_NVM_COMMAND_WRSR                            (1L<<19)
01160 
01161 #define BNX2_NVM_STATUS                                 0x00006404
01162 #define BNX2_NVM_STATUS_PI_FSM_STATE                     (0xfL<<0)
01163 #define BNX2_NVM_STATUS_EE_FSM_STATE                     (0xfL<<4)
01164 #define BNX2_NVM_STATUS_EQ_FSM_STATE                     (0xfL<<8)
01165 
01166 #define BNX2_NVM_WRITE                                  0x00006408
01167 #define BNX2_NVM_WRITE_NVM_WRITE_VALUE                   (0xffffffffL<<0)
01168 #define BNX2_NVM_WRITE_NVM_WRITE_VALUE_BIT_BANG          (0L<<0)
01169 #define BNX2_NVM_WRITE_NVM_WRITE_VALUE_EECLK             (1L<<0)
01170 #define BNX2_NVM_WRITE_NVM_WRITE_VALUE_EEDATA            (2L<<0)
01171 #define BNX2_NVM_WRITE_NVM_WRITE_VALUE_SCLK              (4L<<0)
01172 #define BNX2_NVM_WRITE_NVM_WRITE_VALUE_CS_B              (8L<<0)
01173 #define BNX2_NVM_WRITE_NVM_WRITE_VALUE_SO                (16L<<0)
01174 #define BNX2_NVM_WRITE_NVM_WRITE_VALUE_SI                (32L<<0)
01175 
01176 #define BNX2_NVM_ADDR                                   0x0000640c
01177 #define BNX2_NVM_ADDR_NVM_ADDR_VALUE                     (0xffffffL<<0)
01178 #define BNX2_NVM_ADDR_NVM_ADDR_VALUE_BIT_BANG            (0L<<0)
01179 #define BNX2_NVM_ADDR_NVM_ADDR_VALUE_EECLK               (1L<<0)
01180 #define BNX2_NVM_ADDR_NVM_ADDR_VALUE_EEDATA              (2L<<0)
01181 #define BNX2_NVM_ADDR_NVM_ADDR_VALUE_SCLK                (4L<<0)
01182 #define BNX2_NVM_ADDR_NVM_ADDR_VALUE_CS_B                (8L<<0)
01183 #define BNX2_NVM_ADDR_NVM_ADDR_VALUE_SO                  (16L<<0)
01184 #define BNX2_NVM_ADDR_NVM_ADDR_VALUE_SI                  (32L<<0)
01185 
01186 #define BNX2_NVM_READ                                   0x00006410
01187 #define BNX2_NVM_READ_NVM_READ_VALUE                     (0xffffffffL<<0)
01188 #define BNX2_NVM_READ_NVM_READ_VALUE_BIT_BANG            (0L<<0)
01189 #define BNX2_NVM_READ_NVM_READ_VALUE_EECLK               (1L<<0)
01190 #define BNX2_NVM_READ_NVM_READ_VALUE_EEDATA              (2L<<0)
01191 #define BNX2_NVM_READ_NVM_READ_VALUE_SCLK                (4L<<0)
01192 #define BNX2_NVM_READ_NVM_READ_VALUE_CS_B                (8L<<0)
01193 #define BNX2_NVM_READ_NVM_READ_VALUE_SO                  (16L<<0)
01194 #define BNX2_NVM_READ_NVM_READ_VALUE_SI                  (32L<<0)
01195 
01196 #define BNX2_NVM_CFG1                                   0x00006414
01197 #define BNX2_NVM_CFG1_FLASH_MODE                         (1L<<0)
01198 #define BNX2_NVM_CFG1_BUFFER_MODE                        (1L<<1)
01199 #define BNX2_NVM_CFG1_PASS_MODE                          (1L<<2)
01200 #define BNX2_NVM_CFG1_BITBANG_MODE                       (1L<<3)
01201 #define BNX2_NVM_CFG1_STATUS_BIT                         (0x7L<<4)
01202 #define BNX2_NVM_CFG1_STATUS_BIT_FLASH_RDY               (0L<<4)
01203 #define BNX2_NVM_CFG1_STATUS_BIT_BUFFER_RDY              (7L<<4)
01204 #define BNX2_NVM_CFG1_SPI_CLK_DIV                        (0xfL<<7)
01205 #define BNX2_NVM_CFG1_SEE_CLK_DIV                        (0x7ffL<<11)
01206 #define BNX2_NVM_CFG1_PROTECT_MODE                       (1L<<24)
01207 #define BNX2_NVM_CFG1_FLASH_SIZE                         (1L<<25)
01208 #define BNX2_NVM_CFG1_COMPAT_BYPASSS                     (1L<<31)
01209 
01210 #define BNX2_NVM_CFG2                                   0x00006418
01211 #define BNX2_NVM_CFG2_ERASE_CMD                          (0xffL<<0)
01212 #define BNX2_NVM_CFG2_DUMMY                              (0xffL<<8)
01213 #define BNX2_NVM_CFG2_STATUS_CMD                         (0xffL<<16)
01214 
01215 #define BNX2_NVM_CFG3                                   0x0000641c
01216 #define BNX2_NVM_CFG3_BUFFER_RD_CMD                      (0xffL<<0)
01217 #define BNX2_NVM_CFG3_WRITE_CMD                          (0xffL<<8)
01218 #define BNX2_NVM_CFG3_BUFFER_WRITE_CMD                   (0xffL<<16)
01219 #define BNX2_NVM_CFG3_READ_CMD                           (0xffL<<24)
01220 
01221 #define BNX2_NVM_SW_ARB                                 0x00006420
01222 #define BNX2_NVM_SW_ARB_ARB_REQ_SET0                     (1L<<0)
01223 #define BNX2_NVM_SW_ARB_ARB_REQ_SET1                     (1L<<1)
01224 #define BNX2_NVM_SW_ARB_ARB_REQ_SET2                     (1L<<2)
01225 #define BNX2_NVM_SW_ARB_ARB_REQ_SET3                     (1L<<3)
01226 #define BNX2_NVM_SW_ARB_ARB_REQ_CLR0                     (1L<<4)
01227 #define BNX2_NVM_SW_ARB_ARB_REQ_CLR1                     (1L<<5)
01228 #define BNX2_NVM_SW_ARB_ARB_REQ_CLR2                     (1L<<6)
01229 #define BNX2_NVM_SW_ARB_ARB_REQ_CLR3                     (1L<<7)
01230 #define BNX2_NVM_SW_ARB_ARB_ARB0                         (1L<<8)
01231 #define BNX2_NVM_SW_ARB_ARB_ARB1                         (1L<<9)
01232 #define BNX2_NVM_SW_ARB_ARB_ARB2                         (1L<<10)
01233 #define BNX2_NVM_SW_ARB_ARB_ARB3                         (1L<<11)
01234 #define BNX2_NVM_SW_ARB_REQ0                             (1L<<12)
01235 #define BNX2_NVM_SW_ARB_REQ1                             (1L<<13)
01236 #define BNX2_NVM_SW_ARB_REQ2                             (1L<<14)
01237 #define BNX2_NVM_SW_ARB_REQ3                             (1L<<15)
01238 
01239 #define BNX2_NVM_ACCESS_ENABLE                          0x00006424
01240 #define BNX2_NVM_ACCESS_ENABLE_EN                        (1L<<0)
01241 #define BNX2_NVM_ACCESS_ENABLE_WR_EN                     (1L<<1)
01242 
01243 #define BNX2_NVM_WRITE1                                 0x00006428
01244 #define BNX2_NVM_WRITE1_WREN_CMD                         (0xffL<<0)
01245 #define BNX2_NVM_WRITE1_WRDI_CMD                         (0xffL<<8)
01246 #define BNX2_NVM_WRITE1_SR_DATA                          (0xffL<<16)
01247 
01248 
01249 
01250 /*
01251  *  dma_reg definition
01252  *  offset: 0xc00
01253  */
01254 #define BNX2_DMA_COMMAND                                0x00000c00
01255 #define BNX2_DMA_COMMAND_ENABLE                          (1L<<0)
01256 
01257 #define BNX2_DMA_STATUS                                 0x00000c04
01258 #define BNX2_DMA_STATUS_PAR_ERROR_STATE                  (1L<<0)
01259 #define BNX2_DMA_STATUS_READ_TRANSFERS_STAT              (1L<<16)
01260 #define BNX2_DMA_STATUS_READ_DELAY_PCI_CLKS_STAT         (1L<<17)
01261 #define BNX2_DMA_STATUS_BIG_READ_TRANSFERS_STAT          (1L<<18)
01262 #define BNX2_DMA_STATUS_BIG_READ_DELAY_PCI_CLKS_STAT     (1L<<19)
01263 #define BNX2_DMA_STATUS_BIG_READ_RETRY_AFTER_DATA_STAT   (1L<<20)
01264 #define BNX2_DMA_STATUS_WRITE_TRANSFERS_STAT             (1L<<21)
01265 #define BNX2_DMA_STATUS_WRITE_DELAY_PCI_CLKS_STAT        (1L<<22)
01266 #define BNX2_DMA_STATUS_BIG_WRITE_TRANSFERS_STAT         (1L<<23)
01267 #define BNX2_DMA_STATUS_BIG_WRITE_DELAY_PCI_CLKS_STAT    (1L<<24)
01268 #define BNX2_DMA_STATUS_BIG_WRITE_RETRY_AFTER_DATA_STAT  (1L<<25)
01269 
01270 #define BNX2_DMA_CONFIG                                 0x00000c08
01271 #define BNX2_DMA_CONFIG_DATA_BYTE_SWAP                   (1L<<0)
01272 #define BNX2_DMA_CONFIG_DATA_WORD_SWAP                   (1L<<1)
01273 #define BNX2_DMA_CONFIG_CNTL_BYTE_SWAP                   (1L<<4)
01274 #define BNX2_DMA_CONFIG_CNTL_WORD_SWAP                   (1L<<5)
01275 #define BNX2_DMA_CONFIG_ONE_DMA                          (1L<<6)
01276 #define BNX2_DMA_CONFIG_CNTL_TWO_DMA                     (1L<<7)
01277 #define BNX2_DMA_CONFIG_CNTL_FPGA_MODE                   (1L<<8)
01278 #define BNX2_DMA_CONFIG_CNTL_PING_PONG_DMA               (1L<<10)
01279 #define BNX2_DMA_CONFIG_CNTL_PCI_COMP_DLY                (1L<<11)
01280 #define BNX2_DMA_CONFIG_NO_RCHANS_IN_USE                 (0xfL<<12)
01281 #define BNX2_DMA_CONFIG_NO_WCHANS_IN_USE                 (0xfL<<16)
01282 #define BNX2_DMA_CONFIG_PCI_CLK_CMP_BITS                 (0x7L<<20)
01283 #define BNX2_DMA_CONFIG_PCI_FAST_CLK_CMP                 (1L<<23)
01284 #define BNX2_DMA_CONFIG_BIG_SIZE                         (0xfL<<24)
01285 #define BNX2_DMA_CONFIG_BIG_SIZE_NONE                    (0x0L<<24)
01286 #define BNX2_DMA_CONFIG_BIG_SIZE_64                      (0x1L<<24)
01287 #define BNX2_DMA_CONFIG_BIG_SIZE_128                     (0x2L<<24)
01288 #define BNX2_DMA_CONFIG_BIG_SIZE_256                     (0x4L<<24)
01289 #define BNX2_DMA_CONFIG_BIG_SIZE_512                     (0x8L<<24)
01290 
01291 #define BNX2_DMA_BLACKOUT                               0x00000c0c
01292 #define BNX2_DMA_BLACKOUT_RD_RETRY_BLACKOUT              (0xffL<<0)
01293 #define BNX2_DMA_BLACKOUT_2ND_RD_RETRY_BLACKOUT          (0xffL<<8)
01294 #define BNX2_DMA_BLACKOUT_WR_RETRY_BLACKOUT              (0xffL<<16)
01295 
01296 #define BNX2_DMA_RCHAN_STAT                             0x00000c30
01297 #define BNX2_DMA_RCHAN_STAT_COMP_CODE_0                  (0x7L<<0)
01298 #define BNX2_DMA_RCHAN_STAT_PAR_ERR_0                    (1L<<3)
01299 #define BNX2_DMA_RCHAN_STAT_COMP_CODE_1                  (0x7L<<4)
01300 #define BNX2_DMA_RCHAN_STAT_PAR_ERR_1                    (1L<<7)
01301 #define BNX2_DMA_RCHAN_STAT_COMP_CODE_2                  (0x7L<<8)
01302 #define BNX2_DMA_RCHAN_STAT_PAR_ERR_2                    (1L<<11)
01303 #define BNX2_DMA_RCHAN_STAT_COMP_CODE_3                  (0x7L<<12)
01304 #define BNX2_DMA_RCHAN_STAT_PAR_ERR_3                    (1L<<15)
01305 #define BNX2_DMA_RCHAN_STAT_COMP_CODE_4                  (0x7L<<16)
01306 #define BNX2_DMA_RCHAN_STAT_PAR_ERR_4                    (1L<<19)
01307 #define BNX2_DMA_RCHAN_STAT_COMP_CODE_5                  (0x7L<<20)
01308 #define BNX2_DMA_RCHAN_STAT_PAR_ERR_5                    (1L<<23)
01309 #define BNX2_DMA_RCHAN_STAT_COMP_CODE_6                  (0x7L<<24)
01310 #define BNX2_DMA_RCHAN_STAT_PAR_ERR_6                    (1L<<27)
01311 #define BNX2_DMA_RCHAN_STAT_COMP_CODE_7                  (0x7L<<28)
01312 #define BNX2_DMA_RCHAN_STAT_PAR_ERR_7                    (1L<<31)
01313 
01314 #define BNX2_DMA_WCHAN_STAT                             0x00000c34
01315 #define BNX2_DMA_WCHAN_STAT_COMP_CODE_0                  (0x7L<<0)
01316 #define BNX2_DMA_WCHAN_STAT_PAR_ERR_0                    (1L<<3)
01317 #define BNX2_DMA_WCHAN_STAT_COMP_CODE_1                  (0x7L<<4)
01318 #define BNX2_DMA_WCHAN_STAT_PAR_ERR_1                    (1L<<7)
01319 #define BNX2_DMA_WCHAN_STAT_COMP_CODE_2                  (0x7L<<8)
01320 #define BNX2_DMA_WCHAN_STAT_PAR_ERR_2                    (1L<<11)
01321 #define BNX2_DMA_WCHAN_STAT_COMP_CODE_3                  (0x7L<<12)
01322 #define BNX2_DMA_WCHAN_STAT_PAR_ERR_3                    (1L<<15)
01323 #define BNX2_DMA_WCHAN_STAT_COMP_CODE_4                  (0x7L<<16)
01324 #define BNX2_DMA_WCHAN_STAT_PAR_ERR_4                    (1L<<19)
01325 #define BNX2_DMA_WCHAN_STAT_COMP_CODE_5                  (0x7L<<20)
01326 #define BNX2_DMA_WCHAN_STAT_PAR_ERR_5                    (1L<<23)
01327 #define BNX2_DMA_WCHAN_STAT_COMP_CODE_6                  (0x7L<<24)
01328 #define BNX2_DMA_WCHAN_STAT_PAR_ERR_6                    (1L<<27)
01329 #define BNX2_DMA_WCHAN_STAT_COMP_CODE_7                  (0x7L<<28)
01330 #define BNX2_DMA_WCHAN_STAT_PAR_ERR_7                    (1L<<31)
01331 
01332 #define BNX2_DMA_RCHAN_ASSIGNMENT                       0x00000c38
01333 #define BNX2_DMA_RCHAN_ASSIGNMENT_0                      (0xfL<<0)
01334 #define BNX2_DMA_RCHAN_ASSIGNMENT_1                      (0xfL<<4)
01335 #define BNX2_DMA_RCHAN_ASSIGNMENT_2                      (0xfL<<8)
01336 #define BNX2_DMA_RCHAN_ASSIGNMENT_3                      (0xfL<<12)
01337 #define BNX2_DMA_RCHAN_ASSIGNMENT_4                      (0xfL<<16)
01338 #define BNX2_DMA_RCHAN_ASSIGNMENT_5                      (0xfL<<20)
01339 #define BNX2_DMA_RCHAN_ASSIGNMENT_6                      (0xfL<<24)
01340 #define BNX2_DMA_RCHAN_ASSIGNMENT_7                      (0xfL<<28)
01341 
01342 #define BNX2_DMA_WCHAN_ASSIGNMENT                       0x00000c3c
01343 #define BNX2_DMA_WCHAN_ASSIGNMENT_0                      (0xfL<<0)
01344 #define BNX2_DMA_WCHAN_ASSIGNMENT_1                      (0xfL<<4)
01345 #define BNX2_DMA_WCHAN_ASSIGNMENT_2                      (0xfL<<8)
01346 #define BNX2_DMA_WCHAN_ASSIGNMENT_3                      (0xfL<<12)
01347 #define BNX2_DMA_WCHAN_ASSIGNMENT_4                      (0xfL<<16)
01348 #define BNX2_DMA_WCHAN_ASSIGNMENT_5                      (0xfL<<20)
01349 #define BNX2_DMA_WCHAN_ASSIGNMENT_6                      (0xfL<<24)
01350 #define BNX2_DMA_WCHAN_ASSIGNMENT_7                      (0xfL<<28)
01351 
01352 #define BNX2_DMA_RCHAN_STAT_00                          0x00000c40
01353 #define BNX2_DMA_RCHAN_STAT_00_RCHAN_STA_HOST_ADDR_LOW   (0xffffffffL<<0)
01354 
01355 #define BNX2_DMA_RCHAN_STAT_01                          0x00000c44
01356 #define BNX2_DMA_RCHAN_STAT_01_RCHAN_STA_HOST_ADDR_HIGH  (0xffffffffL<<0)
01357 
01358 #define BNX2_DMA_RCHAN_STAT_02                          0x00000c48
01359 #define BNX2_DMA_RCHAN_STAT_02_LENGTH                    (0xffffL<<0)
01360 #define BNX2_DMA_RCHAN_STAT_02_WORD_SWAP                 (1L<<16)
01361 #define BNX2_DMA_RCHAN_STAT_02_BYTE_SWAP                 (1L<<17)
01362 #define BNX2_DMA_RCHAN_STAT_02_PRIORITY_LVL              (1L<<18)
01363 
01364 #define BNX2_DMA_RCHAN_STAT_10                          0x00000c4c
01365 #define BNX2_DMA_RCHAN_STAT_11                          0x00000c50
01366 #define BNX2_DMA_RCHAN_STAT_12                          0x00000c54
01367 #define BNX2_DMA_RCHAN_STAT_20                          0x00000c58
01368 #define BNX2_DMA_RCHAN_STAT_21                          0x00000c5c
01369 #define BNX2_DMA_RCHAN_STAT_22                          0x00000c60
01370 #define BNX2_DMA_RCHAN_STAT_30                          0x00000c64
01371 #define BNX2_DMA_RCHAN_STAT_31                          0x00000c68
01372 #define BNX2_DMA_RCHAN_STAT_32                          0x00000c6c
01373 #define BNX2_DMA_RCHAN_STAT_40                          0x00000c70
01374 #define BNX2_DMA_RCHAN_STAT_41                          0x00000c74
01375 #define BNX2_DMA_RCHAN_STAT_42                          0x00000c78
01376 #define BNX2_DMA_RCHAN_STAT_50                          0x00000c7c
01377 #define BNX2_DMA_RCHAN_STAT_51                          0x00000c80
01378 #define BNX2_DMA_RCHAN_STAT_52                          0x00000c84
01379 #define BNX2_DMA_RCHAN_STAT_60                          0x00000c88
01380 #define BNX2_DMA_RCHAN_STAT_61                          0x00000c8c
01381 #define BNX2_DMA_RCHAN_STAT_62                          0x00000c90
01382 #define BNX2_DMA_RCHAN_STAT_70                          0x00000c94
01383 #define BNX2_DMA_RCHAN_STAT_71                          0x00000c98
01384 #define BNX2_DMA_RCHAN_STAT_72                          0x00000c9c
01385 #define BNX2_DMA_WCHAN_STAT_00                          0x00000ca0
01386 #define BNX2_DMA_WCHAN_STAT_00_WCHAN_STA_HOST_ADDR_LOW   (0xffffffffL<<0)
01387 
01388 #define BNX2_DMA_WCHAN_STAT_01                          0x00000ca4
01389 #define BNX2_DMA_WCHAN_STAT_01_WCHAN_STA_HOST_ADDR_HIGH  (0xffffffffL<<0)
01390 
01391 #define BNX2_DMA_WCHAN_STAT_02                          0x00000ca8
01392 #define BNX2_DMA_WCHAN_STAT_02_LENGTH                    (0xffffL<<0)
01393 #define BNX2_DMA_WCHAN_STAT_02_WORD_SWAP                 (1L<<16)
01394 #define BNX2_DMA_WCHAN_STAT_02_BYTE_SWAP                 (1L<<17)
01395 #define BNX2_DMA_WCHAN_STAT_02_PRIORITY_LVL              (1L<<18)
01396 
01397 #define BNX2_DMA_WCHAN_STAT_10                          0x00000cac
01398 #define BNX2_DMA_WCHAN_STAT_11                          0x00000cb0
01399 #define BNX2_DMA_WCHAN_STAT_12                          0x00000cb4
01400 #define BNX2_DMA_WCHAN_STAT_20                          0x00000cb8
01401 #define BNX2_DMA_WCHAN_STAT_21                          0x00000cbc
01402 #define BNX2_DMA_WCHAN_STAT_22                          0x00000cc0
01403 #define BNX2_DMA_WCHAN_STAT_30                          0x00000cc4
01404 #define BNX2_DMA_WCHAN_STAT_31                          0x00000cc8
01405 #define BNX2_DMA_WCHAN_STAT_32                          0x00000ccc
01406 #define BNX2_DMA_WCHAN_STAT_40                          0x00000cd0
01407 #define BNX2_DMA_WCHAN_STAT_41                          0x00000cd4
01408 #define BNX2_DMA_WCHAN_STAT_42                          0x00000cd8
01409 #define BNX2_DMA_WCHAN_STAT_50                          0x00000cdc
01410 #define BNX2_DMA_WCHAN_STAT_51                          0x00000ce0
01411 #define BNX2_DMA_WCHAN_STAT_52                          0x00000ce4
01412 #define BNX2_DMA_WCHAN_STAT_60                          0x00000ce8
01413 #define BNX2_DMA_WCHAN_STAT_61                          0x00000cec
01414 #define BNX2_DMA_WCHAN_STAT_62                          0x00000cf0
01415 #define BNX2_DMA_WCHAN_STAT_70                          0x00000cf4
01416 #define BNX2_DMA_WCHAN_STAT_71                          0x00000cf8
01417 #define BNX2_DMA_WCHAN_STAT_72                          0x00000cfc
01418 #define BNX2_DMA_ARB_STAT_00                            0x00000d00
01419 #define BNX2_DMA_ARB_STAT_00_MASTER                      (0xffffL<<0)
01420 #define BNX2_DMA_ARB_STAT_00_MASTER_ENC                  (0xffL<<16)
01421 #define BNX2_DMA_ARB_STAT_00_CUR_BINMSTR                 (0xffL<<24)
01422 
01423 #define BNX2_DMA_ARB_STAT_01                            0x00000d04
01424 #define BNX2_DMA_ARB_STAT_01_LPR_RPTR                    (0xfL<<0)
01425 #define BNX2_DMA_ARB_STAT_01_LPR_WPTR                    (0xfL<<4)
01426 #define BNX2_DMA_ARB_STAT_01_LPB_RPTR                    (0xfL<<8)
01427 #define BNX2_DMA_ARB_STAT_01_LPB_WPTR                    (0xfL<<12)
01428 #define BNX2_DMA_ARB_STAT_01_HPR_RPTR                    (0xfL<<16)
01429 #define BNX2_DMA_ARB_STAT_01_HPR_WPTR                    (0xfL<<20)
01430 #define BNX2_DMA_ARB_STAT_01_HPB_RPTR                    (0xfL<<24)
01431 #define BNX2_DMA_ARB_STAT_01_HPB_WPTR                    (0xfL<<28)
01432 
01433 #define BNX2_DMA_FUSE_CTRL0_CMD                         0x00000f00
01434 #define BNX2_DMA_FUSE_CTRL0_CMD_PWRUP_DONE               (1L<<0)
01435 #define BNX2_DMA_FUSE_CTRL0_CMD_SHIFT_DONE               (1L<<1)
01436 #define BNX2_DMA_FUSE_CTRL0_CMD_SHIFT                    (1L<<2)
01437 #define BNX2_DMA_FUSE_CTRL0_CMD_LOAD                     (1L<<3)
01438 #define BNX2_DMA_FUSE_CTRL0_CMD_SEL                      (0xfL<<8)
01439 
01440 #define BNX2_DMA_FUSE_CTRL0_DATA                        0x00000f04
01441 #define BNX2_DMA_FUSE_CTRL1_CMD                         0x00000f08
01442 #define BNX2_DMA_FUSE_CTRL1_CMD_PWRUP_DONE               (1L<<0)
01443 #define BNX2_DMA_FUSE_CTRL1_CMD_SHIFT_DONE               (1L<<1)
01444 #define BNX2_DMA_FUSE_CTRL1_CMD_SHIFT                    (1L<<2)
01445 #define BNX2_DMA_FUSE_CTRL1_CMD_LOAD                     (1L<<3)
01446 #define BNX2_DMA_FUSE_CTRL1_CMD_SEL                      (0xfL<<8)
01447 
01448 #define BNX2_DMA_FUSE_CTRL1_DATA                        0x00000f0c
01449 #define BNX2_DMA_FUSE_CTRL2_CMD                         0x00000f10
01450 #define BNX2_DMA_FUSE_CTRL2_CMD_PWRUP_DONE               (1L<<0)
01451 #define BNX2_DMA_FUSE_CTRL2_CMD_SHIFT_DONE               (1L<<1)
01452 #define BNX2_DMA_FUSE_CTRL2_CMD_SHIFT                    (1L<<2)
01453 #define BNX2_DMA_FUSE_CTRL2_CMD_LOAD                     (1L<<3)
01454 #define BNX2_DMA_FUSE_CTRL2_CMD_SEL                      (0xfL<<8)
01455 
01456 #define BNX2_DMA_FUSE_CTRL2_DATA                        0x00000f14
01457 
01458 
01459 /*
01460  *  context_reg definition
01461  *  offset: 0x1000
01462  */
01463 #define BNX2_CTX_COMMAND                                0x00001000
01464 #define BNX2_CTX_COMMAND_ENABLED                         (1L<<0)
01465 
01466 #define BNX2_CTX_STATUS                                 0x00001004
01467 #define BNX2_CTX_STATUS_LOCK_WAIT                        (1L<<0)
01468 #define BNX2_CTX_STATUS_READ_STAT                        (1L<<16)
01469 #define BNX2_CTX_STATUS_WRITE_STAT                       (1L<<17)
01470 #define BNX2_CTX_STATUS_ACC_STALL_STAT                   (1L<<18)
01471 #define BNX2_CTX_STATUS_LOCK_STALL_STAT                  (1L<<19)
01472 
01473 #define BNX2_CTX_VIRT_ADDR                              0x00001008
01474 #define BNX2_CTX_VIRT_ADDR_VIRT_ADDR                     (0x7fffL<<6)
01475 
01476 #define BNX2_CTX_PAGE_TBL                               0x0000100c
01477 #define BNX2_CTX_PAGE_TBL_PAGE_TBL                       (0x3fffL<<6)
01478 
01479 #define BNX2_CTX_DATA_ADR                               0x00001010
01480 #define BNX2_CTX_DATA_ADR_DATA_ADR                       (0x7ffffL<<2)
01481 
01482 #define BNX2_CTX_DATA                                   0x00001014
01483 #define BNX2_CTX_LOCK                                   0x00001018
01484 #define BNX2_CTX_LOCK_TYPE                               (0x7L<<0)
01485 #define BNX2_CTX_LOCK_TYPE_LOCK_TYPE_VOID                (0x0L<<0)
01486 #define BNX2_CTX_LOCK_TYPE_LOCK_TYPE_COMPLETE            (0x7L<<0)
01487 #define BNX2_CTX_LOCK_TYPE_LOCK_TYPE_PROTOCOL            (0x1L<<0)
01488 #define BNX2_CTX_LOCK_TYPE_LOCK_TYPE_TX                  (0x2L<<0)
01489 #define BNX2_CTX_LOCK_TYPE_LOCK_TYPE_TIMER               (0x4L<<0)
01490 #define BNX2_CTX_LOCK_CID_VALUE                          (0x3fffL<<7)
01491 #define BNX2_CTX_LOCK_GRANTED                            (1L<<26)
01492 #define BNX2_CTX_LOCK_MODE                               (0x7L<<27)
01493 #define BNX2_CTX_LOCK_MODE_UNLOCK                        (0x0L<<27)
01494 #define BNX2_CTX_LOCK_MODE_IMMEDIATE                     (0x1L<<27)
01495 #define BNX2_CTX_LOCK_MODE_SURE                          (0x2L<<27)
01496 #define BNX2_CTX_LOCK_STATUS                             (1L<<30)
01497 #define BNX2_CTX_LOCK_REQ                                (1L<<31)
01498 
01499 #define BNX2_CTX_ACCESS_STATUS                          0x00001040
01500 #define BNX2_CTX_ACCESS_STATUS_MASTERENCODED             (0xfL<<0)
01501 #define BNX2_CTX_ACCESS_STATUS_ACCESSMEMORYSM            (0x3L<<10)
01502 #define BNX2_CTX_ACCESS_STATUS_PAGETABLEINITSM           (0x3L<<12)
01503 #define BNX2_CTX_ACCESS_STATUS_ACCESSMEMORYINITSM        (0x3L<<14)
01504 #define BNX2_CTX_ACCESS_STATUS_QUALIFIED_REQUEST         (0x7ffL<<17)
01505 
01506 #define BNX2_CTX_DBG_LOCK_STATUS                        0x00001044
01507 #define BNX2_CTX_DBG_LOCK_STATUS_SM                      (0x3ffL<<0)
01508 #define BNX2_CTX_DBG_LOCK_STATUS_MATCH                   (0x3ffL<<22)
01509 
01510 #define BNX2_CTX_CHNL_LOCK_STATUS_0                     0x00001080
01511 #define BNX2_CTX_CHNL_LOCK_STATUS_0_CID                  (0x3fffL<<0)
01512 #define BNX2_CTX_CHNL_LOCK_STATUS_0_TYPE                 (0x3L<<14)
01513 #define BNX2_CTX_CHNL_LOCK_STATUS_0_MODE                 (1L<<16)
01514 
01515 #define BNX2_CTX_CHNL_LOCK_STATUS_1                     0x00001084
01516 #define BNX2_CTX_CHNL_LOCK_STATUS_2                     0x00001088
01517 #define BNX2_CTX_CHNL_LOCK_STATUS_3                     0x0000108c
01518 #define BNX2_CTX_CHNL_LOCK_STATUS_4                     0x00001090
01519 #define BNX2_CTX_CHNL_LOCK_STATUS_5                     0x00001094
01520 #define BNX2_CTX_CHNL_LOCK_STATUS_6                     0x00001098
01521 #define BNX2_CTX_CHNL_LOCK_STATUS_7                     0x0000109c
01522 #define BNX2_CTX_CHNL_LOCK_STATUS_8                     0x000010a0
01523 
01524 
01525 /*
01526  *  emac_reg definition
01527  *  offset: 0x1400
01528  */
01529 #define BNX2_EMAC_MODE                                  0x00001400
01530 #define BNX2_EMAC_MODE_RESET                             (1L<<0)
01531 #define BNX2_EMAC_MODE_HALF_DUPLEX                       (1L<<1)
01532 #define BNX2_EMAC_MODE_PORT                              (0x3L<<2)
01533 #define BNX2_EMAC_MODE_PORT_NONE                         (0L<<2)
01534 #define BNX2_EMAC_MODE_PORT_MII                          (1L<<2)
01535 #define BNX2_EMAC_MODE_PORT_GMII                         (2L<<2)
01536 #define BNX2_EMAC_MODE_PORT_MII_10                       (3L<<2)
01537 #define BNX2_EMAC_MODE_MAC_LOOP                          (1L<<4)
01538 #define BNX2_EMAC_MODE_25G                               (1L<<5)
01539 #define BNX2_EMAC_MODE_TAGGED_MAC_CTL                    (1L<<7)
01540 #define BNX2_EMAC_MODE_TX_BURST                          (1L<<8)
01541 #define BNX2_EMAC_MODE_MAX_DEFER_DROP_ENA                (1L<<9)
01542 #define BNX2_EMAC_MODE_EXT_LINK_POL                      (1L<<10)
01543 #define BNX2_EMAC_MODE_FORCE_LINK                        (1L<<11)
01544 #define BNX2_EMAC_MODE_MPKT                              (1L<<18)
01545 #define BNX2_EMAC_MODE_MPKT_RCVD                         (1L<<19)
01546 #define BNX2_EMAC_MODE_ACPI_RCVD                         (1L<<20)
01547 
01548 #define BNX2_EMAC_STATUS                                0x00001404
01549 #define BNX2_EMAC_STATUS_LINK                            (1L<<11)
01550 #define BNX2_EMAC_STATUS_LINK_CHANGE                     (1L<<12)
01551 #define BNX2_EMAC_STATUS_MI_COMPLETE                     (1L<<22)
01552 #define BNX2_EMAC_STATUS_MI_INT                          (1L<<23)
01553 #define BNX2_EMAC_STATUS_AP_ERROR                        (1L<<24)
01554 #define BNX2_EMAC_STATUS_PARITY_ERROR_STATE              (1L<<31)
01555 
01556 #define BNX2_EMAC_ATTENTION_ENA                         0x00001408
01557 #define BNX2_EMAC_ATTENTION_ENA_LINK                     (1L<<11)
01558 #define BNX2_EMAC_ATTENTION_ENA_MI_COMPLETE              (1L<<22)
01559 #define BNX2_EMAC_ATTENTION_ENA_MI_INT                   (1L<<23)
01560 #define BNX2_EMAC_ATTENTION_ENA_AP_ERROR                 (1L<<24)
01561 
01562 #define BNX2_EMAC_LED                                   0x0000140c
01563 #define BNX2_EMAC_LED_OVERRIDE                           (1L<<0)
01564 #define BNX2_EMAC_LED_1000MB_OVERRIDE                    (1L<<1)
01565 #define BNX2_EMAC_LED_100MB_OVERRIDE                     (1L<<2)
01566 #define BNX2_EMAC_LED_10MB_OVERRIDE                      (1L<<3)
01567 #define BNX2_EMAC_LED_TRAFFIC_OVERRIDE                   (1L<<4)
01568 #define BNX2_EMAC_LED_BLNK_TRAFFIC                       (1L<<5)
01569 #define BNX2_EMAC_LED_TRAFFIC                            (1L<<6)
01570 #define BNX2_EMAC_LED_1000MB                             (1L<<7)
01571 #define BNX2_EMAC_LED_100MB                              (1L<<8)
01572 #define BNX2_EMAC_LED_10MB                               (1L<<9)
01573 #define BNX2_EMAC_LED_TRAFFIC_STAT                       (1L<<10)
01574 #define BNX2_EMAC_LED_BLNK_RATE                          (0xfffL<<19)
01575 #define BNX2_EMAC_LED_BLNK_RATE_ENA                      (1L<<31)
01576 
01577 #define BNX2_EMAC_MAC_MATCH0                            0x00001410
01578 #define BNX2_EMAC_MAC_MATCH1                            0x00001414
01579 #define BNX2_EMAC_MAC_MATCH2                            0x00001418
01580 #define BNX2_EMAC_MAC_MATCH3                            0x0000141c
01581 #define BNX2_EMAC_MAC_MATCH4                            0x00001420
01582 #define BNX2_EMAC_MAC_MATCH5                            0x00001424
01583 #define BNX2_EMAC_MAC_MATCH6                            0x00001428
01584 #define BNX2_EMAC_MAC_MATCH7                            0x0000142c
01585 #define BNX2_EMAC_MAC_MATCH8                            0x00001430
01586 #define BNX2_EMAC_MAC_MATCH9                            0x00001434
01587 #define BNX2_EMAC_MAC_MATCH10                           0x00001438
01588 #define BNX2_EMAC_MAC_MATCH11                           0x0000143c
01589 #define BNX2_EMAC_MAC_MATCH12                           0x00001440
01590 #define BNX2_EMAC_MAC_MATCH13                           0x00001444
01591 #define BNX2_EMAC_MAC_MATCH14                           0x00001448
01592 #define BNX2_EMAC_MAC_MATCH15                           0x0000144c
01593 #define BNX2_EMAC_MAC_MATCH16                           0x00001450
01594 #define BNX2_EMAC_MAC_MATCH17                           0x00001454
01595 #define BNX2_EMAC_MAC_MATCH18                           0x00001458
01596 #define BNX2_EMAC_MAC_MATCH19                           0x0000145c
01597 #define BNX2_EMAC_MAC_MATCH20                           0x00001460
01598 #define BNX2_EMAC_MAC_MATCH21                           0x00001464
01599 #define BNX2_EMAC_MAC_MATCH22                           0x00001468
01600 #define BNX2_EMAC_MAC_MATCH23                           0x0000146c
01601 #define BNX2_EMAC_MAC_MATCH24                           0x00001470
01602 #define BNX2_EMAC_MAC_MATCH25                           0x00001474
01603 #define BNX2_EMAC_MAC_MATCH26                           0x00001478
01604 #define BNX2_EMAC_MAC_MATCH27                           0x0000147c
01605 #define BNX2_EMAC_MAC_MATCH28                           0x00001480
01606 #define BNX2_EMAC_MAC_MATCH29                           0x00001484
01607 #define BNX2_EMAC_MAC_MATCH30                           0x00001488
01608 #define BNX2_EMAC_MAC_MATCH31                           0x0000148c
01609 #define BNX2_EMAC_BACKOFF_SEED                          0x00001498
01610 #define BNX2_EMAC_BACKOFF_SEED_EMAC_BACKOFF_SEED         (0x3ffL<<0)
01611 
01612 #define BNX2_EMAC_RX_MTU_SIZE                           0x0000149c
01613 #define BNX2_EMAC_RX_MTU_SIZE_MTU_SIZE                   (0xffffL<<0)
01614 #define BNX2_EMAC_RX_MTU_SIZE_JUMBO_ENA                  (1L<<31)
01615 
01616 #define BNX2_EMAC_SERDES_CNTL                           0x000014a4
01617 #define BNX2_EMAC_SERDES_CNTL_RXR                        (0x7L<<0)
01618 #define BNX2_EMAC_SERDES_CNTL_RXG                        (0x3L<<3)
01619 #define BNX2_EMAC_SERDES_CNTL_RXCKSEL                    (1L<<6)
01620 #define BNX2_EMAC_SERDES_CNTL_TXBIAS                     (0x7L<<7)
01621 #define BNX2_EMAC_SERDES_CNTL_BGMAX                      (1L<<10)
01622 #define BNX2_EMAC_SERDES_CNTL_BGMIN                      (1L<<11)
01623 #define BNX2_EMAC_SERDES_CNTL_TXMODE                     (1L<<12)
01624 #define BNX2_EMAC_SERDES_CNTL_TXEDGE                     (1L<<13)
01625 #define BNX2_EMAC_SERDES_CNTL_SERDES_MODE                (1L<<14)
01626 #define BNX2_EMAC_SERDES_CNTL_PLLTEST                    (1L<<15)
01627 #define BNX2_EMAC_SERDES_CNTL_CDET_EN                    (1L<<16)
01628 #define BNX2_EMAC_SERDES_CNTL_TBI_LBK                    (1L<<17)
01629 #define BNX2_EMAC_SERDES_CNTL_REMOTE_LBK                 (1L<<18)
01630 #define BNX2_EMAC_SERDES_CNTL_REV_PHASE                  (1L<<19)
01631 #define BNX2_EMAC_SERDES_CNTL_REGCTL12                   (0x3L<<20)
01632 #define BNX2_EMAC_SERDES_CNTL_REGCTL25                   (0x3L<<22)
01633 
01634 #define BNX2_EMAC_SERDES_STATUS                         0x000014a8
01635 #define BNX2_EMAC_SERDES_STATUS_RX_STAT                  (0xffL<<0)
01636 #define BNX2_EMAC_SERDES_STATUS_COMMA_DET                (1L<<8)
01637 
01638 #define BNX2_EMAC_MDIO_COMM                             0x000014ac
01639 #define BNX2_EMAC_MDIO_COMM_DATA                         (0xffffL<<0)
01640 #define BNX2_EMAC_MDIO_COMM_REG_ADDR                     (0x1fL<<16)
01641 #define BNX2_EMAC_MDIO_COMM_PHY_ADDR                     (0x1fL<<21)
01642 #define BNX2_EMAC_MDIO_COMM_COMMAND                      (0x3L<<26)
01643 #define BNX2_EMAC_MDIO_COMM_COMMAND_UNDEFINED_0          (0L<<26)
01644 #define BNX2_EMAC_MDIO_COMM_COMMAND_WRITE                (1L<<26)
01645 #define BNX2_EMAC_MDIO_COMM_COMMAND_READ                 (2L<<26)
01646 #define BNX2_EMAC_MDIO_COMM_COMMAND_UNDEFINED_3          (3L<<26)
01647 #define BNX2_EMAC_MDIO_COMM_FAIL                         (1L<<28)
01648 #define BNX2_EMAC_MDIO_COMM_START_BUSY                   (1L<<29)
01649 #define BNX2_EMAC_MDIO_COMM_DISEXT                       (1L<<30)
01650 
01651 #define BNX2_EMAC_MDIO_STATUS                           0x000014b0
01652 #define BNX2_EMAC_MDIO_STATUS_LINK                       (1L<<0)
01653 #define BNX2_EMAC_MDIO_STATUS_10MB                       (1L<<1)
01654 
01655 #define BNX2_EMAC_MDIO_MODE                             0x000014b4
01656 #define BNX2_EMAC_MDIO_MODE_SHORT_PREAMBLE               (1L<<1)
01657 #define BNX2_EMAC_MDIO_MODE_AUTO_POLL                    (1L<<4)
01658 #define BNX2_EMAC_MDIO_MODE_BIT_BANG                     (1L<<8)
01659 #define BNX2_EMAC_MDIO_MODE_MDIO                         (1L<<9)
01660 #define BNX2_EMAC_MDIO_MODE_MDIO_OE                      (1L<<10)
01661 #define BNX2_EMAC_MDIO_MODE_MDC                          (1L<<11)
01662 #define BNX2_EMAC_MDIO_MODE_MDINT                        (1L<<12)
01663 #define BNX2_EMAC_MDIO_MODE_CLOCK_CNT                    (0x1fL<<16)
01664 
01665 #define BNX2_EMAC_MDIO_AUTO_STATUS                      0x000014b8
01666 #define BNX2_EMAC_MDIO_AUTO_STATUS_AUTO_ERR              (1L<<0)
01667 
01668 #define BNX2_EMAC_TX_MODE                               0x000014bc
01669 #define BNX2_EMAC_TX_MODE_RESET                          (1L<<0)
01670 #define BNX2_EMAC_TX_MODE_EXT_PAUSE_EN                   (1L<<3)
01671 #define BNX2_EMAC_TX_MODE_FLOW_EN                        (1L<<4)
01672 #define BNX2_EMAC_TX_MODE_BIG_BACKOFF                    (1L<<5)
01673 #define BNX2_EMAC_TX_MODE_LONG_PAUSE                     (1L<<6)
01674 #define BNX2_EMAC_TX_MODE_LINK_AWARE                     (1L<<7)
01675 
01676 #define BNX2_EMAC_TX_STATUS                             0x000014c0
01677 #define BNX2_EMAC_TX_STATUS_XOFFED                       (1L<<0)
01678 #define BNX2_EMAC_TX_STATUS_XOFF_SENT                    (1L<<1)
01679 #define BNX2_EMAC_TX_STATUS_XON_SENT                     (1L<<2)
01680 #define BNX2_EMAC_TX_STATUS_LINK_UP                      (1L<<3)
01681 #define BNX2_EMAC_TX_STATUS_UNDERRUN                     (1L<<4)
01682 
01683 #define BNX2_EMAC_TX_LENGTHS                            0x000014c4
01684 #define BNX2_EMAC_TX_LENGTHS_SLOT                        (0xffL<<0)
01685 #define BNX2_EMAC_TX_LENGTHS_IPG                         (0xfL<<8)
01686 #define BNX2_EMAC_TX_LENGTHS_IPG_CRS                     (0x3L<<12)
01687 
01688 #define BNX2_EMAC_RX_MODE                               0x000014c8
01689 #define BNX2_EMAC_RX_MODE_RESET                          (1L<<0)
01690 #define BNX2_EMAC_RX_MODE_FLOW_EN                        (1L<<2)
01691 #define BNX2_EMAC_RX_MODE_KEEP_MAC_CONTROL               (1L<<3)
01692 #define BNX2_EMAC_RX_MODE_KEEP_PAUSE                     (1L<<4)
01693 #define BNX2_EMAC_RX_MODE_ACCEPT_OVERSIZE                (1L<<5)
01694 #define BNX2_EMAC_RX_MODE_ACCEPT_RUNTS                   (1L<<6)
01695 #define BNX2_EMAC_RX_MODE_LLC_CHK                        (1L<<7)
01696 #define BNX2_EMAC_RX_MODE_PROMISCUOUS                    (1L<<8)
01697 #define BNX2_EMAC_RX_MODE_NO_CRC_CHK                     (1L<<9)
01698 #define BNX2_EMAC_RX_MODE_KEEP_VLAN_TAG                  (1L<<10)
01699 #define BNX2_EMAC_RX_MODE_FILT_BROADCAST                 (1L<<11)
01700 #define BNX2_EMAC_RX_MODE_SORT_MODE                      (1L<<12)
01701 
01702 #define BNX2_EMAC_RX_STATUS                             0x000014cc
01703 #define BNX2_EMAC_RX_STATUS_FFED                         (1L<<0)
01704 #define BNX2_EMAC_RX_STATUS_FF_RECEIVED                  (1L<<1)
01705 #define BNX2_EMAC_RX_STATUS_N_RECEIVED                   (1L<<2)
01706 
01707 #define BNX2_EMAC_MULTICAST_HASH0                       0x000014d0
01708 #define BNX2_EMAC_MULTICAST_HASH1                       0x000014d4
01709 #define BNX2_EMAC_MULTICAST_HASH2                       0x000014d8
01710 #define BNX2_EMAC_MULTICAST_HASH3                       0x000014dc
01711 #define BNX2_EMAC_MULTICAST_HASH4                       0x000014e0
01712 #define BNX2_EMAC_MULTICAST_HASH5                       0x000014e4
01713 #define BNX2_EMAC_MULTICAST_HASH6                       0x000014e8
01714 #define BNX2_EMAC_MULTICAST_HASH7                       0x000014ec
01715 #define BNX2_EMAC_RX_STAT_IFHCINOCTETS                  0x00001500
01716 #define BNX2_EMAC_RX_STAT_IFHCINBADOCTETS               0x00001504
01717 #define BNX2_EMAC_RX_STAT_ETHERSTATSFRAGMENTS           0x00001508
01718 #define BNX2_EMAC_RX_STAT_IFHCINUCASTPKTS               0x0000150c
01719 #define BNX2_EMAC_RX_STAT_IFHCINMULTICASTPKTS           0x00001510
01720 #define BNX2_EMAC_RX_STAT_IFHCINBROADCASTPKTS           0x00001514
01721 #define BNX2_EMAC_RX_STAT_DOT3STATSFCSERRORS            0x00001518
01722 #define BNX2_EMAC_RX_STAT_DOT3STATSALIGNMENTERRORS      0x0000151c
01723 #define BNX2_EMAC_RX_STAT_DOT3STATSCARRIERSENSEERRORS   0x00001520
01724 #define BNX2_EMAC_RX_STAT_XONPAUSEFRAMESRECEIVED        0x00001524
01725 #define BNX2_EMAC_RX_STAT_XOFFPAUSEFRAMESRECEIVED       0x00001528
01726 #define BNX2_EMAC_RX_STAT_MACCONTROLFRAMESRECEIVED      0x0000152c
01727 #define BNX2_EMAC_RX_STAT_XOFFSTATEENTERED              0x00001530
01728 #define BNX2_EMAC_RX_STAT_DOT3STATSFRAMESTOOLONG        0x00001534
01729 #define BNX2_EMAC_RX_STAT_ETHERSTATSJABBERS             0x00001538
01730 #define BNX2_EMAC_RX_STAT_ETHERSTATSUNDERSIZEPKTS       0x0000153c
01731 #define BNX2_EMAC_RX_STAT_ETHERSTATSPKTS64OCTETS        0x00001540
01732 #define BNX2_EMAC_RX_STAT_ETHERSTATSPKTS65OCTETSTO127OCTETS     0x00001544
01733 #define BNX2_EMAC_RX_STAT_ETHERSTATSPKTS128OCTETSTO255OCTETS    0x00001548
01734 #define BNX2_EMAC_RX_STAT_ETHERSTATSPKTS256OCTETSTO511OCTETS    0x0000154c
01735 #define BNX2_EMAC_RX_STAT_ETHERSTATSPKTS512OCTETSTO1023OCTETS   0x00001550
01736 #define BNX2_EMAC_RX_STAT_ETHERSTATSPKTS1024OCTETSTO1522OCTETS  0x00001554
01737 #define BNX2_EMAC_RX_STAT_ETHERSTATSPKTS1523OCTETSTO9022OCTETS  0x00001558
01738 #define BNX2_EMAC_RXMAC_DEBUG0                          0x0000155c
01739 #define BNX2_EMAC_RXMAC_DEBUG1                          0x00001560
01740 #define BNX2_EMAC_RXMAC_DEBUG1_LENGTH_NE_BYTE_COUNT      (1L<<0)
01741 #define BNX2_EMAC_RXMAC_DEBUG1_LENGTH_OUT_RANGE          (1L<<1)
01742 #define BNX2_EMAC_RXMAC_DEBUG1_BAD_CRC                   (1L<<2)
01743 #define BNX2_EMAC_RXMAC_DEBUG1_RX_ERROR                  (1L<<3)
01744 #define BNX2_EMAC_RXMAC_DEBUG1_ALIGN_ERROR               (1L<<4)
01745 #define BNX2_EMAC_RXMAC_DEBUG1_LAST_DATA                 (1L<<5)
01746 #define BNX2_EMAC_RXMAC_DEBUG1_ODD_BYTE_START            (1L<<6)
01747 #define BNX2_EMAC_RXMAC_DEBUG1_BYTE_COUNT                (0xffffL<<7)
01748 #define BNX2_EMAC_RXMAC_DEBUG1_SLOT_TIME                 (0xffL<<23)
01749 
01750 #define BNX2_EMAC_RXMAC_DEBUG2                          0x00001564
01751 #define BNX2_EMAC_RXMAC_DEBUG2_SM_STATE                  (0x7L<<0)
01752 #define BNX2_EMAC_RXMAC_DEBUG2_SM_STATE_IDLE             (0x0L<<0)
01753 #define BNX2_EMAC_RXMAC_DEBUG2_SM_STATE_SFD              (0x1L<<0)
01754 #define BNX2_EMAC_RXMAC_DEBUG2_SM_STATE_DATA             (0x2L<<0)
01755 #define BNX2_EMAC_RXMAC_DEBUG2_SM_STATE_SKEEP            (0x3L<<0)
01756 #define BNX2_EMAC_RXMAC_DEBUG2_SM_STATE_EXT              (0x4L<<0)
01757 #define BNX2_EMAC_RXMAC_DEBUG2_SM_STATE_DROP             (0x5L<<0)
01758 #define BNX2_EMAC_RXMAC_DEBUG2_SM_STATE_SDROP            (0x6L<<0)
01759 #define BNX2_EMAC_RXMAC_DEBUG2_SM_STATE_FC               (0x7L<<0)
01760 #define BNX2_EMAC_RXMAC_DEBUG2_IDI_STATE                 (0xfL<<3)
01761 #define BNX2_EMAC_RXMAC_DEBUG2_IDI_STATE_IDLE            (0x0L<<3)
01762 #define BNX2_EMAC_RXMAC_DEBUG2_IDI_STATE_DATA0           (0x1L<<3)
01763 #define BNX2_EMAC_RXMAC_DEBUG2_IDI_STATE_DATA1           (0x2L<<3)
01764 #define BNX2_EMAC_RXMAC_DEBUG2_IDI_STATE_DATA2           (0x3L<<3)
01765 #define BNX2_EMAC_RXMAC_DEBUG2_IDI_STATE_DATA3           (0x4L<<3)
01766 #define BNX2_EMAC_RXMAC_DEBUG2_IDI_STATE_ABORT           (0x5L<<3)
01767 #define BNX2_EMAC_RXMAC_DEBUG2_IDI_STATE_WAIT            (0x6L<<3)
01768 #define BNX2_EMAC_RXMAC_DEBUG2_IDI_STATE_STATUS          (0x7L<<3)
01769 #define BNX2_EMAC_RXMAC_DEBUG2_IDI_STATE_LAST            (0x8L<<3)
01770 #define BNX2_EMAC_RXMAC_DEBUG2_BYTE_IN                   (0xffL<<7)
01771 #define BNX2_EMAC_RXMAC_DEBUG2_FALSEC                    (1L<<15)
01772 #define BNX2_EMAC_RXMAC_DEBUG2_TAGGED                    (1L<<16)
01773 #define BNX2_EMAC_RXMAC_DEBUG2_PAUSE_STATE               (1L<<18)
01774 #define BNX2_EMAC_RXMAC_DEBUG2_PAUSE_STATE_IDLE          (0L<<18)
01775 #define BNX2_EMAC_RXMAC_DEBUG2_PAUSE_STATE_PAUSED        (1L<<18)
01776 #define BNX2_EMAC_RXMAC_DEBUG2_SE_COUNTER                (0xfL<<19)
01777 #define BNX2_EMAC_RXMAC_DEBUG2_QUANTA                    (0x1fL<<23)
01778 
01779 #define BNX2_EMAC_RXMAC_DEBUG3                          0x00001568
01780 #define BNX2_EMAC_RXMAC_DEBUG3_PAUSE_CTR                 (0xffffL<<0)
01781 #define BNX2_EMAC_RXMAC_DEBUG3_TMP_PAUSE_CTR             (0xffffL<<16)
01782 
01783 #define BNX2_EMAC_RXMAC_DEBUG4                          0x0000156c
01784 #define BNX2_EMAC_RXMAC_DEBUG4_TYPE_FIELD                (0xffffL<<0)
01785 #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE                (0x3fL<<16)
01786 #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_IDLE           (0x0L<<16)
01787 #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_UMAC2          (0x1L<<16)
01788 #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_UMAC3          (0x2L<<16)
01789 #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_UNI            (0x3L<<16)
01790 #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_MMAC2          (0x7L<<16)
01791 #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_MMAC3          (0x5L<<16)
01792 #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_PSA1           (0x6L<<16)
01793 #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_PSA2           (0x7L<<16)
01794 #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_PSA3           (0x8L<<16)
01795 #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_MC2            (0x9L<<16)
01796 #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_MC3            (0xaL<<16)
01797 #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_MWAIT1         (0xeL<<16)
01798 #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_MWAIT2         (0xfL<<16)
01799 #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_MCHECK         (0x10L<<16)
01800 #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_MC             (0x11L<<16)
01801 #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_BC2            (0x12L<<16)
01802 #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_BC3            (0x13L<<16)
01803 #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_BSA1           (0x14L<<16)
01804 #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_BSA2           (0x15L<<16)
01805 #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_BSA3           (0x16L<<16)
01806 #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_BTYPE          (0x17L<<16)
01807 #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_BC             (0x18L<<16)
01808 #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_PTYPE          (0x19L<<16)
01809 #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_CMD            (0x1aL<<16)
01810 #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_MAC            (0x1bL<<16)
01811 #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_LATCH          (0x1cL<<16)
01812 #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_XOFF           (0x1dL<<16)
01813 #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_XON            (0x1eL<<16)
01814 #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_PAUSED         (0x1fL<<16)
01815 #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_NPAUSED        (0x20L<<16)
01816 #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_TTYPE          (0x21L<<16)
01817 #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_TVAL           (0x22L<<16)
01818 #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_USA1           (0x23L<<16)
01819 #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_USA2           (0x24L<<16)
01820 #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_USA3           (0x25L<<16)
01821 #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_UTYPE          (0x26L<<16)
01822 #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_UTTYPE         (0x27L<<16)
01823 #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_UTVAL          (0x28L<<16)
01824 #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_MTYPE          (0x29L<<16)
01825 #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_DROP           (0x2aL<<16)
01826 #define BNX2_EMAC_RXMAC_DEBUG4_DROP_PKT                  (1L<<22)
01827 #define BNX2_EMAC_RXMAC_DEBUG4_SLOT_FILLED               (1L<<23)
01828 #define BNX2_EMAC_RXMAC_DEBUG4_FALSE_CARRIER             (1L<<24)
01829 #define BNX2_EMAC_RXMAC_DEBUG4_LAST_DATA                 (1L<<25)
01830 #define BNX2_EMAC_RXMAC_DEBUG4_sfd_FOUND                 (1L<<26)
01831 #define BNX2_EMAC_RXMAC_DEBUG4_ADVANCE                   (1L<<27)
01832 #define BNX2_EMAC_RXMAC_DEBUG4_START                     (1L<<28)
01833 
01834 #define BNX2_EMAC_RXMAC_DEBUG5                          0x00001570
01835 #define BNX2_EMAC_RXMAC_DEBUG5_PS_IDISM                  (0x7L<<0)
01836 #define BNX2_EMAC_RXMAC_DEBUG5_PS_IDISM_IDLE             (0L<<0)
01837 #define BNX2_EMAC_RXMAC_DEBUG5_PS_IDISM_WAIT_EOF         (1L<<0)
01838 #define BNX2_EMAC_RXMAC_DEBUG5_PS_IDISM_WAIT_STAT        (2L<<0)
01839 #define BNX2_EMAC_RXMAC_DEBUG5_PS_IDISM_SET_EOF4FCRC     (3L<<0)
01840 #define BNX2_EMAC_RXMAC_DEBUG5_PS_IDISM_SET_EOF4RDE      (4L<<0)
01841 #define BNX2_EMAC_RXMAC_DEBUG5_PS_IDISM_SET_EOF4ALL      (5L<<0)
01842 #define BNX2_EMAC_RXMAC_DEBUG5_PS_IDISM_1WD_WAIT_STAT    (6L<<0)
01843 #define BNX2_EMAC_RXMAC_DEBUG5_CCODE_BUF1                (0x7L<<4)
01844 #define BNX2_EMAC_RXMAC_DEBUG5_CCODE_BUF1_VDW            (0x0L<<4)
01845 #define BNX2_EMAC_RXMAC_DEBUG5_CCODE_BUF1_STAT           (0x1L<<4)
01846 #define BNX2_EMAC_RXMAC_DEBUG5_CCODE_BUF1_AEOF           (0x2L<<4)
01847 #define BNX2_EMAC_RXMAC_DEBUG5_CCODE_BUF1_NEOF           (0x3L<<4)
01848 #define BNX2_EMAC_RXMAC_DEBUG5_CCODE_BUF1_SOF            (0x4L<<4)
01849 #define BNX2_EMAC_RXMAC_DEBUG5_CCODE_BUF1_SAEOF          (0x6L<<4)
01850 #define BNX2_EMAC_RXMAC_DEBUG5_CCODE_BUF1_SNEOF          (0x7L<<4)
01851 #define BNX2_EMAC_RXMAC_DEBUG5_EOF_DETECTED              (1L<<7)
01852 #define BNX2_EMAC_RXMAC_DEBUG5_CCODE_BUF0                (0x7L<<8)
01853 #define BNX2_EMAC_RXMAC_DEBUG5_RPM_IDI_FIFO_FULL         (1L<<11)
01854 #define BNX2_EMAC_RXMAC_DEBUG5_LOAD_CCODE                (1L<<12)
01855 #define BNX2_EMAC_RXMAC_DEBUG5_LOAD_DATA                 (1L<<13)
01856 #define BNX2_EMAC_RXMAC_DEBUG5_LOAD_STAT                 (1L<<14)
01857 #define BNX2_EMAC_RXMAC_DEBUG5_CLR_STAT                  (1L<<15)
01858 #define BNX2_EMAC_RXMAC_DEBUG5_IDI_RPM_CCODE             (0x3L<<16)
01859 #define BNX2_EMAC_RXMAC_DEBUG5_IDI_RPM_ACCEPT            (1L<<19)
01860 #define BNX2_EMAC_RXMAC_DEBUG5_FMLEN                     (0xfffL<<20)
01861 
01862 #define BNX2_EMAC_RX_STAT_AC0                           0x00001580
01863 #define BNX2_EMAC_RX_STAT_AC1                           0x00001584
01864 #define BNX2_EMAC_RX_STAT_AC2                           0x00001588
01865 #define BNX2_EMAC_RX_STAT_AC3                           0x0000158c
01866 #define BNX2_EMAC_RX_STAT_AC4                           0x00001590
01867 #define BNX2_EMAC_RX_STAT_AC5                           0x00001594
01868 #define BNX2_EMAC_RX_STAT_AC6                           0x00001598
01869 #define BNX2_EMAC_RX_STAT_AC7                           0x0000159c
01870 #define BNX2_EMAC_RX_STAT_AC8                           0x000015a0
01871 #define BNX2_EMAC_RX_STAT_AC9                           0x000015a4
01872 #define BNX2_EMAC_RX_STAT_AC10                          0x000015a8
01873 #define BNX2_EMAC_RX_STAT_AC11                          0x000015ac
01874 #define BNX2_EMAC_RX_STAT_AC12                          0x000015b0
01875 #define BNX2_EMAC_RX_STAT_AC13                          0x000015b4
01876 #define BNX2_EMAC_RX_STAT_AC14                          0x000015b8
01877 #define BNX2_EMAC_RX_STAT_AC15                          0x000015bc
01878 #define BNX2_EMAC_RX_STAT_AC16                          0x000015c0
01879 #define BNX2_EMAC_RX_STAT_AC17                          0x000015c4
01880 #define BNX2_EMAC_RX_STAT_AC18                          0x000015c8
01881 #define BNX2_EMAC_RX_STAT_AC19                          0x000015cc
01882 #define BNX2_EMAC_RX_STAT_AC20                          0x000015d0
01883 #define BNX2_EMAC_RX_STAT_AC21                          0x000015d4
01884 #define BNX2_EMAC_RX_STAT_AC22                          0x000015d8
01885 #define BNX2_EMAC_RXMAC_SUC_DBG_OVERRUNVEC              0x000015dc
01886 #define BNX2_EMAC_TX_STAT_IFHCOUTOCTETS                 0x00001600
01887 #define BNX2_EMAC_TX_STAT_IFHCOUTBADOCTETS              0x00001604
01888 #define BNX2_EMAC_TX_STAT_ETHERSTATSCOLLISIONS          0x00001608
01889 #define BNX2_EMAC_TX_STAT_OUTXONSENT                    0x0000160c
01890 #define BNX2_EMAC_TX_STAT_OUTXOFFSENT                   0x00001610
01891 #define BNX2_EMAC_TX_STAT_FLOWCONTROLDONE               0x00001614
01892 #define BNX2_EMAC_TX_STAT_DOT3STATSSINGLECOLLISIONFRAMES        0x00001618
01893 #define BNX2_EMAC_TX_STAT_DOT3STATSMULTIPLECOLLISIONFRAMES      0x0000161c
01894 #define BNX2_EMAC_TX_STAT_DOT3STATSDEFERREDTRANSMISSIONS        0x00001620
01895 #define BNX2_EMAC_TX_STAT_DOT3STATSEXCESSIVECOLLISIONS  0x00001624
01896 #define BNX2_EMAC_TX_STAT_DOT3STATSLATECOLLISIONS       0x00001628
01897 #define BNX2_EMAC_TX_STAT_IFHCOUTUCASTPKTS              0x0000162c
01898 #define BNX2_EMAC_TX_STAT_IFHCOUTMULTICASTPKTS          0x00001630
01899 #define BNX2_EMAC_TX_STAT_IFHCOUTBROADCASTPKTS          0x00001634
01900 #define BNX2_EMAC_TX_STAT_ETHERSTATSPKTS64OCTETS        0x00001638
01901 #define BNX2_EMAC_TX_STAT_ETHERSTATSPKTS65OCTETSTO127OCTETS     0x0000163c
01902 #define BNX2_EMAC_TX_STAT_ETHERSTATSPKTS128OCTETSTO255OCTETS    0x00001640
01903 #define BNX2_EMAC_TX_STAT_ETHERSTATSPKTS256OCTETSTO511OCTETS    0x00001644
01904 #define BNX2_EMAC_TX_STAT_ETHERSTATSPKTS512OCTETSTO1023OCTETS   0x00001648
01905 #define BNX2_EMAC_TX_STAT_ETHERSTATSPKTS1024OCTETSTO1522OCTETS  0x0000164c
01906 #define BNX2_EMAC_TX_STAT_ETHERSTATSPKTS1523OCTETSTO9022OCTETS  0x00001650
01907 #define BNX2_EMAC_TX_STAT_DOT3STATSINTERNALMACTRANSMITERRORS    0x00001654
01908 #define BNX2_EMAC_TXMAC_DEBUG0                          0x00001658
01909 #define BNX2_EMAC_TXMAC_DEBUG1                          0x0000165c
01910 #define BNX2_EMAC_TXMAC_DEBUG1_ODI_STATE                 (0xfL<<0)
01911 #define BNX2_EMAC_TXMAC_DEBUG1_ODI_STATE_IDLE            (0x0L<<0)
01912 #define BNX2_EMAC_TXMAC_DEBUG1_ODI_STATE_START0          (0x1L<<0)
01913 #define BNX2_EMAC_TXMAC_DEBUG1_ODI_STATE_DATA0           (0x4L<<0)
01914 #define BNX2_EMAC_TXMAC_DEBUG1_ODI_STATE_DATA1           (0x5L<<0)
01915 #define BNX2_EMAC_TXMAC_DEBUG1_ODI_STATE_DATA2           (0x6L<<0)
01916 #define BNX2_EMAC_TXMAC_DEBUG1_ODI_STATE_DATA3           (0x7L<<0)
01917 #define BNX2_EMAC_TXMAC_DEBUG1_ODI_STATE_WAIT0           (0x8L<<0)
01918 #define BNX2_EMAC_TXMAC_DEBUG1_ODI_STATE_WAIT1           (0x9L<<0)
01919 #define BNX2_EMAC_TXMAC_DEBUG1_CRS_ENABLE                (1L<<4)
01920 #define BNX2_EMAC_TXMAC_DEBUG1_BAD_CRC                   (1L<<5)
01921 #define BNX2_EMAC_TXMAC_DEBUG1_SE_COUNTER                (0xfL<<6)
01922 #define BNX2_EMAC_TXMAC_DEBUG1_SEND_PAUSE                (1L<<10)
01923 #define BNX2_EMAC_TXMAC_DEBUG1_LATE_COLLISION            (1L<<11)
01924 #define BNX2_EMAC_TXMAC_DEBUG1_MAX_DEFER                 (1L<<12)
01925 #define BNX2_EMAC_TXMAC_DEBUG1_DEFERRED                  (1L<<13)
01926 #define BNX2_EMAC_TXMAC_DEBUG1_ONE_BYTE                  (1L<<14)
01927 #define BNX2_EMAC_TXMAC_DEBUG1_IPG_TIME                  (0xfL<<15)
01928 #define BNX2_EMAC_TXMAC_DEBUG1_SLOT_TIME                 (0xffL<<19)
01929 
01930 #define BNX2_EMAC_TXMAC_DEBUG2                          0x00001660
01931 #define BNX2_EMAC_TXMAC_DEBUG2_BACK_OFF                  (0x3ffL<<0)
01932 #define BNX2_EMAC_TXMAC_DEBUG2_BYTE_COUNT                (0xffffL<<10)
01933 #define BNX2_EMAC_TXMAC_DEBUG2_COL_COUNT                 (0x1fL<<26)
01934 #define BNX2_EMAC_TXMAC_DEBUG2_COL_BIT                   (1L<<31)
01935 
01936 #define BNX2_EMAC_TXMAC_DEBUG3                          0x00001664
01937 #define BNX2_EMAC_TXMAC_DEBUG3_SM_STATE                  (0xfL<<0)
01938 #define BNX2_EMAC_TXMAC_DEBUG3_SM_STATE_IDLE             (0x0L<<0)
01939 #define BNX2_EMAC_TXMAC_DEBUG3_SM_STATE_PRE1             (0x1L<<0)
01940 #define BNX2_EMAC_TXMAC_DEBUG3_SM_STATE_PRE2             (0x2L<<0)
01941 #define BNX2_EMAC_TXMAC_DEBUG3_SM_STATE_SFD              (0x3L<<0)
01942 #define BNX2_EMAC_TXMAC_DEBUG3_SM_STATE_DATA             (0x4L<<0)
01943 #define BNX2_EMAC_TXMAC_DEBUG3_SM_STATE_CRC1             (0x5L<<0)
01944 #define BNX2_EMAC_TXMAC_DEBUG3_SM_STATE_CRC2             (0x6L<<0)
01945 #define BNX2_EMAC_TXMAC_DEBUG3_SM_STATE_EXT              (0x7L<<0)
01946 #define BNX2_EMAC_TXMAC_DEBUG3_SM_STATE_STATB            (0x8L<<0)
01947 #define BNX2_EMAC_TXMAC_DEBUG3_SM_STATE_STATG            (0x9L<<0)
01948 #define BNX2_EMAC_TXMAC_DEBUG3_SM_STATE_JAM              (0xaL<<0)
01949 #define BNX2_EMAC_TXMAC_DEBUG3_SM_STATE_EJAM             (0xbL<<0)
01950 #define BNX2_EMAC_TXMAC_DEBUG3_SM_STATE_BJAM             (0xcL<<0)
01951 #define BNX2_EMAC_TXMAC_DEBUG3_SM_STATE_SWAIT            (0xdL<<0)
01952 #define BNX2_EMAC_TXMAC_DEBUG3_SM_STATE_BACKOFF          (0xeL<<0)
01953 #define BNX2_EMAC_TXMAC_DEBUG3_FILT_STATE                (0x7L<<4)
01954 #define BNX2_EMAC_TXMAC_DEBUG3_FILT_STATE_IDLE           (0x0L<<4)
01955 #define BNX2_EMAC_TXMAC_DEBUG3_FILT_STATE_WAIT           (0x1L<<4)
01956 #define BNX2_EMAC_TXMAC_DEBUG3_FILT_STATE_UNI            (0x2L<<4)
01957 #define BNX2_EMAC_TXMAC_DEBUG3_FILT_STATE_MC             (0x3L<<4)
01958 #define BNX2_EMAC_TXMAC_DEBUG3_FILT_STATE_BC2            (0x4L<<4)
01959 #define BNX2_EMAC_TXMAC_DEBUG3_FILT_STATE_BC3            (0x5L<<4)
01960 #define BNX2_EMAC_TXMAC_DEBUG3_FILT_STATE_BC             (0x6L<<4)
01961 #define BNX2_EMAC_TXMAC_DEBUG3_CRS_DONE                  (1L<<7)
01962 #define BNX2_EMAC_TXMAC_DEBUG3_XOFF                      (1L<<8)
01963 #define BNX2_EMAC_TXMAC_DEBUG3_SE_COUNTER                (0xfL<<9)
01964 #define BNX2_EMAC_TXMAC_DEBUG3_QUANTA_COUNTER            (0x1fL<<13)
01965 
01966 #define BNX2_EMAC_TXMAC_DEBUG4                          0x00001668
01967 #define BNX2_EMAC_TXMAC_DEBUG4_PAUSE_COUNTER             (0xffffL<<0)
01968 #define BNX2_EMAC_TXMAC_DEBUG4_PAUSE_STATE               (0xfL<<16)
01969 #define BNX2_EMAC_TXMAC_DEBUG4_PAUSE_STATE_IDLE          (0x0L<<16)
01970 #define BNX2_EMAC_TXMAC_DEBUG4_PAUSE_STATE_MCA1          (0x2L<<16)
01971 #define BNX2_EMAC_TXMAC_DEBUG4_PAUSE_STATE_MCA2          (0x3L<<16)
01972 #define BNX2_EMAC_TXMAC_DEBUG4_PAUSE_STATE_MCA3          (0x6L<<16)
01973 #define BNX2_EMAC_TXMAC_DEBUG4_PAUSE_STATE_SRC1          (0x7L<<16)
01974 #define BNX2_EMAC_TXMAC_DEBUG4_PAUSE_STATE_SRC2          (0x5L<<16)
01975 #define BNX2_EMAC_TXMAC_DEBUG4_PAUSE_STATE_SRC3          (0x4L<<16)
01976 #define BNX2_EMAC_TXMAC_DEBUG4_PAUSE_STATE_TYPE          (0xcL<<16)
01977 #define BNX2_EMAC_TXMAC_DEBUG4_PAUSE_STATE_CMD           (0xeL<<16)
01978 #define BNX2_EMAC_TXMAC_DEBUG4_PAUSE_STATE_TIME          (0xaL<<16)
01979 #define BNX2_EMAC_TXMAC_DEBUG4_PAUSE_STATE_CRC1          (0x8L<<16)
01980 #define BNX2_EMAC_TXMAC_DEBUG4_PAUSE_STATE_CRC2          (0x9L<<16)
01981 #define BNX2_EMAC_TXMAC_DEBUG4_PAUSE_STATE_WAIT          (0xdL<<16)
01982 #define BNX2_EMAC_TXMAC_DEBUG4_STATS0_VALID              (1L<<20)
01983 #define BNX2_EMAC_TXMAC_DEBUG4_APPEND_CRC                (1L<<21)
01984 #define BNX2_EMAC_TXMAC_DEBUG4_SLOT_FILLED               (1L<<22)
01985 #define BNX2_EMAC_TXMAC_DEBUG4_MAX_DEFER                 (1L<<23)
01986 #define BNX2_EMAC_TXMAC_DEBUG4_SEND_EXTEND               (1L<<24)
01987 #define BNX2_EMAC_TXMAC_DEBUG4_SEND_PADDING              (1L<<25)
01988 #define BNX2_EMAC_TXMAC_DEBUG4_EOF_LOC                   (1L<<26)
01989 #define BNX2_EMAC_TXMAC_DEBUG4_COLLIDING                 (1L<<27)
01990 #define BNX2_EMAC_TXMAC_DEBUG4_COL_IN                    (1L<<28)
01991 #define BNX2_EMAC_TXMAC_DEBUG4_BURSTING                  (1L<<29)
01992 #define BNX2_EMAC_TXMAC_DEBUG4_ADVANCE                   (1L<<30)
01993 #define BNX2_EMAC_TXMAC_DEBUG4_GO                        (1L<<31)
01994 
01995 #define BNX2_EMAC_TX_STAT_AC0                           0x00001680
01996 #define BNX2_EMAC_TX_STAT_AC1                           0x00001684
01997 #define BNX2_EMAC_TX_STAT_AC2                           0x00001688
01998 #define BNX2_EMAC_TX_STAT_AC3                           0x0000168c
01999 #define BNX2_EMAC_TX_STAT_AC4                           0x00001690
02000 #define BNX2_EMAC_TX_STAT_AC5                           0x00001694
02001 #define BNX2_EMAC_TX_STAT_AC6                           0x00001698
02002 #define BNX2_EMAC_TX_STAT_AC7                           0x0000169c
02003 #define BNX2_EMAC_TX_STAT_AC8                           0x000016a0
02004 #define BNX2_EMAC_TX_STAT_AC9                           0x000016a4
02005 #define BNX2_EMAC_TX_STAT_AC10                          0x000016a8
02006 #define BNX2_EMAC_TX_STAT_AC11                          0x000016ac
02007 #define BNX2_EMAC_TX_STAT_AC12                          0x000016b0
02008 #define BNX2_EMAC_TX_STAT_AC13                          0x000016b4
02009 #define BNX2_EMAC_TX_STAT_AC14                          0x000016b8
02010 #define BNX2_EMAC_TX_STAT_AC15                          0x000016bc
02011 #define BNX2_EMAC_TX_STAT_AC16                          0x000016c0
02012 #define BNX2_EMAC_TX_STAT_AC17                          0x000016c4
02013 #define BNX2_EMAC_TX_STAT_AC18                          0x000016c8
02014 #define BNX2_EMAC_TX_STAT_AC19                          0x000016cc
02015 #define BNX2_EMAC_TX_STAT_AC20                          0x000016d0
02016 #define BNX2_EMAC_TX_STAT_AC21                          0x000016d4
02017 #define BNX2_EMAC_TXMAC_SUC_DBG_OVERRUNVEC              0x000016d8
02018 
02019 
02020 /*
02021  *  rpm_reg definition
02022  *  offset: 0x1800
02023  */
02024 #define BNX2_RPM_COMMAND                                0x00001800
02025 #define BNX2_RPM_COMMAND_ENABLED                         (1L<<0)
02026 #define BNX2_RPM_COMMAND_OVERRUN_ABORT                   (1L<<4)
02027 
02028 #define BNX2_RPM_STATUS                                 0x00001804
02029 #define BNX2_RPM_STATUS_MBUF_WAIT                        (1L<<0)
02030 #define BNX2_RPM_STATUS_FREE_WAIT                        (1L<<1)
02031 
02032 #define BNX2_RPM_CONFIG                                 0x00001808
02033 #define BNX2_RPM_CONFIG_NO_PSD_HDR_CKSUM                 (1L<<0)
02034 #define BNX2_RPM_CONFIG_ACPI_ENA                         (1L<<1)
02035 #define BNX2_RPM_CONFIG_ACPI_KEEP                        (1L<<2)
02036 #define BNX2_RPM_CONFIG_MP_KEEP                          (1L<<3)
02037 #define BNX2_RPM_CONFIG_SORT_VECT_VAL                    (0xfL<<4)
02038 #define BNX2_RPM_CONFIG_IGNORE_VLAN                      (1L<<31)
02039 
02040 #define BNX2_RPM_VLAN_MATCH0                            0x00001810
02041 #define BNX2_RPM_VLAN_MATCH0_RPM_VLAN_MTCH0_VALUE        (0xfffL<<0)
02042 
02043 #define BNX2_RPM_VLAN_MATCH1                            0x00001814
02044 #define BNX2_RPM_VLAN_MATCH1_RPM_VLAN_MTCH1_VALUE        (0xfffL<<0)
02045 
02046 #define BNX2_RPM_VLAN_MATCH2                            0x00001818
02047 #define BNX2_RPM_VLAN_MATCH2_RPM_VLAN_MTCH2_VALUE        (0xfffL<<0)
02048 
02049 #define BNX2_RPM_VLAN_MATCH3                            0x0000181c
02050 #define BNX2_RPM_VLAN_MATCH3_RPM_VLAN_MTCH3_VALUE        (0xfffL<<0)
02051 
02052 #define BNX2_RPM_SORT_USER0                             0x00001820
02053 #define BNX2_RPM_SORT_USER0_PM_EN                        (0xffffL<<0)
02054 #define BNX2_RPM_SORT_USER0_BC_EN                        (1L<<16)
02055 #define BNX2_RPM_SORT_USER0_MC_EN                        (1L<<17)
02056 #define BNX2_RPM_SORT_USER0_MC_HSH_EN                    (1L<<18)
02057 #define BNX2_RPM_SORT_USER0_PROM_EN                      (1L<<19)
02058 #define BNX2_RPM_SORT_USER0_VLAN_EN                      (0xfL<<20)
02059 #define BNX2_RPM_SORT_USER0_PROM_VLAN                    (1L<<24)
02060 #define BNX2_RPM_SORT_USER0_ENA                          (1L<<31)
02061 
02062 #define BNX2_RPM_SORT_USER1                             0x00001824
02063 #define BNX2_RPM_SORT_USER1_PM_EN                        (0xffffL<<0)
02064 #define BNX2_RPM_SORT_USER1_BC_EN                        (1L<<16)
02065 #define BNX2_RPM_SORT_USER1_MC_EN                        (1L<<17)
02066 #define BNX2_RPM_SORT_USER1_MC_HSH_EN                    (1L<<18)
02067 #define BNX2_RPM_SORT_USER1_PROM_EN                      (1L<<19)
02068 #define BNX2_RPM_SORT_USER1_VLAN_EN                      (0xfL<<20)
02069 #define BNX2_RPM_SORT_USER1_PROM_VLAN                    (1L<<24)
02070 #define BNX2_RPM_SORT_USER1_ENA                          (1L<<31)
02071 
02072 #define BNX2_RPM_SORT_USER2                             0x00001828
02073 #define BNX2_RPM_SORT_USER2_PM_EN                        (0xffffL<<0)
02074 #define BNX2_RPM_SORT_USER2_BC_EN                        (1L<<16)
02075 #define BNX2_RPM_SORT_USER2_MC_EN                        (1L<<17)
02076 #define BNX2_RPM_SORT_USER2_MC_HSH_EN                    (1L<<18)
02077 #define BNX2_RPM_SORT_USER2_PROM_EN                      (1L<<19)
02078 #define BNX2_RPM_SORT_USER2_VLAN_EN                      (0xfL<<20)
02079 #define BNX2_RPM_SORT_USER2_PROM_VLAN                    (1L<<24)
02080 #define BNX2_RPM_SORT_USER2_ENA                          (1L<<31)
02081 
02082 #define BNX2_RPM_SORT_USER3                             0x0000182c
02083 #define BNX2_RPM_SORT_USER3_PM_EN                        (0xffffL<<0)
02084 #define BNX2_RPM_SORT_USER3_BC_EN                        (1L<<16)
02085 #define BNX2_RPM_SORT_USER3_MC_EN                        (1L<<17)
02086 #define BNX2_RPM_SORT_USER3_MC_HSH_EN                    (1L<<18)
02087 #define BNX2_RPM_SORT_USER3_PROM_EN                      (1L<<19)
02088 #define BNX2_RPM_SORT_USER3_VLAN_EN                      (0xfL<<20)
02089 #define BNX2_RPM_SORT_USER3_PROM_VLAN                    (1L<<24)
02090 #define BNX2_RPM_SORT_USER3_ENA                          (1L<<31)
02091 
02092 #define BNX2_RPM_STAT_L2_FILTER_DISCARDS                0x00001840
02093 #define BNX2_RPM_STAT_RULE_CHECKER_DISCARDS             0x00001844
02094 #define BNX2_RPM_STAT_IFINFTQDISCARDS                   0x00001848
02095 #define BNX2_RPM_STAT_IFINMBUFDISCARD                   0x0000184c
02096 #define BNX2_RPM_STAT_RULE_CHECKER_P4_HIT               0x00001850
02097 #define BNX2_RPM_STAT_AC0                               0x00001880
02098 #define BNX2_RPM_STAT_AC1                               0x00001884
02099 #define BNX2_RPM_STAT_AC2                               0x00001888
02100 #define BNX2_RPM_STAT_AC3                               0x0000188c
02101 #define BNX2_RPM_STAT_AC4                               0x00001890
02102 #define BNX2_RPM_RC_CNTL_0                              0x00001900
02103 #define BNX2_RPM_RC_CNTL_0_OFFSET                        (0xffL<<0)
02104 #define BNX2_RPM_RC_CNTL_0_CLASS                         (0x7L<<8)
02105 #define BNX2_RPM_RC_CNTL_0_PRIORITY                      (1L<<11)
02106 #define BNX2_RPM_RC_CNTL_0_P4                            (1L<<12)
02107 #define BNX2_RPM_RC_CNTL_0_HDR_TYPE                      (0x7L<<13)
02108 #define BNX2_RPM_RC_CNTL_0_HDR_TYPE_START                (0L<<13)
02109 #define BNX2_RPM_RC_CNTL_0_HDR_TYPE_IP                   (1L<<13)
02110 #define BNX2_RPM_RC_CNTL_0_HDR_TYPE_TCP                  (2L<<13)
02111 #define BNX2_RPM_RC_CNTL_0_HDR_TYPE_UDP                  (3L<<13)
02112 #define BNX2_RPM_RC_CNTL_0_HDR_TYPE_DATA                 (4L<<13)
02113 #define BNX2_RPM_RC_CNTL_0_COMP                          (0x3L<<16)
02114 #define BNX2_RPM_RC_CNTL_0_COMP_EQUAL                    (0L<<16)
02115 #define BNX2_RPM_RC_CNTL_0_COMP_NEQUAL                   (1L<<16)
02116 #define BNX2_RPM_RC_CNTL_0_COMP_GREATER                  (2L<<16)
02117 #define BNX2_RPM_RC_CNTL_0_COMP_LESS                     (3L<<16)
02118 #define BNX2_RPM_RC_CNTL_0_SBIT                          (1L<<19)
02119 #define BNX2_RPM_RC_CNTL_0_CMDSEL                        (0xfL<<20)
02120 #define BNX2_RPM_RC_CNTL_0_MAP                           (1L<<24)
02121 #define BNX2_RPM_RC_CNTL_0_DISCARD                       (1L<<25)
02122 #define BNX2_RPM_RC_CNTL_0_MASK                          (1L<<26)
02123 #define BNX2_RPM_RC_CNTL_0_P1                            (1L<<27)
02124 #define BNX2_RPM_RC_CNTL_0_P2                            (1L<<28)
02125 #define BNX2_RPM_RC_CNTL_0_P3                            (1L<<29)
02126 #define BNX2_RPM_RC_CNTL_0_NBIT                          (1L<<30)
02127 
02128 #define BNX2_RPM_RC_VALUE_MASK_0                        0x00001904
02129 #define BNX2_RPM_RC_VALUE_MASK_0_VALUE                   (0xffffL<<0)
02130 #define BNX2_RPM_RC_VALUE_MASK_0_MASK                    (0xffffL<<16)
02131 
02132 #define BNX2_RPM_RC_CNTL_1                              0x00001908
02133 #define BNX2_RPM_RC_CNTL_1_A                             (0x3ffffL<<0)
02134 #define BNX2_RPM_RC_CNTL_1_B                             (0xfffL<<19)
02135 
02136 #define BNX2_RPM_RC_VALUE_MASK_1                        0x0000190c
02137 #define BNX2_RPM_RC_CNTL_2                              0x00001910
02138 #define BNX2_RPM_RC_CNTL_2_A                             (0x3ffffL<<0)
02139 #define BNX2_RPM_RC_CNTL_2_B                             (0xfffL<<19)
02140 
02141 #define BNX2_RPM_RC_VALUE_MASK_2                        0x00001914
02142 #define BNX2_RPM_RC_CNTL_3                              0x00001918
02143 #define BNX2_RPM_RC_CNTL_3_A                             (0x3ffffL<<0)
02144 #define BNX2_RPM_RC_CNTL_3_B                             (0xfffL<<19)
02145 
02146 #define BNX2_RPM_RC_VALUE_MASK_3                        0x0000191c
02147 #define BNX2_RPM_RC_CNTL_4                              0x00001920
02148 #define BNX2_RPM_RC_CNTL_4_A                             (0x3ffffL<<0)
02149 #define BNX2_RPM_RC_CNTL_4_B                             (0xfffL<<19)
02150 
02151 #define BNX2_RPM_RC_VALUE_MASK_4                        0x00001924
02152 #define BNX2_RPM_RC_CNTL_5                              0x00001928
02153 #define BNX2_RPM_RC_CNTL_5_A                             (0x3ffffL<<0)
02154 #define BNX2_RPM_RC_CNTL_5_B                             (0xfffL<<19)
02155 
02156 #define BNX2_RPM_RC_VALUE_MASK_5                        0x0000192c
02157 #define BNX2_RPM_RC_CNTL_6                              0x00001930
02158 #define BNX2_RPM_RC_CNTL_6_A                             (0x3ffffL<<0)
02159 #define BNX2_RPM_RC_CNTL_6_B                             (0xfffL<<19)
02160 
02161 #define BNX2_RPM_RC_VALUE_MASK_6                        0x00001934
02162 #define BNX2_RPM_RC_CNTL_7                              0x00001938
02163 #define BNX2_RPM_RC_CNTL_7_A                             (0x3ffffL<<0)
02164 #define BNX2_RPM_RC_CNTL_7_B                             (0xfffL<<19)
02165 
02166 #define BNX2_RPM_RC_VALUE_MASK_7                        0x0000193c
02167 #define BNX2_RPM_RC_CNTL_8                              0x00001940
02168 #define BNX2_RPM_RC_CNTL_8_A                             (0x3ffffL<<0)
02169 #define BNX2_RPM_RC_CNTL_8_B                             (0xfffL<<19)
02170 
02171 #define BNX2_RPM_RC_VALUE_MASK_8                        0x00001944
02172 #define BNX2_RPM_RC_CNTL_9                              0x00001948
02173 #define BNX2_RPM_RC_CNTL_9_A                             (0x3ffffL<<0)
02174 #define BNX2_RPM_RC_CNTL_9_B                             (0xfffL<<19)
02175 
02176 #define BNX2_RPM_RC_VALUE_MASK_9                        0x0000194c
02177 #define BNX2_RPM_RC_CNTL_10                             0x00001950
02178 #define BNX2_RPM_RC_CNTL_10_A                            (0x3ffffL<<0)
02179 #define BNX2_RPM_RC_CNTL_10_B                            (0xfffL<<19)
02180 
02181 #define BNX2_RPM_RC_VALUE_MASK_10                       0x00001954
02182 #define BNX2_RPM_RC_CNTL_11                             0x00001958
02183 #define BNX2_RPM_RC_CNTL_11_A                            (0x3ffffL<<0)
02184 #define BNX2_RPM_RC_CNTL_11_B                            (0xfffL<<19)
02185 
02186 #define BNX2_RPM_RC_VALUE_MASK_11                       0x0000195c
02187 #define BNX2_RPM_RC_CNTL_12                             0x00001960
02188 #define BNX2_RPM_RC_CNTL_12_A                            (0x3ffffL<<0)
02189 #define BNX2_RPM_RC_CNTL_12_B                            (0xfffL<<19)
02190 
02191 #define BNX2_RPM_RC_VALUE_MASK_12                       0x00001964
02192 #define BNX2_RPM_RC_CNTL_13                             0x00001968
02193 #define BNX2_RPM_RC_CNTL_13_A                            (0x3ffffL<<0)
02194 #define BNX2_RPM_RC_CNTL_13_B                            (0xfffL<<19)
02195 
02196 #define BNX2_RPM_RC_VALUE_MASK_13                       0x0000196c
02197 #define BNX2_RPM_RC_CNTL_14                             0x00001970
02198 #define BNX2_RPM_RC_CNTL_14_A                            (0x3ffffL<<0)
02199 #define BNX2_RPM_RC_CNTL_14_B                            (0xfffL<<19)
02200 
02201 #define BNX2_RPM_RC_VALUE_MASK_14                       0x00001974
02202 #define BNX2_RPM_RC_CNTL_15                             0x00001978
02203 #define BNX2_RPM_RC_CNTL_15_A                            (0x3ffffL<<0)
02204 #define BNX2_RPM_RC_CNTL_15_B                            (0xfffL<<19)
02205 
02206 #define BNX2_RPM_RC_VALUE_MASK_15                       0x0000197c
02207 #define BNX2_RPM_RC_CONFIG                              0x00001980
02208 #define BNX2_RPM_RC_CONFIG_RULE_ENABLE                   (0xffffL<<0)
02209 #define BNX2_RPM_RC_CONFIG_DEF_CLASS                     (0x7L<<24)
02210 
02211 #define BNX2_RPM_DEBUG0                                 0x00001984
02212 #define BNX2_RPM_DEBUG0_FM_BCNT                          (0xffffL<<0)
02213 #define BNX2_RPM_DEBUG0_T_DATA_OFST_VLD                  (1L<<16)
02214 #define BNX2_RPM_DEBUG0_T_UDP_OFST_VLD                   (1L<<17)
02215 #define BNX2_RPM_DEBUG0_T_TCP_OFST_VLD                   (1L<<18)
02216 #define BNX2_RPM_DEBUG0_T_IP_OFST_VLD                    (1L<<19)
02217 #define BNX2_RPM_DEBUG0_IP_MORE_FRGMT                    (1L<<20)
02218 #define BNX2_RPM_DEBUG0_T_IP_NO_TCP_UDP_HDR              (1L<<21)
02219 #define BNX2_RPM_DEBUG0_LLC_SNAP                         (1L<<22)
02220 #define BNX2_RPM_DEBUG0_FM_STARTED                       (1L<<23)
02221 #define BNX2_RPM_DEBUG0_DONE                             (1L<<24)
02222 #define BNX2_RPM_DEBUG0_WAIT_4_DONE                      (1L<<25)
02223 #define BNX2_RPM_DEBUG0_USE_TPBUF_CKSUM                  (1L<<26)
02224 #define BNX2_RPM_DEBUG0_RX_NO_PSD_HDR_CKSUM              (1L<<27)
02225 #define BNX2_RPM_DEBUG0_IGNORE_VLAN                      (1L<<28)
02226 #define BNX2_RPM_DEBUG0_RP_ENA_ACTIVE                    (1L<<31)
02227 
02228 #define BNX2_RPM_DEBUG1                                 0x00001988
02229 #define BNX2_RPM_DEBUG1_FSM_CUR_ST                       (0xffffL<<0)
02230 #define BNX2_RPM_DEBUG1_FSM_CUR_ST_IDLE                  (0L<<0)
02231 #define BNX2_RPM_DEBUG1_FSM_CUR_ST_ETYPE_B6_ALL          (1L<<0)
02232 #define BNX2_RPM_DEBUG1_FSM_CUR_ST_ETYPE_B2_IPLLC        (2L<<0)
02233 #define BNX2_RPM_DEBUG1_FSM_CUR_ST_ETYPE_B6_IP           (4L<<0)
02234 #define BNX2_RPM_DEBUG1_FSM_CUR_ST_ETYPE_B2_IP           (8L<<0)
02235 #define BNX2_RPM_DEBUG1_FSM_CUR_ST_IP_START              (16L<<0)
02236 #define BNX2_RPM_DEBUG1_FSM_CUR_ST_IP                    (32L<<0)
02237 #define BNX2_RPM_DEBUG1_FSM_CUR_ST_TCP                   (64L<<0)
02238 #define BNX2_RPM_DEBUG1_FSM_CUR_ST_UDP                   (128L<<0)
02239 #define BNX2_RPM_DEBUG1_FSM_CUR_ST_AH                    (256L<<0)
02240 #define BNX2_RPM_DEBUG1_FSM_CUR_ST_ESP                   (512L<<0)
02241 #define BNX2_RPM_DEBUG1_FSM_CUR_ST_ESP_PAYLOAD           (1024L<<0)
02242 #define BNX2_RPM_DEBUG1_FSM_CUR_ST_DATA                  (2048L<<0)
02243 #define BNX2_RPM_DEBUG1_FSM_CUR_ST_ADD_CARRY             (0x2000L<<0)
02244 #define BNX2_RPM_DEBUG1_FSM_CUR_ST_ADD_CARRYOUT          (0x4000L<<0)
02245 #define BNX2_RPM_DEBUG1_FSM_CUR_ST_LATCH_RESULT          (0x8000L<<0)
02246 #define BNX2_RPM_DEBUG1_HDR_BCNT                         (0x7ffL<<16)
02247 #define BNX2_RPM_DEBUG1_UNKNOWN_ETYPE_D                  (1L<<28)
02248 #define BNX2_RPM_DEBUG1_VLAN_REMOVED_D2                  (1L<<29)
02249 #define BNX2_RPM_DEBUG1_VLAN_REMOVED_D1                  (1L<<30)
02250 #define BNX2_RPM_DEBUG1_EOF_0XTRA_WD                     (1L<<31)
02251 
02252 #define BNX2_RPM_DEBUG2                                 0x0000198c
02253 #define BNX2_RPM_DEBUG2_CMD_HIT_VEC                      (0xffffL<<0)
02254 #define BNX2_RPM_DEBUG2_IP_BCNT                          (0xffL<<16)
02255 #define BNX2_RPM_DEBUG2_THIS_CMD_M4                      (1L<<24)
02256 #define BNX2_RPM_DEBUG2_THIS_CMD_M3                      (1L<<25)
02257 #define BNX2_RPM_DEBUG2_THIS_CMD_M2                      (1L<<26)
02258 #define BNX2_RPM_DEBUG2_THIS_CMD_M1                      (1L<<27)
02259 #define BNX2_RPM_DEBUG2_IPIPE_EMPTY                      (1L<<28)
02260 #define BNX2_RPM_DEBUG2_FM_DISCARD                       (1L<<29)
02261 #define BNX2_RPM_DEBUG2_LAST_RULE_IN_FM_D2               (1L<<30)
02262 #define BNX2_RPM_DEBUG2_LAST_RULE_IN_FM_D1               (1L<<31)
02263 
02264 #define BNX2_RPM_DEBUG3                                 0x00001990
02265 #define BNX2_RPM_DEBUG3_AVAIL_MBUF_PTR                   (0x1ffL<<0)
02266 #define BNX2_RPM_DEBUG3_RDE_RLUPQ_WR_REQ_INT             (1L<<9)
02267 #define BNX2_RPM_DEBUG3_RDE_RBUF_WR_LAST_INT             (1L<<10)
02268 #define BNX2_RPM_DEBUG3_RDE_RBUF_WR_REQ_INT              (1L<<11)
02269 #define BNX2_RPM_DEBUG3_RDE_RBUF_FREE_REQ                (1L<<12)
02270 #define BNX2_RPM_DEBUG3_RDE_RBUF_ALLOC_REQ               (1L<<13)
02271 #define BNX2_RPM_DEBUG3_DFSM_MBUF_NOTAVAIL               (1L<<14)
02272 #define BNX2_RPM_DEBUG3_RBUF_RDE_SOF_DROP                (1L<<15)
02273 #define BNX2_RPM_DEBUG3_DFIFO_VLD_ENTRY_CT               (0xfL<<16)
02274 #define BNX2_RPM_DEBUG3_RDE_SRC_FIFO_ALMFULL             (1L<<21)
02275 #define BNX2_RPM_DEBUG3_DROP_NXT_VLD                     (1L<<22)
02276 #define BNX2_RPM_DEBUG3_DROP_NXT                         (1L<<23)
02277 #define BNX2_RPM_DEBUG3_FTQ_FSM                          (0x3L<<24)
02278 #define BNX2_RPM_DEBUG3_FTQ_FSM_IDLE                     (0x0L<<24)
02279 #define BNX2_RPM_DEBUG3_FTQ_FSM_WAIT_ACK                 (0x1L<<24)
02280 #define BNX2_RPM_DEBUG3_FTQ_FSM_WAIT_FREE                (0x2L<<24)
02281 #define BNX2_RPM_DEBUG3_MBWRITE_FSM                      (0x3L<<26)
02282 #define BNX2_RPM_DEBUG3_MBWRITE_FSM_WAIT_SOF             (0x0L<<26)
02283 #define BNX2_RPM_DEBUG3_MBWRITE_FSM_GET_MBUF             (0x1L<<26)
02284 #define BNX2_RPM_DEBUG3_MBWRITE_FSM_DMA_DATA             (0x2L<<26)
02285 #define BNX2_RPM_DEBUG3_MBWRITE_FSM_WAIT_DATA            (0x3L<<26)
02286 #define BNX2_RPM_DEBUG3_MBWRITE_FSM_WAIT_EOF             (0x4L<<26)
02287 #define BNX2_RPM_DEBUG3_MBWRITE_FSM_WAIT_MF_ACK          (0x5L<<26)
02288 #define BNX2_RPM_DEBUG3_MBWRITE_FSM_WAIT_DROP_NXT_VLD    (0x6L<<26)
02289 #define BNX2_RPM_DEBUG3_MBWRITE_FSM_DONE                 (0x7L<<26)
02290 #define BNX2_RPM_DEBUG3_MBFREE_FSM                       (1L<<29)
02291 #define BNX2_RPM_DEBUG3_MBFREE_FSM_IDLE                  (0L<<29)
02292 #define BNX2_RPM_DEBUG3_MBFREE_FSM_WAIT_ACK              (1L<<29)
02293 #define BNX2_RPM_DEBUG3_MBALLOC_FSM                      (1L<<30)
02294 #define BNX2_RPM_DEBUG3_MBALLOC_FSM_ET_MBUF              (0x0L<<30)
02295 #define BNX2_RPM_DEBUG3_MBALLOC_FSM_IVE_MBUF             (0x1L<<30)
02296 #define BNX2_RPM_DEBUG3_CCODE_EOF_ERROR                  (1L<<31)
02297 
02298 #define BNX2_RPM_DEBUG4                                 0x00001994
02299 #define BNX2_RPM_DEBUG4_DFSM_MBUF_CLUSTER                (0x1ffffffL<<0)
02300 #define BNX2_RPM_DEBUG4_DFIFO_CUR_CCODE                  (0x7L<<25)
02301 #define BNX2_RPM_DEBUG4_MBWRITE_FSM                      (0x7L<<28)
02302 #define BNX2_RPM_DEBUG4_DFIFO_EMPTY                      (1L<<31)
02303 
02304 #define BNX2_RPM_DEBUG5                                 0x00001998
02305 #define BNX2_RPM_DEBUG5_RDROP_WPTR                       (0x1fL<<0)
02306 #define BNX2_RPM_DEBUG5_RDROP_ACPI_RPTR                  (0x1fL<<5)
02307 #define BNX2_RPM_DEBUG5_RDROP_MC_RPTR                    (0x1fL<<10)
02308 #define BNX2_RPM_DEBUG5_RDROP_RC_RPTR                    (0x1fL<<15)
02309 #define BNX2_RPM_DEBUG5_RDROP_ACPI_EMPTY                 (1L<<20)
02310 #define BNX2_RPM_DEBUG5_RDROP_MC_EMPTY                   (1L<<21)
02311 #define BNX2_RPM_DEBUG5_RDROP_AEOF_VEC_AT_RDROP_MC_RPTR  (1L<<22)
02312 #define BNX2_RPM_DEBUG5_HOLDREG_WOL_DROP_INT             (1L<<23)
02313 #define BNX2_RPM_DEBUG5_HOLDREG_DISCARD                  (1L<<24)
02314 #define BNX2_RPM_DEBUG5_HOLDREG_MBUF_NOTAVAIL            (1L<<25)
02315 #define BNX2_RPM_DEBUG5_HOLDREG_MC_EMPTY                 (1L<<26)
02316 #define BNX2_RPM_DEBUG5_HOLDREG_RC_EMPTY                 (1L<<27)
02317 #define BNX2_RPM_DEBUG5_HOLDREG_FC_EMPTY                 (1L<<28)
02318 #define BNX2_RPM_DEBUG5_HOLDREG_ACPI_EMPTY               (1L<<29)
02319 #define BNX2_RPM_DEBUG5_HOLDREG_FULL_T                   (1L<<30)
02320 #define BNX2_RPM_DEBUG5_HOLDREG_RD                       (1L<<31)
02321 
02322 #define BNX2_RPM_DEBUG6                                 0x0000199c
02323 #define BNX2_RPM_DEBUG6_ACPI_VEC                         (0xffffL<<0)
02324 #define BNX2_RPM_DEBUG6_VEC                              (0xffffL<<16)
02325 
02326 #define BNX2_RPM_DEBUG7                                 0x000019a0
02327 #define BNX2_RPM_DEBUG7_RPM_DBG7_LAST_CRC                (0xffffffffL<<0)
02328 
02329 #define BNX2_RPM_DEBUG8                                 0x000019a4
02330 #define BNX2_RPM_DEBUG8_PS_ACPI_FSM                      (0xfL<<0)
02331 #define BNX2_RPM_DEBUG8_PS_ACPI_FSM_IDLE                 (0L<<0)
02332 #define BNX2_RPM_DEBUG8_PS_ACPI_FSM_SOF_W1_ADDR          (1L<<0)
02333 #define BNX2_RPM_DEBUG8_PS_ACPI_FSM_SOF_W2_ADDR          (2L<<0)
02334 #define BNX2_RPM_DEBUG8_PS_ACPI_FSM_SOF_W3_ADDR          (3L<<0)
02335 #define BNX2_RPM_DEBUG8_PS_ACPI_FSM_SOF_WAIT_THBUF       (4L<<0)
02336 #define BNX2_RPM_DEBUG8_PS_ACPI_FSM_W3_DATA              (5L<<0)
02337 #define BNX2_RPM_DEBUG8_PS_ACPI_FSM_W0_ADDR              (6L<<0)
02338 #define BNX2_RPM_DEBUG8_PS_ACPI_FSM_W1_ADDR              (7L<<0)
02339 #define BNX2_RPM_DEBUG8_PS_ACPI_FSM_W2_ADDR              (8L<<0)
02340 #define BNX2_RPM_DEBUG8_PS_ACPI_FSM_W3_ADDR              (9L<<0)
02341 #define BNX2_RPM_DEBUG8_PS_ACPI_FSM_WAIT_THBUF           (10L<<0)
02342 #define BNX2_RPM_DEBUG8_COMPARE_AT_W0                    (1L<<4)
02343 #define BNX2_RPM_DEBUG8_COMPARE_AT_W3_DATA               (1L<<5)
02344 #define BNX2_RPM_DEBUG8_COMPARE_AT_SOF_WAIT              (1L<<6)
02345 #define BNX2_RPM_DEBUG8_COMPARE_AT_SOF_W3                (1L<<7)
02346 #define BNX2_RPM_DEBUG8_COMPARE_AT_SOF_W2                (1L<<8)
02347 #define BNX2_RPM_DEBUG8_EOF_W_LTEQ6_VLDBYTES             (1L<<9)
02348 #define BNX2_RPM_DEBUG8_EOF_W_LTEQ4_VLDBYTES             (1L<<10)
02349 #define BNX2_RPM_DEBUG8_NXT_EOF_W_12_VLDBYTES            (1L<<11)
02350 #define BNX2_RPM_DEBUG8_EOF_DET                          (1L<<12)
02351 #define BNX2_RPM_DEBUG8_SOF_DET                          (1L<<13)
02352 #define BNX2_RPM_DEBUG8_WAIT_4_SOF                       (1L<<14)
02353 #define BNX2_RPM_DEBUG8_ALL_DONE                         (1L<<15)
02354 #define BNX2_RPM_DEBUG8_THBUF_ADDR                       (0x7fL<<16)
02355 #define BNX2_RPM_DEBUG8_BYTE_CTR                         (0xffL<<24)
02356 
02357 #define BNX2_RPM_DEBUG9                                 0x000019a8
02358 #define BNX2_RPM_DEBUG9_OUTFIFO_COUNT                    (0x7L<<0)
02359 #define BNX2_RPM_DEBUG9_RDE_ACPI_RDY                     (1L<<3)
02360 #define BNX2_RPM_DEBUG9_VLD_RD_ENTRY_CT                  (0x7L<<4)
02361 #define BNX2_RPM_DEBUG9_OUTFIFO_OVERRUN_OCCURRED         (1L<<28)
02362 #define BNX2_RPM_DEBUG9_INFIFO_OVERRUN_OCCURRED          (1L<<29)
02363 #define BNX2_RPM_DEBUG9_ACPI_MATCH_INT                   (1L<<30)
02364 #define BNX2_RPM_DEBUG9_ACPI_ENABLE_SYN                  (1L<<31)
02365 
02366 #define BNX2_RPM_ACPI_DBG_BUF_W00                       0x000019c0
02367 #define BNX2_RPM_ACPI_DBG_BUF_W01                       0x000019c4
02368 #define BNX2_RPM_ACPI_DBG_BUF_W02                       0x000019c8
02369 #define BNX2_RPM_ACPI_DBG_BUF_W03                       0x000019cc
02370 #define BNX2_RPM_ACPI_DBG_BUF_W10                       0x000019d0
02371 #define BNX2_RPM_ACPI_DBG_BUF_W11                       0x000019d4
02372 #define BNX2_RPM_ACPI_DBG_BUF_W12                       0x000019d8
02373 #define BNX2_RPM_ACPI_DBG_BUF_W13                       0x000019dc
02374 #define BNX2_RPM_ACPI_DBG_BUF_W20                       0x000019e0
02375 #define BNX2_RPM_ACPI_DBG_BUF_W21                       0x000019e4
02376 #define BNX2_RPM_ACPI_DBG_BUF_W22                       0x000019e8
02377 #define BNX2_RPM_ACPI_DBG_BUF_W23                       0x000019ec
02378 #define BNX2_RPM_ACPI_DBG_BUF_W30                       0x000019f0
02379 #define BNX2_RPM_ACPI_DBG_BUF_W31                       0x000019f4
02380 #define BNX2_RPM_ACPI_DBG_BUF_W32                       0x000019f8
02381 #define BNX2_RPM_ACPI_DBG_BUF_W33                       0x000019fc
02382 
02383 
02384 /*
02385  *  rbuf_reg definition
02386  *  offset: 0x200000
02387  */
02388 #define BNX2_RBUF_COMMAND                               0x00200000
02389 #define BNX2_RBUF_COMMAND_ENABLED                        (1L<<0)
02390 #define BNX2_RBUF_COMMAND_FREE_INIT                      (1L<<1)
02391 #define BNX2_RBUF_COMMAND_RAM_INIT                       (1L<<2)
02392 #define BNX2_RBUF_COMMAND_OVER_FREE                      (1L<<4)
02393 #define BNX2_RBUF_COMMAND_ALLOC_REQ                      (1L<<5)
02394 
02395 #define BNX2_RBUF_STATUS1                               0x00200004
02396 #define BNX2_RBUF_STATUS1_FREE_COUNT                     (0x3ffL<<0)
02397 
02398 #define BNX2_RBUF_STATUS2                               0x00200008
02399 #define BNX2_RBUF_STATUS2_FREE_TAIL                      (0x3ffL<<0)
02400 #define BNX2_RBUF_STATUS2_FREE_HEAD                      (0x3ffL<<16)
02401 
02402 #define BNX2_RBUF_CONFIG                                0x0020000c
02403 #define BNX2_RBUF_CONFIG_XOFF_TRIP                       (0x3ffL<<0)
02404 #define BNX2_RBUF_CONFIG_XON_TRIP                        (0x3ffL<<16)
02405 
02406 #define BNX2_RBUF_FW_BUF_ALLOC                          0x00200010
02407 #define BNX2_RBUF_FW_BUF_ALLOC_VALUE                     (0x1ffL<<7)
02408 
02409 #define BNX2_RBUF_FW_BUF_FREE                           0x00200014
02410 #define BNX2_RBUF_FW_BUF_FREE_COUNT                      (0x7fL<<0)
02411 #define BNX2_RBUF_FW_BUF_FREE_TAIL                       (0x1ffL<<7)
02412 #define BNX2_RBUF_FW_BUF_FREE_HEAD                       (0x1ffL<<16)
02413 
02414 #define BNX2_RBUF_FW_BUF_SEL                            0x00200018
02415 #define BNX2_RBUF_FW_BUF_SEL_COUNT                       (0x7fL<<0)
02416 #define BNX2_RBUF_FW_BUF_SEL_TAIL                        (0x1ffL<<7)
02417 #define BNX2_RBUF_FW_BUF_SEL_HEAD                        (0x1ffL<<16)
02418 
02419 #define BNX2_RBUF_CONFIG2                               0x0020001c
02420 #define BNX2_RBUF_CONFIG2_MAC_DROP_TRIP                  (0x3ffL<<0)
02421 #define BNX2_RBUF_CONFIG2_MAC_KEEP_TRIP                  (0x3ffL<<16)
02422 
02423 #define BNX2_RBUF_CONFIG3                               0x00200020
02424 #define BNX2_RBUF_CONFIG3_CU_DROP_TRIP                   (0x3ffL<<0)
02425 #define BNX2_RBUF_CONFIG3_CU_KEEP_TRIP                   (0x3ffL<<16)
02426 
02427 #define BNX2_RBUF_PKT_DATA                              0x00208000
02428 #define BNX2_RBUF_CLIST_DATA                            0x00210000
02429 #define BNX2_RBUF_BUF_DATA                              0x00220000
02430 
02431 
02432 /*
02433  *  rv2p_reg definition
02434  *  offset: 0x2800
02435  */
02436 #define BNX2_RV2P_COMMAND                               0x00002800
02437 #define BNX2_RV2P_COMMAND_ENABLED                        (1L<<0)
02438 #define BNX2_RV2P_COMMAND_PROC1_INTRPT                   (1L<<1)
02439 #define BNX2_RV2P_COMMAND_PROC2_INTRPT                   (1L<<2)
02440 #define BNX2_RV2P_COMMAND_ABORT0                         (1L<<4)
02441 #define BNX2_RV2P_COMMAND_ABORT1                         (1L<<5)
02442 #define BNX2_RV2P_COMMAND_ABORT2                         (1L<<6)
02443 #define BNX2_RV2P_COMMAND_ABORT3                         (1L<<7)
02444 #define BNX2_RV2P_COMMAND_ABORT4                         (1L<<8)
02445 #define BNX2_RV2P_COMMAND_ABORT5                         (1L<<9)
02446 #define BNX2_RV2P_COMMAND_PROC1_RESET                    (1L<<16)
02447 #define BNX2_RV2P_COMMAND_PROC2_RESET                    (1L<<17)
02448 #define BNX2_RV2P_COMMAND_CTXIF_RESET                    (1L<<18)
02449 
02450 #define BNX2_RV2P_STATUS                                0x00002804
02451 #define BNX2_RV2P_STATUS_ALWAYS_0                        (1L<<0)
02452 #define BNX2_RV2P_STATUS_RV2P_GEN_STAT0_CNT              (1L<<8)
02453 #define BNX2_RV2P_STATUS_RV2P_GEN_STAT1_CNT              (1L<<9)
02454 #define BNX2_RV2P_STATUS_RV2P_GEN_STAT2_CNT              (1L<<10)
02455 #define BNX2_RV2P_STATUS_RV2P_GEN_STAT3_CNT              (1L<<11)
02456 #define BNX2_RV2P_STATUS_RV2P_GEN_STAT4_CNT              (1L<<12)
02457 #define BNX2_RV2P_STATUS_RV2P_GEN_STAT5_CNT              (1L<<13)
02458 
02459 #define BNX2_RV2P_CONFIG                                0x00002808
02460 #define BNX2_RV2P_CONFIG_STALL_PROC1                     (1L<<0)
02461 #define BNX2_RV2P_CONFIG_STALL_PROC2                     (1L<<1)
02462 #define BNX2_RV2P_CONFIG_PROC1_STALL_ON_ABORT0           (1L<<8)
02463 #define BNX2_RV2P_CONFIG_PROC1_STALL_ON_ABORT1           (1L<<9)
02464 #define BNX2_RV2P_CONFIG_PROC1_STALL_ON_ABORT2           (1L<<10)
02465 #define BNX2_RV2P_CONFIG_PROC1_STALL_ON_ABORT3           (1L<<11)
02466 #define BNX2_RV2P_CONFIG_PROC1_STALL_ON_ABORT4           (1L<<12)
02467 #define BNX2_RV2P_CONFIG_PROC1_STALL_ON_ABORT5           (1L<<13)
02468 #define BNX2_RV2P_CONFIG_PROC2_STALL_ON_ABORT0           (1L<<16)
02469 #define BNX2_RV2P_CONFIG_PROC2_STALL_ON_ABORT1           (1L<<17)
02470 #define BNX2_RV2P_CONFIG_PROC2_STALL_ON_ABORT2           (1L<<18)
02471 #define BNX2_RV2P_CONFIG_PROC2_STALL_ON_ABORT3           (1L<<19)
02472 #define BNX2_RV2P_CONFIG_PROC2_STALL_ON_ABORT4           (1L<<20)
02473 #define BNX2_RV2P_CONFIG_PROC2_STALL_ON_ABORT5           (1L<<21)
02474 #define BNX2_RV2P_CONFIG_PAGE_SIZE                       (0xfL<<24)
02475 #define BNX2_RV2P_CONFIG_PAGE_SIZE_256                   (0L<<24)
02476 #define BNX2_RV2P_CONFIG_PAGE_SIZE_512                   (1L<<24)
02477 #define BNX2_RV2P_CONFIG_PAGE_SIZE_1K                    (2L<<24)
02478 #define BNX2_RV2P_CONFIG_PAGE_SIZE_2K                    (3L<<24)
02479 #define BNX2_RV2P_CONFIG_PAGE_SIZE_4K                    (4L<<24)
02480 #define BNX2_RV2P_CONFIG_PAGE_SIZE_8K                    (5L<<24)
02481 #define BNX2_RV2P_CONFIG_PAGE_SIZE_16K                   (6L<<24)
02482 #define BNX2_RV2P_CONFIG_PAGE_SIZE_32K                   (7L<<24)
02483 #define BNX2_RV2P_CONFIG_PAGE_SIZE_64K                   (8L<<24)
02484 #define BNX2_RV2P_CONFIG_PAGE_SIZE_128K                  (9L<<24)
02485 #define BNX2_RV2P_CONFIG_PAGE_SIZE_256K                  (10L<<24)
02486 #define BNX2_RV2P_CONFIG_PAGE_SIZE_512K                  (11L<<24)
02487 #define BNX2_RV2P_CONFIG_PAGE_SIZE_1M                    (12L<<24)
02488 
02489 #define BNX2_RV2P_GEN_BFR_ADDR_0                        0x00002810
02490 #define BNX2_RV2P_GEN_BFR_ADDR_0_VALUE                   (0xffffL<<16)
02491 
02492 #define BNX2_RV2P_GEN_BFR_ADDR_1                        0x00002814
02493 #define BNX2_RV2P_GEN_BFR_ADDR_1_VALUE                   (0xffffL<<16)
02494 
02495 #define BNX2_RV2P_GEN_BFR_ADDR_2                        0x00002818
02496 #define BNX2_RV2P_GEN_BFR_ADDR_2_VALUE                   (0xffffL<<16)
02497 
02498 #define BNX2_RV2P_GEN_BFR_ADDR_3                        0x0000281c
02499 #define BNX2_RV2P_GEN_BFR_ADDR_3_VALUE                   (0xffffL<<16)
02500 
02501 #define BNX2_RV2P_INSTR_HIGH                            0x00002830
02502 #define BNX2_RV2P_INSTR_HIGH_HIGH                        (0x1fL<<0)
02503 
02504 #define BNX2_RV2P_INSTR_LOW                             0x00002834
02505 #define BNX2_RV2P_PROC1_ADDR_CMD                        0x00002838
02506 #define BNX2_RV2P_PROC1_ADDR_CMD_ADD                     (0x3ffL<<0)
02507 #define BNX2_RV2P_PROC1_ADDR_CMD_RDWR                    (1L<<31)
02508 
02509 #define BNX2_RV2P_PROC2_ADDR_CMD                        0x0000283c
02510 #define BNX2_RV2P_PROC2_ADDR_CMD_ADD                     (0x3ffL<<0)
02511 #define BNX2_RV2P_PROC2_ADDR_CMD_RDWR                    (1L<<31)
02512 
02513 #define BNX2_RV2P_PROC1_GRC_DEBUG                       0x00002840
02514 #define BNX2_RV2P_PROC2_GRC_DEBUG                       0x00002844
02515 #define BNX2_RV2P_GRC_PROC_DEBUG                        0x00002848
02516 #define BNX2_RV2P_DEBUG_VECT_PEEK                       0x0000284c
02517 #define BNX2_RV2P_DEBUG_VECT_PEEK_1_VALUE                (0x7ffL<<0)
02518 #define BNX2_RV2P_DEBUG_VECT_PEEK_1_PEEK_EN              (1L<<11)
02519 #define BNX2_RV2P_DEBUG_VECT_PEEK_1_SEL                  (0xfL<<12)
02520 #define BNX2_RV2P_DEBUG_VECT_PEEK_2_VALUE                (0x7ffL<<16)
02521 #define BNX2_RV2P_DEBUG_VECT_PEEK_2_PEEK_EN              (1L<<27)
02522 #define BNX2_RV2P_DEBUG_VECT_PEEK_2_SEL                  (0xfL<<28)
02523 
02524 #define BNX2_RV2P_PFTQ_DATA                             0x00002b40
02525 #define BNX2_RV2P_PFTQ_CMD                              0x00002b78
02526 #define BNX2_RV2P_PFTQ_CMD_OFFSET                        (0x3ffL<<0)
02527 #define BNX2_RV2P_PFTQ_CMD_WR_TOP                        (1L<<10)
02528 #define BNX2_RV2P_PFTQ_CMD_WR_TOP_0                      (0L<<10)
02529 #define BNX2_RV2P_PFTQ_CMD_WR_TOP_1                      (1L<<10)
02530 #define BNX2_RV2P_PFTQ_CMD_SFT_RESET                     (1L<<25)
02531 #define BNX2_RV2P_PFTQ_CMD_RD_DATA                       (1L<<26)
02532 #define BNX2_RV2P_PFTQ_CMD_ADD_INTERVEN                  (1L<<27)
02533 #define BNX2_RV2P_PFTQ_CMD_ADD_DATA                      (1L<<28)
02534 #define BNX2_RV2P_PFTQ_CMD_INTERVENE_CLR                 (1L<<29)
02535 #define BNX2_RV2P_PFTQ_CMD_POP                           (1L<<30)
02536 #define BNX2_RV2P_PFTQ_CMD_BUSY                          (1L<<31)
02537 
02538 #define BNX2_RV2P_PFTQ_CTL                              0x00002b7c
02539 #define BNX2_RV2P_PFTQ_CTL_INTERVENE                     (1L<<0)
02540 #define BNX2_RV2P_PFTQ_CTL_OVERFLOW                      (1L<<1)
02541 #define BNX2_RV2P_PFTQ_CTL_FORCE_INTERVENE               (1L<<2)
02542 #define BNX2_RV2P_PFTQ_CTL_MAX_DEPTH                     (0x3ffL<<12)
02543 #define BNX2_RV2P_PFTQ_CTL_CUR_DEPTH                     (0x3ffL<<22)
02544 
02545 #define BNX2_RV2P_TFTQ_DATA                             0x00002b80
02546 #define BNX2_RV2P_TFTQ_CMD                              0x00002bb8
02547 #define BNX2_RV2P_TFTQ_CMD_OFFSET                        (0x3ffL<<0)
02548 #define BNX2_RV2P_TFTQ_CMD_WR_TOP                        (1L<<10)
02549 #define BNX2_RV2P_TFTQ_CMD_WR_TOP_0                      (0L<<10)
02550 #define BNX2_RV2P_TFTQ_CMD_WR_TOP_1                      (1L<<10)
02551 #define BNX2_RV2P_TFTQ_CMD_SFT_RESET                     (1L<<25)
02552 #define BNX2_RV2P_TFTQ_CMD_RD_DATA                       (1L<<26)
02553 #define BNX2_RV2P_TFTQ_CMD_ADD_INTERVEN                  (1L<<27)
02554 #define BNX2_RV2P_TFTQ_CMD_ADD_DATA                      (1L<<28)
02555 #define BNX2_RV2P_TFTQ_CMD_INTERVENE_CLR                 (1L<<29)
02556 #define BNX2_RV2P_TFTQ_CMD_POP                           (1L<<30)
02557 #define BNX2_RV2P_TFTQ_CMD_BUSY                          (1L<<31)
02558 
02559 #define BNX2_RV2P_TFTQ_CTL                              0x00002bbc
02560 #define BNX2_RV2P_TFTQ_CTL_INTERVENE                     (1L<<0)
02561 #define BNX2_RV2P_TFTQ_CTL_OVERFLOW                      (1L<<1)
02562 #define BNX2_RV2P_TFTQ_CTL_FORCE_INTERVENE               (1L<<2)
02563 #define BNX2_RV2P_TFTQ_CTL_MAX_DEPTH                     (0x3ffL<<12)
02564 #define BNX2_RV2P_TFTQ_CTL_CUR_DEPTH                     (0x3ffL<<22)
02565 
02566 #define BNX2_RV2P_MFTQ_DATA                             0x00002bc0
02567 #define BNX2_RV2P_MFTQ_CMD                              0x00002bf8
02568 #define BNX2_RV2P_MFTQ_CMD_OFFSET                        (0x3ffL<<0)
02569 #define BNX2_RV2P_MFTQ_CMD_WR_TOP                        (1L<<10)
02570 #define BNX2_RV2P_MFTQ_CMD_WR_TOP_0                      (0L<<10)
02571 #define BNX2_RV2P_MFTQ_CMD_WR_TOP_1                      (1L<<10)
02572 #define BNX2_RV2P_MFTQ_CMD_SFT_RESET                     (1L<<25)
02573 #define BNX2_RV2P_MFTQ_CMD_RD_DATA                       (1L<<26)
02574 #define BNX2_RV2P_MFTQ_CMD_ADD_INTERVEN                  (1L<<27)
02575 #define BNX2_RV2P_MFTQ_CMD_ADD_DATA                      (1L<<28)
02576 #define BNX2_RV2P_MFTQ_CMD_INTERVENE_CLR                 (1L<<29)
02577 #define BNX2_RV2P_MFTQ_CMD_POP                           (1L<<30)
02578 #define BNX2_RV2P_MFTQ_CMD_BUSY                          (1L<<31)
02579 
02580 #define BNX2_RV2P_MFTQ_CTL                              0x00002bfc
02581 #define BNX2_RV2P_MFTQ_CTL_INTERVENE                     (1L<<0)
02582 #define BNX2_RV2P_MFTQ_CTL_OVERFLOW                      (1L<<1)
02583 #define BNX2_RV2P_MFTQ_CTL_FORCE_INTERVENE               (1L<<2)
02584 #define BNX2_RV2P_MFTQ_CTL_MAX_DEPTH                     (0x3ffL<<12)
02585 #define BNX2_RV2P_MFTQ_CTL_CUR_DEPTH                     (0x3ffL<<22)
02586 
02587 
02588 
02589 /*
02590  *  mq_reg definition
02591  *  offset: 0x3c00
02592  */
02593 #define BNX2_MQ_COMMAND                                 0x00003c00
02594 #define BNX2_MQ_COMMAND_ENABLED                          (1L<<0)
02595 #define BNX2_MQ_COMMAND_OVERFLOW                         (1L<<4)
02596 #define BNX2_MQ_COMMAND_WR_ERROR                         (1L<<5)
02597 #define BNX2_MQ_COMMAND_RD_ERROR                         (1L<<6)
02598 
02599 #define BNX2_MQ_STATUS                                  0x00003c04
02600 #define BNX2_MQ_STATUS_CTX_ACCESS_STAT                   (1L<<16)
02601 #define BNX2_MQ_STATUS_CTX_ACCESS64_STAT                 (1L<<17)
02602 #define BNX2_MQ_STATUS_PCI_STALL_STAT                    (1L<<18)
02603 
02604 #define BNX2_MQ_CONFIG                                  0x00003c08
02605 #define BNX2_MQ_CONFIG_TX_HIGH_PRI                       (1L<<0)
02606 #define BNX2_MQ_CONFIG_HALT_DIS                          (1L<<1)
02607 #define BNX2_MQ_CONFIG_KNL_BYP_BLK_SIZE                  (0x7L<<4)
02608 #define BNX2_MQ_CONFIG_KNL_BYP_BLK_SIZE_256              (0L<<4)
02609 #define BNX2_MQ_CONFIG_KNL_BYP_BLK_SIZE_512              (1L<<4)
02610 #define BNX2_MQ_CONFIG_KNL_BYP_BLK_SIZE_1K               (2L<<4)
02611 #define BNX2_MQ_CONFIG_KNL_BYP_BLK_SIZE_2K               (3L<<4)
02612 #define BNX2_MQ_CONFIG_KNL_BYP_BLK_SIZE_4K               (4L<<4)
02613 #define BNX2_MQ_CONFIG_MAX_DEPTH                         (0x7fL<<8)
02614 #define BNX2_MQ_CONFIG_CUR_DEPTH                         (0x7fL<<20)
02615 
02616 #define BNX2_MQ_ENQUEUE1                                0x00003c0c
02617 #define BNX2_MQ_ENQUEUE1_OFFSET                          (0x3fL<<2)
02618 #define BNX2_MQ_ENQUEUE1_CID                             (0x3fffL<<8)
02619 #define BNX2_MQ_ENQUEUE1_BYTE_MASK                       (0xfL<<24)
02620 #define BNX2_MQ_ENQUEUE1_KNL_MODE                        (1L<<28)
02621 
02622 #define BNX2_MQ_ENQUEUE2                                0x00003c10
02623 #define BNX2_MQ_BAD_WR_ADDR                             0x00003c14
02624 #define BNX2_MQ_BAD_RD_ADDR                             0x00003c18
02625 #define BNX2_MQ_KNL_BYP_WIND_START                      0x00003c1c
02626 #define BNX2_MQ_KNL_BYP_WIND_START_VALUE                 (0xfffffL<<12)
02627 
02628 #define BNX2_MQ_KNL_WIND_END                            0x00003c20
02629 #define BNX2_MQ_KNL_WIND_END_VALUE                       (0xffffffL<<8)
02630 
02631 #define BNX2_MQ_KNL_WRITE_MASK1                         0x00003c24
02632 #define BNX2_MQ_KNL_TX_MASK1                            0x00003c28
02633 #define BNX2_MQ_KNL_CMD_MASK1                           0x00003c2c
02634 #define BNX2_MQ_KNL_COND_ENQUEUE_MASK1                  0x00003c30
02635 #define BNX2_MQ_KNL_RX_V2P_MASK1                        0x00003c34
02636 #define BNX2_MQ_KNL_WRITE_MASK2                         0x00003c38
02637 #define BNX2_MQ_KNL_TX_MASK2                            0x00003c3c
02638 #define BNX2_MQ_KNL_CMD_MASK2                           0x00003c40
02639 #define BNX2_MQ_KNL_COND_ENQUEUE_MASK2                  0x00003c44
02640 #define BNX2_MQ_KNL_RX_V2P_MASK2                        0x00003c48
02641 #define BNX2_MQ_KNL_BYP_WRITE_MASK1                     0x00003c4c
02642 #define BNX2_MQ_KNL_BYP_TX_MASK1                        0x00003c50
02643 #define BNX2_MQ_KNL_BYP_CMD_MASK1                       0x00003c54
02644 #define BNX2_MQ_KNL_BYP_COND_ENQUEUE_MASK1              0x00003c58
02645 #define BNX2_MQ_KNL_BYP_RX_V2P_MASK1                    0x00003c5c
02646 #define BNX2_MQ_KNL_BYP_WRITE_MASK2                     0x00003c60
02647 #define BNX2_MQ_KNL_BYP_TX_MASK2                        0x00003c64
02648 #define BNX2_MQ_KNL_BYP_CMD_MASK2                       0x00003c68
02649 #define BNX2_MQ_KNL_BYP_COND_ENQUEUE_MASK2              0x00003c6c
02650 #define BNX2_MQ_KNL_BYP_RX_V2P_MASK2                    0x00003c70
02651 #define BNX2_MQ_MEM_WR_ADDR                             0x00003c74
02652 #define BNX2_MQ_MEM_WR_ADDR_VALUE                        (0x3fL<<0)
02653 
02654 #define BNX2_MQ_MEM_WR_DATA0                            0x00003c78
02655 #define BNX2_MQ_MEM_WR_DATA0_VALUE                       (0xffffffffL<<0)
02656 
02657 #define BNX2_MQ_MEM_WR_DATA1                            0x00003c7c
02658 #define BNX2_MQ_MEM_WR_DATA1_VALUE                       (0xffffffffL<<0)
02659 
02660 #define BNX2_MQ_MEM_WR_DATA2                            0x00003c80
02661 #define BNX2_MQ_MEM_WR_DATA2_VALUE                       (0x3fffffffL<<0)
02662 
02663 #define BNX2_MQ_MEM_RD_ADDR                             0x00003c84
02664 #define BNX2_MQ_MEM_RD_ADDR_VALUE                        (0x3fL<<0)
02665 
02666 #define BNX2_MQ_MEM_RD_DATA0                            0x00003c88
02667 #define BNX2_MQ_MEM_RD_DATA0_VALUE                       (0xffffffffL<<0)
02668 
02669 #define BNX2_MQ_MEM_RD_DATA1                            0x00003c8c
02670 #define BNX2_MQ_MEM_RD_DATA1_VALUE                       (0xffffffffL<<0)
02671 
02672 #define BNX2_MQ_MEM_RD_DATA2                            0x00003c90
02673 #define BNX2_MQ_MEM_RD_DATA2_VALUE                       (0x3fffffffL<<0)
02674 
02675 
02676 
02677 /*
02678  *  tbdr_reg definition
02679  *  offset: 0x5000
02680  */
02681 #define BNX2_TBDR_COMMAND                               0x00005000
02682 #define BNX2_TBDR_COMMAND_ENABLE                         (1L<<0)
02683 #define BNX2_TBDR_COMMAND_SOFT_RST                       (1L<<1)
02684 #define BNX2_TBDR_COMMAND_MSTR_ABORT                     (1L<<4)
02685 
02686 #define BNX2_TBDR_STATUS                                0x00005004
02687 #define BNX2_TBDR_STATUS_DMA_WAIT                        (1L<<0)
02688 #define BNX2_TBDR_STATUS_FTQ_WAIT                        (1L<<1)
02689 #define BNX2_TBDR_STATUS_FIFO_OVERFLOW                   (1L<<2)
02690 #define BNX2_TBDR_STATUS_FIFO_UNDERFLOW                  (1L<<3)
02691 #define BNX2_TBDR_STATUS_SEARCHMISS_ERROR                (1L<<4)
02692 #define BNX2_TBDR_STATUS_FTQ_ENTRY_CNT                   (1L<<5)
02693 #define BNX2_TBDR_STATUS_BURST_CNT                       (1L<<6)
02694 
02695 #define BNX2_TBDR_CONFIG                                0x00005008
02696 #define BNX2_TBDR_CONFIG_MAX_BDS                         (0xffL<<0)
02697 #define BNX2_TBDR_CONFIG_SWAP_MODE                       (1L<<8)
02698 #define BNX2_TBDR_CONFIG_PRIORITY                        (1L<<9)
02699 #define BNX2_TBDR_CONFIG_CACHE_NEXT_PAGE_PTRS            (1L<<10)
02700 #define BNX2_TBDR_CONFIG_PAGE_SIZE                       (0xfL<<24)
02701 #define BNX2_TBDR_CONFIG_PAGE_SIZE_256                   (0L<<24)
02702 #define BNX2_TBDR_CONFIG_PAGE_SIZE_512                   (1L<<24)
02703 #define BNX2_TBDR_CONFIG_PAGE_SIZE_1K                    (2L<<24)
02704 #define BNX2_TBDR_CONFIG_PAGE_SIZE_2K                    (3L<<24)
02705 #define BNX2_TBDR_CONFIG_PAGE_SIZE_4K                    (4L<<24)
02706 #define BNX2_TBDR_CONFIG_PAGE_SIZE_8K                    (5L<<24)
02707 #define BNX2_TBDR_CONFIG_PAGE_SIZE_16K                   (6L<<24)
02708 #define BNX2_TBDR_CONFIG_PAGE_SIZE_32K                   (7L<<24)
02709 #define BNX2_TBDR_CONFIG_PAGE_SIZE_64K                   (8L<<24)
02710 #define BNX2_TBDR_CONFIG_PAGE_SIZE_128K                  (9L<<24)
02711 #define BNX2_TBDR_CONFIG_PAGE_SIZE_256K                  (10L<<24)
02712 #define BNX2_TBDR_CONFIG_PAGE_SIZE_512K                  (11L<<24)
02713 #define BNX2_TBDR_CONFIG_PAGE_SIZE_1M                    (12L<<24)
02714 
02715 #define BNX2_TBDR_DEBUG_VECT_PEEK                       0x0000500c
02716 #define BNX2_TBDR_DEBUG_VECT_PEEK_1_VALUE                (0x7ffL<<0)
02717 #define BNX2_TBDR_DEBUG_VECT_PEEK_1_PEEK_EN              (1L<<11)
02718 #define BNX2_TBDR_DEBUG_VECT_PEEK_1_SEL                  (0xfL<<12)
02719 #define BNX2_TBDR_DEBUG_VECT_PEEK_2_VALUE                (0x7ffL<<16)
02720 #define BNX2_TBDR_DEBUG_VECT_PEEK_2_PEEK_EN              (1L<<27)
02721 #define BNX2_TBDR_DEBUG_VECT_PEEK_2_SEL                  (0xfL<<28)
02722 
02723 #define BNX2_TBDR_FTQ_DATA                              0x000053c0
02724 #define BNX2_TBDR_FTQ_CMD                               0x000053f8
02725 #define BNX2_TBDR_FTQ_CMD_OFFSET                         (0x3ffL<<0)
02726 #define BNX2_TBDR_FTQ_CMD_WR_TOP                         (1L<<10)
02727 #define BNX2_TBDR_FTQ_CMD_WR_TOP_0                       (0L<<10)
02728 #define BNX2_TBDR_FTQ_CMD_WR_TOP_1                       (1L<<10)
02729 #define BNX2_TBDR_FTQ_CMD_SFT_RESET                      (1L<<25)
02730 #define BNX2_TBDR_FTQ_CMD_RD_DATA                        (1L<<26)
02731 #define BNX2_TBDR_FTQ_CMD_ADD_INTERVEN                   (1L<<27)
02732 #define BNX2_TBDR_FTQ_CMD_ADD_DATA                       (1L<<28)
02733 #define BNX2_TBDR_FTQ_CMD_INTERVENE_CLR                  (1L<<29)
02734 #define BNX2_TBDR_FTQ_CMD_POP                            (1L<<30)
02735 #define BNX2_TBDR_FTQ_CMD_BUSY                           (1L<<31)
02736 
02737 #define BNX2_TBDR_FTQ_CTL                               0x000053fc
02738 #define BNX2_TBDR_FTQ_CTL_INTERVENE                      (1L<<0)
02739 #define BNX2_TBDR_FTQ_CTL_OVERFLOW                       (1L<<1)
02740 #define BNX2_TBDR_FTQ_CTL_FORCE_INTERVENE                (1L<<2)
02741 #define BNX2_TBDR_FTQ_CTL_MAX_DEPTH                      (0x3ffL<<12)
02742 #define BNX2_TBDR_FTQ_CTL_CUR_DEPTH                      (0x3ffL<<22)
02743 
02744 
02745 
02746 /*
02747  *  tdma_reg definition
02748  *  offset: 0x5c00
02749  */
02750 #define BNX2_TDMA_COMMAND                               0x00005c00
02751 #define BNX2_TDMA_COMMAND_ENABLED                        (1L<<0)
02752 #define BNX2_TDMA_COMMAND_MASTER_ABORT                   (1L<<4)
02753 #define BNX2_TDMA_COMMAND_BAD_L2_LENGTH_ABORT            (1L<<7)
02754 
02755 #define BNX2_TDMA_STATUS                                0x00005c04
02756 #define BNX2_TDMA_STATUS_DMA_WAIT                        (1L<<0)
02757 #define BNX2_TDMA_STATUS_PAYLOAD_WAIT                    (1L<<1)
02758 #define BNX2_TDMA_STATUS_PATCH_FTQ_WAIT                  (1L<<2)
02759 #define BNX2_TDMA_STATUS_LOCK_WAIT                       (1L<<3)
02760 #define BNX2_TDMA_STATUS_FTQ_ENTRY_CNT                   (1L<<16)
02761 #define BNX2_TDMA_STATUS_BURST_CNT                       (1L<<17)
02762 
02763 #define BNX2_TDMA_CONFIG                                0x00005c08
02764 #define BNX2_TDMA_CONFIG_ONE_DMA                         (1L<<0)
02765 #define BNX2_TDMA_CONFIG_ONE_RECORD                      (1L<<1)
02766 #define BNX2_TDMA_CONFIG_LIMIT_SZ                        (0xfL<<4)
02767 #define BNX2_TDMA_CONFIG_LIMIT_SZ_64                     (0L<<4)
02768 #define BNX2_TDMA_CONFIG_LIMIT_SZ_128                    (0x4L<<4)
02769 #define BNX2_TDMA_CONFIG_LIMIT_SZ_256                    (0x6L<<4)
02770 #define BNX2_TDMA_CONFIG_LIMIT_SZ_512                    (0x8L<<4)
02771 #define BNX2_TDMA_CONFIG_LINE_SZ                         (0xfL<<8)
02772 #define BNX2_TDMA_CONFIG_LINE_SZ_64                      (0L<<8)
02773 #define BNX2_TDMA_CONFIG_LINE_SZ_128                     (4L<<8)
02774 #define BNX2_TDMA_CONFIG_LINE_SZ_256                     (6L<<8)
02775 #define BNX2_TDMA_CONFIG_LINE_SZ_512                     (8L<<8)
02776 #define BNX2_TDMA_CONFIG_ALIGN_ENA                       (1L<<15)
02777 #define BNX2_TDMA_CONFIG_CHK_L2_BD                       (1L<<16)
02778 #define BNX2_TDMA_CONFIG_FIFO_CMP                        (0xfL<<20)
02779 
02780 #define BNX2_TDMA_PAYLOAD_PROD                          0x00005c0c
02781 #define BNX2_TDMA_PAYLOAD_PROD_VALUE                     (0x1fffL<<3)
02782 
02783 #define BNX2_TDMA_DBG_WATCHDOG                          0x00005c10
02784 #define BNX2_TDMA_DBG_TRIGGER                           0x00005c14
02785 #define BNX2_TDMA_DMAD_FSM                              0x00005c80
02786 #define BNX2_TDMA_DMAD_FSM_BD_INVLD                      (1L<<0)
02787 #define BNX2_TDMA_DMAD_FSM_PUSH                          (0xfL<<4)
02788 #define BNX2_TDMA_DMAD_FSM_ARB_TBDC                      (0x3L<<8)
02789 #define BNX2_TDMA_DMAD_FSM_ARB_CTX                       (1L<<12)
02790 #define BNX2_TDMA_DMAD_FSM_DR_INTF                       (1L<<16)
02791 #define BNX2_TDMA_DMAD_FSM_DMAD                          (0x7L<<20)
02792 #define BNX2_TDMA_DMAD_FSM_BD                            (0xfL<<24)
02793 
02794 #define BNX2_TDMA_DMAD_STATUS                           0x00005c84
02795 #define BNX2_TDMA_DMAD_STATUS_RHOLD_PUSH_ENTRY           (0x3L<<0)
02796 #define BNX2_TDMA_DMAD_STATUS_RHOLD_DMAD_ENTRY           (0x3L<<4)
02797 #define BNX2_TDMA_DMAD_STATUS_RHOLD_BD_ENTRY             (0x3L<<8)
02798 #define BNX2_TDMA_DMAD_STATUS_IFTQ_ENUM                  (0xfL<<12)
02799 
02800 #define BNX2_TDMA_DR_INTF_FSM                           0x00005c88
02801 #define BNX2_TDMA_DR_INTF_FSM_L2_COMP                    (0x3L<<0)
02802 #define BNX2_TDMA_DR_INTF_FSM_TPATQ                      (0x7L<<4)
02803 #define BNX2_TDMA_DR_INTF_FSM_TPBUF                      (0x3L<<8)
02804 #define BNX2_TDMA_DR_INTF_FSM_DR_BUF                     (0x7L<<12)
02805 #define BNX2_TDMA_DR_INTF_FSM_DMAD                       (0x7L<<16)
02806 
02807 #define BNX2_TDMA_DR_INTF_STATUS                        0x00005c8c
02808 #define BNX2_TDMA_DR_INTF_STATUS_HOLE_PHASE              (0x7L<<0)
02809 #define BNX2_TDMA_DR_INTF_STATUS_DATA_AVAIL              (0x3L<<4)
02810 #define BNX2_TDMA_DR_INTF_STATUS_SHIFT_ADDR              (0x7L<<8)
02811 #define BNX2_TDMA_DR_INTF_STATUS_NXT_PNTR                (0xfL<<12)
02812 #define BNX2_TDMA_DR_INTF_STATUS_BYTE_COUNT              (0x7L<<16)
02813 
02814 #define BNX2_TDMA_FTQ_DATA                              0x00005fc0
02815 #define BNX2_TDMA_FTQ_CMD                               0x00005ff8
02816 #define BNX2_TDMA_FTQ_CMD_OFFSET                         (0x3ffL<<0)
02817 #define BNX2_TDMA_FTQ_CMD_WR_TOP                         (1L<<10)
02818 #define BNX2_TDMA_FTQ_CMD_WR_TOP_0                       (0L<<10)
02819 #define BNX2_TDMA_FTQ_CMD_WR_TOP_1                       (1L<<10)
02820 #define BNX2_TDMA_FTQ_CMD_SFT_RESET                      (1L<<25)
02821 #define BNX2_TDMA_FTQ_CMD_RD_DATA                        (1L<<26)
02822 #define BNX2_TDMA_FTQ_CMD_ADD_INTERVEN                   (1L<<27)
02823 #define BNX2_TDMA_FTQ_CMD_ADD_DATA                       (1L<<28)
02824 #define BNX2_TDMA_FTQ_CMD_INTERVENE_CLR                  (1L<<29)
02825 #define BNX2_TDMA_FTQ_CMD_POP                            (1L<<30)
02826 #define BNX2_TDMA_FTQ_CMD_BUSY                           (1L<<31)
02827 
02828 #define BNX2_TDMA_FTQ_CTL                               0x00005ffc
02829 #define BNX2_TDMA_FTQ_CTL_INTERVENE                      (1L<<0)
02830 #define BNX2_TDMA_FTQ_CTL_OVERFLOW                       (1L<<1)
02831 #define BNX2_TDMA_FTQ_CTL_FORCE_INTERVENE                (1L<<2)
02832 #define BNX2_TDMA_FTQ_CTL_MAX_DEPTH                      (0x3ffL<<12)
02833 #define BNX2_TDMA_FTQ_CTL_CUR_DEPTH                      (0x3ffL<<22)
02834 
02835 
02836 
02837 /*
02838  *  hc_reg definition
02839  *  offset: 0x6800
02840  */
02841 #define BNX2_HC_COMMAND                                 0x00006800
02842 #define BNX2_HC_COMMAND_ENABLE                           (1L<<0)
02843 #define BNX2_HC_COMMAND_SKIP_ABORT                       (1L<<4)
02844 #define BNX2_HC_COMMAND_COAL_NOW                         (1L<<16)
02845 #define BNX2_HC_COMMAND_COAL_NOW_WO_INT                  (1L<<17)
02846 #define BNX2_HC_COMMAND_STATS_NOW                        (1L<<18)
02847 #define BNX2_HC_COMMAND_FORCE_INT                        (0x3L<<19)
02848 #define BNX2_HC_COMMAND_FORCE_INT_NULL                   (0L<<19)
02849 #define BNX2_HC_COMMAND_FORCE_INT_HIGH                   (1L<<19)
02850 #define BNX2_HC_COMMAND_FORCE_INT_LOW                    (2L<<19)
02851 #define BNX2_HC_COMMAND_FORCE_INT_FREE                   (3L<<19)
02852 #define BNX2_HC_COMMAND_CLR_STAT_NOW                     (1L<<21)
02853 
02854 #define BNX2_HC_STATUS                                  0x00006804
02855 #define BNX2_HC_STATUS_MASTER_ABORT                      (1L<<0)
02856 #define BNX2_HC_STATUS_PARITY_ERROR_STATE                (1L<<1)
02857 #define BNX2_HC_STATUS_PCI_CLK_CNT_STAT                  (1L<<16)
02858 #define BNX2_HC_STATUS_CORE_CLK_CNT_STAT                 (1L<<17)
02859 #define BNX2_HC_STATUS_NUM_STATUS_BLOCKS_STAT            (1L<<18)
02860 #define BNX2_HC_STATUS_NUM_INT_GEN_STAT                  (1L<<19)
02861 #define BNX2_HC_STATUS_NUM_INT_MBOX_WR_STAT              (1L<<20)
02862 #define BNX2_HC_STATUS_CORE_CLKS_TO_HW_INTACK_STAT       (1L<<23)
02863 #define BNX2_HC_STATUS_CORE_CLKS_TO_SW_INTACK_STAT       (1L<<24)
02864 #define BNX2_HC_STATUS_CORE_CLKS_DURING_SW_INTACK_STAT   (1L<<25)
02865 
02866 #define BNX2_HC_CONFIG                                  0x00006808
02867 #define BNX2_HC_CONFIG_COLLECT_STATS                     (1L<<0)
02868 #define BNX2_HC_CONFIG_RX_TMR_MODE                       (1L<<1)
02869 #define BNX2_HC_CONFIG_TX_TMR_MODE                       (1L<<2)
02870 #define BNX2_HC_CONFIG_COM_TMR_MODE                      (1L<<3)
02871 #define BNX2_HC_CONFIG_CMD_TMR_MODE                      (1L<<4)
02872 #define BNX2_HC_CONFIG_STATISTIC_PRIORITY                (1L<<5)
02873 #define BNX2_HC_CONFIG_STATUS_PRIORITY                   (1L<<6)
02874 #define BNX2_HC_CONFIG_STAT_MEM_ADDR                     (0xffL<<8)
02875 
02876 #define BNX2_HC_ATTN_BITS_ENABLE                        0x0000680c
02877 #define BNX2_HC_STATUS_ADDR_L                           0x00006810
02878 #define BNX2_HC_STATUS_ADDR_H                           0x00006814
02879 #define BNX2_HC_STATISTICS_ADDR_L                       0x00006818
02880 #define BNX2_HC_STATISTICS_ADDR_H                       0x0000681c
02881 #define BNX2_HC_TX_QUICK_CONS_TRIP                      0x00006820
02882 #define BNX2_HC_TX_QUICK_CONS_TRIP_VALUE                 (0xffL<<0)
02883 #define BNX2_HC_TX_QUICK_CONS_TRIP_INT                   (0xffL<<16)
02884 
02885 #define BNX2_HC_COMP_PROD_TRIP                          0x00006824
02886 #define BNX2_HC_COMP_PROD_TRIP_VALUE                     (0xffL<<0)
02887 #define BNX2_HC_COMP_PROD_TRIP_INT                       (0xffL<<16)
02888 
02889 #define BNX2_HC_RX_QUICK_CONS_TRIP                      0x00006828
02890 #define BNX2_HC_RX_QUICK_CONS_TRIP_VALUE                 (0xffL<<0)
02891 #define BNX2_HC_RX_QUICK_CONS_TRIP_INT                   (0xffL<<16)
02892 
02893 #define BNX2_HC_RX_TICKS                                0x0000682c
02894 #define BNX2_HC_RX_TICKS_VALUE                           (0x3ffL<<0)
02895 #define BNX2_HC_RX_TICKS_INT                             (0x3ffL<<16)
02896 
02897 #define BNX2_HC_TX_TICKS                                0x00006830
02898 #define BNX2_HC_TX_TICKS_VALUE                           (0x3ffL<<0)
02899 #define BNX2_HC_TX_TICKS_INT                             (0x3ffL<<16)
02900 
02901 #define BNX2_HC_COM_TICKS                               0x00006834
02902 #define BNX2_HC_COM_TICKS_VALUE                          (0x3ffL<<0)
02903 #define BNX2_HC_COM_TICKS_INT                            (0x3ffL<<16)
02904 
02905 #define BNX2_HC_CMD_TICKS                               0x00006838
02906 #define BNX2_HC_CMD_TICKS_VALUE                          (0x3ffL<<0)
02907 #define BNX2_HC_CMD_TICKS_INT                            (0x3ffL<<16)
02908 
02909 #define BNX2_HC_PERIODIC_TICKS                          0x0000683c
02910 #define BNX2_HC_PERIODIC_TICKS_HC_PERIODIC_TICKS         (0xffffL<<0)
02911 
02912 #define BNX2_HC_STAT_COLLECT_TICKS                      0x00006840
02913 #define BNX2_HC_STAT_COLLECT_TICKS_HC_STAT_COLL_TICKS    (0xffL<<4)
02914 
02915 #define BNX2_HC_STATS_TICKS                             0x00006844
02916 #define BNX2_HC_STATS_TICKS_HC_STAT_TICKS                (0xffffL<<8)
02917 
02918 #define BNX2_HC_STAT_MEM_DATA                           0x0000684c
02919 #define BNX2_HC_STAT_GEN_SEL_0                          0x00006850
02920 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0                 (0x7fL<<0)
02921 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT0       (0L<<0)
02922 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT1       (1L<<0)
02923 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT2       (2L<<0)
02924 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT3       (3L<<0)
02925 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT4       (4L<<0)
02926 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT5       (5L<<0)
02927 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT6       (6L<<0)
02928 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT7       (7L<<0)
02929 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT8       (8L<<0)
02930 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT9       (9L<<0)
02931 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT10      (10L<<0)
02932 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT11      (11L<<0)
02933 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TXP_STAT0       (12L<<0)
02934 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TXP_STAT1       (13L<<0)
02935 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TXP_STAT2       (14L<<0)
02936 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TXP_STAT3       (15L<<0)
02937 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TXP_STAT4       (16L<<0)
02938 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TXP_STAT5       (17L<<0)
02939 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TXP_STAT6       (18L<<0)
02940 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TXP_STAT7       (19L<<0)
02941 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT0       (20L<<0)
02942 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT1       (21L<<0)
02943 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT2       (22L<<0)
02944 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT3       (23L<<0)
02945 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT4       (24L<<0)
02946 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT5       (25L<<0)
02947 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT6       (26L<<0)
02948 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT7       (27L<<0)
02949 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT8       (28L<<0)
02950 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT9       (29L<<0)
02951 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT10      (30L<<0)
02952 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT11      (31L<<0)
02953 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TPAT_STAT0      (32L<<0)
02954 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TPAT_STAT1      (33L<<0)
02955 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TPAT_STAT2      (34L<<0)
02956 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TPAT_STAT3      (35L<<0)
02957 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_CP_STAT0        (36L<<0)
02958 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_CP_STAT1        (37L<<0)
02959 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_CP_STAT2        (38L<<0)
02960 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_CP_STAT3        (39L<<0)
02961 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_CP_STAT4        (40L<<0)
02962 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_CP_STAT5        (41L<<0)
02963 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_CP_STAT6        (42L<<0)
02964 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_CP_STAT7        (43L<<0)
02965 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_MCP_STAT0       (44L<<0)
02966 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_MCP_STAT1       (45L<<0)
02967 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_MCP_STAT2       (46L<<0)
02968 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_MCP_STAT3       (47L<<0)
02969 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_MCP_STAT4       (48L<<0)
02970 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_MCP_STAT5       (49L<<0)
02971 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_MCP_STAT6       (50L<<0)
02972 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_MCP_STAT7       (51L<<0)
02973 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_PCI_CLK_CNT     (52L<<0)
02974 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_CORE_CLK_CNT    (53L<<0)
02975 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_STATUS_BLOCKS    (54L<<0)
02976 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_INT_GEN  (55L<<0)
02977 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_INT_MBOX_WR      (56L<<0)
02978 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_TO_HW_INTACK       (59L<<0)
02979 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_TO_SW_INTACK       (60L<<0)
02980 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_DURING_SW_INTACK   (61L<<0)
02981 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TSCH_CMD_CNT    (62L<<0)
02982 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TSCH_SLOT_CNT   (63L<<0)
02983 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_CSCH_CMD_CNT    (64L<<0)
02984 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_CSCH_SLOT_CNT   (65L<<0)
02985 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RLUPQ_VALID_CNT         (66L<<0)
02986 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXPQ_VALID_CNT  (67L<<0)
02987 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXPCQ_VALID_CNT         (68L<<0)
02988 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2PPQ_VALID_CNT        (69L<<0)
02989 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2PMQ_VALID_CNT        (70L<<0)
02990 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2PTQ_VALID_CNT        (71L<<0)
02991 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RDMAQ_VALID_CNT         (72L<<0)
02992 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TSCHQ_VALID_CNT         (73L<<0)
02993 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TBDRQ_VALID_CNT         (74L<<0)
02994 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TXPQ_VALID_CNT  (75L<<0)
02995 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TDMAQ_VALID_CNT         (76L<<0)
02996 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TPATQ_VALID_CNT         (77L<<0)
02997 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TASQ_VALID_CNT  (78L<<0)
02998 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_CSQ_VALID_CNT   (79L<<0)
02999 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_CPQ_VALID_CNT   (80L<<0)
03000 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_COMXQ_VALID_CNT         (81L<<0)
03001 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_COMTQ_VALID_CNT         (82L<<0)
03002 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_COMQ_VALID_CNT  (83L<<0)
03003 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_MGMQ_VALID_CNT  (84L<<0)
03004 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_DMAE_READ_TRANSFERS_CNT         (85L<<0)
03005 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_DMAE_READ_DELAY_PCI_CLKS_CNT    (86L<<0)
03006 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_DMAE_BIG_READ_TRANSFERS_CNT     (87L<<0)
03007 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_DMAE_BIG_READ_DELAY_PCI_CLKS_CNT        (88L<<0)
03008 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_DMAE_BIG_READ_RETRY_AFTER_DATA_CNT      (89L<<0)
03009 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_DMAE_WRITE_TRANSFERS_CNT        (90L<<0)
03010 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_DMAE_WRITE_DELAY_PCI_CLKS_CNT   (91L<<0)
03011 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_DMAE_BIG_WRITE_TRANSFERS_CNT    (92L<<0)
03012 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_DMAE_BIG_WRITE_DELAY_PCI_CLKS_CNT       (93L<<0)
03013 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_DMAE_BIG_WRITE_RETRY_AFTER_DATA_CNT     (94L<<0)
03014 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_CTX_WR_CNT64    (95L<<0)
03015 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_CTX_RD_CNT64    (96L<<0)
03016 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_CTX_ACC_STALL_CLKS      (97L<<0)
03017 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_CTX_LOCK_STALL_CLKS     (98L<<0)
03018 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_MBQ_CTX_ACCESS_STAT     (99L<<0)
03019 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_MBQ_CTX_ACCESS64_STAT   (100L<<0)
03020 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_MBQ_PCI_STALL_STAT      (101L<<0)
03021 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TBDR_FTQ_ENTRY_CNT      (102L<<0)
03022 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TBDR_BURST_CNT  (103L<<0)
03023 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TDMA_FTQ_ENTRY_CNT      (104L<<0)
03024 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TDMA_BURST_CNT  (105L<<0)
03025 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RDMA_FTQ_ENTRY_CNT      (106L<<0)
03026 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RDMA_BURST_CNT  (107L<<0)
03027 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RLUP_MATCH_CNT  (108L<<0)
03028 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TMR_POLL_PASS_CNT       (109L<<0)
03029 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TMR_TMR1_CNT    (110L<<0)
03030 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TMR_TMR2_CNT    (111L<<0)
03031 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TMR_TMR3_CNT    (112L<<0)
03032 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TMR_TMR4_CNT    (113L<<0)
03033 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TMR_TMR5_CNT    (114L<<0)
03034 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2P_STAT0      (115L<<0)
03035 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2P_STAT1      (116L<<0)
03036 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2P_STAT2      (117L<<0)
03037 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2P_STAT3      (118L<<0)
03038 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2P_STAT4      (119L<<0)
03039 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2P_STAT5      (120L<<0)
03040 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RBDC_PROC1_MISS         (121L<<0)
03041 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RBDC_PROC2_MISS         (122L<<0)
03042 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RBDC_BURST_CNT  (127L<<0)
03043 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_1                 (0x7fL<<8)
03044 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_2                 (0x7fL<<16)
03045 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_3                 (0x7fL<<24)
03046 
03047 #define BNX2_HC_STAT_GEN_SEL_1                          0x00006854
03048 #define BNX2_HC_STAT_GEN_SEL_1_GEN_SEL_4                 (0x7fL<<0)
03049 #define BNX2_HC_STAT_GEN_SEL_1_GEN_SEL_5                 (0x7fL<<8)
03050 #define BNX2_HC_STAT_GEN_SEL_1_GEN_SEL_6                 (0x7fL<<16)
03051 #define BNX2_HC_STAT_GEN_SEL_1_GEN_SEL_7                 (0x7fL<<24)
03052 
03053 #define BNX2_HC_STAT_GEN_SEL_2                          0x00006858
03054 #define BNX2_HC_STAT_GEN_SEL_2_GEN_SEL_8                 (0x7fL<<0)
03055 #define BNX2_HC_STAT_GEN_SEL_2_GEN_SEL_9                 (0x7fL<<8)
03056 #define BNX2_HC_STAT_GEN_SEL_2_GEN_SEL_10                (0x7fL<<16)
03057 #define BNX2_HC_STAT_GEN_SEL_2_GEN_SEL_11                (0x7fL<<24)
03058 
03059 #define BNX2_HC_STAT_GEN_SEL_3                          0x0000685c
03060 #define BNX2_HC_STAT_GEN_SEL_3_GEN_SEL_12                (0x7fL<<0)
03061 #define BNX2_HC_STAT_GEN_SEL_3_GEN_SEL_13                (0x7fL<<8)
03062 #define BNX2_HC_STAT_GEN_SEL_3_GEN_SEL_14                (0x7fL<<16)
03063 #define BNX2_HC_STAT_GEN_SEL_3_GEN_SEL_15                (0x7fL<<24)
03064 
03065 #define BNX2_HC_STAT_GEN_STAT0                          0x00006888
03066 #define BNX2_HC_STAT_GEN_STAT1                          0x0000688c
03067 #define BNX2_HC_STAT_GEN_STAT2                          0x00006890
03068 #define BNX2_HC_STAT_GEN_STAT3                          0x00006894
03069 #define BNX2_HC_STAT_GEN_STAT4                          0x00006898
03070 #define BNX2_HC_STAT_GEN_STAT5                          0x0000689c
03071 #define BNX2_HC_STAT_GEN_STAT6                          0x000068a0
03072 #define BNX2_HC_STAT_GEN_STAT7                          0x000068a4
03073 #define BNX2_HC_STAT_GEN_STAT8                          0x000068a8
03074 #define BNX2_HC_STAT_GEN_STAT9                          0x000068ac
03075 #define BNX2_HC_STAT_GEN_STAT10                         0x000068b0
03076 #define BNX2_HC_STAT_GEN_STAT11                         0x000068b4
03077 #define BNX2_HC_STAT_GEN_STAT12                         0x000068b8
03078 #define BNX2_HC_STAT_GEN_STAT13                         0x000068bc
03079 #define BNX2_HC_STAT_GEN_STAT14                         0x000068c0
03080 #define BNX2_HC_STAT_GEN_STAT15                         0x000068c4
03081 #define BNX2_HC_STAT_GEN_STAT_AC0                       0x000068c8
03082 #define BNX2_HC_STAT_GEN_STAT_AC1                       0x000068cc
03083 #define BNX2_HC_STAT_GEN_STAT_AC2                       0x000068d0
03084 #define BNX2_HC_STAT_GEN_STAT_AC3                       0x000068d4
03085 #define BNX2_HC_STAT_GEN_STAT_AC4                       0x000068d8
03086 #define BNX2_HC_STAT_GEN_STAT_AC5                       0x000068dc
03087 #define BNX2_HC_STAT_GEN_STAT_AC6                       0x000068e0
03088 #define BNX2_HC_STAT_GEN_STAT_AC7                       0x000068e4
03089 #define BNX2_HC_STAT_GEN_STAT_AC8                       0x000068e8
03090 #define BNX2_HC_STAT_GEN_STAT_AC9                       0x000068ec
03091 #define BNX2_HC_STAT_GEN_STAT_AC10                      0x000068f0
03092 #define BNX2_HC_STAT_GEN_STAT_AC11                      0x000068f4
03093 #define BNX2_HC_STAT_GEN_STAT_AC12                      0x000068f8
03094 #define BNX2_HC_STAT_GEN_STAT_AC13                      0x000068fc
03095 #define BNX2_HC_STAT_GEN_STAT_AC14                      0x00006900
03096 #define BNX2_HC_STAT_GEN_STAT_AC15                      0x00006904
03097 #define BNX2_HC_VIS                                     0x00006908
03098 #define BNX2_HC_VIS_STAT_BUILD_STATE                     (0xfL<<0)
03099 #define BNX2_HC_VIS_STAT_BUILD_STATE_IDLE                (0L<<0)
03100 #define BNX2_HC_VIS_STAT_BUILD_STATE_START               (1L<<0)
03101 #define BNX2_HC_VIS_STAT_BUILD_STATE_REQUEST             (2L<<0)
03102 #define BNX2_HC_VIS_STAT_BUILD_STATE_UPDATE64            (3L<<0)
03103 #define BNX2_HC_VIS_STAT_BUILD_STATE_UPDATE32            (4L<<0)
03104 #define BNX2_HC_VIS_STAT_BUILD_STATE_UPDATE_DONE         (5L<<0)
03105 #define BNX2_HC_VIS_STAT_BUILD_STATE_DMA                 (6L<<0)
03106 #define BNX2_HC_VIS_STAT_BUILD_STATE_MSI_CONTROL         (7L<<0)
03107 #define BNX2_HC_VIS_STAT_BUILD_STATE_MSI_LOW             (8L<<0)
03108 #define BNX2_HC_VIS_STAT_BUILD_STATE_MSI_HIGH            (9L<<0)
03109 #define BNX2_HC_VIS_STAT_BUILD_STATE_MSI_DATA            (10L<<0)
03110 #define BNX2_HC_VIS_DMA_STAT_STATE                       (0xfL<<8)
03111 #define BNX2_HC_VIS_DMA_STAT_STATE_IDLE                  (0L<<8)
03112 #define BNX2_HC_VIS_DMA_STAT_STATE_STATUS_PARAM          (1L<<8)
03113 #define BNX2_HC_VIS_DMA_STAT_STATE_STATUS_DMA            (2L<<8)
03114 #define BNX2_HC_VIS_DMA_STAT_STATE_WRITE_COMP            (3L<<8)
03115 #define BNX2_HC_VIS_DMA_STAT_STATE_COMP                  (4L<<8)
03116 #define BNX2_HC_VIS_DMA_STAT_STATE_STATISTIC_PARAM       (5L<<8)
03117 #define BNX2_HC_VIS_DMA_STAT_STATE_STATISTIC_DMA         (6L<<8)
03118 #define BNX2_HC_VIS_DMA_STAT_STATE_WRITE_COMP_1          (7L<<8)
03119 #define BNX2_HC_VIS_DMA_STAT_STATE_WRITE_COMP_2          (8L<<8)
03120 #define BNX2_HC_VIS_DMA_STAT_STATE_WAIT                  (9L<<8)
03121 #define BNX2_HC_VIS_DMA_STAT_STATE_ABORT                 (15L<<8)
03122 #define BNX2_HC_VIS_DMA_MSI_STATE                        (0x7L<<12)
03123 #define BNX2_HC_VIS_STATISTIC_DMA_EN_STATE               (0x3L<<15)
03124 #define BNX2_HC_VIS_STATISTIC_DMA_EN_STATE_IDLE          (0L<<15)
03125 #define BNX2_HC_VIS_STATISTIC_DMA_EN_STATE_COUNT         (1L<<15)
03126 #define BNX2_HC_VIS_STATISTIC_DMA_EN_STATE_START         (2L<<15)
03127 
03128 #define BNX2_HC_VIS_1                                   0x0000690c
03129 #define BNX2_HC_VIS_1_HW_INTACK_STATE                    (1L<<4)
03130 #define BNX2_HC_VIS_1_HW_INTACK_STATE_IDLE               (0L<<4)
03131 #define BNX2_HC_VIS_1_HW_INTACK_STATE_COUNT              (1L<<4)
03132 #define BNX2_HC_VIS_1_SW_INTACK_STATE                    (1L<<5)
03133 #define BNX2_HC_VIS_1_SW_INTACK_STATE_IDLE               (0L<<5)
03134 #define BNX2_HC_VIS_1_SW_INTACK_STATE_COUNT              (1L<<5)
03135 #define BNX2_HC_VIS_1_DURING_SW_INTACK_STATE             (1L<<6)
03136 #define BNX2_HC_VIS_1_DURING_SW_INTACK_STATE_IDLE        (0L<<6)
03137 #define BNX2_HC_VIS_1_DURING_SW_INTACK_STATE_COUNT       (1L<<6)
03138 #define BNX2_HC_VIS_1_MAILBOX_COUNT_STATE                (1L<<7)
03139 #define BNX2_HC_VIS_1_MAILBOX_COUNT_STATE_IDLE           (0L<<7)
03140 #define BNX2_HC_VIS_1_MAILBOX_COUNT_STATE_COUNT          (1L<<7)
03141 #define BNX2_HC_VIS_1_RAM_RD_ARB_STATE                   (0xfL<<17)
03142 #define BNX2_HC_VIS_1_RAM_RD_ARB_STATE_IDLE              (0L<<17)
03143 #define BNX2_HC_VIS_1_RAM_RD_ARB_STATE_DMA               (1L<<17)
03144 #define BNX2_HC_VIS_1_RAM_RD_ARB_STATE_UPDATE            (2L<<17)
03145 #define BNX2_HC_VIS_1_RAM_RD_ARB_STATE_ASSIGN            (3L<<17)
03146 #define BNX2_HC_VIS_1_RAM_RD_ARB_STATE_WAIT              (4L<<17)
03147 #define BNX2_HC_VIS_1_RAM_RD_ARB_STATE_REG_UPDATE        (5L<<17)
03148 #define BNX2_HC_VIS_1_RAM_RD_ARB_STATE_REG_ASSIGN        (6L<<17)
03149 #define BNX2_HC_VIS_1_RAM_RD_ARB_STATE_REG_WAIT          (7L<<17)
03150 #define BNX2_HC_VIS_1_RAM_WR_ARB_STATE                   (0x3L<<21)
03151 #define BNX2_HC_VIS_1_RAM_WR_ARB_STATE_NORMAL            (0L<<21)
03152 #define BNX2_HC_VIS_1_RAM_WR_ARB_STATE_CLEAR             (1L<<21)
03153 #define BNX2_HC_VIS_1_INT_GEN_STATE                      (1L<<23)
03154 #define BNX2_HC_VIS_1_INT_GEN_STATE_DLE                  (0L<<23)
03155 #define BNX2_HC_VIS_1_INT_GEN_STATE_NTERRUPT             (1L<<23)
03156 #define BNX2_HC_VIS_1_STAT_CHAN_ID                       (0x7L<<24)
03157 #define BNX2_HC_VIS_1_INT_B                              (1L<<27)
03158 
03159 #define BNX2_HC_DEBUG_VECT_PEEK                         0x00006910
03160 #define BNX2_HC_DEBUG_VECT_PEEK_1_VALUE                  (0x7ffL<<0)
03161 #define BNX2_HC_DEBUG_VECT_PEEK_1_PEEK_EN                (1L<<11)
03162 #define BNX2_HC_DEBUG_VECT_PEEK_1_SEL                    (0xfL<<12)
03163 #define BNX2_HC_DEBUG_VECT_PEEK_2_VALUE                  (0x7ffL<<16)
03164 #define BNX2_HC_DEBUG_VECT_PEEK_2_PEEK_EN                (1L<<27)
03165 #define BNX2_HC_DEBUG_VECT_PEEK_2_SEL                    (0xfL<<28)
03166 
03167 
03168 
03169 /*
03170  *  txp_reg definition
03171  *  offset: 0x40000
03172  */
03173 #define BNX2_TXP_CPU_MODE                               0x00045000
03174 #define BNX2_TXP_CPU_MODE_LOCAL_RST                      (1L<<0)
03175 #define BNX2_TXP_CPU_MODE_STEP_ENA                       (1L<<1)
03176 #define BNX2_TXP_CPU_MODE_PAGE_0_DATA_ENA                (1L<<2)
03177 #define BNX2_TXP_CPU_MODE_PAGE_0_INST_ENA                (1L<<3)
03178 #define BNX2_TXP_CPU_MODE_MSG_BIT1                       (1L<<6)
03179 #define BNX2_TXP_CPU_MODE_INTERRUPT_ENA                  (1L<<7)
03180 #define BNX2_TXP_CPU_MODE_SOFT_HALT                      (1L<<10)
03181 #define BNX2_TXP_CPU_MODE_BAD_DATA_HALT_ENA              (1L<<11)
03182 #define BNX2_TXP_CPU_MODE_BAD_INST_HALT_ENA              (1L<<12)
03183 #define BNX2_TXP_CPU_MODE_FIO_ABORT_HALT_ENA             (1L<<13)
03184 #define BNX2_TXP_CPU_MODE_SPAD_UNDERFLOW_HALT_ENA        (1L<<15)
03185 
03186 #define BNX2_TXP_CPU_STATE                              0x00045004
03187 #define BNX2_TXP_CPU_STATE_BREAKPOINT                    (1L<<0)
03188 #define BNX2_TXP_CPU_STATE_BAD_INST_HALTED               (1L<<2)
03189 #define BNX2_TXP_CPU_STATE_PAGE_0_DATA_HALTED            (1L<<3)
03190 #define BNX2_TXP_CPU_STATE_PAGE_0_INST_HALTED            (1L<<4)
03191 #define BNX2_TXP_CPU_STATE_BAD_DATA_ADDR_HALTED          (1L<<5)
03192 #define BNX2_TXP_CPU_STATE_BAD_pc_HALTED                 (1L<<6)
03193 #define BNX2_TXP_CPU_STATE_ALIGN_HALTED                  (1L<<7)
03194 #define BNX2_TXP_CPU_STATE_FIO_ABORT_HALTED              (1L<<8)
03195 #define BNX2_TXP_CPU_STATE_SOFT_HALTED                   (1L<<10)
03196 #define BNX2_TXP_CPU_STATE_SPAD_UNDERFLOW                (1L<<11)
03197 #define BNX2_TXP_CPU_STATE_INTERRRUPT                    (1L<<12)
03198 #define BNX2_TXP_CPU_STATE_DATA_ACCESS_STALL             (1L<<14)
03199 #define BNX2_TXP_CPU_STATE_INST_FETCH_STALL              (1L<<15)
03200 #define BNX2_TXP_CPU_STATE_BLOCKED_READ                  (1L<<31)
03201 
03202 #define BNX2_TXP_CPU_EVENT_MASK                         0x00045008
03203 #define BNX2_TXP_CPU_EVENT_MASK_BREAKPOINT_MASK          (1L<<0)
03204 #define BNX2_TXP_CPU_EVENT_MASK_BAD_INST_HALTED_MASK     (1L<<2)
03205 #define BNX2_TXP_CPU_EVENT_MASK_PAGE_0_DATA_HALTED_MASK  (1L<<3)
03206 #define BNX2_TXP_CPU_EVENT_MASK_PAGE_0_INST_HALTED_MASK  (1L<<4)
03207 #define BNX2_TXP_CPU_EVENT_MASK_BAD_DATA_ADDR_HALTED_MASK        (1L<<5)
03208 #define BNX2_TXP_CPU_EVENT_MASK_BAD_PC_HALTED_MASK       (1L<<6)
03209 #define BNX2_TXP_CPU_EVENT_MASK_ALIGN_HALTED_MASK        (1L<<7)
03210 #define BNX2_TXP_CPU_EVENT_MASK_FIO_ABORT_MASK           (1L<<8)
03211 #define BNX2_TXP_CPU_EVENT_MASK_SOFT_HALTED_MASK         (1L<<10)
03212 #define BNX2_TXP_CPU_EVENT_MASK_SPAD_UNDERFLOW_MASK      (1L<<11)
03213 #define BNX2_TXP_CPU_EVENT_MASK_INTERRUPT_MASK           (1L<<12)
03214 
03215 #define BNX2_TXP_CPU_PROGRAM_COUNTER                    0x0004501c
03216 #define BNX2_TXP_CPU_INSTRUCTION                        0x00045020
03217 #define BNX2_TXP_CPU_DATA_ACCESS                        0x00045024
03218 #define BNX2_TXP_CPU_INTERRUPT_ENABLE                   0x00045028
03219 #define BNX2_TXP_CPU_INTERRUPT_VECTOR                   0x0004502c
03220 #define BNX2_TXP_CPU_INTERRUPT_SAVED_PC                 0x00045030
03221 #define BNX2_TXP_CPU_HW_BREAKPOINT                      0x00045034
03222 #define BNX2_TXP_CPU_HW_BREAKPOINT_DISABLE               (1L<<0)
03223 #define BNX2_TXP_CPU_HW_BREAKPOINT_ADDRESS               (0x3fffffffL<<2)
03224 
03225 #define BNX2_TXP_CPU_DEBUG_VECT_PEEK                    0x00045038
03226 #define BNX2_TXP_CPU_DEBUG_VECT_PEEK_1_VALUE             (0x7ffL<<0)
03227 #define BNX2_TXP_CPU_DEBUG_VECT_PEEK_1_PEEK_EN           (1L<<11)
03228 #define BNX2_TXP_CPU_DEBUG_VECT_PEEK_1_SEL               (0xfL<<12)
03229 #define BNX2_TXP_CPU_DEBUG_VECT_PEEK_2_VALUE             (0x7ffL<<16)
03230 #define BNX2_TXP_CPU_DEBUG_VECT_PEEK_2_PEEK_EN           (1L<<27)
03231 #define BNX2_TXP_CPU_DEBUG_VECT_PEEK_2_SEL               (0xfL<<28)
03232 
03233 #define BNX2_TXP_CPU_LAST_BRANCH_ADDR                   0x00045048
03234 #define BNX2_TXP_CPU_LAST_BRANCH_ADDR_TYPE               (1L<<1)
03235 #define BNX2_TXP_CPU_LAST_BRANCH_ADDR_TYPE_JUMP          (0L<<1)
03236 #define BNX2_TXP_CPU_LAST_BRANCH_ADDR_TYPE_BRANCH        (1L<<1)
03237 #define BNX2_TXP_CPU_LAST_BRANCH_ADDR_LBA                (0x3fffffffL<<2)
03238 
03239 #define BNX2_TXP_CPU_REG_FILE                           0x00045200
03240 #define BNX2_TXP_FTQ_DATA                               0x000453c0
03241 #define BNX2_TXP_FTQ_CMD                                0x000453f8
03242 #define BNX2_TXP_FTQ_CMD_OFFSET                          (0x3ffL<<0)
03243 #define BNX2_TXP_FTQ_CMD_WR_TOP                          (1L<<10)
03244 #define BNX2_TXP_FTQ_CMD_WR_TOP_0                        (0L<<10)
03245 #define BNX2_TXP_FTQ_CMD_WR_TOP_1                        (1L<<10)
03246 #define BNX2_TXP_FTQ_CMD_SFT_RESET                       (1L<<25)
03247 #define BNX2_TXP_FTQ_CMD_RD_DATA                         (1L<<26)
03248 #define BNX2_TXP_FTQ_CMD_ADD_INTERVEN                    (1L<<27)
03249 #define BNX2_TXP_FTQ_CMD_ADD_DATA                        (1L<<28)
03250 #define BNX2_TXP_FTQ_CMD_INTERVENE_CLR                   (1L<<29)
03251 #define BNX2_TXP_FTQ_CMD_POP                             (1L<<30)
03252 #define BNX2_TXP_FTQ_CMD_BUSY                            (1L<<31)
03253 
03254 #define BNX2_TXP_FTQ_CTL                                0x000453fc
03255 #define BNX2_TXP_FTQ_CTL_INTERVENE                       (1L<<0)
03256 #define BNX2_TXP_FTQ_CTL_OVERFLOW                        (1L<<1)
03257 #define BNX2_TXP_FTQ_CTL_FORCE_INTERVENE                 (1L<<2)
03258 #define BNX2_TXP_FTQ_CTL_MAX_DEPTH                       (0x3ffL<<12)
03259 #define BNX2_TXP_FTQ_CTL_CUR_DEPTH                       (0x3ffL<<22)
03260 
03261 #define BNX2_TXP_SCRATCH                                0x00060000
03262 
03263 
03264 /*
03265  *  tpat_reg definition
03266  *  offset: 0x80000
03267  */
03268 #define BNX2_TPAT_CPU_MODE                              0x00085000
03269 #define BNX2_TPAT_CPU_MODE_LOCAL_RST                     (1L<<0)
03270 #define BNX2_TPAT_CPU_MODE_STEP_ENA                      (1L<<1)
03271 #define BNX2_TPAT_CPU_MODE_PAGE_0_DATA_ENA               (1L<<2)
03272 #define BNX2_TPAT_CPU_MODE_PAGE_0_INST_ENA               (1L<<3)
03273 #define BNX2_TPAT_CPU_MODE_MSG_BIT1                      (1L<<6)
03274 #define BNX2_TPAT_CPU_MODE_INTERRUPT_ENA                 (1L<<7)
03275 #define BNX2_TPAT_CPU_MODE_SOFT_HALT                     (1L<<10)
03276 #define BNX2_TPAT_CPU_MODE_BAD_DATA_HALT_ENA             (1L<<11)
03277 #define BNX2_TPAT_CPU_MODE_BAD_INST_HALT_ENA             (1L<<12)
03278 #define BNX2_TPAT_CPU_MODE_FIO_ABORT_HALT_ENA            (1L<<13)
03279 #define BNX2_TPAT_CPU_MODE_SPAD_UNDERFLOW_HALT_ENA       (1L<<15)
03280 
03281 #define BNX2_TPAT_CPU_STATE                             0x00085004
03282 #define BNX2_TPAT_CPU_STATE_BREAKPOINT                   (1L<<0)
03283 #define BNX2_TPAT_CPU_STATE_BAD_INST_HALTED              (1L<<2)
03284 #define BNX2_TPAT_CPU_STATE_PAGE_0_DATA_HALTED           (1L<<3)
03285 #define BNX2_TPAT_CPU_STATE_PAGE_0_INST_HALTED           (1L<<4)
03286 #define BNX2_TPAT_CPU_STATE_BAD_DATA_ADDR_HALTED         (1L<<5)
03287 #define BNX2_TPAT_CPU_STATE_BAD_pc_HALTED                (1L<<6)
03288 #define BNX2_TPAT_CPU_STATE_ALIGN_HALTED                 (1L<<7)
03289 #define BNX2_TPAT_CPU_STATE_FIO_ABORT_HALTED             (1L<<8)
03290 #define BNX2_TPAT_CPU_STATE_SOFT_HALTED                  (1L<<10)
03291 #define BNX2_TPAT_CPU_STATE_SPAD_UNDERFLOW               (1L<<11)
03292 #define BNX2_TPAT_CPU_STATE_INTERRRUPT                   (1L<<12)
03293 #define BNX2_TPAT_CPU_STATE_DATA_ACCESS_STALL            (1L<<14)
03294 #define BNX2_TPAT_CPU_STATE_INST_FETCH_STALL             (1L<<15)
03295 #define BNX2_TPAT_CPU_STATE_BLOCKED_READ                 (1L<<31)
03296 
03297 #define BNX2_TPAT_CPU_EVENT_MASK                        0x00085008
03298 #define BNX2_TPAT_CPU_EVENT_MASK_BREAKPOINT_MASK         (1L<<0)
03299 #define BNX2_TPAT_CPU_EVENT_MASK_BAD_INST_HALTED_MASK    (1L<<2)
03300 #define BNX2_TPAT_CPU_EVENT_MASK_PAGE_0_DATA_HALTED_MASK         (1L<<3)
03301 #define BNX2_TPAT_CPU_EVENT_MASK_PAGE_0_INST_HALTED_MASK         (1L<<4)
03302 #define BNX2_TPAT_CPU_EVENT_MASK_BAD_DATA_ADDR_HALTED_MASK       (1L<<5)
03303 #define BNX2_TPAT_CPU_EVENT_MASK_BAD_PC_HALTED_MASK      (1L<<6)
03304 #define BNX2_TPAT_CPU_EVENT_MASK_ALIGN_HALTED_MASK       (1L<<7)
03305 #define BNX2_TPAT_CPU_EVENT_MASK_FIO_ABORT_MASK          (1L<<8)
03306 #define BNX2_TPAT_CPU_EVENT_MASK_SOFT_HALTED_MASK        (1L<<10)
03307 #define BNX2_TPAT_CPU_EVENT_MASK_SPAD_UNDERFLOW_MASK     (1L<<11)
03308 #define BNX2_TPAT_CPU_EVENT_MASK_INTERRUPT_MASK          (1L<<12)
03309 
03310 #define BNX2_TPAT_CPU_PROGRAM_COUNTER                   0x0008501c
03311 #define BNX2_TPAT_CPU_INSTRUCTION                       0x00085020
03312 #define BNX2_TPAT_CPU_DATA_ACCESS                       0x00085024
03313 #define BNX2_TPAT_CPU_INTERRUPT_ENABLE                  0x00085028
03314 #define BNX2_TPAT_CPU_INTERRUPT_VECTOR                  0x0008502c
03315 #define BNX2_TPAT_CPU_INTERRUPT_SAVED_PC                0x00085030
03316 #define BNX2_TPAT_CPU_HW_BREAKPOINT                     0x00085034
03317 #define BNX2_TPAT_CPU_HW_BREAKPOINT_DISABLE              (1L<<0)
03318 #define BNX2_TPAT_CPU_HW_BREAKPOINT_ADDRESS              (0x3fffffffL<<2)
03319 
03320 #define BNX2_TPAT_CPU_DEBUG_VECT_PEEK                   0x00085038
03321 #define BNX2_TPAT_CPU_DEBUG_VECT_PEEK_1_VALUE            (0x7ffL<<0)
03322 #define BNX2_TPAT_CPU_DEBUG_VECT_PEEK_1_PEEK_EN          (1L<<11)
03323 #define BNX2_TPAT_CPU_DEBUG_VECT_PEEK_1_SEL              (0xfL<<12)
03324 #define BNX2_TPAT_CPU_DEBUG_VECT_PEEK_2_VALUE            (0x7ffL<<16)
03325 #define BNX2_TPAT_CPU_DEBUG_VECT_PEEK_2_PEEK_EN          (1L<<27)
03326 #define BNX2_TPAT_CPU_DEBUG_VECT_PEEK_2_SEL              (0xfL<<28)
03327 
03328 #define BNX2_TPAT_CPU_LAST_BRANCH_ADDR                  0x00085048
03329 #define BNX2_TPAT_CPU_LAST_BRANCH_ADDR_TYPE              (1L<<1)
03330 #define BNX2_TPAT_CPU_LAST_BRANCH_ADDR_TYPE_JUMP         (0L<<1)
03331 #define BNX2_TPAT_CPU_LAST_BRANCH_ADDR_TYPE_BRANCH       (1L<<1)
03332 #define BNX2_TPAT_CPU_LAST_BRANCH_ADDR_LBA               (0x3fffffffL<<2)
03333 
03334 #define BNX2_TPAT_CPU_REG_FILE                          0x00085200
03335 #define BNX2_TPAT_FTQ_DATA                              0x000853c0
03336 #define BNX2_TPAT_FTQ_CMD                               0x000853f8
03337 #define BNX2_TPAT_FTQ_CMD_OFFSET                         (0x3ffL<<0)
03338 #define BNX2_TPAT_FTQ_CMD_WR_TOP                         (1L<<10)
03339 #define BNX2_TPAT_FTQ_CMD_WR_TOP_0                       (0L<<10)
03340 #define BNX2_TPAT_FTQ_CMD_WR_TOP_1                       (1L<<10)
03341 #define BNX2_TPAT_FTQ_CMD_SFT_RESET                      (1L<<25)
03342 #define BNX2_TPAT_FTQ_CMD_RD_DATA                        (1L<<26)
03343 #define BNX2_TPAT_FTQ_CMD_ADD_INTERVEN                   (1L<<27)
03344 #define BNX2_TPAT_FTQ_CMD_ADD_DATA                       (1L<<28)
03345 #define BNX2_TPAT_FTQ_CMD_INTERVENE_CLR                  (1L<<29)
03346 #define BNX2_TPAT_FTQ_CMD_POP                            (1L<<30)
03347 #define BNX2_TPAT_FTQ_CMD_BUSY                           (1L<<31)
03348 
03349 #define BNX2_TPAT_FTQ_CTL                               0x000853fc
03350 #define BNX2_TPAT_FTQ_CTL_INTERVENE                      (1L<<0)
03351 #define BNX2_TPAT_FTQ_CTL_OVERFLOW                       (1L<<1)
03352 #define BNX2_TPAT_FTQ_CTL_FORCE_INTERVENE                (1L<<2)
03353 #define BNX2_TPAT_FTQ_CTL_MAX_DEPTH                      (0x3ffL<<12)
03354 #define BNX2_TPAT_FTQ_CTL_CUR_DEPTH                      (0x3ffL<<22)
03355 
03356 #define BNX2_TPAT_SCRATCH                               0x000a0000
03357 
03358 
03359 /*
03360  *  rxp_reg definition
03361  *  offset: 0xc0000
03362  */
03363 #define BNX2_RXP_CPU_MODE                               0x000c5000
03364 #define BNX2_RXP_CPU_MODE_LOCAL_RST                      (1L<<0)
03365 #define BNX2_RXP_CPU_MODE_STEP_ENA                       (1L<<1)
03366 #define BNX2_RXP_CPU_MODE_PAGE_0_DATA_ENA                (1L<<2)
03367 #define BNX2_RXP_CPU_MODE_PAGE_0_INST_ENA                (1L<<3)
03368 #define BNX2_RXP_CPU_MODE_MSG_BIT1                       (1L<<6)
03369 #define BNX2_RXP_CPU_MODE_INTERRUPT_ENA                  (1L<<7)
03370 #define BNX2_RXP_CPU_MODE_SOFT_HALT                      (1L<<10)
03371 #define BNX2_RXP_CPU_MODE_BAD_DATA_HALT_ENA              (1L<<11)
03372 #define BNX2_RXP_CPU_MODE_BAD_INST_HALT_ENA              (1L<<12)
03373 #define BNX2_RXP_CPU_MODE_FIO_ABORT_HALT_ENA             (1L<<13)
03374 #define BNX2_RXP_CPU_MODE_SPAD_UNDERFLOW_HALT_ENA        (1L<<15)
03375 
03376 #define BNX2_RXP_CPU_STATE                              0x000c5004
03377 #define BNX2_RXP_CPU_STATE_BREAKPOINT                    (1L<<0)
03378 #define BNX2_RXP_CPU_STATE_BAD_INST_HALTED               (1L<<2)
03379 #define BNX2_RXP_CPU_STATE_PAGE_0_DATA_HALTED            (1L<<3)
03380 #define BNX2_RXP_CPU_STATE_PAGE_0_INST_HALTED            (1L<<4)
03381 #define BNX2_RXP_CPU_STATE_BAD_DATA_ADDR_HALTED          (1L<<5)
03382 #define BNX2_RXP_CPU_STATE_BAD_pc_HALTED                 (1L<<6)
03383 #define BNX2_RXP_CPU_STATE_ALIGN_HALTED                  (1L<<7)
03384 #define BNX2_RXP_CPU_STATE_FIO_ABORT_HALTED              (1L<<8)
03385 #define BNX2_RXP_CPU_STATE_SOFT_HALTED                   (1L<<10)
03386 #define BNX2_RXP_CPU_STATE_SPAD_UNDERFLOW                (1L<<11)
03387 #define BNX2_RXP_CPU_STATE_INTERRRUPT                    (1L<<12)
03388 #define BNX2_RXP_CPU_STATE_DATA_ACCESS_STALL             (1L<<14)
03389 #define BNX2_RXP_CPU_STATE_INST_FETCH_STALL              (1L<<15)
03390 #define BNX2_RXP_CPU_STATE_BLOCKED_READ                  (1L<<31)
03391 
03392 #define BNX2_RXP_CPU_EVENT_MASK                         0x000c5008
03393 #define BNX2_RXP_CPU_EVENT_MASK_BREAKPOINT_MASK          (1L<<0)
03394 #define BNX2_RXP_CPU_EVENT_MASK_BAD_INST_HALTED_MASK     (1L<<2)
03395 #define BNX2_RXP_CPU_EVENT_MASK_PAGE_0_DATA_HALTED_MASK  (1L<<3)
03396 #define BNX2_RXP_CPU_EVENT_MASK_PAGE_0_INST_HALTED_MASK  (1L<<4)
03397 #define BNX2_RXP_CPU_EVENT_MASK_BAD_DATA_ADDR_HALTED_MASK        (1L<<5)
03398 #define BNX2_RXP_CPU_EVENT_MASK_BAD_PC_HALTED_MASK       (1L<<6)
03399 #define BNX2_RXP_CPU_EVENT_MASK_ALIGN_HALTED_MASK        (1L<<7)
03400 #define BNX2_RXP_CPU_EVENT_MASK_FIO_ABORT_MASK           (1L<<8)
03401 #define BNX2_RXP_CPU_EVENT_MASK_SOFT_HALTED_MASK         (1L<<10)
03402 #define BNX2_RXP_CPU_EVENT_MASK_SPAD_UNDERFLOW_MASK      (1L<<11)
03403 #define BNX2_RXP_CPU_EVENT_MASK_INTERRUPT_MASK           (1L<<12)
03404 
03405 #define BNX2_RXP_CPU_PROGRAM_COUNTER                    0x000c501c
03406 #define BNX2_RXP_CPU_INSTRUCTION                        0x000c5020
03407 #define BNX2_RXP_CPU_DATA_ACCESS                        0x000c5024
03408 #define BNX2_RXP_CPU_INTERRUPT_ENABLE                   0x000c5028
03409 #define BNX2_RXP_CPU_INTERRUPT_VECTOR                   0x000c502c
03410 #define BNX2_RXP_CPU_INTERRUPT_SAVED_PC                 0x000c5030
03411 #define BNX2_RXP_CPU_HW_BREAKPOINT                      0x000c5034
03412 #define BNX2_RXP_CPU_HW_BREAKPOINT_DISABLE               (1L<<0)
03413 #define BNX2_RXP_CPU_HW_BREAKPOINT_ADDRESS               (0x3fffffffL<<2)
03414 
03415 #define BNX2_RXP_CPU_DEBUG_VECT_PEEK                    0x000c5038
03416 #define BNX2_RXP_CPU_DEBUG_VECT_PEEK_1_VALUE             (0x7ffL<<0)
03417 #define BNX2_RXP_CPU_DEBUG_VECT_PEEK_1_PEEK_EN           (1L<<11)
03418 #define BNX2_RXP_CPU_DEBUG_VECT_PEEK_1_SEL               (0xfL<<12)
03419 #define BNX2_RXP_CPU_DEBUG_VECT_PEEK_2_VALUE             (0x7ffL<<16)
03420 #define BNX2_RXP_CPU_DEBUG_VECT_PEEK_2_PEEK_EN           (1L<<27)
03421 #define BNX2_RXP_CPU_DEBUG_VECT_PEEK_2_SEL               (0xfL<<28)
03422 
03423 #define BNX2_RXP_CPU_LAST_BRANCH_ADDR                   0x000c5048
03424 #define BNX2_RXP_CPU_LAST_BRANCH_ADDR_TYPE               (1L<<1)
03425 #define BNX2_RXP_CPU_LAST_BRANCH_ADDR_TYPE_JUMP          (0L<<1)
03426 #define BNX2_RXP_CPU_LAST_BRANCH_ADDR_TYPE_BRANCH        (1L<<1)
03427 #define BNX2_RXP_CPU_LAST_BRANCH_ADDR_LBA                (0x3fffffffL<<2)
03428 
03429 #define BNX2_RXP_CPU_REG_FILE                           0x000c5200
03430 #define BNX2_RXP_CFTQ_DATA                              0x000c5380
03431 #define BNX2_RXP_CFTQ_CMD                               0x000c53b8
03432 #define BNX2_RXP_CFTQ_CMD_OFFSET                         (0x3ffL<<0)
03433 #define BNX2_RXP_CFTQ_CMD_WR_TOP                         (1L<<10)
03434 #define BNX2_RXP_CFTQ_CMD_WR_TOP_0                       (0L<<10)
03435 #define BNX2_RXP_CFTQ_CMD_WR_TOP_1                       (1L<<10)
03436 #define BNX2_RXP_CFTQ_CMD_SFT_RESET                      (1L<<25)
03437 #define BNX2_RXP_CFTQ_CMD_RD_DATA                        (1L<<26)
03438 #define BNX2_RXP_CFTQ_CMD_ADD_INTERVEN                   (1L<<27)
03439 #define BNX2_RXP_CFTQ_CMD_ADD_DATA                       (1L<<28)
03440 #define BNX2_RXP_CFTQ_CMD_INTERVENE_CLR                  (1L<<29)
03441 #define BNX2_RXP_CFTQ_CMD_POP                            (1L<<30)
03442 #define BNX2_RXP_CFTQ_CMD_BUSY                           (1L<<31)
03443 
03444 #define BNX2_RXP_CFTQ_CTL                               0x000c53bc
03445 #define BNX2_RXP_CFTQ_CTL_INTERVENE                      (1L<<0)
03446 #define BNX2_RXP_CFTQ_CTL_OVERFLOW                       (1L<<1)
03447 #define BNX2_RXP_CFTQ_CTL_FORCE_INTERVENE                (1L<<2)
03448 #define BNX2_RXP_CFTQ_CTL_MAX_DEPTH                      (0x3ffL<<12)
03449 #define BNX2_RXP_CFTQ_CTL_CUR_DEPTH                      (0x3ffL<<22)
03450 
03451 #define BNX2_RXP_FTQ_DATA                               0x000c53c0
03452 #define BNX2_RXP_FTQ_CMD                                0x000c53f8
03453 #define BNX2_RXP_FTQ_CMD_OFFSET                          (0x3ffL<<0)
03454 #define BNX2_RXP_FTQ_CMD_WR_TOP                          (1L<<10)
03455 #define BNX2_RXP_FTQ_CMD_WR_TOP_0                        (0L<<10)
03456 #define BNX2_RXP_FTQ_CMD_WR_TOP_1                        (1L<<10)
03457 #define BNX2_RXP_FTQ_CMD_SFT_RESET                       (1L<<25)
03458 #define BNX2_RXP_FTQ_CMD_RD_DATA                         (1L<<26)
03459 #define BNX2_RXP_FTQ_CMD_ADD_INTERVEN                    (1L<<27)
03460 #define BNX2_RXP_FTQ_CMD_ADD_DATA                        (1L<<28)
03461 #define BNX2_RXP_FTQ_CMD_INTERVENE_CLR                   (1L<<29)
03462 #define BNX2_RXP_FTQ_CMD_POP                             (1L<<30)
03463 #define BNX2_RXP_FTQ_CMD_BUSY                            (1L<<31)
03464 
03465 #define BNX2_RXP_FTQ_CTL                                0x000c53fc
03466 #define BNX2_RXP_FTQ_CTL_INTERVENE                       (1L<<0)
03467 #define BNX2_RXP_FTQ_CTL_OVERFLOW                        (1L<<1)
03468 #define BNX2_RXP_FTQ_CTL_FORCE_INTERVENE                 (1L<<2)
03469 #define BNX2_RXP_FTQ_CTL_MAX_DEPTH                       (0x3ffL<<12)
03470 #define BNX2_RXP_FTQ_CTL_CUR_DEPTH                       (0x3ffL<<22)
03471 
03472 #define BNX2_RXP_SCRATCH                                0x000e0000
03473 
03474 
03475 /*
03476  *  com_reg definition
03477  *  offset: 0x100000
03478  */
03479 #define BNX2_COM_CPU_MODE                               0x00105000
03480 #define BNX2_COM_CPU_MODE_LOCAL_RST                      (1L<<0)
03481 #define BNX2_COM_CPU_MODE_STEP_ENA                       (1L<<1)
03482 #define BNX2_COM_CPU_MODE_PAGE_0_DATA_ENA                (1L<<2)
03483 #define BNX2_COM_CPU_MODE_PAGE_0_INST_ENA                (1L<<3)
03484 #define BNX2_COM_CPU_MODE_MSG_BIT1                       (1L<<6)
03485 #define BNX2_COM_CPU_MODE_INTERRUPT_ENA                  (1L<<7)
03486 #define BNX2_COM_CPU_MODE_SOFT_HALT                      (1L<<10)
03487 #define BNX2_COM_CPU_MODE_BAD_DATA_HALT_ENA              (1L<<11)
03488 #define BNX2_COM_CPU_MODE_BAD_INST_HALT_ENA              (1L<<12)
03489 #define BNX2_COM_CPU_MODE_FIO_ABORT_HALT_ENA             (1L<<13)
03490 #define BNX2_COM_CPU_MODE_SPAD_UNDERFLOW_HALT_ENA        (1L<<15)
03491 
03492 #define BNX2_COM_CPU_STATE                              0x00105004
03493 #define BNX2_COM_CPU_STATE_BREAKPOINT                    (1L<<0)
03494 #define BNX2_COM_CPU_STATE_BAD_INST_HALTED               (1L<<2)
03495 #define BNX2_COM_CPU_STATE_PAGE_0_DATA_HALTED            (1L<<3)
03496 #define BNX2_COM_CPU_STATE_PAGE_0_INST_HALTED            (1L<<4)
03497 #define BNX2_COM_CPU_STATE_BAD_DATA_ADDR_HALTED          (1L<<5)
03498 #define BNX2_COM_CPU_STATE_BAD_pc_HALTED                 (1L<<6)
03499 #define BNX2_COM_CPU_STATE_ALIGN_HALTED                  (1L<<7)
03500 #define BNX2_COM_CPU_STATE_FIO_ABORT_HALTED              (1L<<8)
03501 #define BNX2_COM_CPU_STATE_SOFT_HALTED                   (1L<<10)
03502 #define BNX2_COM_CPU_STATE_SPAD_UNDERFLOW                (1L<<11)
03503 #define BNX2_COM_CPU_STATE_INTERRRUPT                    (1L<<12)
03504 #define BNX2_COM_CPU_STATE_DATA_ACCESS_STALL             (1L<<14)
03505 #define BNX2_COM_CPU_STATE_INST_FETCH_STALL              (1L<<15)
03506 #define BNX2_COM_CPU_STATE_BLOCKED_READ                  (1L<<31)
03507 
03508 #define BNX2_COM_CPU_EVENT_MASK                         0x00105008
03509 #define BNX2_COM_CPU_EVENT_MASK_BREAKPOINT_MASK          (1L<<0)
03510 #define BNX2_COM_CPU_EVENT_MASK_BAD_INST_HALTED_MASK     (1L<<2)
03511 #define BNX2_COM_CPU_EVENT_MASK_PAGE_0_DATA_HALTED_MASK  (1L<<3)
03512 #define BNX2_COM_CPU_EVENT_MASK_PAGE_0_INST_HALTED_MASK  (1L<<4)
03513 #define BNX2_COM_CPU_EVENT_MASK_BAD_DATA_ADDR_HALTED_MASK        (1L<<5)
03514 #define BNX2_COM_CPU_EVENT_MASK_BAD_PC_HALTED_MASK       (1L<<6)
03515 #define BNX2_COM_CPU_EVENT_MASK_ALIGN_HALTED_MASK        (1L<<7)
03516 #define BNX2_COM_CPU_EVENT_MASK_FIO_ABORT_MASK           (1L<<8)
03517 #define BNX2_COM_CPU_EVENT_MASK_SOFT_HALTED_MASK         (1L<<10)
03518 #define BNX2_COM_CPU_EVENT_MASK_SPAD_UNDERFLOW_MASK      (1L<<11)
03519 #define BNX2_COM_CPU_EVENT_MASK_INTERRUPT_MASK           (1L<<12)
03520 
03521 #define BNX2_COM_CPU_PROGRAM_COUNTER                    0x0010501c
03522 #define BNX2_COM_CPU_INSTRUCTION                        0x00105020
03523 #define BNX2_COM_CPU_DATA_ACCESS                        0x00105024
03524 #define BNX2_COM_CPU_INTERRUPT_ENABLE                   0x00105028
03525 #define BNX2_COM_CPU_INTERRUPT_VECTOR                   0x0010502c
03526 #define BNX2_COM_CPU_INTERRUPT_SAVED_PC                 0x00105030
03527 #define BNX2_COM_CPU_HW_BREAKPOINT                      0x00105034
03528 #define BNX2_COM_CPU_HW_BREAKPOINT_DISABLE               (1L<<0)
03529 #define BNX2_COM_CPU_HW_BREAKPOINT_ADDRESS               (0x3fffffffL<<2)
03530 
03531 #define BNX2_COM_CPU_DEBUG_VECT_PEEK                    0x00105038
03532 #define BNX2_COM_CPU_DEBUG_VECT_PEEK_1_VALUE             (0x7ffL<<0)
03533 #define BNX2_COM_CPU_DEBUG_VECT_PEEK_1_PEEK_EN           (1L<<11)
03534 #define BNX2_COM_CPU_DEBUG_VECT_PEEK_1_SEL               (0xfL<<12)
03535 #define BNX2_COM_CPU_DEBUG_VECT_PEEK_2_VALUE             (0x7ffL<<16)
03536 #define BNX2_COM_CPU_DEBUG_VECT_PEEK_2_PEEK_EN           (1L<<27)
03537 #define BNX2_COM_CPU_DEBUG_VECT_PEEK_2_SEL               (0xfL<<28)
03538 
03539 #define BNX2_COM_CPU_LAST_BRANCH_ADDR                   0x00105048
03540 #define BNX2_COM_CPU_LAST_BRANCH_ADDR_TYPE               (1L<<1)
03541 #define BNX2_COM_CPU_LAST_BRANCH_ADDR_TYPE_JUMP          (0L<<1)
03542 #define BNX2_COM_CPU_LAST_BRANCH_ADDR_TYPE_BRANCH        (1L<<1)
03543 #define BNX2_COM_CPU_LAST_BRANCH_ADDR_LBA                (0x3fffffffL<<2)
03544 
03545 #define BNX2_COM_CPU_REG_FILE                           0x00105200
03546 #define BNX2_COM_COMXQ_FTQ_DATA                         0x00105340
03547 #define BNX2_COM_COMXQ_FTQ_CMD                          0x00105378
03548 #define BNX2_COM_COMXQ_FTQ_CMD_OFFSET                    (0x3ffL<<0)
03549 #define BNX2_COM_COMXQ_FTQ_CMD_WR_TOP                    (1L<<10)
03550 #define BNX2_COM_COMXQ_FTQ_CMD_WR_TOP_0                  (0L<<10)
03551 #define BNX2_COM_COMXQ_FTQ_CMD_WR_TOP_1                  (1L<<10)
03552 #define BNX2_COM_COMXQ_FTQ_CMD_SFT_RESET                 (1L<<25)
03553 #define BNX2_COM_COMXQ_FTQ_CMD_RD_DATA                   (1L<<26)
03554 #define BNX2_COM_COMXQ_FTQ_CMD_ADD_INTERVEN              (1L<<27)
03555 #define BNX2_COM_COMXQ_FTQ_CMD_ADD_DATA                  (1L<<28)
03556 #define BNX2_COM_COMXQ_FTQ_CMD_INTERVENE_CLR             (1L<<29)
03557 #define BNX2_COM_COMXQ_FTQ_CMD_POP                       (1L<<30)
03558 #define BNX2_COM_COMXQ_FTQ_CMD_BUSY                      (1L<<31)
03559 
03560 #define BNX2_COM_COMXQ_FTQ_CTL                          0x0010537c
03561 #define BNX2_COM_COMXQ_FTQ_CTL_INTERVENE                 (1L<<0)
03562 #define BNX2_COM_COMXQ_FTQ_CTL_OVERFLOW                  (1L<<1)
03563 #define BNX2_COM_COMXQ_FTQ_CTL_FORCE_INTERVENE           (1L<<2)
03564 #define BNX2_COM_COMXQ_FTQ_CTL_MAX_DEPTH                 (0x3ffL<<12)
03565 #define BNX2_COM_COMXQ_FTQ_CTL_CUR_DEPTH                 (0x3ffL<<22)
03566 
03567 #define BNX2_COM_COMTQ_FTQ_DATA                         0x00105380
03568 #define BNX2_COM_COMTQ_FTQ_CMD                          0x001053b8
03569 #define BNX2_COM_COMTQ_FTQ_CMD_OFFSET                    (0x3ffL<<0)
03570 #define BNX2_COM_COMTQ_FTQ_CMD_WR_TOP                    (1L<<10)
03571 #define BNX2_COM_COMTQ_FTQ_CMD_WR_TOP_0                  (0L<<10)
03572 #define BNX2_COM_COMTQ_FTQ_CMD_WR_TOP_1                  (1L<<10)
03573 #define BNX2_COM_COMTQ_FTQ_CMD_SFT_RESET                 (1L<<25)
03574 #define BNX2_COM_COMTQ_FTQ_CMD_RD_DATA                   (1L<<26)
03575 #define BNX2_COM_COMTQ_FTQ_CMD_ADD_INTERVEN              (1L<<27)
03576 #define BNX2_COM_COMTQ_FTQ_CMD_ADD_DATA                  (1L<<28)
03577 #define BNX2_COM_COMTQ_FTQ_CMD_INTERVENE_CLR             (1L<<29)
03578 #define BNX2_COM_COMTQ_FTQ_CMD_POP                       (1L<<30)
03579 #define BNX2_COM_COMTQ_FTQ_CMD_BUSY                      (1L<<31)
03580 
03581 #define BNX2_COM_COMTQ_FTQ_CTL                          0x001053bc
03582 #define BNX2_COM_COMTQ_FTQ_CTL_INTERVENE                 (1L<<0)
03583 #define BNX2_COM_COMTQ_FTQ_CTL_OVERFLOW                  (1L<<1)
03584 #define BNX2_COM_COMTQ_FTQ_CTL_FORCE_INTERVENE           (1L<<2)
03585 #define BNX2_COM_COMTQ_FTQ_CTL_MAX_DEPTH                 (0x3ffL<<12)
03586 #define BNX2_COM_COMTQ_FTQ_CTL_CUR_DEPTH                 (0x3ffL<<22)
03587 
03588 #define BNX2_COM_COMQ_FTQ_DATA                          0x001053c0
03589 #define BNX2_COM_COMQ_FTQ_CMD                           0x001053f8
03590 #define BNX2_COM_COMQ_FTQ_CMD_OFFSET                     (0x3ffL<<0)
03591 #define BNX2_COM_COMQ_FTQ_CMD_WR_TOP                     (1L<<10)
03592 #define BNX2_COM_COMQ_FTQ_CMD_WR_TOP_0                   (0L<<10)
03593 #define BNX2_COM_COMQ_FTQ_CMD_WR_TOP_1                   (1L<<10)
03594 #define BNX2_COM_COMQ_FTQ_CMD_SFT_RESET                  (1L<<25)
03595 #define BNX2_COM_COMQ_FTQ_CMD_RD_DATA                    (1L<<26)
03596 #define BNX2_COM_COMQ_FTQ_CMD_ADD_INTERVEN               (1L<<27)
03597 #define BNX2_COM_COMQ_FTQ_CMD_ADD_DATA                   (1L<<28)
03598 #define BNX2_COM_COMQ_FTQ_CMD_INTERVENE_CLR              (1L<<29)
03599 #define BNX2_COM_COMQ_FTQ_CMD_POP                        (1L<<30)
03600 #define BNX2_COM_COMQ_FTQ_CMD_BUSY                       (1L<<31)
03601 
03602 #define BNX2_COM_COMQ_FTQ_CTL                           0x001053fc
03603 #define BNX2_COM_COMQ_FTQ_CTL_INTERVENE                  (1L<<0)
03604 #define BNX2_COM_COMQ_FTQ_CTL_OVERFLOW                   (1L<<1)
03605 #define BNX2_COM_COMQ_FTQ_CTL_FORCE_INTERVENE            (1L<<2)
03606 #define BNX2_COM_COMQ_FTQ_CTL_MAX_DEPTH                  (0x3ffL<<12)
03607 #define BNX2_COM_COMQ_FTQ_CTL_CUR_DEPTH                  (0x3ffL<<22)
03608 
03609 #define BNX2_COM_SCRATCH                                0x00120000
03610 
03611 
03612 /*
03613  *  cp_reg definition
03614  *  offset: 0x180000
03615  */
03616 #define BNX2_CP_CPU_MODE                                0x00185000
03617 #define BNX2_CP_CPU_MODE_LOCAL_RST                       (1L<<0)
03618 #define BNX2_CP_CPU_MODE_STEP_ENA                        (1L<<1)
03619 #define BNX2_CP_CPU_MODE_PAGE_0_DATA_ENA                 (1L<<2)
03620 #define BNX2_CP_CPU_MODE_PAGE_0_INST_ENA                 (1L<<3)
03621 #define BNX2_CP_CPU_MODE_MSG_BIT1                        (1L<<6)
03622 #define BNX2_CP_CPU_MODE_INTERRUPT_ENA                   (1L<<7)
03623 #define BNX2_CP_CPU_MODE_SOFT_HALT                       (1L<<10)
03624 #define BNX2_CP_CPU_MODE_BAD_DATA_HALT_ENA               (1L<<11)
03625 #define BNX2_CP_CPU_MODE_BAD_INST_HALT_ENA               (1L<<12)
03626 #define BNX2_CP_CPU_MODE_FIO_ABORT_HALT_ENA              (1L<<13)
03627 #define BNX2_CP_CPU_MODE_SPAD_UNDERFLOW_HALT_ENA         (1L<<15)
03628 
03629 #define BNX2_CP_CPU_STATE                               0x00185004
03630 #define BNX2_CP_CPU_STATE_BREAKPOINT                     (1L<<0)
03631 #define BNX2_CP_CPU_STATE_BAD_INST_HALTED                (1L<<2)
03632 #define BNX2_CP_CPU_STATE_PAGE_0_DATA_HALTED             (1L<<3)
03633 #define BNX2_CP_CPU_STATE_PAGE_0_INST_HALTED             (1L<<4)
03634 #define BNX2_CP_CPU_STATE_BAD_DATA_ADDR_HALTED           (1L<<5)
03635 #define BNX2_CP_CPU_STATE_BAD_pc_HALTED                  (1L<<6)
03636 #define BNX2_CP_CPU_STATE_ALIGN_HALTED                   (1L<<7)
03637 #define BNX2_CP_CPU_STATE_FIO_ABORT_HALTED               (1L<<8)
03638 #define BNX2_CP_CPU_STATE_SOFT_HALTED                    (1L<<10)
03639 #define BNX2_CP_CPU_STATE_SPAD_UNDERFLOW                 (1L<<11)
03640 #define BNX2_CP_CPU_STATE_INTERRRUPT                     (1L<<12)
03641 #define BNX2_CP_CPU_STATE_DATA_ACCESS_STALL              (1L<<14)
03642 #define BNX2_CP_CPU_STATE_INST_FETCH_STALL               (1L<<15)
03643 #define BNX2_CP_CPU_STATE_BLOCKED_READ                   (1L<<31)
03644 
03645 #define BNX2_CP_CPU_EVENT_MASK                          0x00185008
03646 #define BNX2_CP_CPU_EVENT_MASK_BREAKPOINT_MASK           (1L<<0)
03647 #define BNX2_CP_CPU_EVENT_MASK_BAD_INST_HALTED_MASK      (1L<<2)
03648 #define BNX2_CP_CPU_EVENT_MASK_PAGE_0_DATA_HALTED_MASK   (1L<<3)
03649 #define BNX2_CP_CPU_EVENT_MASK_PAGE_0_INST_HALTED_MASK   (1L<<4)
03650 #define BNX2_CP_CPU_EVENT_MASK_BAD_DATA_ADDR_HALTED_MASK         (1L<<5)
03651 #define BNX2_CP_CPU_EVENT_MASK_BAD_PC_HALTED_MASK        (1L<<6)
03652 #define BNX2_CP_CPU_EVENT_MASK_ALIGN_HALTED_MASK         (1L<<7)
03653 #define BNX2_CP_CPU_EVENT_MASK_FIO_ABORT_MASK            (1L<<8)
03654 #define BNX2_CP_CPU_EVENT_MASK_SOFT_HALTED_MASK          (1L<<10)
03655 #define BNX2_CP_CPU_EVENT_MASK_SPAD_UNDERFLOW_MASK       (1L<<11)
03656 #define BNX2_CP_CPU_EVENT_MASK_INTERRUPT_MASK            (1L<<12)
03657 
03658 #define BNX2_CP_CPU_PROGRAM_COUNTER                     0x0018501c
03659 #define BNX2_CP_CPU_INSTRUCTION                         0x00185020
03660 #define BNX2_CP_CPU_DATA_ACCESS                         0x00185024
03661 #define BNX2_CP_CPU_INTERRUPT_ENABLE                    0x00185028
03662 #define BNX2_CP_CPU_INTERRUPT_VECTOR                    0x0018502c
03663 #define BNX2_CP_CPU_INTERRUPT_SAVED_PC                  0x00185030
03664 #define BNX2_CP_CPU_HW_BREAKPOINT                       0x00185034
03665 #define BNX2_CP_CPU_HW_BREAKPOINT_DISABLE                (1L<<0)
03666 #define BNX2_CP_CPU_HW_BREAKPOINT_ADDRESS                (0x3fffffffL<<2)
03667 
03668 #define BNX2_CP_CPU_DEBUG_VECT_PEEK                     0x00185038
03669 #define BNX2_CP_CPU_DEBUG_VECT_PEEK_1_VALUE              (0x7ffL<<0)
03670 #define BNX2_CP_CPU_DEBUG_VECT_PEEK_1_PEEK_EN            (1L<<11)
03671 #define BNX2_CP_CPU_DEBUG_VECT_PEEK_1_SEL                (0xfL<<12)
03672 #define BNX2_CP_CPU_DEBUG_VECT_PEEK_2_VALUE              (0x7ffL<<16)
03673 #define BNX2_CP_CPU_DEBUG_VECT_PEEK_2_PEEK_EN            (1L<<27)
03674 #define BNX2_CP_CPU_DEBUG_VECT_PEEK_2_SEL                (0xfL<<28)
03675 
03676 #define BNX2_CP_CPU_LAST_BRANCH_ADDR                    0x00185048
03677 #define BNX2_CP_CPU_LAST_BRANCH_ADDR_TYPE                (1L<<1)
03678 #define BNX2_CP_CPU_LAST_BRANCH_ADDR_TYPE_JUMP           (0L<<1)
03679 #define BNX2_CP_CPU_LAST_BRANCH_ADDR_TYPE_BRANCH         (1L<<1)
03680 #define BNX2_CP_CPU_LAST_BRANCH_ADDR_LBA                 (0x3fffffffL<<2)
03681 
03682 #define BNX2_CP_CPU_REG_FILE                            0x00185200
03683 #define BNX2_CP_CPQ_FTQ_DATA                            0x001853c0
03684 #define BNX2_CP_CPQ_FTQ_CMD                             0x001853f8
03685 #define BNX2_CP_CPQ_FTQ_CMD_OFFSET                       (0x3ffL<<0)
03686 #define BNX2_CP_CPQ_FTQ_CMD_WR_TOP                       (1L<<10)
03687 #define BNX2_CP_CPQ_FTQ_CMD_WR_TOP_0                     (0L<<10)
03688 #define BNX2_CP_CPQ_FTQ_CMD_WR_TOP_1                     (1L<<10)
03689 #define BNX2_CP_CPQ_FTQ_CMD_SFT_RESET                    (1L<<25)
03690 #define BNX2_CP_CPQ_FTQ_CMD_RD_DATA                      (1L<<26)
03691 #define BNX2_CP_CPQ_FTQ_CMD_ADD_INTERVEN                 (1L<<27)
03692 #define BNX2_CP_CPQ_FTQ_CMD_ADD_DATA                     (1L<<28)
03693 #define BNX2_CP_CPQ_FTQ_CMD_INTERVENE_CLR                (1L<<29)
03694 #define BNX2_CP_CPQ_FTQ_CMD_POP                          (1L<<30)
03695 #define BNX2_CP_CPQ_FTQ_CMD_BUSY                         (1L<<31)
03696 
03697 #define BNX2_CP_CPQ_FTQ_CTL                             0x001853fc
03698 #define BNX2_CP_CPQ_FTQ_CTL_INTERVENE                    (1L<<0)
03699 #define BNX2_CP_CPQ_FTQ_CTL_OVERFLOW                     (1L<<1)
03700 #define BNX2_CP_CPQ_FTQ_CTL_FORCE_INTERVENE              (1L<<2)
03701 #define BNX2_CP_CPQ_FTQ_CTL_MAX_DEPTH                    (0x3ffL<<12)
03702 #define BNX2_CP_CPQ_FTQ_CTL_CUR_DEPTH                    (0x3ffL<<22)
03703 
03704 #define BNX2_CP_SCRATCH                                 0x001a0000
03705 
03706 
03707 /*
03708  *  mcp_reg definition
03709  *  offset: 0x140000
03710  */
03711 #define BNX2_MCP_CPU_MODE                               0x00145000
03712 #define BNX2_MCP_CPU_MODE_LOCAL_RST                      (1L<<0)
03713 #define BNX2_MCP_CPU_MODE_STEP_ENA                       (1L<<1)
03714 #define BNX2_MCP_CPU_MODE_PAGE_0_DATA_ENA                (1L<<2)
03715 #define BNX2_MCP_CPU_MODE_PAGE_0_INST_ENA                (1L<<3)
03716 #define BNX2_MCP_CPU_MODE_MSG_BIT1                       (1L<<6)
03717 #define BNX2_MCP_CPU_MODE_INTERRUPT_ENA                  (1L<<7)
03718 #define BNX2_MCP_CPU_MODE_SOFT_HALT                      (1L<<10)
03719 #define BNX2_MCP_CPU_MODE_BAD_DATA_HALT_ENA              (1L<<11)
03720 #define BNX2_MCP_CPU_MODE_BAD_INST_HALT_ENA              (1L<<12)
03721 #define BNX2_MCP_CPU_MODE_FIO_ABORT_HALT_ENA             (1L<<13)
03722 #define BNX2_MCP_CPU_MODE_SPAD_UNDERFLOW_HALT_ENA        (1L<<15)
03723 
03724 #define BNX2_MCP_CPU_STATE                              0x00145004
03725 #define BNX2_MCP_CPU_STATE_BREAKPOINT                    (1L<<0)
03726 #define BNX2_MCP_CPU_STATE_BAD_INST_HALTED               (1L<<2)
03727 #define BNX2_MCP_CPU_STATE_PAGE_0_DATA_HALTED            (1L<<3)
03728 #define BNX2_MCP_CPU_STATE_PAGE_0_INST_HALTED            (1L<<4)
03729 #define BNX2_MCP_CPU_STATE_BAD_DATA_ADDR_HALTED          (1L<<5)
03730 #define BNX2_MCP_CPU_STATE_BAD_pc_HALTED                 (1L<<6)
03731 #define BNX2_MCP_CPU_STATE_ALIGN_HALTED                  (1L<<7)
03732 #define BNX2_MCP_CPU_STATE_FIO_ABORT_HALTED              (1L<<8)
03733 #define BNX2_MCP_CPU_STATE_SOFT_HALTED                   (1L<<10)
03734 #define BNX2_MCP_CPU_STATE_SPAD_UNDERFLOW                (1L<<11)
03735 #define BNX2_MCP_CPU_STATE_INTERRRUPT                    (1L<<12)
03736 #define BNX2_MCP_CPU_STATE_DATA_ACCESS_STALL             (1L<<14)
03737 #define BNX2_MCP_CPU_STATE_INST_FETCH_STALL              (1L<<15)
03738 #define BNX2_MCP_CPU_STATE_BLOCKED_READ                  (1L<<31)
03739 
03740 #define BNX2_MCP_CPU_EVENT_MASK                         0x00145008
03741 #define BNX2_MCP_CPU_EVENT_MASK_BREAKPOINT_MASK          (1L<<0)
03742 #define BNX2_MCP_CPU_EVENT_MASK_BAD_INST_HALTED_MASK     (1L<<2)
03743 #define BNX2_MCP_CPU_EVENT_MASK_PAGE_0_DATA_HALTED_MASK  (1L<<3)
03744 #define BNX2_MCP_CPU_EVENT_MASK_PAGE_0_INST_HALTED_MASK  (1L<<4)
03745 #define BNX2_MCP_CPU_EVENT_MASK_BAD_DATA_ADDR_HALTED_MASK        (1L<<5)
03746 #define BNX2_MCP_CPU_EVENT_MASK_BAD_PC_HALTED_MASK       (1L<<6)
03747 #define BNX2_MCP_CPU_EVENT_MASK_ALIGN_HALTED_MASK        (1L<<7)
03748 #define BNX2_MCP_CPU_EVENT_MASK_FIO_ABORT_MASK           (1L<<8)
03749 #define BNX2_MCP_CPU_EVENT_MASK_SOFT_HALTED_MASK         (1L<<10)
03750 #define BNX2_MCP_CPU_EVENT_MASK_SPAD_UNDERFLOW_MASK      (1L<<11)
03751 #define BNX2_MCP_CPU_EVENT_MASK_INTERRUPT_MASK           (1L<<12)
03752 
03753 #define BNX2_MCP_CPU_PROGRAM_COUNTER                    0x0014501c
03754 #define BNX2_MCP_CPU_INSTRUCTION                        0x00145020
03755 #define BNX2_MCP_CPU_DATA_ACCESS                        0x00145024
03756 #define BNX2_MCP_CPU_INTERRUPT_ENABLE                   0x00145028
03757 #define BNX2_MCP_CPU_INTERRUPT_VECTOR                   0x0014502c
03758 #define BNX2_MCP_CPU_INTERRUPT_SAVED_PC                 0x00145030
03759 #define BNX2_MCP_CPU_HW_BREAKPOINT                      0x00145034
03760 #define BNX2_MCP_CPU_HW_BREAKPOINT_DISABLE               (1L<<0)
03761 #define BNX2_MCP_CPU_HW_BREAKPOINT_ADDRESS               (0x3fffffffL<<2)
03762 
03763 #define BNX2_MCP_CPU_DEBUG_VECT_PEEK                    0x00145038
03764 #define BNX2_MCP_CPU_DEBUG_VECT_PEEK_1_VALUE             (0x7ffL<<0)
03765 #define BNX2_MCP_CPU_DEBUG_VECT_PEEK_1_PEEK_EN           (1L<<11)
03766 #define BNX2_MCP_CPU_DEBUG_VECT_PEEK_1_SEL               (0xfL<<12)
03767 #define BNX2_MCP_CPU_DEBUG_VECT_PEEK_2_VALUE             (0x7ffL<<16)
03768 #define BNX2_MCP_CPU_DEBUG_VECT_PEEK_2_PEEK_EN           (1L<<27)
03769 #define BNX2_MCP_CPU_DEBUG_VECT_PEEK_2_SEL               (0xfL<<28)
03770 
03771 #define BNX2_MCP_CPU_LAST_BRANCH_ADDR                   0x00145048
03772 #define BNX2_MCP_CPU_LAST_BRANCH_ADDR_TYPE               (1L<<1)
03773 #define BNX2_MCP_CPU_LAST_BRANCH_ADDR_TYPE_JUMP          (0L<<1)
03774 #define BNX2_MCP_CPU_LAST_BRANCH_ADDR_TYPE_BRANCH        (1L<<1)
03775 #define BNX2_MCP_CPU_LAST_BRANCH_ADDR_LBA                (0x3fffffffL<<2)
03776 
03777 #define BNX2_MCP_CPU_REG_FILE                           0x00145200
03778 #define BNX2_MCP_MCPQ_FTQ_DATA                          0x001453c0
03779 #define BNX2_MCP_MCPQ_FTQ_CMD                           0x001453f8
03780 #define BNX2_MCP_MCPQ_FTQ_CMD_OFFSET                     (0x3ffL<<0)
03781 #define BNX2_MCP_MCPQ_FTQ_CMD_WR_TOP                     (1L<<10)
03782 #define BNX2_MCP_MCPQ_FTQ_CMD_WR_TOP_0                   (0L<<10)
03783 #define BNX2_MCP_MCPQ_FTQ_CMD_WR_TOP_1                   (1L<<10)
03784 #define BNX2_MCP_MCPQ_FTQ_CMD_SFT_RESET                  (1L<<25)
03785 #define BNX2_MCP_MCPQ_FTQ_CMD_RD_DATA                    (1L<<26)
03786 #define BNX2_MCP_MCPQ_FTQ_CMD_ADD_INTERVEN               (1L<<27)
03787 #define BNX2_MCP_MCPQ_FTQ_CMD_ADD_DATA                   (1L<<28)
03788 #define BNX2_MCP_MCPQ_FTQ_CMD_INTERVENE_CLR              (1L<<29)
03789 #define BNX2_MCP_MCPQ_FTQ_CMD_POP                        (1L<<30)
03790 #define BNX2_MCP_MCPQ_FTQ_CMD_BUSY                       (1L<<31)
03791 
03792 #define BNX2_MCP_MCPQ_FTQ_CTL                           0x001453fc
03793 #define BNX2_MCP_MCPQ_FTQ_CTL_INTERVENE                  (1L<<0)
03794 #define BNX2_MCP_MCPQ_FTQ_CTL_OVERFLOW                   (1L<<1)
03795 #define BNX2_MCP_MCPQ_FTQ_CTL_FORCE_INTERVENE            (1L<<2)
03796 #define BNX2_MCP_MCPQ_FTQ_CTL_MAX_DEPTH                  (0x3ffL<<12)
03797 #define BNX2_MCP_MCPQ_FTQ_CTL_CUR_DEPTH                  (0x3ffL<<22)
03798 
03799 #define BNX2_MCP_ROM                                    0x00150000
03800 #define BNX2_MCP_SCRATCH                                0x00160000
03801 
03802 #define BNX2_SHM_HDR_SIGNATURE                          BNX2_MCP_SCRATCH
03803 #define BNX2_SHM_HDR_SIGNATURE_SIG_MASK                  0xffff0000
03804 #define BNX2_SHM_HDR_SIGNATURE_SIG                       0x53530000
03805 #define BNX2_SHM_HDR_SIGNATURE_VER_MASK                  0x000000ff
03806 #define BNX2_SHM_HDR_SIGNATURE_VER_ONE                   0x00000001
03807 
03808 #define BNX2_SHM_HDR_ADDR_0                             BNX2_MCP_SCRATCH + 4
03809 #define BNX2_SHM_HDR_ADDR_1                             BNX2_MCP_SCRATCH + 8
03810 
03811 
03812 #define NUM_MC_HASH_REGISTERS   8
03813 
03814 
03815 /* PHY_ID1: bits 31-16; PHY_ID2: bits 15-0.  */
03816 #define PHY_BCM5706_PHY_ID                          0x00206160
03817 
03818 #define PHY_ID(id)                                  ((id) & 0xfffffff0)
03819 #define PHY_REV_ID(id)                              ((id) & 0xf)
03820 
03821 /* 5708 Serdes PHY registers */
03822 
03823 #define BCM5708S_UP1                            0xb
03824 
03825 #define BCM5708S_UP1_2G5                        0x1
03826 
03827 #define BCM5708S_BLK_ADDR                       0x1f
03828 
03829 #define BCM5708S_BLK_ADDR_DIG                   0x0000
03830 #define BCM5708S_BLK_ADDR_DIG3                  0x0002
03831 #define BCM5708S_BLK_ADDR_TX_MISC               0x0005
03832 
03833 /* Digital Block */
03834 #define BCM5708S_1000X_CTL1                     0x10
03835 
03836 #define BCM5708S_1000X_CTL1_FIBER_MODE          0x0001
03837 #define BCM5708S_1000X_CTL1_AUTODET_EN          0x0010
03838 
03839 #define BCM5708S_1000X_CTL2                     0x11
03840 
03841 #define BCM5708S_1000X_CTL2_PLLEL_DET_EN        0x0001
03842 
03843 #define BCM5708S_1000X_STAT1                    0x14
03844 
03845 #define BCM5708S_1000X_STAT1_SGMII              0x0001
03846 #define BCM5708S_1000X_STAT1_LINK               0x0002
03847 #define BCM5708S_1000X_STAT1_FD                 0x0004
03848 #define BCM5708S_1000X_STAT1_SPEED_MASK         0x0018
03849 #define BCM5708S_1000X_STAT1_SPEED_10           0x0000
03850 #define BCM5708S_1000X_STAT1_SPEED_100          0x0008
03851 #define BCM5708S_1000X_STAT1_SPEED_1G           0x0010
03852 #define BCM5708S_1000X_STAT1_SPEED_2G5          0x0018
03853 #define BCM5708S_1000X_STAT1_TX_PAUSE           0x0020
03854 #define BCM5708S_1000X_STAT1_RX_PAUSE           0x0040
03855 
03856 /* Digital3 Block */
03857 #define BCM5708S_DIG_3_0                        0x10
03858 
03859 #define BCM5708S_DIG_3_0_USE_IEEE               0x0001
03860 
03861 /* Tx/Misc Block */
03862 #define BCM5708S_TX_ACTL1                       0x15
03863 
03864 #define BCM5708S_TX_ACTL1_DRIVER_VCM            0x30
03865 
03866 #define BCM5708S_TX_ACTL3                       0x17
03867 
03868 #define MIN_ETHERNET_PACKET_SIZE        60
03869 #define MAX_ETHERNET_PACKET_SIZE        1514
03870 #define MAX_ETHERNET_JUMBO_PACKET_SIZE  9014
03871 
03872 #define RX_COPY_THRESH                  92
03873 
03874 #define DMA_READ_CHANS  5
03875 #define DMA_WRITE_CHANS 3
03876 
03877 #define BCM_PAGE_BITS   12
03878 #define BCM_PAGE_SIZE   (1 << BCM_PAGE_BITS)
03879 
03880 #define TX_DESC_CNT  (BCM_PAGE_SIZE / sizeof(struct tx_bd))
03881 #define MAX_TX_DESC_CNT (TX_DESC_CNT - 1)
03882 
03883 #define MAX_RX_RINGS    4
03884 #define RX_DESC_CNT  (BCM_PAGE_SIZE / sizeof(struct rx_bd))
03885 #define MAX_RX_DESC_CNT (RX_DESC_CNT - 1)
03886 #define MAX_TOTAL_RX_DESC_CNT (MAX_RX_DESC_CNT * MAX_RX_RINGS)
03887 
03888 #define NEXT_TX_BD(x) (((x) & (MAX_TX_DESC_CNT - 1)) ==                 \
03889                 (MAX_TX_DESC_CNT - 1)) ?                                \
03890         (x) + 2 : (x) + 1
03891 
03892 #define PREV_TX_BD(x) ((((x)-1) & (MAX_TX_DESC_CNT)) ==                 \
03893                 (MAX_TX_DESC_CNT)) ?                            \
03894         (x) - 2 : (x) - 1
03895 
03896 #define TX_RING_IDX(x) ((x) & MAX_TX_DESC_CNT)
03897 
03898 #define NEXT_RX_BD(x) (((x) & (MAX_RX_DESC_CNT - 1)) ==                 \
03899                 (MAX_RX_DESC_CNT - 1)) ?                                \
03900         (x) + 2 : (x) + 1
03901 
03902 #define RX_RING_IDX(x) ((x) & bp->rx_max_ring_idx)
03903 
03904 //#define RX_RING(x) (((x) & ~MAX_RX_DESC_CNT) >> 8)
03905 #define RX_IDX(x) ((x) & MAX_RX_DESC_CNT)
03906 
03907 /* Context size. */
03908 #define CTX_SHIFT                   7
03909 #define CTX_SIZE                    (1 << CTX_SHIFT)
03910 #define CTX_MASK                    (CTX_SIZE - 1)
03911 #define GET_CID_ADDR(_cid)          ((_cid) << CTX_SHIFT)
03912 #define GET_CID(_cid_addr)          ((_cid_addr) >> CTX_SHIFT)
03913 
03914 #define PHY_CTX_SHIFT               6
03915 #define PHY_CTX_SIZE                (1 << PHY_CTX_SHIFT)
03916 #define PHY_CTX_MASK                (PHY_CTX_SIZE - 1)
03917 #define GET_PCID_ADDR(_pcid)        ((_pcid) << PHY_CTX_SHIFT)
03918 #define GET_PCID(_pcid_addr)        ((_pcid_addr) >> PHY_CTX_SHIFT)
03919 
03920 #define MB_KERNEL_CTX_SHIFT         8
03921 #define MB_KERNEL_CTX_SIZE          (1 << MB_KERNEL_CTX_SHIFT)
03922 #define MB_KERNEL_CTX_MASK          (MB_KERNEL_CTX_SIZE - 1)
03923 #define MB_GET_CID_ADDR(_cid)       (0x10000 + ((_cid) << MB_KERNEL_CTX_SHIFT))
03924 
03925 #define MAX_CID_CNT                 0x4000
03926 #define MAX_CID_ADDR                (GET_CID_ADDR(MAX_CID_CNT))
03927 #define INVALID_CID_ADDR            0xffffffff
03928 
03929 #define TX_CID          16
03930 #define RX_CID          0
03931 
03932 #define MB_TX_CID_ADDR  MB_GET_CID_ADDR(TX_CID)
03933 #define MB_RX_CID_ADDR  MB_GET_CID_ADDR(RX_CID)
03934 
03935 #if 0
03936 struct sw_bd {
03937         struct sk_buff          *skb;
03938         DECLARE_PCI_UNMAP_ADDR(mapping)
03939 };
03940 #endif
03941 
03942 /* Buffered flash (Atmel: AT45DB011B) specific information */
03943 #define SEEPROM_PAGE_BITS                       2
03944 #define SEEPROM_PHY_PAGE_SIZE                   (1 << SEEPROM_PAGE_BITS)
03945 #define SEEPROM_BYTE_ADDR_MASK                  (SEEPROM_PHY_PAGE_SIZE-1)
03946 #define SEEPROM_PAGE_SIZE                       4
03947 #define SEEPROM_TOTAL_SIZE                      65536
03948 
03949 #define BUFFERED_FLASH_PAGE_BITS                9
03950 #define BUFFERED_FLASH_PHY_PAGE_SIZE            (1 << BUFFERED_FLASH_PAGE_BITS)
03951 #define BUFFERED_FLASH_BYTE_ADDR_MASK           (BUFFERED_FLASH_PHY_PAGE_SIZE-1)
03952 #define BUFFERED_FLASH_PAGE_SIZE                264
03953 #define BUFFERED_FLASH_TOTAL_SIZE               0x21000
03954 
03955 #define SAIFUN_FLASH_PAGE_BITS                  8
03956 #define SAIFUN_FLASH_PHY_PAGE_SIZE              (1 << SAIFUN_FLASH_PAGE_BITS)
03957 #define SAIFUN_FLASH_BYTE_ADDR_MASK             (SAIFUN_FLASH_PHY_PAGE_SIZE-1)
03958 #define SAIFUN_FLASH_PAGE_SIZE                  256
03959 #define SAIFUN_FLASH_BASE_TOTAL_SIZE            65536
03960 
03961 #define ST_MICRO_FLASH_PAGE_BITS                8
03962 #define ST_MICRO_FLASH_PHY_PAGE_SIZE            (1 << ST_MICRO_FLASH_PAGE_BITS)
03963 #define ST_MICRO_FLASH_BYTE_ADDR_MASK           (ST_MICRO_FLASH_PHY_PAGE_SIZE-1)
03964 #define ST_MICRO_FLASH_PAGE_SIZE                256
03965 #define ST_MICRO_FLASH_BASE_TOTAL_SIZE          65536
03966 
03967 #define NVRAM_TIMEOUT_COUNT                     30000
03968 
03969 
03970 #define FLASH_STRAP_MASK                        (BNX2_NVM_CFG1_FLASH_MODE   | \
03971                                                  BNX2_NVM_CFG1_BUFFER_MODE  | \
03972                                                  BNX2_NVM_CFG1_PROTECT_MODE | \
03973                                                  BNX2_NVM_CFG1_FLASH_SIZE)
03974 
03975 #define FLASH_BACKUP_STRAP_MASK                 (0xf << 26)
03976 
03977 struct flash_spec {
03978         u32 strapping;
03979         u32 config1;
03980         u32 config2;
03981         u32 config3;
03982         u32 write1;
03983         u32 buffered;
03984         u32 page_bits;
03985         u32 page_size;
03986         u32 addr_mask;
03987         u32 total_size;
03988         char  *name;
03989 };
03990 
03991 struct bnx2 {
03992         /* Fields used in the tx and intr/napi performance paths are grouped */
03993         /* together in the beginning of the structure. */
03994         void /*__iomem*/                *regview;
03995 
03996         struct nic              *nic;
03997         struct pci_device       *pdev;
03998 
03999         /* atomic_t             intr_sem; */
04000 
04001         struct status_block     *status_blk;
04002         u32                     last_status_idx;
04003 
04004         u32                     flags;
04005 #define PCIX_FLAG                       1
04006 #define PCI_32BIT_FLAG                  2
04007 #define ONE_TDMA_FLAG                   4       /* no longer used */
04008 #define NO_WOL_FLAG                     8
04009 #define USING_DAC_FLAG                  0x10
04010 #define USING_MSI_FLAG                  0x20
04011 #define ASF_ENABLE_FLAG                 0x40
04012 
04013         /* Put tx producer and consumer fields in separate cache lines. */
04014         u32             tx_prod_bseq __attribute__((aligned(L1_CACHE_BYTES)));
04015         u16             tx_prod;
04016 
04017         struct tx_bd    *tx_desc_ring;
04018         struct sw_bd    *tx_buf_ring;
04019         int             tx_ring_size;
04020 
04021         u16             tx_cons __attribute__((aligned(L1_CACHE_BYTES))); 
04022         u16             hw_tx_cons;
04023 
04024 #ifdef BCM_VLAN 
04025         struct                  vlan_group *vlgrp;
04026 #endif
04027 
04028         u32                     rx_offset;
04029         u32                     rx_buf_use_size;        /* useable size */
04030         u32                     rx_buf_size;            /* with alignment */
04031         u32                     rx_max_ring_idx;
04032 
04033         u32                     rx_prod_bseq;
04034         u16                     rx_prod;
04035         u16                     rx_cons;
04036         u16                     hw_rx_cons;
04037 
04038         u32                     rx_csum;
04039 
04040 #if 0
04041         struct rx_bd            *rx_desc_ring[MAX_RX_RINGS];
04042 #endif
04043         struct rx_bd            *rx_desc_ring;
04044 
04045         /* End of fields used in the performance code paths. */
04046 
04047         char                    *name;
04048 
04049 #if 0
04050         int                     timer_interval;
04051         int                     current_interval;
04052         struct                  timer_list timer;
04053         struct work_struct      reset_task;
04054         int                     in_reset_task;
04055 
04056         /* Used to synchronize phy accesses. */
04057         spinlock_t              phy_lock;
04058 #endif
04059 
04060         u32                     phy_flags;
04061 #define PHY_SERDES_FLAG                 1
04062 #define PHY_CRC_FIX_FLAG                2
04063 #define PHY_PARALLEL_DETECT_FLAG        4
04064 #define PHY_2_5G_CAPABLE_FLAG           8
04065 #define PHY_INT_MODE_MASK_FLAG          0x300
04066 #define PHY_INT_MODE_AUTO_POLLING_FLAG  0x100
04067 #define PHY_INT_MODE_LINK_READY_FLAG    0x200
04068 
04069         u32                     chip_id;
04070         /* chip num:16-31, rev:12-15, metal:4-11, bond_id:0-3 */
04071 #define CHIP_NUM(bp)                    (((bp)->chip_id) & 0xffff0000)
04072 #define CHIP_NUM_5706                   0x57060000
04073 #define CHIP_NUM_5708                   0x57080000
04074 
04075 #define CHIP_REV(bp)                    (((bp)->chip_id) & 0x0000f000)
04076 #define CHIP_REV_Ax                     0x00000000
04077 #define CHIP_REV_Bx                     0x00001000
04078 #define CHIP_REV_Cx                     0x00002000
04079     
04080 #define CHIP_METAL(bp)                  (((bp)->chip_id) & 0x00000ff0)
04081 #define CHIP_BONDING(bp)                (((bp)->chip_id) & 0x0000000f)
04082 
04083 #define CHIP_ID(bp)                     (((bp)->chip_id) & 0xfffffff0)
04084 #define CHIP_ID_5706_A0                 0x57060000
04085 #define CHIP_ID_5706_A1                 0x57060010
04086 #define CHIP_ID_5706_A2                 0x57060020
04087 #define CHIP_ID_5708_A0                 0x57080000
04088 #define CHIP_ID_5708_B0                 0x57081000
04089 #define CHIP_ID_5708_B1                 0x57081010
04090 
04091 #define CHIP_BOND_ID(bp)                (((bp)->chip_id) & 0xf)
04092 
04093 /* A serdes chip will have the first bit of the bond id set. */
04094 #define CHIP_BOND_ID_SERDES_BIT         0x01
04095 
04096         u32                     phy_addr;
04097         u32                     phy_id;
04098         
04099         u16                     bus_speed_mhz;
04100         u8                      wol;
04101 
04102         u8                      pad;
04103 
04104         u16                     fw_wr_seq;
04105         u16                     fw_drv_pulse_wr_seq;
04106 
04107         dma_addr_t              tx_desc_mapping;
04108 
04109 
04110         int                     rx_max_ring;
04111         int                     rx_ring_size;
04112 #if 0
04113         dma_addr_t              rx_desc_mapping[MAX_RX_RINGS];
04114 #endif
04115         dma_addr_t              rx_desc_mapping;
04116 
04117         u16                     tx_quick_cons_trip;
04118         u16                     tx_quick_cons_trip_int;
04119         u16                     rx_quick_cons_trip;
04120         u16                     rx_quick_cons_trip_int;
04121         u16                     comp_prod_trip;
04122         u16                     comp_prod_trip_int;
04123         u16                     tx_ticks;
04124         u16                     tx_ticks_int;
04125         u16                     com_ticks;
04126         u16                     com_ticks_int;
04127         u16                     cmd_ticks;
04128         u16                     cmd_ticks_int;
04129         u16                     rx_ticks;
04130         u16                     rx_ticks_int;
04131 
04132         u32                     stats_ticks;
04133 
04134         dma_addr_t              status_blk_mapping;
04135 
04136         struct statistics_block *stats_blk;
04137         dma_addr_t              stats_blk_mapping;
04138 
04139         u32                     hc_cmd;
04140         u32                     rx_mode;
04141 
04142         u16                     req_line_speed;
04143         u8                      req_duplex;
04144 
04145         u8                      link_up;
04146 
04147         u16                     line_speed;
04148         u8                      duplex;
04149         u8                      flow_ctrl;      /* actual flow ctrl settings */
04150                                                 /* may be different from     */
04151                                                 /* req_flow_ctrl if autoneg  */
04152 #define FLOW_CTRL_TX            1
04153 #define FLOW_CTRL_RX            2
04154 
04155         u32                     advertising;
04156 
04157         u8                      req_flow_ctrl;  /* flow ctrl advertisement */ 
04158                                                 /* settings or forced      */
04159                                                 /* settings                */
04160         u8                      autoneg;
04161 #define AUTONEG_SPEED           1
04162 #define AUTONEG_FLOW_CTRL       2
04163 
04164         u8                      loopback;
04165 #define MAC_LOOPBACK            1
04166 #define PHY_LOOPBACK            2
04167 
04168         u8                      serdes_an_pending;
04169 #define SERDES_AN_TIMEOUT       (HZ / 3)
04170 
04171         u8                      mac_addr[8];
04172 
04173         u32                     shmem_base;
04174 
04175         u32                     fw_ver;
04176 
04177         int                     pm_cap;
04178         int                     pcix_cap;
04179 
04180         /* struct net_device_stats net_stats; */
04181 
04182         struct flash_spec       *flash_info;
04183         u32                     flash_size;
04184 
04185         int                     status_stats_size;
04186 };
04187 
04188 static u32 bnx2_reg_rd_ind(struct bnx2 *bp, u32 offset);
04189 static void bnx2_reg_wr_ind(struct bnx2 *bp, u32 offset, u32 val);
04190 
04191 #define REG_RD(bp, offset)                                      \
04192         readl(bp->regview + offset)
04193 
04194 #define REG_WR(bp, offset, val)                                 \
04195         writel(val, bp->regview + offset)
04196 
04197 #define REG_WR16(bp, offset, val)                               \
04198         writew(val, bp->regview + offset)
04199 
04200 #define REG_RD_IND(bp, offset)                                  \
04201         bnx2_reg_rd_ind(bp, offset)
04202 
04203 #define REG_WR_IND(bp, offset, val)                             \
04204         bnx2_reg_wr_ind(bp, offset, val)
04205 
04206 /* Indirect context access.  Unlike the MBQ_WR, these macros will not
04207  * trigger a chip event. */
04208 static void bnx2_ctx_wr(struct bnx2 *bp, u32 cid_addr, u32 offset, u32 val);
04209 
04210 #define CTX_WR(bp, cid_addr, offset, val)                       \
04211         bnx2_ctx_wr(bp, cid_addr, offset, val)
04212 
04213 struct cpu_reg {
04214         u32 mode;
04215         u32 mode_value_halt;
04216         u32 mode_value_sstep;
04217 
04218         u32 state;
04219         u32 state_value_clear;
04220 
04221         u32 gpr0;
04222         u32 evmask;
04223         u32 pc;
04224         u32 inst;
04225         u32 bp;
04226 
04227         u32 spad_base;
04228 
04229         u32 mips_view_base;
04230 };
04231 
04232 struct fw_info {
04233         u32 ver_major;
04234         u32 ver_minor;
04235         u32 ver_fix;
04236 
04237         u32 start_addr;
04238 
04239         /* Text section. */
04240         u32 text_addr;
04241         u32 text_len;
04242         u32 text_index;
04243         u32 *text;
04244 
04245         /* Data section. */
04246         u32 data_addr;
04247         u32 data_len;
04248         u32 data_index;
04249         u32 *data;
04250 
04251         /* SBSS section. */
04252         u32 sbss_addr;
04253         u32 sbss_len;
04254         u32 sbss_index;
04255         u32 *sbss;
04256 
04257         /* BSS section. */
04258         u32 bss_addr;
04259         u32 bss_len;
04260         u32 bss_index;
04261         u32 *bss;
04262 
04263         /* Read-only section. */
04264         u32 rodata_addr;
04265         u32 rodata_len;
04266         u32 rodata_index;
04267         u32 *rodata;
04268 };
04269 
04270 #define RV2P_PROC1                              0
04271 #define RV2P_PROC2                              1
04272 
04273 
04274 /* This value (in milliseconds) determines the frequency of the driver
04275  * issuing the PULSE message code.  The firmware monitors this periodic
04276  * pulse to determine when to switch to an OS-absent mode. */
04277 #define DRV_PULSE_PERIOD_MS                 250
04278 
04279 /* This value (in milliseconds) determines how long the driver should
04280  * wait for an acknowledgement from the firmware before timing out.  Once
04281  * the firmware has timed out, the driver will assume there is no firmware
04282  * running and there won't be any firmware-driver synchronization during a
04283  * driver reset. */
04284 #define FW_ACK_TIME_OUT_MS                  100
04285 
04286 
04287 #define BNX2_DRV_RESET_SIGNATURE                0x00000000
04288 #define BNX2_DRV_RESET_SIGNATURE_MAGIC           0x4841564b /* HAVK */
04289 //#define DRV_RESET_SIGNATURE_MAGIC              0x47495352 /* RSIG */
04290 
04291 #define BNX2_DRV_MB                             0x00000004
04292 #define BNX2_DRV_MSG_CODE                        0xff000000
04293 #define BNX2_DRV_MSG_CODE_RESET                  0x01000000
04294 #define BNX2_DRV_MSG_CODE_UNLOAD                 0x02000000
04295 #define BNX2_DRV_MSG_CODE_SHUTDOWN               0x03000000
04296 #define BNX2_DRV_MSG_CODE_SUSPEND_WOL            0x04000000
04297 #define BNX2_DRV_MSG_CODE_FW_TIMEOUT             0x05000000
04298 #define BNX2_DRV_MSG_CODE_PULSE                  0x06000000
04299 #define BNX2_DRV_MSG_CODE_DIAG                   0x07000000
04300 #define BNX2_DRV_MSG_CODE_SUSPEND_NO_WOL         0x09000000
04301 
04302 #define BNX2_DRV_MSG_DATA                        0x00ff0000
04303 #define BNX2_DRV_MSG_DATA_WAIT0                  0x00010000
04304 #define BNX2_DRV_MSG_DATA_WAIT1                  0x00020000
04305 #define BNX2_DRV_MSG_DATA_WAIT2                  0x00030000
04306 #define BNX2_DRV_MSG_DATA_WAIT3                  0x00040000
04307         
04308 #define BNX2_DRV_MSG_SEQ                         0x0000ffff
04309 
04310 #define BNX2_FW_MB                              0x00000008
04311 #define BNX2_FW_MSG_ACK                          0x0000ffff
04312 #define BNX2_FW_MSG_STATUS_MASK                  0x00ff0000
04313 #define BNX2_FW_MSG_STATUS_OK                    0x00000000
04314 #define BNX2_FW_MSG_STATUS_FAILURE               0x00ff0000
04315 
04316 #define BNX2_LINK_STATUS                        0x0000000c
04317 #define BNX2_LINK_STATUS_INIT_VALUE              0xffffffff 
04318 #define BNX2_LINK_STATUS_LINK_UP                 0x1 
04319 #define BNX2_LINK_STATUS_LINK_DOWN               0x0 
04320 #define BNX2_LINK_STATUS_SPEED_MASK              0x1e
04321 #define BNX2_LINK_STATUS_AN_INCOMPLETE           (0<<1) 
04322 #define BNX2_LINK_STATUS_10HALF                  (1<<1) 
04323 #define BNX2_LINK_STATUS_10FULL                  (2<<1) 
04324 #define BNX2_LINK_STATUS_100HALF                 (3<<1) 
04325 #define BNX2_LINK_STATUS_100BASE_T4              (4<<1) 
04326 #define BNX2_LINK_STATUS_100FULL                 (5<<1) 
04327 #define BNX2_LINK_STATUS_1000HALF                (6<<1) 
04328 #define BNX2_LINK_STATUS_1000FULL                (7<<1) 
04329 #define BNX2_LINK_STATUS_2500HALF                (8<<1) 
04330 #define BNX2_LINK_STATUS_2500FULL                (9<<1) 
04331 #define BNX2_LINK_STATUS_AN_ENABLED              (1<<5) 
04332 #define BNX2_LINK_STATUS_AN_COMPLETE             (1<<6) 
04333 #define BNX2_LINK_STATUS_PARALLEL_DET            (1<<7) 
04334 #define BNX2_LINK_STATUS_RESERVED                (1<<8) 
04335 #define BNX2_LINK_STATUS_PARTNER_AD_1000FULL     (1<<9) 
04336 #define BNX2_LINK_STATUS_PARTNER_AD_1000HALF     (1<<10) 
04337 #define BNX2_LINK_STATUS_PARTNER_AD_100BT4       (1<<11) 
04338 #define BNX2_LINK_STATUS_PARTNER_AD_100FULL      (1<<12) 
04339 #define BNX2_LINK_STATUS_PARTNER_AD_100HALF      (1<<13) 
04340 #define BNX2_LINK_STATUS_PARTNER_AD_10FULL       (1<<14) 
04341 #define BNX2_LINK_STATUS_PARTNER_AD_10HALF       (1<<15) 
04342 #define BNX2_LINK_STATUS_TX_FC_ENABLED           (1<<16) 
04343 #define BNX2_LINK_STATUS_RX_FC_ENABLED           (1<<17) 
04344 #define BNX2_LINK_STATUS_PARTNER_SYM_PAUSE_CAP   (1<<18) 
04345 #define BNX2_LINK_STATUS_PARTNER_ASYM_PAUSE_CAP  (1<<19) 
04346 #define BNX2_LINK_STATUS_SERDES_LINK             (1<<20) 
04347 #define BNX2_LINK_STATUS_PARTNER_AD_2500FULL     (1<<21) 
04348 #define BNX2_LINK_STATUS_PARTNER_AD_2500HALF     (1<<22) 
04349 
04350 #define BNX2_DRV_PULSE_MB                       0x00000010
04351 #define BNX2_DRV_PULSE_SEQ_MASK                  0x00007fff
04352 
04353 /* Indicate to the firmware not to go into the
04354  * OS absent when it is not getting driver pulse.
04355  * This is used for debugging. */
04356 #define BNX2_DRV_MSG_DATA_PULSE_CODE_ALWAYS_ALIVE        0x00080000
04357 
04358 #define BNX2_DEV_INFO_SIGNATURE                 0x00000020
04359 #define BNX2_DEV_INFO_SIGNATURE_MAGIC            0x44564900
04360 #define BNX2_DEV_INFO_SIGNATURE_MAGIC_MASK       0xffffff00
04361 #define BNX2_DEV_INFO_FEATURE_CFG_VALID          0x01
04362 #define BNX2_DEV_INFO_SECONDARY_PORT             0x80
04363 #define BNX2_DEV_INFO_DRV_ALWAYS_ALIVE           0x40
04364 
04365 #define BNX2_SHARED_HW_CFG_PART_NUM             0x00000024
04366 
04367 #define BNX2_SHARED_HW_CFG_POWER_DISSIPATED     0x00000034
04368 #define BNX2_SHARED_HW_CFG_POWER_STATE_D3_MASK   0xff000000
04369 #define BNX2_SHARED_HW_CFG_POWER_STATE_D2_MASK   0xff0000
04370 #define BNX2_SHARED_HW_CFG_POWER_STATE_D1_MASK   0xff00
04371 #define BNX2_SHARED_HW_CFG_POWER_STATE_D0_MASK   0xff
04372 
04373 #define BNX2_SHARED_HW_CFG POWER_CONSUMED       0x00000038
04374 #define BNX2_SHARED_HW_CFG_CONFIG               0x0000003c
04375 #define BNX2_SHARED_HW_CFG_DESIGN_NIC            0
04376 #define BNX2_SHARED_HW_CFG_DESIGN_LOM            0x1
04377 #define BNX2_SHARED_HW_CFG_PHY_COPPER            0
04378 #define BNX2_SHARED_HW_CFG_PHY_FIBER             0x2
04379 #define BNX2_SHARED_HW_CFG_PHY_2_5G              0x20
04380 #define BNX2_SHARED_HW_CFG_PHY_BACKPLANE         0x40
04381 #define BNX2_SHARED_HW_CFG_LED_MODE_SHIFT_BITS   8
04382 #define BNX2_SHARED_HW_CFG_LED_MODE_MASK         0x300
04383 #define BNX2_SHARED_HW_CFG_LED_MODE_MAC          0
04384 #define BNX2_SHARED_HW_CFG_LED_MODE_GPHY1        0x100
04385 #define BNX2_SHARED_HW_CFG_LED_MODE_GPHY2        0x200
04386 
04387 #define BNX2_SHARED_HW_CFG_CONFIG2              0x00000040
04388 #define BNX2_SHARED_HW_CFG2_NVM_SIZE_MASK        0x00fff000
04389 
04390 #define BNX2_DEV_INFO_BC_REV                    0x0000004c
04391 
04392 #define BNX2_PORT_HW_CFG_MAC_UPPER              0x00000050
04393 #define BNX2_PORT_HW_CFG_UPPERMAC_MASK           0xffff
04394 
04395 #define BNX2_PORT_HW_CFG_MAC_LOWER              0x00000054
04396 #define BNX2_PORT_HW_CFG_CONFIG                 0x00000058
04397 #define BNX2_PORT_HW_CFG_CFG_TXCTL3_MASK         0x0000ffff
04398 #define BNX2_PORT_HW_CFG_CFG_DFLT_LINK_MASK      0x001f0000
04399 #define BNX2_PORT_HW_CFG_CFG_DFLT_LINK_AN        0x00000000
04400 #define BNX2_PORT_HW_CFG_CFG_DFLT_LINK_1G        0x00030000
04401 #define BNX2_PORT_HW_CFG_CFG_DFLT_LINK_2_5G      0x00040000
04402 
04403 #define BNX2_PORT_HW_CFG_IMD_MAC_A_UPPER        0x00000068
04404 #define BNX2_PORT_HW_CFG_IMD_MAC_A_LOWER        0x0000006c
04405 #define BNX2_PORT_HW_CFG_IMD_MAC_B_UPPER        0x00000070
04406 #define BNX2_PORT_HW_CFG_IMD_MAC_B_LOWER        0x00000074
04407 #define BNX2_PORT_HW_CFG_ISCSI_MAC_UPPER        0x00000078
04408 #define BNX2_PORT_HW_CFG_ISCSI_MAC_LOWER        0x0000007c
04409 
04410 #define BNX2_DEV_INFO_PER_PORT_HW_CONFIG2       0x000000b4
04411 
04412 #define BNX2_DEV_INFO_FORMAT_REV                0x000000c4
04413 #define BNX2_DEV_INFO_FORMAT_REV_MASK            0xff000000
04414 #define BNX2_DEV_INFO_FORMAT_REV_ID              ('A' << 24)
04415 
04416 #define BNX2_SHARED_FEATURE                     0x000000c8
04417 #define BNX2_SHARED_FEATURE_MASK                 0xffffffff
04418 
04419 #define BNX2_PORT_FEATURE                       0x000000d8
04420 #define BNX2_PORT2_FEATURE                      0x00000014c
04421 #define BNX2_PORT_FEATURE_WOL_ENABLED            0x01000000
04422 #define BNX2_PORT_FEATURE_MBA_ENABLED            0x02000000
04423 #define BNX2_PORT_FEATURE_ASF_ENABLED            0x04000000
04424 #define BNX2_PORT_FEATURE_IMD_ENABLED            0x08000000
04425 #define BNX2_PORT_FEATURE_BAR1_SIZE_MASK         0xf
04426 #define BNX2_PORT_FEATURE_BAR1_SIZE_DISABLED     0x0
04427 #define BNX2_PORT_FEATURE_BAR1_SIZE_64K          0x1
04428 #define BNX2_PORT_FEATURE_BAR1_SIZE_128K         0x2
04429 #define BNX2_PORT_FEATURE_BAR1_SIZE_256K         0x3
04430 #define BNX2_PORT_FEATURE_BAR1_SIZE_512K         0x4
04431 #define BNX2_PORT_FEATURE_BAR1_SIZE_1M           0x5
04432 #define BNX2_PORT_FEATURE_BAR1_SIZE_2M           0x6
04433 #define BNX2_PORT_FEATURE_BAR1_SIZE_4M           0x7
04434 #define BNX2_PORT_FEATURE_BAR1_SIZE_8M           0x8
04435 #define BNX2_PORT_FEATURE_BAR1_SIZE_16M          0x9
04436 #define BNX2_PORT_FEATURE_BAR1_SIZE_32M          0xa
04437 #define BNX2_PORT_FEATURE_BAR1_SIZE_64M          0xb
04438 #define BNX2_PORT_FEATURE_BAR1_SIZE_128M         0xc
04439 #define BNX2_PORT_FEATURE_BAR1_SIZE_256M         0xd
04440 #define BNX2_PORT_FEATURE_BAR1_SIZE_512M         0xe
04441 #define BNX2_PORT_FEATURE_BAR1_SIZE_1G           0xf
04442 
04443 #define BNX2_PORT_FEATURE_WOL                   0xdc
04444 #define BNX2_PORT2_FEATURE_WOL                  0x150
04445 #define BNX2_PORT_FEATURE_WOL_DEFAULT_SHIFT_BITS         4
04446 #define BNX2_PORT_FEATURE_WOL_DEFAULT_MASK       0x30
04447 #define BNX2_PORT_FEATURE_WOL_DEFAULT_DISABLE    0
04448 #define BNX2_PORT_FEATURE_WOL_DEFAULT_MAGIC      0x10
04449 #define BNX2_PORT_FEATURE_WOL_DEFAULT_ACPI       0x20
04450 #define BNX2_PORT_FEATURE_WOL_DEFAULT_MAGIC_AND_ACPI     0x30
04451 #define BNX2_PORT_FEATURE_WOL_LINK_SPEED_MASK    0xf
04452 #define BNX2_PORT_FEATURE_WOL_LINK_SPEED_AUTONEG         0
04453 #define BNX2_PORT_FEATURE_WOL_LINK_SPEED_10HALF  1
04454 #define BNX2_PORT_FEATURE_WOL_LINK_SPEED_10FULL  2
04455 #define BNX2_PORT_FEATURE_WOL_LINK_SPEED_100HALF 3
04456 #define BNX2_PORT_FEATURE_WOL_LINK_SPEED_100FULL 4
04457 #define BNX2_PORT_FEATURE_WOL_LINK_SPEED_1000HALF        5
04458 #define BNX2_PORT_FEATURE_WOL_LINK_SPEED_1000FULL        6
04459 #define BNX2_PORT_FEATURE_WOL_AUTONEG_ADVERTISE_1000     0x40
04460 #define BNX2_PORT_FEATURE_WOL_RESERVED_PAUSE_CAP 0x400
04461 #define BNX2_PORT_FEATURE_WOL_RESERVED_ASYM_PAUSE_CAP    0x800
04462 
04463 #define BNX2_PORT_FEATURE_MBA                   0xe0
04464 #define BNX2_PORT2_FEATURE_MBA                  0x154
04465 #define BNX2_PORT_FEATURE_MBA_BOOT_AGENT_TYPE_SHIFT_BITS         0
04466 #define BNX2_PORT_FEATURE_MBA_BOOT_AGENT_TYPE_MASK       0x3
04467 #define BNX2_PORT_FEATURE_MBA_BOOT_AGENT_TYPE_PXE        0
04468 #define BNX2_PORT_FEATURE_MBA_BOOT_AGENT_TYPE_RPL        1
04469 #define BNX2_PORT_FEATURE_MBA_BOOT_AGENT_TYPE_BOOTP      2
04470 #define BNX2_PORT_FEATURE_MBA_LINK_SPEED_SHIFT_BITS      2
04471 #define BNX2_PORT_FEATURE_MBA_LINK_SPEED_MASK    0x3c
04472 #define BNX2_PORT_FEATURE_MBA_LINK_SPEED_AUTONEG         0
04473 #define BNX2_PORT_FEATURE_MBA_LINK_SPEED_10HALF  0x4
04474 #define BNX2_PORT_FEATURE_MBA_LINK_SPEED_10FULL  0x8
04475 #define BNX2_PORT_FEATURE_MBA_LINK_SPEED_100HALF         0xc
04476 #define BNX2_PORT_FEATURE_MBA_LINK_SPEED_100FULL         0x10
04477 #define BNX2_PORT_FEATURE_MBA_LINK_SPEED_1000HALF        0x14
04478 #define BNX2_PORT_FEATURE_MBA_LINK_SPEED_1000FULL        0x18
04479 #define BNX2_PORT_FEATURE_MBA_SETUP_PROMPT_ENABLE        0x40
04480 #define BNX2_PORT_FEATURE_MBA_HOTKEY_CTRL_S      0
04481 #define BNX2_PORT_FEATURE_MBA_HOTKEY_CTRL_B      0x80
04482 #define BNX2_PORT_FEATURE_MBA_EXP_ROM_SIZE_SHIFT_BITS    8
04483 #define BNX2_PORT_FEATURE_MBA_EXP_ROM_SIZE_MASK  0xff00
04484 #define BNX2_PORT_FEATURE_MBA_EXP_ROM_SIZE_DISABLED      0
04485 #define BNX2_PORT_FEATURE_MBA_EXP_ROM_SIZE_1K    0x100
04486 #define BNX2_PORT_FEATURE_MBA_EXP_ROM_SIZE_2K    0x200
04487 #define BNX2_PORT_FEATURE_MBA_EXP_ROM_SIZE_4K    0x300
04488 #define BNX2_PORT_FEATURE_MBA_EXP_ROM_SIZE_8K    0x400
04489 #define BNX2_PORT_FEATURE_MBA_EXP_ROM_SIZE_16K   0x500
04490 #define BNX2_PORT_FEATURE_MBA_EXP_ROM_SIZE_32K   0x600
04491 #define BNX2_PORT_FEATURE_MBA_EXP_ROM_SIZE_64K   0x700
04492 #define BNX2_PORT_FEATURE_MBA_EXP_ROM_SIZE_128K  0x800
04493 #define BNX2_PORT_FEATURE_MBA_EXP_ROM_SIZE_256K  0x900
04494 #define BNX2_PORT_FEATURE_MBA_EXP_ROM_SIZE_512K  0xa00
04495 #define BNX2_PORT_FEATURE_MBA_EXP_ROM_SIZE_1M    0xb00
04496 #define BNX2_PORT_FEATURE_MBA_EXP_ROM_SIZE_2M    0xc00
04497 #define BNX2_PORT_FEATURE_MBA_EXP_ROM_SIZE_4M    0xd00
04498 #define BNX2_PORT_FEATURE_MBA_EXP_ROM_SIZE_8M    0xe00
04499 #define BNX2_PORT_FEATURE_MBA_EXP_ROM_SIZE_16M   0xf00
04500 #define BNX2_PORT_FEATURE_MBA_MSG_TIMEOUT_SHIFT_BITS     16
04501 #define BNX2_PORT_FEATURE_MBA_MSG_TIMEOUT_MASK   0xf0000
04502 #define BNX2_PORT_FEATURE_MBA_BIOS_BOOTSTRAP_SHIFT_BITS  20
04503 #define BNX2_PORT_FEATURE_MBA_BIOS_BOOTSTRAP_MASK        0x300000
04504 #define BNX2_PORT_FEATURE_MBA_BIOS_BOOTSTRAP_AUTO        0
04505 #define BNX2_PORT_FEATURE_MBA_BIOS_BOOTSTRAP_BBS         0x100000
04506 #define BNX2_PORT_FEATURE_MBA_BIOS_BOOTSTRAP_INT18H      0x200000
04507 #define BNX2_PORT_FEATURE_MBA_BIOS_BOOTSTRAP_INT19H      0x300000
04508 
04509 #define BNX2_PORT_FEATURE_IMD                   0xe4
04510 #define BNX2_PORT2_FEATURE_IMD                  0x158
04511 #define BNX2_PORT_FEATURE_IMD_LINK_OVERRIDE_DEFAULT      0
04512 #define BNX2_PORT_FEATURE_IMD_LINK_OVERRIDE_ENABLE       1
04513 
04514 #define BNX2_PORT_FEATURE_VLAN                  0xe8
04515 #define BNX2_PORT2_FEATURE_VLAN                 0x15c
04516 #define BNX2_PORT_FEATURE_MBA_VLAN_TAG_MASK      0xffff
04517 #define BNX2_PORT_FEATURE_MBA_VLAN_ENABLE        0x10000
04518 
04519 #define BNX2_BC_STATE_RESET_TYPE                0x000001c0
04520 #define BNX2_BC_STATE_RESET_TYPE_SIG             0x00005254
04521 #define BNX2_BC_STATE_RESET_TYPE_SIG_MASK        0x0000ffff
04522 #define BNX2_BC_STATE_RESET_TYPE_NONE    (BNX2_BC_STATE_RESET_TYPE_SIG | \
04523                                           0x00010000)
04524 #define BNX2_BC_STATE_RESET_TYPE_PCI     (BNX2_BC_STATE_RESET_TYPE_SIG | \
04525                                           0x00020000)
04526 #define BNX2_BC_STATE_RESET_TYPE_VAUX    (BNX2_BC_STATE_RESET_TYPE_SIG | \
04527                                           0x00030000)
04528 #define BNX2_BC_STATE_RESET_TYPE_DRV_MASK        DRV_MSG_CODE         
04529 #define BNX2_BC_STATE_RESET_TYPE_DRV_RESET (BNX2_BC_STATE_RESET_TYPE_SIG | \
04530                                             DRV_MSG_CODE_RESET)
04531 #define BNX2_BC_STATE_RESET_TYPE_DRV_UNLOAD (BNX2_BC_STATE_RESET_TYPE_SIG | \
04532                                              DRV_MSG_CODE_UNLOAD)
04533 #define BNX2_BC_STATE_RESET_TYPE_DRV_SHUTDOWN (BNX2_BC_STATE_RESET_TYPE_SIG | \
04534                                                DRV_MSG_CODE_SHUTDOWN)
04535 #define BNX2_BC_STATE_RESET_TYPE_DRV_WOL (BNX2_BC_STATE_RESET_TYPE_SIG | \
04536                                           DRV_MSG_CODE_WOL)
04537 #define BNX2_BC_STATE_RESET_TYPE_DRV_DIAG (BNX2_BC_STATE_RESET_TYPE_SIG | \
04538                                            DRV_MSG_CODE_DIAG)
04539 #define BNX2_BC_STATE_RESET_TYPE_VALUE(msg) (BNX2_BC_STATE_RESET_TYPE_SIG | \
04540                                              (msg))
04541 
04542 #define BNX2_BC_STATE                           0x000001c4
04543 #define BNX2_BC_STATE_ERR_MASK                   0x0000ff00
04544 #define BNX2_BC_STATE_SIGN                       0x42530000
04545 #define BNX2_BC_STATE_SIGN_MASK                  0xffff0000
04546 #define BNX2_BC_STATE_BC1_START                  (BNX2_BC_STATE_SIGN | 0x1)
04547 #define BNX2_BC_STATE_GET_NVM_CFG1               (BNX2_BC_STATE_SIGN | 0x2)
04548 #define BNX2_BC_STATE_PROG_BAR                   (BNX2_BC_STATE_SIGN | 0x3)
04549 #define BNX2_BC_STATE_INIT_VID                   (BNX2_BC_STATE_SIGN | 0x4)
04550 #define BNX2_BC_STATE_GET_NVM_CFG2               (BNX2_BC_STATE_SIGN | 0x5)
04551 #define BNX2_BC_STATE_APPLY_WKARND               (BNX2_BC_STATE_SIGN | 0x6)
04552 #define BNX2_BC_STATE_LOAD_BC2                   (BNX2_BC_STATE_SIGN | 0x7)
04553 #define BNX2_BC_STATE_GOING_BC2                  (BNX2_BC_STATE_SIGN | 0x8)
04554 #define BNX2_BC_STATE_GOING_DIAG                 (BNX2_BC_STATE_SIGN | 0x9)
04555 #define BNX2_BC_STATE_RT_FINAL_INIT              (BNX2_BC_STATE_SIGN | 0x81)
04556 #define BNX2_BC_STATE_RT_WKARND                  (BNX2_BC_STATE_SIGN | 0x82)
04557 #define BNX2_BC_STATE_RT_DRV_PULSE               (BNX2_BC_STATE_SIGN | 0x83)
04558 #define BNX2_BC_STATE_RT_FIOEVTS                 (BNX2_BC_STATE_SIGN | 0x84)
04559 #define BNX2_BC_STATE_RT_DRV_CMD                 (BNX2_BC_STATE_SIGN | 0x85)
04560 #define BNX2_BC_STATE_RT_LOW_POWER               (BNX2_BC_STATE_SIGN | 0x86)
04561 #define BNX2_BC_STATE_RT_SET_WOL                 (BNX2_BC_STATE_SIGN | 0x87)
04562 #define BNX2_BC_STATE_RT_OTHER_FW                (BNX2_BC_STATE_SIGN | 0x88)
04563 #define BNX2_BC_STATE_RT_GOING_D3                (BNX2_BC_STATE_SIGN | 0x89)
04564 #define BNX2_BC_STATE_ERR_BAD_VERSION            (BNX2_BC_STATE_SIGN | 0x0100)
04565 #define BNX2_BC_STATE_ERR_BAD_BC2_CRC            (BNX2_BC_STATE_SIGN | 0x0200)
04566 #define BNX2_BC_STATE_ERR_BC1_LOOP               (BNX2_BC_STATE_SIGN | 0x0300)
04567 #define BNX2_BC_STATE_ERR_UNKNOWN_CMD            (BNX2_BC_STATE_SIGN | 0x0400)
04568 #define BNX2_BC_STATE_ERR_DRV_DEAD               (BNX2_BC_STATE_SIGN | 0x0500)
04569 #define BNX2_BC_STATE_ERR_NO_RXP                 (BNX2_BC_STATE_SIGN | 0x0600)
04570 #define BNX2_BC_STATE_ERR_TOO_MANY_RBUF          (BNX2_BC_STATE_SIGN | 0x0700)
04571         
04572 #define BNX2_BC_STATE_DEBUG_CMD                 0x1dc
04573 #define BNX2_BC_STATE_BC_DBG_CMD_SIGNATURE       0x42440000
04574 #define BNX2_BC_STATE_BC_DBG_CMD_SIGNATURE_MASK  0xffff0000
04575 #define BNX2_BC_STATE_BC_DBG_CMD_LOOP_CNT_MASK   0xffff
04576 #define BNX2_BC_STATE_BC_DBG_CMD_LOOP_INFINITE   0xffff
04577 
04578 #define HOST_VIEW_SHMEM_BASE                    0x167c00
04579 
04580 /* Enable or disable autonegotiation.  If this is set to enable,
04581  * the forced link modes above are completely ignored.
04582  */
04583 #define AUTONEG_DISABLE         0x00
04584 #define AUTONEG_ENABLE          0x01
04585 
04586 #define RX_OFFSET               (sizeof(struct l2_fhdr) + 2)
04587 
04588 #define RX_BUF_CNT              20
04589 
04590 /* 8 for CRC and VLAN */
04591 #define RX_BUF_USE_SIZE         (ETH_MAX_MTU + ETH_HLEN + RX_OFFSET + 8)
04592 
04593 /* 8 for alignment */
04594 //#define RX_BUF_SIZE           (RX_BUF_USE_SIZE + 8)
04595 #define RX_BUF_SIZE             (L1_CACHE_ALIGN(RX_BUF_USE_SIZE + 8))
04596 
04597 
04598 #endif