iPXE
exanic.h
Go to the documentation of this file.
00001 #ifndef _EXANIC_H
00002 #define _EXANIC_H
00003 
00004 /** @file
00005  *
00006  * Exablaze ExaNIC driver
00007  *
00008  */
00009 
00010 FILE_LICENCE ( GPL2_OR_LATER_OR_UBDL );
00011 
00012 #include <stdint.h>
00013 #include <ipxe/pci.h>
00014 #include <ipxe/ethernet.h>
00015 #include <ipxe/uaccess.h>
00016 #include <ipxe/retry.h>
00017 #include <ipxe/i2c.h>
00018 #include <ipxe/bitbash.h>
00019 
00020 /** Maximum number of ports */
00021 #define EXANIC_MAX_PORTS 8
00022 
00023 /** Register BAR */
00024 #define EXANIC_REGS_BAR PCI_BASE_ADDRESS_0
00025 
00026 /** Transmit region BAR */
00027 #define EXANIC_TX_BAR PCI_BASE_ADDRESS_2
00028 
00029 /** Alignment for DMA regions */
00030 #define EXANIC_ALIGN 0x1000
00031 
00032 /** Flag for 32-bit DMA addresses */
00033 #define EXANIC_DMA_32_BIT 0x00000001UL
00034 
00035 /** Register set length */
00036 #define EXANIC_REGS_LEN 0x2000
00037 
00038 /** Transmit feedback region length */
00039 #define EXANIC_TXF_LEN 0x1000
00040 
00041 /** Transmit feedback slot
00042  *
00043  * This is a policy decision.
00044  */
00045 #define EXANIC_TXF_SLOT( index ) ( 0x40 * (index) )
00046 
00047 /** Receive region length */
00048 #define EXANIC_RX_LEN 0x200000
00049 
00050 /** Transmit feedback base address register */
00051 #define EXANIC_TXF_BASE 0x0014
00052 
00053 /** Capabilities register */
00054 #define EXANIC_CAPS 0x0038
00055 #define EXANIC_CAPS_100M 0x01000000UL           /**< 100Mbps supported */
00056 #define EXANIC_CAPS_1G 0x02000000UL             /**< 1Gbps supported */
00057 #define EXANIC_CAPS_10G 0x04000000UL            /**< 10Gbps supported */
00058 #define EXANIC_CAPS_40G 0x08000000UL            /**< 40Gbps supported */
00059 #define EXANIC_CAPS_100G 0x10000000UL           /**< 100Gbps supported */
00060 #define EXANIC_CAPS_SPEED_MASK 0x1f000000UL     /**< Supported speeds mask */
00061 
00062 /** I2C GPIO register */
00063 #define EXANIC_I2C 0x012c
00064 
00065 /** Power control register */
00066 #define EXANIC_POWER 0x0138
00067 #define EXANIC_POWER_ON 0x000000f0UL            /**< Power on PHYs */
00068 
00069 /** Port register offset */
00070 #define EXANIC_PORT_REGS( index ) ( 0x0200 + ( 0x40 * (index) ) )
00071 
00072 /** Port enable register */
00073 #define EXANIC_PORT_ENABLE 0x0000
00074 #define EXANIC_PORT_ENABLE_ENABLED 0x00000001UL /**< Port is enabled */
00075 
00076 /** Port speed register */
00077 #define EXANIC_PORT_SPEED 0x0004
00078 
00079 /** Port status register */
00080 #define EXANIC_PORT_STATUS 0x0008
00081 #define EXANIC_PORT_STATUS_LINK 0x00000008UL    /**< Link is up */
00082 #define EXANIC_PORT_STATUS_ABSENT 0x80000000UL  /**< Port is not present */
00083 
00084 /** Port MAC address (second half) register */
00085 #define EXANIC_PORT_MAC 0x000c
00086 
00087 /** Port flags register */
00088 #define EXANIC_PORT_FLAGS 0x0010
00089 #define EXANIC_PORT_FLAGS_PROMISC 0x00000001UL  /**< Promiscuous mode */
00090 
00091 /** Port receive chunk base address register */
00092 #define EXANIC_PORT_RX_BASE 0x0014
00093 
00094 /** Port transmit command register */
00095 #define EXANIC_PORT_TX_COMMAND 0x0020
00096 
00097 /** Port transmit region offset register */
00098 #define EXANIC_PORT_TX_OFFSET 0x0024
00099 
00100 /** Port transmit region length register */
00101 #define EXANIC_PORT_TX_LEN 0x0028
00102 
00103 /** Port MAC address (first half) register */
00104 #define EXANIC_PORT_OUI 0x0030
00105 
00106 /** Port interrupt configuration register */
00107 #define EXANIC_PORT_IRQ 0x0034
00108 
00109 /** An ExaNIC transmit chunk descriptor */
00110 struct exanic_tx_descriptor {
00111         /** Feedback ID */
00112         uint16_t txf_id;
00113         /** Feedback slot */
00114         uint16_t txf_slot;
00115         /** Payload length (including padding */
00116         uint16_t len;
00117         /** Payload type */
00118         uint8_t type;
00119         /** Flags */
00120         uint8_t flags;
00121 } __attribute__ (( packed ));
00122 
00123 /** An ExaNIC transmit chunk */
00124 struct exanic_tx_chunk {
00125         /** Descriptor */
00126         struct exanic_tx_descriptor desc;
00127         /** Padding */
00128         uint8_t pad[2];
00129         /** Payload data */
00130         uint8_t data[2038];
00131 } __attribute__ (( packed ));
00132 
00133 /** Raw Ethernet frame type */
00134 #define EXANIC_TYPE_RAW 0x01
00135 
00136 /** An ExaNIC receive chunk descriptor */
00137 struct exanic_rx_descriptor {
00138         /** Timestamp */
00139         uint32_t timestamp;
00140         /** Status (valid only on final chunk) */
00141         uint8_t status;
00142         /** Length (zero except on the final chunk) */
00143         uint8_t len;
00144         /** Filter number */
00145         uint8_t filter;
00146         /** Generation */
00147         uint8_t generation;
00148 } __attribute__ (( packed ));
00149 
00150 /** An ExaNIC receive chunk */
00151 struct exanic_rx_chunk {
00152         /** Payload data */
00153         uint8_t data[120];
00154         /** Descriptor */
00155         struct exanic_rx_descriptor desc;
00156 } __attribute__ (( packed ));
00157 
00158 /** Receive status error mask */
00159 #define EXANIC_STATUS_ERROR_MASK 0x0f
00160 
00161 /** An ExaNIC I2C bus configuration */
00162 struct exanic_i2c_config {
00163         /** GPIO bit for pulling SCL low */
00164         uint8_t setscl;
00165         /** GPIO bit for pulling SDA low */
00166         uint8_t setsda;
00167         /** GPIO bit for reading SDA */
00168         uint8_t getsda;
00169 };
00170 
00171 /** EEPROM address */
00172 #define EXANIC_EEPROM_ADDRESS 0x50
00173 
00174 /** An ExaNIC port */
00175 struct exanic_port {
00176         /** Network device */
00177         struct net_device *netdev;
00178         /** Port registers */
00179         void *regs;
00180 
00181         /** Transmit region offset */
00182         size_t tx_offset;
00183         /** Transmit region */
00184         void *tx;
00185         /** Number of transmit descriptors */
00186         uint16_t tx_count;
00187         /** Transmit producer counter */
00188         uint16_t tx_prod;
00189         /** Transmit consumer counter */
00190         uint16_t tx_cons;
00191         /** Transmit feedback slot */
00192         uint16_t txf_slot;
00193         /** Transmit feedback region */
00194         uint16_t *txf;
00195 
00196         /** Receive region */
00197         userptr_t rx;
00198         /** Receive consumer counter */
00199         unsigned int rx_cons;
00200         /** Receive I/O buffer (if any) */
00201         struct io_buffer *rx_iobuf;
00202         /** Receive status */
00203         int rx_rc;
00204 
00205         /** Port status */
00206         uint32_t status;
00207         /** Default link speed (as raw register value) */
00208         uint32_t default_speed;
00209         /** Speed capability bitmask */
00210         uint32_t speeds;
00211         /** Current attempted link speed (as a capability bit index) */
00212         unsigned int speed;
00213         /** Port status check timer */
00214         struct retry_timer timer;
00215 };
00216 
00217 /** An ExaNIC */
00218 struct exanic {
00219         /** Registers */
00220         void *regs;
00221         /** Transmit region */
00222         void *tx;
00223         /** Transmit feedback region */
00224         void *txf;
00225 
00226         /** I2C bus configuration */
00227         struct exanic_i2c_config i2cfg;
00228         /** I2C bit-bashing interface */
00229         struct i2c_bit_basher basher;
00230         /** I2C serial EEPROM */
00231         struct i2c_device eeprom;
00232 
00233         /** Capabilities */
00234         uint32_t caps;
00235         /** Base MAC address */
00236         uint8_t mac[ETH_ALEN];
00237 
00238         /** Ports */
00239         struct exanic_port *port[EXANIC_MAX_PORTS];
00240 };
00241 
00242 /** Maximum used length of transmit region
00243  *
00244  * This is a policy decision to avoid overflowing the 16-bit transmit
00245  * producer and consumer counters.
00246  */
00247 #define EXANIC_MAX_TX_LEN ( 256 * sizeof ( struct exanic_tx_chunk ) )
00248 
00249 /** Maximum length of received packet
00250  *
00251  * This is a policy decision.
00252  */
00253 #define EXANIC_MAX_RX_LEN ( ETH_FRAME_LEN + 4 /* VLAN */ + 4 /* CRC */ )
00254 
00255 /** Interval between link state checks
00256  *
00257  * This is a policy decision.
00258  */
00259 #define EXANIC_LINK_INTERVAL ( 1 * TICKS_PER_SEC )
00260 
00261 #endif /* _EXANIC_H */