iPXE
jme.h
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00001 /*
00002  * JMicron JMC2x0 series PCIe Ethernet gPXE Device Driver
00003  *
00004  * Copyright 2010 Guo-Fu Tseng <cooldavid@cooldavid.org>
00005  *
00006  * This program is free software; you can redistribute it and/or modify
00007  * it under the terms of the GNU General Public License as published by
00008  * the Free Software Foundation; either version 2 of the License.
00009  *
00010  * This program is distributed in the hope that it will be useful,
00011  * but WITHOUT ANY WARRANTY; without even the implied warranty of
00012  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
00013  * GNU General Public License for more details.
00014  *
00015  * You should have received a copy of the GNU General Public License
00016  * along with this program; if not, write to the Free Software
00017  * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
00018  * 02110-1301, USA.
00019  *
00020  */
00021 FILE_LICENCE ( GPL2_OR_LATER );
00022 
00023 #ifndef __JME_H_INCLUDED__
00024 #define __JME_H_INCLUDED__
00025 
00026 #define PCI_VENDOR_ID_JMICRON           0x197b
00027 #define PCI_DEVICE_ID_JMICRON_JMC250    0x0250
00028 #define PCI_DEVICE_ID_JMICRON_JMC260    0x0260
00029 
00030 /*
00031  * Extra PCI Configuration space interface
00032  */
00033 #define PCI_DCSR_MRRS           0x59
00034 #define PCI_DCSR_MRRS_MASK      0x70
00035 
00036 enum pci_dcsr_mrrs_vals {
00037         MRRS_128B       = 0x00,
00038         MRRS_256B       = 0x10,
00039         MRRS_512B       = 0x20,
00040         MRRS_1024B      = 0x30,
00041         MRRS_2048B      = 0x40,
00042         MRRS_4096B      = 0x50,
00043 };
00044 
00045 /*
00046  * TX/RX Descriptors
00047  *
00048  * TX/RX Ring DESC Count Must be multiple of 16 and <= 1024
00049  */
00050 #define RING_DESC_ALIGN         16      /* Descriptor alignment */
00051 #define TX_DESC_SIZE            16
00052 
00053 struct txdesc {
00054         union {
00055                 uint8_t         all[16];
00056                 uint32_t        dw[4];
00057                 struct {
00058                         /* DW0 */
00059                         uint16_t        vlan;
00060                         uint8_t         rsv1;
00061                         uint8_t         flags;
00062 
00063                         /* DW1 */
00064                         uint16_t        datalen;
00065                         uint16_t        mss;
00066 
00067                         /* DW2 */
00068                         uint16_t        pktsize;
00069                         uint16_t        rsv2;
00070 
00071                         /* DW3 */
00072                         uint32_t        bufaddr;
00073                 } desc1;
00074                 struct {
00075                         /* DW0 */
00076                         uint16_t        rsv1;
00077                         uint8_t         rsv2;
00078                         uint8_t         flags;
00079 
00080                         /* DW1 */
00081                         uint16_t        datalen;
00082                         uint16_t        rsv3;
00083 
00084                         /* DW2 */
00085                         uint32_t        bufaddrh;
00086 
00087                         /* DW3 */
00088                         uint32_t        bufaddrl;
00089                 } desc2;
00090                 struct {
00091                         /* DW0 */
00092                         uint8_t         ehdrsz;
00093                         uint8_t         rsv1;
00094                         uint8_t         rsv2;
00095                         uint8_t         flags;
00096 
00097                         /* DW1 */
00098                         uint16_t        trycnt;
00099                         uint16_t        segcnt;
00100 
00101                         /* DW2 */
00102                         uint16_t        pktsz;
00103                         uint16_t        rsv3;
00104 
00105                         /* DW3 */
00106                         uint32_t        bufaddrl;
00107                 } descwb;
00108         };
00109 };
00110 
00111 enum jme_txdesc_flags_bits {
00112         TXFLAG_OWN      = 0x80,
00113         TXFLAG_INT      = 0x40,
00114         TXFLAG_64BIT    = 0x20,
00115         TXFLAG_TCPCS    = 0x10,
00116         TXFLAG_UDPCS    = 0x08,
00117         TXFLAG_IPCS     = 0x04,
00118         TXFLAG_LSEN     = 0x02,
00119         TXFLAG_TAGON    = 0x01,
00120 };
00121 
00122 #define TXDESC_MSS_SHIFT        2
00123 enum jme_txwbdesc_flags_bits {
00124         TXWBFLAG_OWN    = 0x80,
00125         TXWBFLAG_INT    = 0x40,
00126         TXWBFLAG_TMOUT  = 0x20,
00127         TXWBFLAG_TRYOUT = 0x10,
00128         TXWBFLAG_COL    = 0x08,
00129 
00130         TXWBFLAG_ALLERR = TXWBFLAG_TMOUT |
00131                           TXWBFLAG_TRYOUT |
00132                           TXWBFLAG_COL,
00133 };
00134 
00135 #define RX_DESC_SIZE            16
00136 #define RX_BUF_DMA_ALIGN        8
00137 #define RX_PREPAD_SIZE          10
00138 #define ETH_CRC_LEN             2
00139 #define RX_VLANHDR_LEN          2
00140 #define RX_EXTRA_LEN            (ETH_HLEN + \
00141                                 ETH_CRC_LEN + \
00142                                 RX_VLANHDR_LEN + \
00143                                 RX_BUF_DMA_ALIGN)
00144 #define FIXED_MTU               1500
00145 #define RX_ALLOC_LEN            (FIXED_MTU + RX_EXTRA_LEN)
00146 
00147 struct rxdesc {
00148         union {
00149                 uint8_t         all[16];
00150                 uint32_t        dw[4];
00151                 struct {
00152                         /* DW0 */
00153                         uint16_t        rsv2;
00154                         uint8_t         rsv1;
00155                         uint8_t         flags;
00156 
00157                         /* DW1 */
00158                         uint16_t        datalen;
00159                         uint16_t        wbcpl;
00160 
00161                         /* DW2 */
00162                         uint32_t        bufaddrh;
00163 
00164                         /* DW3 */
00165                         uint32_t        bufaddrl;
00166                 } desc1;
00167                 struct {
00168                         /* DW0 */
00169                         uint16_t        vlan;
00170                         uint16_t        flags;
00171 
00172                         /* DW1 */
00173                         uint16_t        framesize;
00174                         uint8_t         errstat;
00175                         uint8_t         desccnt;
00176 
00177                         /* DW2 */
00178                         uint32_t        rsshash;
00179 
00180                         /* DW3 */
00181                         uint8_t         hashfun;
00182                         uint8_t         hashtype;
00183                         uint16_t        resrv;
00184                 } descwb;
00185         };
00186 };
00187 
00188 enum jme_rxdesc_flags_bits {
00189         RXFLAG_OWN      = 0x80,
00190         RXFLAG_INT      = 0x40,
00191         RXFLAG_64BIT    = 0x20,
00192 };
00193 
00194 enum jme_rxwbdesc_flags_bits {
00195         RXWBFLAG_OWN            = 0x8000,
00196         RXWBFLAG_INT            = 0x4000,
00197         RXWBFLAG_MF             = 0x2000,
00198         RXWBFLAG_64BIT          = 0x2000,
00199         RXWBFLAG_TCPON          = 0x1000,
00200         RXWBFLAG_UDPON          = 0x0800,
00201         RXWBFLAG_IPCS           = 0x0400,
00202         RXWBFLAG_TCPCS          = 0x0200,
00203         RXWBFLAG_UDPCS          = 0x0100,
00204         RXWBFLAG_TAGON          = 0x0080,
00205         RXWBFLAG_IPV4           = 0x0040,
00206         RXWBFLAG_IPV6           = 0x0020,
00207         RXWBFLAG_PAUSE          = 0x0010,
00208         RXWBFLAG_MAGIC          = 0x0008,
00209         RXWBFLAG_WAKEUP         = 0x0004,
00210         RXWBFLAG_DEST           = 0x0003,
00211         RXWBFLAG_DEST_UNI       = 0x0001,
00212         RXWBFLAG_DEST_MUL       = 0x0002,
00213         RXWBFLAG_DEST_BRO       = 0x0003,
00214 };
00215 
00216 enum jme_rxwbdesc_desccnt_mask {
00217         RXWBDCNT_WBCPL  = 0x80,
00218         RXWBDCNT_DCNT   = 0x7F,
00219 };
00220 
00221 enum jme_rxwbdesc_errstat_bits {
00222         RXWBERR_LIMIT   = 0x80,
00223         RXWBERR_MIIER   = 0x40,
00224         RXWBERR_NIBON   = 0x20,
00225         RXWBERR_COLON   = 0x10,
00226         RXWBERR_ABORT   = 0x08,
00227         RXWBERR_SHORT   = 0x04,
00228         RXWBERR_OVERUN  = 0x02,
00229         RXWBERR_CRCERR  = 0x01,
00230         RXWBERR_ALLERR  = 0xFF,
00231 };
00232 
00233 /*
00234  * The structure holding buffer information and ring descriptors all together.
00235  */
00236 struct jme_ring {
00237         void *desc;             /* pointer to ring memory  */
00238         unsigned long dma;      /* phys address for ring dma */
00239 
00240         /* Buffer information corresponding to each descriptor */
00241         struct io_buffer **bufinf;
00242 
00243         int next_to_clean;
00244         int next_to_fill;
00245         int next_to_use;
00246         int nr_free;
00247 };
00248 
00249 /*
00250  * Jmac Adapter Private data
00251  */
00252 struct jme_adapter {
00253         void                    *regs;
00254         struct mii_if_info      mii_if;
00255         struct pci_device       *pdev;
00256         unsigned int            fpgaver;
00257         unsigned int            chiprev;
00258         uint32_t                reg_ghc;
00259         uint32_t                reg_txcs;
00260         uint32_t                reg_rxcs;
00261         uint32_t                reg_rxmcs;
00262         uint32_t                phylink;
00263         struct jme_ring         rxring;
00264         uint32_t                rx_ring_size;
00265         uint32_t                rx_ring_mask;
00266         struct jme_ring         txring;
00267         uint32_t                tx_ring_size;
00268         uint32_t                tx_ring_mask;
00269 };
00270 
00271 /*
00272  * I/O Resters
00273  */
00274 enum jme_iomap_regs_value {
00275         JME_REGS_SIZE   = 0x1000,
00276 };
00277 
00278 enum jme_iomap_offsets {
00279         JME_MAC         = 0x0000,
00280         JME_PHY         = 0x0400,
00281         JME_MISC        = 0x0800,
00282         JME_RSS         = 0x0C00,
00283 };
00284 
00285 enum jme_iomap_lens {
00286         JME_MAC_LEN     = 0x80,
00287         JME_PHY_LEN     = 0x58,
00288         JME_MISC_LEN    = 0x98,
00289         JME_RSS_LEN     = 0xFF,
00290 };
00291 
00292 enum jme_iomap_regs {
00293         JME_TXCS        = JME_MAC | 0x00, /* Transmit Control and Status */
00294         JME_TXDBA_LO    = JME_MAC | 0x04, /* Transmit Queue Desc Base Addr */
00295         JME_TXDBA_HI    = JME_MAC | 0x08, /* Transmit Queue Desc Base Addr */
00296         JME_TXQDC       = JME_MAC | 0x0C, /* Transmit Queue Desc Count */
00297         JME_TXNDA       = JME_MAC | 0x10, /* Transmit Queue Next Desc Addr */
00298         JME_TXMCS       = JME_MAC | 0x14, /* Transmit MAC Control Status */
00299         JME_TXPFC       = JME_MAC | 0x18, /* Transmit Pause Frame Control */
00300         JME_TXTRHD      = JME_MAC | 0x1C, /* Transmit Timer/Retry@Half-Dup */
00301 
00302         JME_RXCS        = JME_MAC | 0x20, /* Receive Control and Status */
00303         JME_RXDBA_LO    = JME_MAC | 0x24, /* Receive Queue Desc Base Addr */
00304         JME_RXDBA_HI    = JME_MAC | 0x28, /* Receive Queue Desc Base Addr */
00305         JME_RXQDC       = JME_MAC | 0x2C, /* Receive Queue Desc Count */
00306         JME_RXNDA       = JME_MAC | 0x30, /* Receive Queue Next Desc Addr */
00307         JME_RXMCS       = JME_MAC | 0x34, /* Receive MAC Control Status */
00308         JME_RXUMA_LO    = JME_MAC | 0x38, /* Receive Unicast MAC Address */
00309         JME_RXUMA_HI    = JME_MAC | 0x3C, /* Receive Unicast MAC Address */
00310         JME_RXMCHT_LO   = JME_MAC | 0x40, /* Recv Multicast Addr HashTable */
00311         JME_RXMCHT_HI   = JME_MAC | 0x44, /* Recv Multicast Addr HashTable */
00312         JME_WFODP       = JME_MAC | 0x48, /* Wakeup Frame Output Data Port */
00313         JME_WFOI        = JME_MAC | 0x4C, /* Wakeup Frame Output Interface */
00314 
00315         JME_SMI         = JME_MAC | 0x50, /* Station Management Interface */
00316         JME_GHC         = JME_MAC | 0x54, /* Global Host Control */
00317         JME_PMCS        = JME_MAC | 0x60, /* Power Management Control/Stat */
00318 
00319 
00320         JME_PHY_CS      = JME_PHY | 0x28, /* PHY Ctrl and Status Register */
00321         JME_PHY_LINK    = JME_PHY | 0x30, /* PHY Link Status Register */
00322         JME_SMBCSR      = JME_PHY | 0x40, /* SMB Control and Status */
00323         JME_SMBINTF     = JME_PHY | 0x44, /* SMB Interface */
00324 
00325 
00326         JME_TMCSR       = JME_MISC | 0x00, /* Timer Control/Status Register */
00327         JME_GPREG0      = JME_MISC | 0x08, /* General purpose REG-0 */
00328         JME_GPREG1      = JME_MISC | 0x0C, /* General purpose REG-1 */
00329         JME_IEVE        = JME_MISC | 0x20, /* Interrupt Event Status */
00330         JME_IREQ        = JME_MISC | 0x24, /* Intr Req Status(For Debug) */
00331         JME_IENS        = JME_MISC | 0x28, /* Intr Enable - Setting Port */
00332         JME_IENC        = JME_MISC | 0x2C, /* Interrupt Enable - Clear Port */
00333         JME_PCCRX0      = JME_MISC | 0x30, /* PCC Control for RX Queue 0 */
00334         JME_PCCTX       = JME_MISC | 0x40, /* PCC Control for TX Queues */
00335         JME_CHIPMODE    = JME_MISC | 0x44, /* Identify FPGA Version */
00336         JME_SHBA_HI     = JME_MISC | 0x48, /* Shadow Register Base HI */
00337         JME_SHBA_LO     = JME_MISC | 0x4C, /* Shadow Register Base LO */
00338         JME_TIMER1      = JME_MISC | 0x70, /* Timer1 */
00339         JME_TIMER2      = JME_MISC | 0x74, /* Timer2 */
00340         JME_APMC        = JME_MISC | 0x7C, /* Aggressive Power Mode Control */
00341         JME_PCCSRX0     = JME_MISC | 0x80, /* PCC Status of RX0 */
00342 };
00343 
00344 /*
00345  * TX Control/Status Bits
00346  */
00347 enum jme_txcs_bits {
00348         TXCS_QUEUE7S    = 0x00008000,
00349         TXCS_QUEUE6S    = 0x00004000,
00350         TXCS_QUEUE5S    = 0x00002000,
00351         TXCS_QUEUE4S    = 0x00001000,
00352         TXCS_QUEUE3S    = 0x00000800,
00353         TXCS_QUEUE2S    = 0x00000400,
00354         TXCS_QUEUE1S    = 0x00000200,
00355         TXCS_QUEUE0S    = 0x00000100,
00356         TXCS_FIFOTH     = 0x000000C0,
00357         TXCS_DMASIZE    = 0x00000030,
00358         TXCS_BURST      = 0x00000004,
00359         TXCS_ENABLE     = 0x00000001,
00360 };
00361 
00362 enum jme_txcs_value {
00363         TXCS_FIFOTH_16QW        = 0x000000C0,
00364         TXCS_FIFOTH_12QW        = 0x00000080,
00365         TXCS_FIFOTH_8QW         = 0x00000040,
00366         TXCS_FIFOTH_4QW         = 0x00000000,
00367 
00368         TXCS_DMASIZE_64B        = 0x00000000,
00369         TXCS_DMASIZE_128B       = 0x00000010,
00370         TXCS_DMASIZE_256B       = 0x00000020,
00371         TXCS_DMASIZE_512B       = 0x00000030,
00372 
00373         TXCS_SELECT_QUEUE0      = 0x00000000,
00374         TXCS_SELECT_QUEUE1      = 0x00010000,
00375         TXCS_SELECT_QUEUE2      = 0x00020000,
00376         TXCS_SELECT_QUEUE3      = 0x00030000,
00377         TXCS_SELECT_QUEUE4      = 0x00040000,
00378         TXCS_SELECT_QUEUE5      = 0x00050000,
00379         TXCS_SELECT_QUEUE6      = 0x00060000,
00380         TXCS_SELECT_QUEUE7      = 0x00070000,
00381 
00382         TXCS_DEFAULT            = TXCS_FIFOTH_4QW |
00383                                   TXCS_BURST,
00384 };
00385 
00386 #define JME_TX_DISABLE_TIMEOUT 10 /* 10 msec */
00387 
00388 /*
00389  * TX MAC Control/Status Bits
00390  */
00391 enum jme_txmcs_bit_masks {
00392         TXMCS_IFG2              = 0xC0000000,
00393         TXMCS_IFG1              = 0x30000000,
00394         TXMCS_TTHOLD            = 0x00000300,
00395         TXMCS_FBURST            = 0x00000080,
00396         TXMCS_CARRIEREXT        = 0x00000040,
00397         TXMCS_DEFER             = 0x00000020,
00398         TXMCS_BACKOFF           = 0x00000010,
00399         TXMCS_CARRIERSENSE      = 0x00000008,
00400         TXMCS_COLLISION         = 0x00000004,
00401         TXMCS_CRC               = 0x00000002,
00402         TXMCS_PADDING           = 0x00000001,
00403 };
00404 
00405 enum jme_txmcs_values {
00406         TXMCS_IFG2_6_4          = 0x00000000,
00407         TXMCS_IFG2_8_5          = 0x40000000,
00408         TXMCS_IFG2_10_6         = 0x80000000,
00409         TXMCS_IFG2_12_7         = 0xC0000000,
00410 
00411         TXMCS_IFG1_8_4          = 0x00000000,
00412         TXMCS_IFG1_12_6         = 0x10000000,
00413         TXMCS_IFG1_16_8         = 0x20000000,
00414         TXMCS_IFG1_20_10        = 0x30000000,
00415 
00416         TXMCS_TTHOLD_1_8        = 0x00000000,
00417         TXMCS_TTHOLD_1_4        = 0x00000100,
00418         TXMCS_TTHOLD_1_2        = 0x00000200,
00419         TXMCS_TTHOLD_FULL       = 0x00000300,
00420 
00421         TXMCS_DEFAULT           = TXMCS_IFG2_8_5 |
00422                                   TXMCS_IFG1_16_8 |
00423                                   TXMCS_TTHOLD_FULL |
00424                                   TXMCS_DEFER |
00425                                   TXMCS_CRC |
00426                                   TXMCS_PADDING,
00427 };
00428 
00429 enum jme_txpfc_bits_masks {
00430         TXPFC_VLAN_TAG          = 0xFFFF0000,
00431         TXPFC_VLAN_EN           = 0x00008000,
00432         TXPFC_PF_EN             = 0x00000001,
00433 };
00434 
00435 enum jme_txtrhd_bits_masks {
00436         TXTRHD_TXPEN            = 0x80000000,
00437         TXTRHD_TXP              = 0x7FFFFF00,
00438         TXTRHD_TXREN            = 0x00000080,
00439         TXTRHD_TXRL             = 0x0000007F,
00440 };
00441 
00442 enum jme_txtrhd_shifts {
00443         TXTRHD_TXP_SHIFT        = 8,
00444         TXTRHD_TXRL_SHIFT       = 0,
00445 };
00446 
00447 /*
00448  * RX Control/Status Bits
00449  */
00450 enum jme_rxcs_bit_masks {
00451         /* FIFO full threshold for transmitting Tx Pause Packet */
00452         RXCS_FIFOTHTP   = 0x30000000,
00453         /* FIFO threshold for processing next packet */
00454         RXCS_FIFOTHNP   = 0x0C000000,
00455         RXCS_DMAREQSZ   = 0x03000000, /* DMA Request Size */
00456         RXCS_QUEUESEL   = 0x00030000, /* Queue selection */
00457         RXCS_RETRYGAP   = 0x0000F000, /* RX Desc full retry gap */
00458         RXCS_RETRYCNT   = 0x00000F00, /* RX Desc full retry counter */
00459         RXCS_WAKEUP     = 0x00000040, /* Enable receive wakeup packet */
00460         RXCS_MAGIC      = 0x00000020, /* Enable receive magic packet */
00461         RXCS_SHORT      = 0x00000010, /* Enable receive short packet */
00462         RXCS_ABORT      = 0x00000008, /* Enable receive errorr packet */
00463         RXCS_QST        = 0x00000004, /* Receive queue start */
00464         RXCS_SUSPEND    = 0x00000002,
00465         RXCS_ENABLE     = 0x00000001,
00466 };
00467 
00468 enum jme_rxcs_values {
00469         RXCS_FIFOTHTP_16T       = 0x00000000,
00470         RXCS_FIFOTHTP_32T       = 0x10000000,
00471         RXCS_FIFOTHTP_64T       = 0x20000000,
00472         RXCS_FIFOTHTP_128T      = 0x30000000,
00473 
00474         RXCS_FIFOTHNP_16QW      = 0x00000000,
00475         RXCS_FIFOTHNP_32QW      = 0x04000000,
00476         RXCS_FIFOTHNP_64QW      = 0x08000000,
00477         RXCS_FIFOTHNP_128QW     = 0x0C000000,
00478 
00479         RXCS_DMAREQSZ_16B       = 0x00000000,
00480         RXCS_DMAREQSZ_32B       = 0x01000000,
00481         RXCS_DMAREQSZ_64B       = 0x02000000,
00482         RXCS_DMAREQSZ_128B      = 0x03000000,
00483 
00484         RXCS_QUEUESEL_Q0        = 0x00000000,
00485         RXCS_QUEUESEL_Q1        = 0x00010000,
00486         RXCS_QUEUESEL_Q2        = 0x00020000,
00487         RXCS_QUEUESEL_Q3        = 0x00030000,
00488 
00489         RXCS_RETRYGAP_256ns     = 0x00000000,
00490         RXCS_RETRYGAP_512ns     = 0x00001000,
00491         RXCS_RETRYGAP_1024ns    = 0x00002000,
00492         RXCS_RETRYGAP_2048ns    = 0x00003000,
00493         RXCS_RETRYGAP_4096ns    = 0x00004000,
00494         RXCS_RETRYGAP_8192ns    = 0x00005000,
00495         RXCS_RETRYGAP_16384ns   = 0x00006000,
00496         RXCS_RETRYGAP_32768ns   = 0x00007000,
00497 
00498         RXCS_RETRYCNT_0         = 0x00000000,
00499         RXCS_RETRYCNT_4         = 0x00000100,
00500         RXCS_RETRYCNT_8         = 0x00000200,
00501         RXCS_RETRYCNT_12        = 0x00000300,
00502         RXCS_RETRYCNT_16        = 0x00000400,
00503         RXCS_RETRYCNT_20        = 0x00000500,
00504         RXCS_RETRYCNT_24        = 0x00000600,
00505         RXCS_RETRYCNT_28        = 0x00000700,
00506         RXCS_RETRYCNT_32        = 0x00000800,
00507         RXCS_RETRYCNT_36        = 0x00000900,
00508         RXCS_RETRYCNT_40        = 0x00000A00,
00509         RXCS_RETRYCNT_44        = 0x00000B00,
00510         RXCS_RETRYCNT_48        = 0x00000C00,
00511         RXCS_RETRYCNT_52        = 0x00000D00,
00512         RXCS_RETRYCNT_56        = 0x00000E00,
00513         RXCS_RETRYCNT_60        = 0x00000F00,
00514 
00515         RXCS_DEFAULT            = RXCS_FIFOTHTP_128T |
00516                                   RXCS_FIFOTHNP_128QW |
00517                                   RXCS_DMAREQSZ_128B |
00518                                   RXCS_RETRYGAP_256ns |
00519                                   RXCS_RETRYCNT_32,
00520 };
00521 
00522 #define JME_RX_DISABLE_TIMEOUT 10 /* 10 msec */
00523 
00524 /*
00525  * RX MAC Control/Status Bits
00526  */
00527 enum jme_rxmcs_bits {
00528         RXMCS_ALLFRAME          = 0x00000800,
00529         RXMCS_BRDFRAME          = 0x00000400,
00530         RXMCS_MULFRAME          = 0x00000200,
00531         RXMCS_UNIFRAME          = 0x00000100,
00532         RXMCS_ALLMULFRAME       = 0x00000080,
00533         RXMCS_MULFILTERED       = 0x00000040,
00534         RXMCS_RXCOLLDEC         = 0x00000020,
00535         RXMCS_FLOWCTRL          = 0x00000008,
00536         RXMCS_VTAGRM            = 0x00000004,
00537         RXMCS_PREPAD            = 0x00000002,
00538         RXMCS_CHECKSUM          = 0x00000001,
00539 
00540         RXMCS_DEFAULT           = RXMCS_VTAGRM |
00541                                   RXMCS_FLOWCTRL |
00542                                   RXMCS_CHECKSUM,
00543 };
00544 
00545 /*
00546  * Wakeup Frame setup interface registers
00547  */
00548 #define WAKEUP_FRAME_NR 8
00549 #define WAKEUP_FRAME_MASK_DWNR  4
00550 
00551 enum jme_wfoi_bit_masks {
00552         WFOI_MASK_SEL           = 0x00000070,
00553         WFOI_CRC_SEL            = 0x00000008,
00554         WFOI_FRAME_SEL          = 0x00000007,
00555 };
00556 
00557 enum jme_wfoi_shifts {
00558         WFOI_MASK_SHIFT         = 4,
00559 };
00560 
00561 /*
00562  * SMI Related definitions
00563  */
00564 enum jme_smi_bit_mask {
00565         SMI_DATA_MASK           = 0xFFFF0000,
00566         SMI_REG_ADDR_MASK       = 0x0000F800,
00567         SMI_PHY_ADDR_MASK       = 0x000007C0,
00568         SMI_OP_WRITE            = 0x00000020,
00569         /* Set to 1, after req done it'll be cleared to 0 */
00570         SMI_OP_REQ              = 0x00000010,
00571         SMI_OP_MDIO             = 0x00000008, /* Software assess In/Out */
00572         SMI_OP_MDOE             = 0x00000004, /* Software Output Enable */
00573         SMI_OP_MDC              = 0x00000002, /* Software CLK Control */
00574         SMI_OP_MDEN             = 0x00000001, /* Software access Enable */
00575 };
00576 
00577 enum jme_smi_bit_shift {
00578         SMI_DATA_SHIFT          = 16,
00579         SMI_REG_ADDR_SHIFT      = 11,
00580         SMI_PHY_ADDR_SHIFT      = 6,
00581 };
00582 
00583 static inline uint32_t smi_reg_addr(int x)
00584 {
00585         return (x << SMI_REG_ADDR_SHIFT) & SMI_REG_ADDR_MASK;
00586 }
00587 
00588 static inline uint32_t smi_phy_addr(int x)
00589 {
00590         return (x << SMI_PHY_ADDR_SHIFT) & SMI_PHY_ADDR_MASK;
00591 }
00592 
00593 #define JME_PHY_TIMEOUT 100 /* 100 msec */
00594 #define JME_PHY_REG_NR 32
00595 
00596 /*
00597  * Global Host Control
00598  */
00599 enum jme_ghc_bit_mask {
00600         GHC_SWRST               = 0x40000000,
00601         GHC_DPX                 = 0x00000040,
00602         GHC_SPEED               = 0x00000030,
00603         GHC_LINK_POLL           = 0x00000001,
00604 };
00605 
00606 enum jme_ghc_speed_val {
00607         GHC_SPEED_10M           = 0x00000010,
00608         GHC_SPEED_100M          = 0x00000020,
00609         GHC_SPEED_1000M         = 0x00000030,
00610 };
00611 
00612 enum jme_ghc_to_clk {
00613         GHC_TO_CLK_OFF          = 0x00000000,
00614         GHC_TO_CLK_GPHY         = 0x00400000,
00615         GHC_TO_CLK_PCIE         = 0x00800000,
00616         GHC_TO_CLK_INVALID      = 0x00C00000,
00617 };
00618 
00619 enum jme_ghc_txmac_clk {
00620         GHC_TXMAC_CLK_OFF       = 0x00000000,
00621         GHC_TXMAC_CLK_GPHY      = 0x00100000,
00622         GHC_TXMAC_CLK_PCIE      = 0x00200000,
00623         GHC_TXMAC_CLK_INVALID   = 0x00300000,
00624 };
00625 
00626 /*
00627  * Power management control and status register
00628  */
00629 enum jme_pmcs_bit_masks {
00630         PMCS_WF7DET     = 0x80000000,
00631         PMCS_WF6DET     = 0x40000000,
00632         PMCS_WF5DET     = 0x20000000,
00633         PMCS_WF4DET     = 0x10000000,
00634         PMCS_WF3DET     = 0x08000000,
00635         PMCS_WF2DET     = 0x04000000,
00636         PMCS_WF1DET     = 0x02000000,
00637         PMCS_WF0DET     = 0x01000000,
00638         PMCS_LFDET      = 0x00040000,
00639         PMCS_LRDET      = 0x00020000,
00640         PMCS_MFDET      = 0x00010000,
00641         PMCS_WF7EN      = 0x00008000,
00642         PMCS_WF6EN      = 0x00004000,
00643         PMCS_WF5EN      = 0x00002000,
00644         PMCS_WF4EN      = 0x00001000,
00645         PMCS_WF3EN      = 0x00000800,
00646         PMCS_WF2EN      = 0x00000400,
00647         PMCS_WF1EN      = 0x00000200,
00648         PMCS_WF0EN      = 0x00000100,
00649         PMCS_LFEN       = 0x00000004,
00650         PMCS_LREN       = 0x00000002,
00651         PMCS_MFEN       = 0x00000001,
00652 };
00653 
00654 /*
00655  * Giga PHY Status Registers
00656  */
00657 enum jme_phy_link_bit_mask {
00658         PHY_LINK_SPEED_MASK             = 0x0000C000,
00659         PHY_LINK_DUPLEX                 = 0x00002000,
00660         PHY_LINK_SPEEDDPU_RESOLVED      = 0x00000800,
00661         PHY_LINK_UP                     = 0x00000400,
00662         PHY_LINK_AUTONEG_COMPLETE       = 0x00000200,
00663         PHY_LINK_MDI_STAT               = 0x00000040,
00664 };
00665 
00666 enum jme_phy_link_speed_val {
00667         PHY_LINK_SPEED_10M              = 0x00000000,
00668         PHY_LINK_SPEED_100M             = 0x00004000,
00669         PHY_LINK_SPEED_1000M            = 0x00008000,
00670 };
00671 
00672 #define JME_SPDRSV_TIMEOUT      500     /* 500 us */
00673 
00674 /*
00675  * SMB Control and Status
00676  */
00677 enum jme_smbcsr_bit_mask {
00678         SMBCSR_CNACK    = 0x00020000,
00679         SMBCSR_RELOAD   = 0x00010000,
00680         SMBCSR_EEPROMD  = 0x00000020,
00681         SMBCSR_INITDONE = 0x00000010,
00682         SMBCSR_BUSY     = 0x0000000F,
00683 };
00684 
00685 enum jme_smbintf_bit_mask {
00686         SMBINTF_HWDATR  = 0xFF000000,
00687         SMBINTF_HWDATW  = 0x00FF0000,
00688         SMBINTF_HWADDR  = 0x0000FF00,
00689         SMBINTF_HWRWN   = 0x00000020,
00690         SMBINTF_HWCMD   = 0x00000010,
00691         SMBINTF_FASTM   = 0x00000008,
00692         SMBINTF_GPIOSCL = 0x00000004,
00693         SMBINTF_GPIOSDA = 0x00000002,
00694         SMBINTF_GPIOEN  = 0x00000001,
00695 };
00696 
00697 enum jme_smbintf_vals {
00698         SMBINTF_HWRWN_READ      = 0x00000020,
00699         SMBINTF_HWRWN_WRITE     = 0x00000000,
00700 };
00701 
00702 enum jme_smbintf_shifts {
00703         SMBINTF_HWDATR_SHIFT    = 24,
00704         SMBINTF_HWDATW_SHIFT    = 16,
00705         SMBINTF_HWADDR_SHIFT    = 8,
00706 };
00707 
00708 #define JME_EEPROM_RELOAD_TIMEOUT 2000 /* 2000 msec */
00709 #define JME_SMB_BUSY_TIMEOUT 20 /* 20 msec */
00710 #define JME_SMB_LEN 256
00711 #define JME_EEPROM_MAGIC 0x250
00712 
00713 /*
00714  * Timer Control/Status Register
00715  */
00716 enum jme_tmcsr_bit_masks {
00717         TMCSR_SWIT      = 0x80000000,
00718         TMCSR_EN        = 0x01000000,
00719         TMCSR_CNT       = 0x00FFFFFF,
00720 };
00721 
00722 /*
00723  * General Purpose REG-0
00724  */
00725 enum jme_gpreg0_masks {
00726         GPREG0_DISSH            = 0xFF000000,
00727         GPREG0_PCIRLMT          = 0x00300000,
00728         GPREG0_PCCNOMUTCLR      = 0x00040000,
00729         GPREG0_LNKINTPOLL       = 0x00001000,
00730         GPREG0_PCCTMR           = 0x00000300,
00731         GPREG0_PHYADDR          = 0x0000001F,
00732 };
00733 
00734 enum jme_gpreg0_vals {
00735         GPREG0_DISSH_DW7        = 0x80000000,
00736         GPREG0_DISSH_DW6        = 0x40000000,
00737         GPREG0_DISSH_DW5        = 0x20000000,
00738         GPREG0_DISSH_DW4        = 0x10000000,
00739         GPREG0_DISSH_DW3        = 0x08000000,
00740         GPREG0_DISSH_DW2        = 0x04000000,
00741         GPREG0_DISSH_DW1        = 0x02000000,
00742         GPREG0_DISSH_DW0        = 0x01000000,
00743         GPREG0_DISSH_ALL        = 0xFF000000,
00744 
00745         GPREG0_PCIRLMT_8        = 0x00000000,
00746         GPREG0_PCIRLMT_6        = 0x00100000,
00747         GPREG0_PCIRLMT_5        = 0x00200000,
00748         GPREG0_PCIRLMT_4        = 0x00300000,
00749 
00750         GPREG0_PCCTMR_16ns      = 0x00000000,
00751         GPREG0_PCCTMR_256ns     = 0x00000100,
00752         GPREG0_PCCTMR_1us       = 0x00000200,
00753         GPREG0_PCCTMR_1ms       = 0x00000300,
00754 
00755         GPREG0_PHYADDR_1        = 0x00000001,
00756 
00757         GPREG0_DEFAULT          = GPREG0_DISSH_ALL |
00758                                   GPREG0_PCIRLMT_4 |
00759                                   GPREG0_PCCTMR_1us |
00760                                   GPREG0_PHYADDR_1,
00761 };
00762 
00763 /*
00764  * General Purpose REG-1
00765  * Note: All theses bits defined here are for
00766  *       Chip mode revision 0x11 only
00767  */
00768 enum jme_gpreg1_masks {
00769         GPREG1_INTRDELAYUNIT    = 0x00000018,
00770         GPREG1_INTRDELAYENABLE  = 0x00000007,
00771 };
00772 
00773 enum jme_gpreg1_vals {
00774         GPREG1_RSSPATCH         = 0x00000040,
00775         GPREG1_HALFMODEPATCH    = 0x00000020,
00776 
00777         GPREG1_INTDLYUNIT_16NS  = 0x00000000,
00778         GPREG1_INTDLYUNIT_256NS = 0x00000008,
00779         GPREG1_INTDLYUNIT_1US   = 0x00000010,
00780         GPREG1_INTDLYUNIT_16US  = 0x00000018,
00781 
00782         GPREG1_INTDLYEN_1U      = 0x00000001,
00783         GPREG1_INTDLYEN_2U      = 0x00000002,
00784         GPREG1_INTDLYEN_3U      = 0x00000003,
00785         GPREG1_INTDLYEN_4U      = 0x00000004,
00786         GPREG1_INTDLYEN_5U      = 0x00000005,
00787         GPREG1_INTDLYEN_6U      = 0x00000006,
00788         GPREG1_INTDLYEN_7U      = 0x00000007,
00789 
00790         GPREG1_DEFAULT          = 0x00000000,
00791 };
00792 
00793 /*
00794  * Interrupt Status Bits
00795  */
00796 enum jme_interrupt_bits {
00797         INTR_SWINTR     = 0x80000000,
00798         INTR_TMINTR     = 0x40000000,
00799         INTR_LINKCH     = 0x20000000,
00800         INTR_PAUSERCV   = 0x10000000,
00801         INTR_MAGICRCV   = 0x08000000,
00802         INTR_WAKERCV    = 0x04000000,
00803         INTR_PCCRX0TO   = 0x02000000,
00804         INTR_PCCRX1TO   = 0x01000000,
00805         INTR_PCCRX2TO   = 0x00800000,
00806         INTR_PCCRX3TO   = 0x00400000,
00807         INTR_PCCTXTO    = 0x00200000,
00808         INTR_PCCRX0     = 0x00100000,
00809         INTR_PCCRX1     = 0x00080000,
00810         INTR_PCCRX2     = 0x00040000,
00811         INTR_PCCRX3     = 0x00020000,
00812         INTR_PCCTX      = 0x00010000,
00813         INTR_RX3EMP     = 0x00008000,
00814         INTR_RX2EMP     = 0x00004000,
00815         INTR_RX1EMP     = 0x00002000,
00816         INTR_RX0EMP     = 0x00001000,
00817         INTR_RX3        = 0x00000800,
00818         INTR_RX2        = 0x00000400,
00819         INTR_RX1        = 0x00000200,
00820         INTR_RX0        = 0x00000100,
00821         INTR_TX7        = 0x00000080,
00822         INTR_TX6        = 0x00000040,
00823         INTR_TX5        = 0x00000020,
00824         INTR_TX4        = 0x00000010,
00825         INTR_TX3        = 0x00000008,
00826         INTR_TX2        = 0x00000004,
00827         INTR_TX1        = 0x00000002,
00828         INTR_TX0        = 0x00000001,
00829 };
00830 
00831 static const uint32_t INTR_ENABLE = INTR_LINKCH |
00832                                     INTR_RX0EMP |
00833                                     INTR_RX0 |
00834                                     INTR_TX0;
00835 
00836 /*
00837  * PCC Control Registers
00838  */
00839 enum jme_pccrx_masks {
00840         PCCRXTO_MASK    = 0xFFFF0000,
00841         PCCRX_MASK      = 0x0000FF00,
00842 };
00843 
00844 enum jme_pcctx_masks {
00845         PCCTXTO_MASK    = 0xFFFF0000,
00846         PCCTX_MASK      = 0x0000FF00,
00847         PCCTX_QS_MASK   = 0x000000FF,
00848 };
00849 
00850 enum jme_pccrx_shifts {
00851         PCCRXTO_SHIFT   = 16,
00852         PCCRX_SHIFT     = 8,
00853 };
00854 
00855 enum jme_pcctx_shifts {
00856         PCCTXTO_SHIFT   = 16,
00857         PCCTX_SHIFT     = 8,
00858 };
00859 
00860 enum jme_pcctx_bits {
00861         PCCTXQ0_EN      = 0x00000001,
00862         PCCTXQ1_EN      = 0x00000002,
00863         PCCTXQ2_EN      = 0x00000004,
00864         PCCTXQ3_EN      = 0x00000008,
00865         PCCTXQ4_EN      = 0x00000010,
00866         PCCTXQ5_EN      = 0x00000020,
00867         PCCTXQ6_EN      = 0x00000040,
00868         PCCTXQ7_EN      = 0x00000080,
00869 };
00870 
00871 /*
00872  * Chip Mode Register
00873  */
00874 enum jme_chipmode_bit_masks {
00875         CM_FPGAVER_MASK         = 0xFFFF0000,
00876         CM_CHIPREV_MASK         = 0x0000FF00,
00877         CM_CHIPMODE_MASK        = 0x0000000F,
00878 };
00879 
00880 enum jme_chipmode_shifts {
00881         CM_FPGAVER_SHIFT        = 16,
00882         CM_CHIPREV_SHIFT        = 8,
00883 };
00884 
00885 /*
00886  * Workaround
00887  */
00888 static inline int is_buggy250(unsigned short device, unsigned int chiprev)
00889 {
00890         return device == PCI_DEVICE_ID_JMICRON_JMC250 && chiprev == 0x11;
00891 }
00892 
00893 /*
00894  * Read/Write I/O Registers
00895  */
00896 static inline uint32_t jread32(struct jme_adapter *jme, uint32_t reg)
00897 {
00898         return readl(jme->regs + reg);
00899 }
00900 
00901 static inline void jwrite32(struct jme_adapter *jme, uint32_t reg, uint32_t val)
00902 {
00903         writel(val, jme->regs + reg);
00904 }
00905 
00906 static void jwrite32f(struct jme_adapter *jme, uint32_t reg, uint32_t val)
00907 {
00908         /*
00909          * Read after write should cause flush
00910          */
00911         writel(val, jme->regs + reg);
00912         readl(jme->regs + reg);
00913 }
00914 
00915 #endif