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myri10ge_mcp.h
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00001 /************************************************* -*- linux-c -*-
00002  * Myricom 10Gb Network Interface Card Software
00003  * Copyright 2005-2010, Myricom, Inc.
00004  *
00005  * This program is free software; you can redistribute it and/or
00006  * modify it under the terms of the GNU General Public License,
00007  * version 2, as published by the Free Software Foundation.
00008  *
00009  * This program is distributed in the hope that it will be useful,
00010  * but WITHOUT ANY WARRANTY; without even the implied warranty of
00011  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
00012  * GNU General Public License for more details.
00013  *
00014  * You should have received a copy of the GNU General Public License
00015  * along with this program; if not, write to the Free Software
00016  * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
00017  * 02110-1301, USA.
00018  ****************************************************************/
00019 
00020 FILE_LICENCE ( GPL2_ONLY );
00021 
00022 #ifndef _myri10ge_mcp_h
00023 #define _myri10ge_mcp_h
00024 
00025 #define MXGEFW_VERSION_MAJOR    1
00026 #define MXGEFW_VERSION_MINOR    4
00027 
00028 #ifdef MXGEFW
00029 #ifndef _stdint_h_
00030 typedef signed char          int8_t;
00031 typedef signed short        int16_t;
00032 typedef signed int          int32_t;
00033 typedef signed long long    int64_t;
00034 typedef unsigned char       uint8_t;
00035 typedef unsigned short     uint16_t;
00036 typedef unsigned int       uint32_t;
00037 typedef unsigned long long uint64_t;
00038 #endif
00039 #endif
00040 
00041 /* 8 Bytes */
00042 struct mcp_dma_addr {
00043   uint32_t high;
00044   uint32_t low;
00045 };
00046 typedef struct mcp_dma_addr mcp_dma_addr_t;
00047 
00048 /* 4 Bytes */
00049 struct mcp_slot {
00050   uint16_t checksum;
00051   uint16_t length;
00052 };
00053 typedef struct mcp_slot mcp_slot_t;
00054 
00055 #ifdef MXGEFW_NDIS
00056 /* 8-byte descriptor, exclusively used by NDIS drivers. */
00057 struct mcp_slot_8 {
00058   /* Place hash value at the top so it gets written before length.
00059    * The driver polls length.
00060    */
00061   uint32_t hash;
00062   uint16_t checksum;
00063   uint16_t length;
00064 };
00065 typedef struct mcp_slot_8 mcp_slot_8_t;
00066 
00067 /* Two bits of length in mcp_slot are used to indicate hash type. */
00068 #define MXGEFW_RSS_HASH_NULL (0 << 14) /* bit 15:14 = 00 */
00069 #define MXGEFW_RSS_HASH_IPV4 (1 << 14) /* bit 15:14 = 01 */
00070 #define MXGEFW_RSS_HASH_TCP_IPV4 (2 << 14) /* bit 15:14 = 10 */
00071 #define MXGEFW_RSS_HASH_MASK (3 << 14) /* bit 15:14 = 11 */
00072 #endif
00073 
00074 /* 64 Bytes */
00075 struct mcp_cmd {
00076   uint32_t cmd;
00077   uint32_t data0;       /* will be low portion if data > 32 bits */
00078   /* 8 */
00079   uint32_t data1;       /* will be high portion if data > 32 bits */
00080   uint32_t data2;       /* currently unused.. */
00081   /* 16 */
00082   struct mcp_dma_addr response_addr;
00083   /* 24 */
00084   uint32_t pad[10];
00085 };
00086 typedef struct mcp_cmd mcp_cmd_t;
00087 
00088 /* 8 Bytes */
00089 struct mcp_cmd_response {
00090   uint32_t data;
00091   uint32_t result;
00092 };
00093 typedef struct mcp_cmd_response mcp_cmd_response_t;
00094 
00095 
00096 
00097 /*
00098    flags used in mcp_kreq_ether_send_t:
00099 
00100    The SMALL flag is only needed in the first segment. It is raised
00101    for packets that are total less or equal 512 bytes.
00102 
00103    The CKSUM flag must be set in all segments.
00104 
00105    The PADDED flags is set if the packet needs to be padded, and it
00106    must be set for all segments.
00107 
00108    The  MXGEFW_FLAGS_ALIGN_ODD must be set if the cumulative
00109    length of all previous segments was odd.
00110 */
00111 
00112 
00113 #define MXGEFW_FLAGS_SMALL      0x1
00114 #define MXGEFW_FLAGS_TSO_HDR    0x1
00115 #define MXGEFW_FLAGS_FIRST      0x2
00116 #define MXGEFW_FLAGS_ALIGN_ODD  0x4
00117 #define MXGEFW_FLAGS_CKSUM      0x8
00118 #define MXGEFW_FLAGS_TSO_LAST   0x8
00119 #define MXGEFW_FLAGS_NO_TSO     0x10
00120 #define MXGEFW_FLAGS_TSO_CHOP   0x10
00121 #define MXGEFW_FLAGS_TSO_PLD    0x20
00122 
00123 #define MXGEFW_SEND_SMALL_SIZE  1520
00124 #define MXGEFW_MAX_MTU          9400
00125 
00126 union mcp_pso_or_cumlen {
00127   uint16_t pseudo_hdr_offset;
00128   uint16_t cum_len;
00129 };
00130 typedef union mcp_pso_or_cumlen mcp_pso_or_cumlen_t;
00131 
00132 #define MXGEFW_MAX_SEND_DESC 12
00133 #define MXGEFW_PAD          2
00134 
00135 /* 16 Bytes */
00136 struct mcp_kreq_ether_send {
00137   uint32_t addr_high;
00138   uint32_t addr_low;
00139   uint16_t pseudo_hdr_offset;
00140   uint16_t length;
00141   uint8_t  pad;
00142   uint8_t  rdma_count;
00143   uint8_t  cksum_offset;        /* where to start computing cksum */
00144   uint8_t  flags;               /* as defined above */
00145 };
00146 typedef struct mcp_kreq_ether_send mcp_kreq_ether_send_t;
00147 
00148 /* 8 Bytes */
00149 struct mcp_kreq_ether_recv {
00150   uint32_t addr_high;
00151   uint32_t addr_low;
00152 };
00153 typedef struct mcp_kreq_ether_recv mcp_kreq_ether_recv_t;
00154 
00155 
00156 /* Commands */
00157 
00158 #define MXGEFW_BOOT_HANDOFF     0xfc0000
00159 #define MXGEFW_BOOT_DUMMY_RDMA  0xfc01c0
00160 
00161 #define MXGEFW_ETH_CMD          0xf80000
00162 #define MXGEFW_ETH_SEND_4       0x200000
00163 #define MXGEFW_ETH_SEND_1       0x240000
00164 #define MXGEFW_ETH_SEND_2       0x280000
00165 #define MXGEFW_ETH_SEND_3       0x2c0000
00166 #define MXGEFW_ETH_RECV_SMALL   0x300000
00167 #define MXGEFW_ETH_RECV_BIG     0x340000
00168 #define MXGEFW_ETH_SEND_GO      0x380000
00169 #define MXGEFW_ETH_SEND_STOP    0x3C0000
00170 
00171 #define MXGEFW_ETH_SEND(n)              (0x200000 + (((n) & 0x03) * 0x40000))
00172 #define MXGEFW_ETH_SEND_OFFSET(n)       (MXGEFW_ETH_SEND(n) - MXGEFW_ETH_SEND_4)
00173 
00174 enum myri10ge_mcp_cmd_type {
00175   MXGEFW_CMD_NONE = 0,
00176   /* Reset the mcp, it is left in a safe state, waiting
00177      for the driver to set all its parameters */
00178   MXGEFW_CMD_RESET = 1,
00179 
00180   /* get the version number of the current firmware..
00181      (may be available in the eeprom strings..? */
00182   MXGEFW_GET_MCP_VERSION = 2,
00183 
00184 
00185   /* Parameters which must be set by the driver before it can
00186      issue MXGEFW_CMD_ETHERNET_UP. They persist until the next
00187      MXGEFW_CMD_RESET is issued */
00188 
00189   MXGEFW_CMD_SET_INTRQ_DMA = 3,
00190   /* data0 = LSW of the host address
00191    * data1 = MSW of the host address
00192    * data2 = slice number if multiple slices are used
00193    */
00194 
00195   MXGEFW_CMD_SET_BIG_BUFFER_SIZE = 4,   /* in bytes, power of 2 */
00196   MXGEFW_CMD_SET_SMALL_BUFFER_SIZE = 5, /* in bytes */
00197 
00198 
00199   /* Parameters which refer to lanai SRAM addresses where the
00200      driver must issue PIO writes for various things */
00201 
00202   MXGEFW_CMD_GET_SEND_OFFSET = 6,
00203   MXGEFW_CMD_GET_SMALL_RX_OFFSET = 7,
00204   MXGEFW_CMD_GET_BIG_RX_OFFSET = 8,
00205   /* data0 = slice number if multiple slices are used */
00206 
00207   MXGEFW_CMD_GET_IRQ_ACK_OFFSET = 9,
00208   MXGEFW_CMD_GET_IRQ_DEASSERT_OFFSET = 10,
00209 
00210   /* Parameters which refer to rings stored on the MCP,
00211      and whose size is controlled by the mcp */
00212 
00213   MXGEFW_CMD_GET_SEND_RING_SIZE = 11,   /* in bytes */
00214   MXGEFW_CMD_GET_RX_RING_SIZE = 12,     /* in bytes */
00215 
00216   /* Parameters which refer to rings stored in the host,
00217      and whose size is controlled by the host.  Note that
00218      all must be physically contiguous and must contain
00219      a power of 2 number of entries.  */
00220 
00221   MXGEFW_CMD_SET_INTRQ_SIZE = 13,       /* in bytes */
00222 #define MXGEFW_CMD_SET_INTRQ_SIZE_FLAG_NO_STRICT_SIZE_CHECK  (1 << 31)
00223 
00224   /* command to bring ethernet interface up.  Above parameters
00225      (plus mtu & mac address) must have been exchanged prior
00226      to issuing this command  */
00227   MXGEFW_CMD_ETHERNET_UP = 14,
00228 
00229   /* command to bring ethernet interface down.  No further sends
00230      or receives may be processed until an MXGEFW_CMD_ETHERNET_UP
00231      is issued, and all interrupt queues must be flushed prior
00232      to ack'ing this command */
00233 
00234   MXGEFW_CMD_ETHERNET_DOWN = 15,
00235 
00236   /* commands the driver may issue live, without resetting
00237      the nic.  Note that increasing the mtu "live" should
00238      only be done if the driver has already supplied buffers
00239      sufficiently large to handle the new mtu.  Decreasing
00240      the mtu live is safe */
00241 
00242   MXGEFW_CMD_SET_MTU = 16,
00243   MXGEFW_CMD_GET_INTR_COAL_DELAY_OFFSET = 17,  /* in microseconds */
00244   MXGEFW_CMD_SET_STATS_INTERVAL = 18,   /* in microseconds */
00245   MXGEFW_CMD_SET_STATS_DMA_OBSOLETE = 19, /* replaced by SET_STATS_DMA_V2 */
00246 
00247   MXGEFW_ENABLE_PROMISC = 20,
00248   MXGEFW_DISABLE_PROMISC = 21,
00249   MXGEFW_SET_MAC_ADDRESS = 22,
00250 
00251   MXGEFW_ENABLE_FLOW_CONTROL = 23,
00252   MXGEFW_DISABLE_FLOW_CONTROL = 24,
00253 
00254   /* do a DMA test
00255      data0,data1 = DMA address
00256      data2       = RDMA length (MSH), WDMA length (LSH)
00257      command return data = repetitions (MSH), 0.5-ms ticks (LSH)
00258   */
00259   MXGEFW_DMA_TEST = 25,
00260 
00261   MXGEFW_ENABLE_ALLMULTI = 26,
00262   MXGEFW_DISABLE_ALLMULTI = 27,
00263 
00264   /* returns MXGEFW_CMD_ERROR_MULTICAST
00265      if there is no room in the cache
00266      data0,MSH(data1) = multicast group address */
00267   MXGEFW_JOIN_MULTICAST_GROUP = 28,
00268   /* returns MXGEFW_CMD_ERROR_MULTICAST
00269      if the address is not in the cache,
00270      or is equal to FF-FF-FF-FF-FF-FF
00271      data0,MSH(data1) = multicast group address */
00272   MXGEFW_LEAVE_MULTICAST_GROUP = 29,
00273   MXGEFW_LEAVE_ALL_MULTICAST_GROUPS = 30,
00274 
00275   MXGEFW_CMD_SET_STATS_DMA_V2 = 31,
00276   /* data0, data1 = bus addr,
00277    * data2 = sizeof(struct mcp_irq_data) from driver point of view, allows
00278    * adding new stuff to mcp_irq_data without changing the ABI
00279    *
00280    * If multiple slices are used, data2 contains both the size of the
00281    * structure (in the lower 16 bits) and the slice number
00282    * (in the upper 16 bits).
00283    */
00284 
00285   MXGEFW_CMD_UNALIGNED_TEST = 32,
00286   /* same than DMA_TEST (same args) but abort with UNALIGNED on unaligned
00287      chipset */
00288 
00289   MXGEFW_CMD_UNALIGNED_STATUS = 33,
00290   /* return data = boolean, true if the chipset is known to be unaligned */
00291 
00292   MXGEFW_CMD_ALWAYS_USE_N_BIG_BUFFERS = 34,
00293   /* data0 = number of big buffers to use.  It must be 0 or a power of 2.
00294    * 0 indicates that the NIC consumes as many buffers as they are required
00295    * for packet. This is the default behavior.
00296    * A power of 2 number indicates that the NIC always uses the specified
00297    * number of buffers for each big receive packet.
00298    * It is up to the driver to ensure that this value is big enough for
00299    * the NIC to be able to receive maximum-sized packets.
00300    */
00301 
00302   MXGEFW_CMD_GET_MAX_RSS_QUEUES = 35,
00303   MXGEFW_CMD_ENABLE_RSS_QUEUES = 36,
00304   /* data0 = number of slices n (0, 1, ..., n-1) to enable
00305    * data1 = interrupt mode | use of multiple transmit queues.
00306    * 0=share one INTx/MSI.
00307    * 1=use one MSI-X per queue.
00308    * If all queues share one interrupt, the driver must have set
00309    * RSS_SHARED_INTERRUPT_DMA before enabling queues.
00310    * 2=enable both receive and send queues.
00311    * Without this bit set, only one send queue (slice 0's send queue)
00312    * is enabled.  The receive queues are always enabled.
00313    */
00314 #define MXGEFW_SLICE_INTR_MODE_SHARED          0x0
00315 #define MXGEFW_SLICE_INTR_MODE_ONE_PER_SLICE   0x1
00316 #define MXGEFW_SLICE_ENABLE_MULTIPLE_TX_QUEUES 0x2
00317 
00318   MXGEFW_CMD_GET_RSS_SHARED_INTERRUPT_MASK_OFFSET = 37,
00319   MXGEFW_CMD_SET_RSS_SHARED_INTERRUPT_DMA = 38,
00320   /* data0, data1 = bus address lsw, msw */
00321   MXGEFW_CMD_GET_RSS_TABLE_OFFSET = 39,
00322   /* get the offset of the indirection table */
00323   MXGEFW_CMD_SET_RSS_TABLE_SIZE = 40,
00324   /* set the size of the indirection table */
00325   MXGEFW_CMD_GET_RSS_KEY_OFFSET = 41,
00326   /* get the offset of the secret key */
00327   MXGEFW_CMD_RSS_KEY_UPDATED = 42,
00328   /* tell nic that the secret key's been updated */
00329   MXGEFW_CMD_SET_RSS_ENABLE = 43,
00330   /* data0 = enable/disable rss
00331    * 0: disable rss.  nic does not distribute receive packets.
00332    * 1: enable rss.  nic distributes receive packets among queues.
00333    * data1 = hash type
00334    * 1: IPV4            (required by RSS)
00335    * 2: TCP_IPV4        (required by RSS)
00336    * 3: IPV4 | TCP_IPV4 (required by RSS)
00337    * 4: source port
00338    * 5: source port + destination port
00339    */
00340 #define MXGEFW_RSS_HASH_TYPE_IPV4      0x1
00341 #define MXGEFW_RSS_HASH_TYPE_TCP_IPV4  0x2
00342 #define MXGEFW_RSS_HASH_TYPE_SRC_PORT  0x4
00343 #define MXGEFW_RSS_HASH_TYPE_SRC_DST_PORT 0x5
00344 #define MXGEFW_RSS_HASH_TYPE_MAX 0x5
00345 
00346   MXGEFW_CMD_GET_MAX_TSO6_HDR_SIZE = 44,
00347   /* Return data = the max. size of the entire headers of a IPv6 TSO packet.
00348    * If the header size of a IPv6 TSO packet is larger than the specified
00349    * value, then the driver must not use TSO.
00350    * This size restriction only applies to IPv6 TSO.
00351    * For IPv4 TSO, the maximum size of the headers is fixed, and the NIC
00352    * always has enough header buffer to store maximum-sized headers.
00353    */
00354 
00355   MXGEFW_CMD_SET_TSO_MODE = 45,
00356   /* data0 = TSO mode.
00357    * 0: Linux/FreeBSD style (NIC default)
00358    * 1: NDIS/NetBSD style
00359    */
00360 #define MXGEFW_TSO_MODE_LINUX  0
00361 #define MXGEFW_TSO_MODE_NDIS   1
00362 
00363   MXGEFW_CMD_MDIO_READ = 46,
00364   /* data0 = dev_addr (PMA/PMD or PCS ...), data1 = register/addr */
00365   MXGEFW_CMD_MDIO_WRITE = 47,
00366   /* data0 = dev_addr,  data1 = register/addr, data2 = value  */
00367 
00368   MXGEFW_CMD_I2C_READ = 48,
00369   /* Starts to get a fresh copy of one byte or of the module i2c table, the
00370    * obtained data is cached inside the xaui-xfi chip :
00371    *   data0 :  0 => get one byte, 1=> get 256 bytes
00372    *   data1 :  If data0 == 0: location to refresh
00373    *               bit 7:0  register location
00374    *               bit 8:15 is the i2c slave addr (0 is interpreted as 0xA1)
00375    *               bit 23:16 is the i2c bus number (for multi-port NICs)
00376    *            If data0 == 1: unused
00377    * The operation might take ~1ms for a single byte or ~65ms when refreshing all 256 bytes
00378    * During the i2c operation,  MXGEFW_CMD_I2C_READ or MXGEFW_CMD_I2C_BYTE attempts
00379    *  will return MXGEFW_CMD_ERROR_BUSY
00380    */
00381   MXGEFW_CMD_I2C_BYTE = 49,
00382   /* Return the last obtained copy of a given byte in the xfp i2c table
00383    * (copy cached during the last relevant MXGEFW_CMD_I2C_READ)
00384    *   data0 : index of the desired table entry
00385    *  Return data = the byte stored at the requested index in the table
00386    */
00387 
00388   MXGEFW_CMD_GET_VPUMP_OFFSET = 50,
00389   /* Return data = NIC memory offset of mcp_vpump_public_global */
00390   MXGEFW_CMD_RESET_VPUMP = 51,
00391   /* Resets the VPUMP state */
00392 
00393   MXGEFW_CMD_SET_RSS_MCP_SLOT_TYPE = 52,
00394   /* data0 = mcp_slot type to use.
00395    * 0 = the default 4B mcp_slot
00396    * 1 = 8B mcp_slot_8
00397    */
00398 #define MXGEFW_RSS_MCP_SLOT_TYPE_MIN        0
00399 #define MXGEFW_RSS_MCP_SLOT_TYPE_WITH_HASH  1
00400 
00401   MXGEFW_CMD_SET_THROTTLE_FACTOR = 53,
00402   /* set the throttle factor for ethp_z8e
00403      data0 = throttle_factor
00404      throttle_factor = 256 * pcie-raw-speed / tx_speed
00405      tx_speed = 256 * pcie-raw-speed / throttle_factor
00406 
00407      For PCI-E x8: pcie-raw-speed == 16Gb/s
00408      For PCI-E x4: pcie-raw-speed == 8Gb/s
00409 
00410      ex1: throttle_factor == 0x1a0 (416), tx_speed == 1.23GB/s == 9.846 Gb/s
00411      ex2: throttle_factor == 0x200 (512), tx_speed == 1.0GB/s == 8 Gb/s
00412 
00413      with tx_boundary == 2048, max-throttle-factor == 8191 => min-speed == 500Mb/s
00414      with tx_boundary == 4096, max-throttle-factor == 4095 => min-speed == 1Gb/s
00415   */
00416 
00417   MXGEFW_CMD_VPUMP_UP = 54,
00418   /* Allocates VPump Connection, Send Request and Zero copy buffer address tables */
00419   MXGEFW_CMD_GET_VPUMP_CLK = 55,
00420   /* Get the lanai clock */
00421 
00422   MXGEFW_CMD_GET_DCA_OFFSET = 56,
00423   /* offset of dca control for WDMAs */
00424 
00425   /* VMWare NetQueue commands */
00426   MXGEFW_CMD_NETQ_GET_FILTERS_PER_QUEUE = 57,
00427   MXGEFW_CMD_NETQ_ADD_FILTER = 58,
00428   /* data0 = filter_id << 16 | queue << 8 | type */
00429   /* data1 = MS4 of MAC Addr */
00430   /* data2 = LS2_MAC << 16 | VLAN_tag */
00431   MXGEFW_CMD_NETQ_DEL_FILTER = 59,
00432   /* data0 = filter_id */
00433   MXGEFW_CMD_NETQ_QUERY1 = 60,
00434   MXGEFW_CMD_NETQ_QUERY2 = 61,
00435   MXGEFW_CMD_NETQ_QUERY3 = 62,
00436   MXGEFW_CMD_NETQ_QUERY4 = 63,
00437 
00438   MXGEFW_CMD_RELAX_RXBUFFER_ALIGNMENT = 64,
00439   /* When set, small receive buffers can cross page boundaries.
00440    * Both small and big receive buffers may start at any address.
00441    * This option has performance implications, so use with caution.
00442    */
00443 };
00444 typedef enum myri10ge_mcp_cmd_type myri10ge_mcp_cmd_type_t;
00445 
00446 
00447 enum myri10ge_mcp_cmd_status {
00448   MXGEFW_CMD_OK = 0,
00449   MXGEFW_CMD_UNKNOWN = 1,
00450   MXGEFW_CMD_ERROR_RANGE = 2,
00451   MXGEFW_CMD_ERROR_BUSY = 3,
00452   MXGEFW_CMD_ERROR_EMPTY = 4,
00453   MXGEFW_CMD_ERROR_CLOSED = 5,
00454   MXGEFW_CMD_ERROR_HASH_ERROR = 6,
00455   MXGEFW_CMD_ERROR_BAD_PORT = 7,
00456   MXGEFW_CMD_ERROR_RESOURCES = 8,
00457   MXGEFW_CMD_ERROR_MULTICAST = 9,
00458   MXGEFW_CMD_ERROR_UNALIGNED = 10,
00459   MXGEFW_CMD_ERROR_NO_MDIO = 11,
00460   MXGEFW_CMD_ERROR_I2C_FAILURE = 12,
00461   MXGEFW_CMD_ERROR_I2C_ABSENT = 13,
00462   MXGEFW_CMD_ERROR_BAD_PCIE_LINK = 14
00463 };
00464 typedef enum myri10ge_mcp_cmd_status myri10ge_mcp_cmd_status_t;
00465 
00466 
00467 #define MXGEFW_OLD_IRQ_DATA_LEN 40
00468 
00469 struct mcp_irq_data {
00470   /* add new counters at the beginning */
00471   uint32_t future_use[1];
00472   uint32_t dropped_pause;
00473   uint32_t dropped_unicast_filtered;
00474   uint32_t dropped_bad_crc32;
00475   uint32_t dropped_bad_phy;
00476   uint32_t dropped_multicast_filtered;
00477 /* 40 Bytes */
00478   uint32_t send_done_count;
00479 
00480 #define MXGEFW_LINK_DOWN 0
00481 #define MXGEFW_LINK_UP 1
00482 #define MXGEFW_LINK_MYRINET 2
00483 #define MXGEFW_LINK_UNKNOWN 3
00484   uint32_t link_up;
00485   uint32_t dropped_link_overflow;
00486   uint32_t dropped_link_error_or_filtered;
00487   uint32_t dropped_runt;
00488   uint32_t dropped_overrun;
00489   uint32_t dropped_no_small_buffer;
00490   uint32_t dropped_no_big_buffer;
00491   uint32_t rdma_tags_available;
00492 
00493   uint8_t tx_stopped;
00494   uint8_t link_down;
00495   uint8_t stats_updated;
00496   uint8_t valid;
00497 };
00498 typedef struct mcp_irq_data mcp_irq_data_t;
00499 
00500 #ifdef MXGEFW_NDIS
00501 /* Exclusively used by NDIS drivers */
00502 struct mcp_rss_shared_interrupt {
00503   uint8_t pad[2];
00504   uint8_t queue;
00505   uint8_t valid;
00506 };
00507 #endif
00508 
00509 /* definitions for NETQ filter type */
00510 #define MXGEFW_NETQ_FILTERTYPE_NONE 0
00511 #define MXGEFW_NETQ_FILTERTYPE_MACADDR 1
00512 #define MXGEFW_NETQ_FILTERTYPE_VLAN 2
00513 #define MXGEFW_NETQ_FILTERTYPE_VLANMACADDR 3
00514 
00515 #endif /* _myri10ge_mcp_h */