iPXE
arbel.h
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00001 #ifndef _ARBEL_H
00002 #define _ARBEL_H
00003 
00004 /** @file
00005  *
00006  * Mellanox Arbel Infiniband HCA driver
00007  *
00008  */
00009 
00010 FILE_LICENCE ( GPL2_OR_LATER_OR_UBDL );
00011 
00012 #include <stdint.h>
00013 #include <ipxe/uaccess.h>
00014 #include <ipxe/ib_packet.h>
00015 #include "mlx_bitops.h"
00016 #include "MT25218_PRM.h"
00017 
00018 /*
00019  * Hardware constants
00020  *
00021  */
00022 
00023 /* Ports in existence */
00024 #define ARBEL_NUM_PORTS                 2
00025 #define ARBEL_PORT_BASE                 1
00026 
00027 /* PCI BARs */
00028 #define ARBEL_PCI_CONFIG_BAR            PCI_BASE_ADDRESS_0
00029 #define ARBEL_PCI_CONFIG_BAR_SIZE       0x100000
00030 #define ARBEL_PCI_UAR_BAR               PCI_BASE_ADDRESS_2
00031 #define ARBEL_PCI_UAR_IDX               1
00032 #define ARBEL_PCI_UAR_SIZE              0x1000
00033 
00034 /* Device reset */
00035 #define ARBEL_RESET_OFFSET              0x0f0010
00036 #define ARBEL_RESET_MAGIC               0x01000000UL
00037 #define ARBEL_RESET_WAIT_TIME_MS        1000
00038 
00039 /* UAR context table (UCE) resource types */
00040 #define ARBEL_UAR_RES_NONE              0x00
00041 #define ARBEL_UAR_RES_CQ_CI             0x01
00042 #define ARBEL_UAR_RES_CQ_ARM            0x02
00043 #define ARBEL_UAR_RES_SQ                0x03
00044 #define ARBEL_UAR_RES_RQ                0x04
00045 #define ARBEL_UAR_RES_GROUP_SEP         0x07
00046 
00047 /* Work queue entry and completion queue entry opcodes */
00048 #define ARBEL_OPCODE_SEND               0x0a
00049 #define ARBEL_OPCODE_RECV_ERROR         0xfe
00050 #define ARBEL_OPCODE_SEND_ERROR         0xff
00051 
00052 /* HCA command register opcodes */
00053 #define ARBEL_HCR_QUERY_DEV_LIM         0x0003
00054 #define ARBEL_HCR_QUERY_FW              0x0004
00055 #define ARBEL_HCR_INIT_HCA              0x0007
00056 #define ARBEL_HCR_CLOSE_HCA             0x0008
00057 #define ARBEL_HCR_INIT_IB               0x0009
00058 #define ARBEL_HCR_CLOSE_IB              0x000a
00059 #define ARBEL_HCR_SW2HW_MPT             0x000d
00060 #define ARBEL_HCR_MAP_EQ                0x0012
00061 #define ARBEL_HCR_SW2HW_EQ              0x0013
00062 #define ARBEL_HCR_HW2SW_EQ              0x0014
00063 #define ARBEL_HCR_SW2HW_CQ              0x0016
00064 #define ARBEL_HCR_HW2SW_CQ              0x0017
00065 #define ARBEL_HCR_QUERY_CQ              0x0018
00066 #define ARBEL_HCR_RST2INIT_QPEE         0x0019
00067 #define ARBEL_HCR_INIT2RTR_QPEE         0x001a
00068 #define ARBEL_HCR_RTR2RTS_QPEE          0x001b
00069 #define ARBEL_HCR_RTS2RTS_QPEE          0x001c
00070 #define ARBEL_HCR_2RST_QPEE             0x0021
00071 #define ARBEL_HCR_QUERY_QPEE            0x0022
00072 #define ARBEL_HCR_CONF_SPECIAL_QP       0x0023
00073 #define ARBEL_HCR_MAD_IFC               0x0024
00074 #define ARBEL_HCR_READ_MGM              0x0025
00075 #define ARBEL_HCR_WRITE_MGM             0x0026
00076 #define ARBEL_HCR_MGID_HASH             0x0027
00077 #define ARBEL_HCR_RUN_FW                0x0ff6
00078 #define ARBEL_HCR_DISABLE_LAM           0x0ff7
00079 #define ARBEL_HCR_ENABLE_LAM            0x0ff8
00080 #define ARBEL_HCR_UNMAP_ICM             0x0ff9
00081 #define ARBEL_HCR_MAP_ICM               0x0ffa
00082 #define ARBEL_HCR_UNMAP_ICM_AUX         0x0ffb
00083 #define ARBEL_HCR_MAP_ICM_AUX           0x0ffc
00084 #define ARBEL_HCR_SET_ICM_SIZE          0x0ffd
00085 #define ARBEL_HCR_UNMAP_FA              0x0ffe
00086 #define ARBEL_HCR_MAP_FA                0x0fff
00087 
00088 /* Service types */
00089 #define ARBEL_ST_RC                     0x00
00090 #define ARBEL_ST_UD                     0x03
00091 #define ARBEL_ST_MLX                    0x07
00092 
00093 /* MTUs */
00094 #define ARBEL_MTU_2048                  0x04
00095 
00096 #define ARBEL_NO_EQ                     64
00097 
00098 #define ARBEL_INVALID_LKEY              0x00000100UL
00099 
00100 #define ARBEL_PAGE_SIZE                 ( ( size_t ) 4096 )
00101 
00102 #define ARBEL_RDB_ENTRY_SIZE            ( ( size_t ) 32 )
00103 
00104 #define ARBEL_DB_POST_SND_OFFSET        0x10
00105 #define ARBEL_DB_EQ_OFFSET(_eqn)        ( 0x08 * (_eqn) )
00106 
00107 #define ARBEL_QPEE_OPT_PARAM_QKEY       0x00000020UL
00108 
00109 #define ARBEL_MAP_EQ                    ( 0UL << 31 )
00110 #define ARBEL_UNMAP_EQ                  ( 1UL << 31 )
00111 
00112 #define ARBEL_EV_PORT_STATE_CHANGE      0x09
00113 
00114 #define ARBEL_LOG_MULTICAST_HASH_SIZE   3
00115 
00116 #define ARBEL_PM_STATE_ARMED            0x00
00117 #define ARBEL_PM_STATE_REARM            0x01
00118 #define ARBEL_PM_STATE_MIGRATED         0x03
00119 
00120 #define ARBEL_RETRY_MAX                 0x07
00121 
00122 /*
00123  * Datatypes that seem to be missing from the autogenerated documentation
00124  *
00125  */
00126 struct arbelprm_mgm_hash_st {
00127         pseudo_bit_t reserved0[0x00020];
00128 /* -------------- */
00129         pseudo_bit_t hash[0x00010];
00130         pseudo_bit_t reserved1[0x00010];
00131 } __attribute__ (( packed ));
00132 
00133 struct arbelprm_scalar_parameter_st {
00134         pseudo_bit_t reserved0[0x00020];
00135 /* -------------- */
00136         pseudo_bit_t value[0x00020];
00137 } __attribute__ (( packed ));
00138 
00139 struct arbelprm_event_mask_st {
00140         pseudo_bit_t reserved0[0x00020];
00141 /* -------------- */
00142         pseudo_bit_t completion[0x00001];
00143         pseudo_bit_t path_migration_succeeded[0x00001];
00144         pseudo_bit_t communication_established[0x00001];
00145         pseudo_bit_t send_queue_drained[0x00001];
00146         pseudo_bit_t cq_error[0x00001];
00147         pseudo_bit_t wq_catastrophe[0x00001];
00148         pseudo_bit_t qpc_catastrophe[0x00001];
00149         pseudo_bit_t path_migration_failed[0x00001];
00150         pseudo_bit_t reserved1[0x00001];
00151         pseudo_bit_t port_state_change[0x00001];
00152         pseudo_bit_t command_done[0x00001];
00153         pseudo_bit_t reserved2[0x00005];
00154         pseudo_bit_t wq_invalid_request[0x00001];
00155         pseudo_bit_t wq_access_violation[0x00001];
00156         pseudo_bit_t srq_catastrophe[0x00001];
00157         pseudo_bit_t srq_last_wqe[0x00001];
00158         pseudo_bit_t srq_rq_limit[0x00001];
00159         pseudo_bit_t gpio[0x00001];
00160         pseudo_bit_t clientreregister[0x00001];
00161         pseudo_bit_t path_migration_armed[0x00001];
00162         pseudo_bit_t reserved3[0x00008];
00163 } __attribute__ (( packed ));
00164 
00165 struct arbelprm_eq_set_ci_st {
00166         pseudo_bit_t ci[0x00020];
00167 } __attribute__ (( packed ));
00168 
00169 struct arbelprm_port_state_change_event_st {
00170         pseudo_bit_t reserved[0x00020];
00171         struct arbelprm_port_state_change_st data;
00172 } __attribute__ (( packed ));
00173 
00174 /*
00175  * Wrapper structures for hardware datatypes
00176  *
00177  */
00178 
00179 struct MLX_DECLARE_STRUCT ( arbelprm_access_lam );
00180 struct MLX_DECLARE_STRUCT ( arbelprm_completion_queue_context );
00181 struct MLX_DECLARE_STRUCT ( arbelprm_completion_queue_entry );
00182 struct MLX_DECLARE_STRUCT ( arbelprm_completion_with_error );
00183 struct MLX_DECLARE_STRUCT ( arbelprm_cq_arm_db_record );
00184 struct MLX_DECLARE_STRUCT ( arbelprm_cq_ci_db_record );
00185 struct MLX_DECLARE_STRUCT ( arbelprm_event_mask );
00186 struct MLX_DECLARE_STRUCT ( arbelprm_event_queue_entry );
00187 struct MLX_DECLARE_STRUCT ( arbelprm_eq_set_ci );
00188 struct MLX_DECLARE_STRUCT ( arbelprm_eqc );
00189 struct MLX_DECLARE_STRUCT ( arbelprm_hca_command_register );
00190 struct MLX_DECLARE_STRUCT ( arbelprm_init_hca );
00191 struct MLX_DECLARE_STRUCT ( arbelprm_init_ib );
00192 struct MLX_DECLARE_STRUCT ( arbelprm_mad_ifc );
00193 struct MLX_DECLARE_STRUCT ( arbelprm_mgm_entry );
00194 struct MLX_DECLARE_STRUCT ( arbelprm_mgm_hash );
00195 struct MLX_DECLARE_STRUCT ( arbelprm_mpt );
00196 struct MLX_DECLARE_STRUCT ( arbelprm_port_state_change_event );
00197 struct MLX_DECLARE_STRUCT ( arbelprm_qp_db_record );
00198 struct MLX_DECLARE_STRUCT ( arbelprm_qp_ee_state_transitions );
00199 struct MLX_DECLARE_STRUCT ( arbelprm_query_dev_lim );
00200 struct MLX_DECLARE_STRUCT ( arbelprm_query_fw );
00201 struct MLX_DECLARE_STRUCT ( arbelprm_queue_pair_ee_context_entry );
00202 struct MLX_DECLARE_STRUCT ( arbelprm_recv_wqe_segment_next );
00203 struct MLX_DECLARE_STRUCT ( arbelprm_scalar_parameter );
00204 struct MLX_DECLARE_STRUCT ( arbelprm_send_doorbell );
00205 struct MLX_DECLARE_STRUCT ( arbelprm_ud_address_vector );
00206 struct MLX_DECLARE_STRUCT ( arbelprm_virtual_physical_mapping );
00207 struct MLX_DECLARE_STRUCT ( arbelprm_wqe_segment_ctrl_mlx );
00208 struct MLX_DECLARE_STRUCT ( arbelprm_wqe_segment_ctrl_send );
00209 struct MLX_DECLARE_STRUCT ( arbelprm_wqe_segment_data_ptr );
00210 struct MLX_DECLARE_STRUCT ( arbelprm_wqe_segment_next );
00211 struct MLX_DECLARE_STRUCT ( arbelprm_wqe_segment_ud );
00212 
00213 /*
00214  * Composite hardware datatypes
00215  *
00216  */
00217 
00218 #define ARBEL_MAX_GATHER 2
00219 
00220 struct arbelprm_ud_send_wqe {
00221         struct arbelprm_wqe_segment_next next;
00222         struct arbelprm_wqe_segment_ctrl_send ctrl;
00223         struct arbelprm_wqe_segment_ud ud;
00224         struct arbelprm_wqe_segment_data_ptr data[ARBEL_MAX_GATHER];
00225 } __attribute__ (( packed ));
00226 
00227 struct arbelprm_mlx_send_wqe {
00228         struct arbelprm_wqe_segment_next next;
00229         struct arbelprm_wqe_segment_ctrl_mlx ctrl;
00230         struct arbelprm_wqe_segment_data_ptr data[ARBEL_MAX_GATHER];
00231         uint8_t headers[IB_MAX_HEADER_SIZE];
00232 } __attribute__ (( packed ));
00233 
00234 struct arbelprm_rc_send_wqe {
00235         struct arbelprm_wqe_segment_next next;
00236         struct arbelprm_wqe_segment_ctrl_send ctrl;
00237         struct arbelprm_wqe_segment_data_ptr data[ARBEL_MAX_GATHER];
00238 } __attribute__ (( packed ));
00239 
00240 #define ARBEL_MAX_SCATTER 2
00241 
00242 struct arbelprm_recv_wqe {
00243         /* The autogenerated header is inconsistent between send and
00244          * receive WQEs.  The "ctrl" structure for receive WQEs is
00245          * defined to include the "next" structure.  Since the "ctrl"
00246          * part of the "ctrl" structure contains only "reserved, must
00247          * be zero" bits, we ignore its definition and provide
00248          * something more usable.
00249          */
00250         struct arbelprm_recv_wqe_segment_next next;
00251         uint32_t ctrl[2]; /* All "reserved, must be zero" */
00252         struct arbelprm_wqe_segment_data_ptr data[ARBEL_MAX_SCATTER];
00253 } __attribute__ (( packed ));
00254 
00255 union arbelprm_completion_entry {
00256         struct arbelprm_completion_queue_entry normal;
00257         struct arbelprm_completion_with_error error;
00258 } __attribute__ (( packed ));
00259 
00260 union arbelprm_event_entry {
00261         struct arbelprm_event_queue_entry generic;
00262         struct arbelprm_port_state_change_event port_state_change;
00263 } __attribute__ (( packed ));
00264 
00265 union arbelprm_doorbell_record {
00266         struct arbelprm_cq_arm_db_record cq_arm;
00267         struct arbelprm_cq_ci_db_record cq_ci;
00268         struct arbelprm_qp_db_record qp;
00269 } __attribute__ (( packed ));
00270 
00271 union arbelprm_doorbell_register {
00272         struct arbelprm_send_doorbell send;
00273         uint32_t dword[2];
00274 } __attribute__ (( packed ));
00275 
00276 union arbelprm_eq_doorbell_register {
00277         struct arbelprm_eq_set_ci ci;
00278         uint32_t dword[1];
00279 } __attribute__ (( packed ));
00280 
00281 union arbelprm_mad {
00282         struct arbelprm_mad_ifc ifc;
00283         union ib_mad mad;
00284 } __attribute__ (( packed ));
00285 
00286 /*
00287  * iPXE-specific definitions
00288  *
00289  */
00290 
00291 /** Arbel device limits */
00292 struct arbel_dev_limits {
00293         /** Number of reserved QPs */
00294         unsigned int reserved_qps;
00295         /** QP context entry size */
00296         size_t qpc_entry_size;
00297         /** Extended QP context entry size */
00298         size_t eqpc_entry_size;
00299         /** Number of reserved SRQs */
00300         unsigned int reserved_srqs;
00301         /** SRQ context entry size */
00302         size_t srqc_entry_size;
00303         /** Number of reserved EEs */
00304         unsigned int reserved_ees;
00305         /** EE context entry size */
00306         size_t eec_entry_size;
00307         /** Extended EE context entry size */
00308         size_t eeec_entry_size;
00309         /** Number of reserved CQs */
00310         unsigned int reserved_cqs;
00311         /** CQ context entry size */
00312         size_t cqc_entry_size;
00313         /** Number of reserved EQs */
00314         unsigned int reserved_eqs;
00315         /** Number of reserved MTTs */
00316         unsigned int reserved_mtts;
00317         /** MTT entry size */
00318         size_t mtt_entry_size;
00319         /** Number of reserved MRWs */
00320         unsigned int reserved_mrws;
00321         /** MPT entry size */
00322         size_t mpt_entry_size;
00323         /** Number of reserved RDBs */
00324         unsigned int reserved_rdbs;
00325         /** EQ context entry size */
00326         size_t eqc_entry_size;
00327         /** Number of reserved UARs */
00328         unsigned int reserved_uars;
00329         /** UAR scratchpad entry size */
00330         size_t uar_scratch_entry_size;
00331 };
00332 
00333 /** Alignment of Arbel send work queue entries */
00334 #define ARBEL_SEND_WQE_ALIGN 128
00335 
00336 /** An Arbel send work queue entry */
00337 union arbel_send_wqe {
00338         struct arbelprm_wqe_segment_next next;
00339         struct arbelprm_ud_send_wqe ud;
00340         struct arbelprm_mlx_send_wqe mlx;
00341         struct arbelprm_rc_send_wqe rc;
00342         uint8_t force_align[ARBEL_SEND_WQE_ALIGN];
00343 } __attribute__ (( packed ));
00344 
00345 /** An Arbel send work queue */
00346 struct arbel_send_work_queue {
00347         /** Doorbell record number */
00348         unsigned int doorbell_idx;
00349         /** Work queue entries */
00350         union arbel_send_wqe *wqe;
00351         /** Size of work queue */
00352         size_t wqe_size;
00353 };
00354 
00355 /** Alignment of Arbel receive work queue entries */
00356 #define ARBEL_RECV_WQE_ALIGN 64
00357 
00358 /** An Arbel receive work queue entry */
00359 union arbel_recv_wqe {
00360         struct arbelprm_recv_wqe recv;
00361         uint8_t force_align[ARBEL_RECV_WQE_ALIGN];
00362 } __attribute__ (( packed ));
00363 
00364 /** An Arbel receive work queue */
00365 struct arbel_recv_work_queue {
00366         /** Doorbell record number */
00367         unsigned int doorbell_idx;
00368         /** Work queue entries */
00369         union arbel_recv_wqe *wqe;
00370         /** Size of work queue */
00371         size_t wqe_size;
00372         /** GRH buffers (if applicable) */
00373         struct ib_global_route_header *grh;
00374         /** Size of GRB buffers */
00375         size_t grh_size;
00376 };
00377 
00378 /** Number of special queue pairs */
00379 #define ARBEL_NUM_SPECIAL_QPS 4
00380 
00381 /** Number of queue pairs reserved for the "special QP" block
00382  *
00383  * The special QPs must be in (2n,2n+1) pairs, hence we need to
00384  * reserve one extra QP to allow for alignment.
00385  */
00386 #define ARBEL_RSVD_SPECIAL_QPS  ( ARBEL_NUM_SPECIAL_QPS + 1 )
00387 
00388 /** Maximum number of allocatable queue pairs
00389  *
00390  * This is a policy decision, not a device limit.
00391  */
00392 #define ARBEL_MAX_QPS           8
00393 
00394 /** Queue pair number randomisation mask */
00395 #define ARBEL_QPN_RANDOM_MASK 0xfff000
00396 
00397 /** Arbel queue pair state */
00398 enum arbel_queue_pair_state {
00399         ARBEL_QP_ST_RST = 0,
00400         ARBEL_QP_ST_INIT,
00401         ARBEL_QP_ST_RTR,
00402         ARBEL_QP_ST_RTS,
00403 };
00404 
00405 /** An Arbel queue pair */
00406 struct arbel_queue_pair {
00407         /** Send work queue */
00408         struct arbel_send_work_queue send;
00409         /** Receive work queue */
00410         struct arbel_recv_work_queue recv;
00411         /** Queue state */
00412         enum arbel_queue_pair_state state;
00413 };
00414 
00415 /** Maximum number of allocatable completion queues
00416  *
00417  * This is a policy decision, not a device limit.
00418  */
00419 #define ARBEL_MAX_CQS           8
00420 
00421 /** An Arbel completion queue */
00422 struct arbel_completion_queue {
00423         /** Consumer counter doorbell record number */
00424         unsigned int ci_doorbell_idx;
00425         /** Arm queue doorbell record number */
00426         unsigned int arm_doorbell_idx;
00427         /** Completion queue entries */
00428         union arbelprm_completion_entry *cqe;
00429         /** Size of completion queue */
00430         size_t cqe_size;
00431 };
00432 
00433 /** Maximum number of allocatable event queues
00434  *
00435  * This is a policy decision, not a device limit.
00436  */
00437 #define ARBEL_MAX_EQS           64
00438 
00439 /** A Arbel event queue */
00440 struct arbel_event_queue {
00441         /** Event queue entries */
00442         union arbelprm_event_entry *eqe;
00443         /** Size of event queue */
00444         size_t eqe_size;
00445         /** Event queue number */
00446         unsigned long eqn;
00447         /** Next event queue entry index */
00448         unsigned long next_idx;
00449         /** Doorbell register */
00450         void *doorbell;
00451 };
00452 
00453 /** Number of event queue entries
00454  *
00455  * This is a policy decision.
00456  */
00457 #define ARBEL_NUM_EQES          4
00458 
00459 
00460 /** An Arbel resource bitmask */
00461 typedef uint32_t arbel_bitmask_t;
00462 
00463 /** Size of an Arbel resource bitmask */
00464 #define ARBEL_BITMASK_SIZE(max_entries)                                      \
00465         ( ( (max_entries) + ( 8 * sizeof ( arbel_bitmask_t ) ) - 1 ) /       \
00466           ( 8 * sizeof ( arbel_bitmask_t ) ) )
00467 
00468 /** An Arbel device */
00469 struct arbel {
00470         /** PCI device */
00471         struct pci_device *pci;
00472         /** PCI configuration registers */
00473         void *config;
00474         /** PCI user Access Region */
00475         void *uar;
00476         /** Event queue consumer index doorbells */
00477         void *eq_ci_doorbells;
00478 
00479         /** Command input mailbox */
00480         void *mailbox_in;
00481         /** Command output mailbox */
00482         void *mailbox_out;
00483 
00484         /** Device open request counter */
00485         unsigned int open_count;
00486 
00487         /** Firmware size */
00488         size_t firmware_len;
00489         /** Firmware area in external memory
00490          *
00491          * This is allocated when first needed, and freed only on
00492          * final teardown, in order to avoid memory map changes at
00493          * runtime.
00494          */
00495         userptr_t firmware_area;
00496         /** ICM size */
00497         size_t icm_len;
00498         /** ICM AUX size */
00499         size_t icm_aux_len;
00500         /** ICM area
00501          *
00502          * This is allocated when first needed, and freed only on
00503          * final teardown, in order to avoid memory map changes at
00504          * runtime.
00505          */
00506         userptr_t icm;
00507         /** Offset within ICM of doorbell records */
00508         size_t db_rec_offset;
00509         /** Doorbell records */
00510         union arbelprm_doorbell_record *db_rec;
00511         /** Event queue */
00512         struct arbel_event_queue eq;
00513         /** Unrestricted LKey
00514          *
00515          * Used to get unrestricted memory access.
00516          */
00517         unsigned long lkey;
00518 
00519         /** Completion queue in-use bitmask */
00520         arbel_bitmask_t cq_inuse[ ARBEL_BITMASK_SIZE ( ARBEL_MAX_CQS ) ];
00521         /** Queue pair in-use bitmask */
00522         arbel_bitmask_t qp_inuse[ ARBEL_BITMASK_SIZE ( ARBEL_MAX_QPS ) ];
00523         
00524         /** Device limits */
00525         struct arbel_dev_limits limits;
00526         /** Special QPN base */
00527         unsigned long special_qpn_base;
00528         /** QPN base */
00529         unsigned long qpn_base;
00530 
00531         /** Infiniband devices */
00532         struct ib_device *ibdev[ARBEL_NUM_PORTS];
00533 };
00534 
00535 /** Global protection domain */
00536 #define ARBEL_GLOBAL_PD                 0x123456
00537 
00538 /** Memory key prefix */
00539 #define ARBEL_MKEY_PREFIX               0x77000000UL
00540 
00541 /*
00542  * HCA commands
00543  *
00544  */
00545 
00546 #define ARBEL_HCR_BASE                  0x80680
00547 #define ARBEL_HCR_REG(x)                ( ARBEL_HCR_BASE + 4 * (x) )
00548 #define ARBEL_HCR_MAX_WAIT_MS           2000
00549 #define ARBEL_MBOX_ALIGN                4096
00550 #define ARBEL_MBOX_SIZE                 512
00551 
00552 /* HCA command is split into
00553  *
00554  * bits  11:0   Opcode
00555  * bit     12   Input uses mailbox
00556  * bit     13   Output uses mailbox
00557  * bits 22:14   Input parameter length (in dwords)
00558  * bits 31:23   Output parameter length (in dwords)
00559  *
00560  * Encoding the information in this way allows us to cut out several
00561  * parameters to the arbel_command() call.
00562  */
00563 #define ARBEL_HCR_IN_MBOX               0x00001000UL
00564 #define ARBEL_HCR_OUT_MBOX              0x00002000UL
00565 #define ARBEL_HCR_OPCODE( _command )    ( (_command) & 0xfff )
00566 #define ARBEL_HCR_IN_LEN( _command )    ( ( (_command) >> 12 ) & 0x7fc )
00567 #define ARBEL_HCR_OUT_LEN( _command )   ( ( (_command) >> 21 ) & 0x7fc )
00568 
00569 /** Build HCR command from component parts */
00570 #define ARBEL_HCR_INOUT_CMD( _opcode, _in_mbox, _in_len,                     \
00571                              _out_mbox, _out_len )                           \
00572         ( (_opcode) |                                                        \
00573           ( (_in_mbox) ? ARBEL_HCR_IN_MBOX : 0 ) |                           \
00574           ( ( (_in_len) / 4 ) << 14 ) |                                      \
00575           ( (_out_mbox) ? ARBEL_HCR_OUT_MBOX : 0 ) |                         \
00576           ( ( (_out_len) / 4 ) << 23 ) )
00577 
00578 #define ARBEL_HCR_IN_CMD( _opcode, _in_mbox, _in_len )                       \
00579         ARBEL_HCR_INOUT_CMD ( _opcode, _in_mbox, _in_len, 0, 0 )
00580 
00581 #define ARBEL_HCR_OUT_CMD( _opcode, _out_mbox, _out_len )                    \
00582         ARBEL_HCR_INOUT_CMD ( _opcode, 0, 0, _out_mbox, _out_len )
00583 
00584 #define ARBEL_HCR_VOID_CMD( _opcode )                                        \
00585         ARBEL_HCR_INOUT_CMD ( _opcode, 0, 0, 0, 0 )
00586 
00587 /*
00588  * Doorbell record allocation
00589  *
00590  * The doorbell record map looks like:
00591  *
00592  *    ARBEL_MAX_CQS * Arm completion queue doorbell
00593  *    ARBEL_MAX_QPS * Send work request doorbell
00594  *    Group separator
00595  *    ...(empty space)...
00596  *    ARBEL_MAX_QPS * Receive work request doorbell
00597  *    ARBEL_MAX_CQS * Completion queue consumer counter update doorbell
00598  */
00599 
00600 #define ARBEL_MAX_DOORBELL_RECORDS 512
00601 #define ARBEL_GROUP_SEPARATOR_DOORBELL \
00602         ( ARBEL_MAX_CQS + ARBEL_RSVD_SPECIAL_QPS + ARBEL_MAX_QPS )
00603 
00604 /**
00605  * Get arm completion queue doorbell index
00606  *
00607  * @v arbel             Arbel device
00608  * @v cq                Completion queue
00609  * @ret doorbell_idx    Doorbell index
00610  */
00611 static inline unsigned int
00612 arbel_cq_arm_doorbell_idx ( struct arbel *arbel,
00613                             struct ib_completion_queue *cq ) {
00614         return ( cq->cqn - arbel->limits.reserved_cqs );
00615 }
00616 
00617 /**
00618  * Get send work request doorbell index
00619  *
00620  * @v arbel             Arbel device
00621  * @v qp                Queue pair
00622  * @ret doorbell_idx    Doorbell index
00623  */
00624 static inline unsigned int
00625 arbel_send_doorbell_idx ( struct arbel *arbel, struct ib_queue_pair *qp ) {
00626         return ( ARBEL_MAX_CQS +
00627                  ( ( qp->qpn & ~ARBEL_QPN_RANDOM_MASK ) -
00628                    arbel->special_qpn_base ) );
00629 }
00630 
00631 /**
00632  * Get receive work request doorbell index
00633  *
00634  * @v arbel             Arbel device
00635  * @v qp                Queue pair
00636  * @ret doorbell_idx    Doorbell index
00637  */
00638 static inline unsigned int
00639 arbel_recv_doorbell_idx ( struct arbel *arbel, struct ib_queue_pair *qp ) {
00640         return ( ARBEL_MAX_DOORBELL_RECORDS - ARBEL_MAX_CQS -
00641                  ( ( qp->qpn & ~ARBEL_QPN_RANDOM_MASK ) -
00642                    arbel->special_qpn_base ) - 1 );
00643 }
00644 
00645 /**
00646  * Get completion queue consumer counter doorbell index
00647  *
00648  * @v arbel             Arbel device
00649  * @v cq                Completion queue
00650  * @ret doorbell_idx    Doorbell index
00651  */
00652 static inline unsigned int
00653 arbel_cq_ci_doorbell_idx ( struct arbel *arbel,
00654                            struct ib_completion_queue *cq ) {
00655         return ( ARBEL_MAX_DOORBELL_RECORDS -
00656                  ( cq->cqn - arbel->limits.reserved_cqs ) - 1 );
00657 }
00658 
00659 #endif /* _ARBEL_H */