iPXE
pcnet32.h
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00001 /*
00002  * Copyright (c) 2010 Andrei Faur <da3drus@gmail.com>
00003  *
00004  * This program is free software; you can redistribute it and/or
00005  * modify it under the terms of the GNU General Public License as
00006  * published by the Free Software Foundation; either version 2 of the
00007  * License, or any later version.
00008  *
00009  * This program is distributed in the hope that it will be useful, but
00010  * WITHOUT ANY WARRANTY; without even the implied warranty of
00011  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
00012  * General Public License for more details.
00013  *
00014  * You should have received a copy of the GNU General Public License
00015  * along with this program; if not, write to the Free Software
00016  * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
00017  * 02110-1301, USA.
00018  *
00019  */
00020 
00021 FILE_LICENCE ( GPL2_OR_LATER );
00022 
00023 #ifndef _PCNET32_H_
00024 #define _PCNET32_H_
00025 
00026 /*
00027  * Set the number of Tx and Rx buffers, using Log_2(# buffers).
00028  * Set default values to 16 Tx buffers and 32 Rx buffers.
00029  */
00030 #define PCNET32_LOG_TX_BUFFERS          4
00031 #define PCNET32_LOG_RX_BUFFERS          5
00032 
00033 /* Maximum number of descriptor rings is 512 */
00034 #define PCNET32_LOG_MAX_TX_BUFFERS      9
00035 #define PCNET32_LOG_MAX_RX_BUFFERS      9
00036 
00037 #define TX_RING_SIZE            ( 1 << ( PCNET32_LOG_TX_BUFFERS ) )
00038 #define TX_MAX_RING_SIZE        ( 1 << ( PCNET32_LOG_MAX_TX_BUFFERS ) )
00039 
00040 #define RX_RING_SIZE            ( 1 << ( PCNET32_LOG_RX_BUFFERS ) )
00041 #define RX_MAX_RING_SIZE        ( 1 << ( PCNET32_LOG_MAX_RX_BUFFERS ) )
00042 
00043 #define RX_RING_BYTES           ( RX_RING_SIZE * sizeof(struct pcnet32_rx_desc ) )
00044 #define TX_RING_BYTES           ( TX_RING_SIZE * sizeof(struct pcnet32_tx_desc ) )
00045 
00046 #define PKT_BUF_SIZE    1536
00047 
00048 #define RX_RING_ALIGN           16
00049 #define TX_RING_ALIGN           16
00050 
00051 #define INIT_BLOCK_ALIGN        32
00052 
00053 #define PCNET32_WIO_RDP         0x10
00054 #define PCNET32_WIO_RAP         0x12
00055 #define PCNET32_WIO_RESET       0x14
00056 #define PCNET32_WIO_BDP         0x16
00057 
00058 #define PCNET32_DWIO_RDP        0x10
00059 #define PCNET32_DWIO_RAP        0x14
00060 #define PCNET32_DWIO_RESET      0x18
00061 #define PCNET32_DWIO_BDP        0x1C
00062 
00063 #define PCNET32_PORT_AUI        0x00
00064 #define PCNET32_PORT_10BT       0x01
00065 #define PCNET32_PORT_GPSI       0x02
00066 #define PCNET32_PORT_MII        0x03
00067 
00068 #define PCNET32_PORT_PORTSEL    0x03
00069 #define PCNET32_PORT_ASEL       0x04
00070 #define PCNET32_PORT_100        0x40
00071 #define PCNET32_PORT_FD         0x80
00072 
00073 #define PCNET32_SWSTYLE_LANCE   0x00
00074 #define PCNET32_SWSTYLE_ILACC   0x01
00075 #define PCNET32_SWSTYLE_PCNET32 0x02
00076 
00077 #define PCNET32_MAX_PHYS        32
00078 
00079 #ifndef PCI_VENDOR_ID_AT
00080 #define PCI_VENDOR_ID_AT        0x1259
00081 #endif
00082 
00083 #ifndef PCI_SUBDEVICE_ID_AT_2700FX
00084 #define PCI_SUBDEVICE_ID_AT_2700FX      0x2701
00085 #endif
00086 
00087 #ifndef PCI_SUBDEVICE_ID_AT_2701FX
00088 #define PCI_SUBDEVICE_ID_AT_2701FX      0x2703
00089 #endif
00090 
00091 struct pcnet32_rx_desc {
00092         u32 base;
00093         s16 buf_length;
00094         s16 status;
00095         u32 msg_length;
00096         u32 reserved;
00097 };
00098 
00099 struct pcnet32_tx_desc {
00100         u32 base;
00101         s16 length;
00102         s16 status;
00103         u32 misc;
00104         u32 reserved;
00105 };
00106 
00107 struct pcnet32_init_block {
00108         u16 mode;
00109         u16 tlen_rlen;
00110         u8 phys_addr[6];
00111         u16 reserved;
00112         u32 filter[2];
00113         u32 rx_ring;
00114         u32 tx_ring;
00115 };
00116 
00117 struct pcnet32_access {
00118         u16 ( *read_csr ) ( unsigned long, int );
00119         void ( *write_csr ) ( unsigned long, int, u16 );
00120         u16 ( *read_bcr ) ( unsigned long, int );
00121         void ( *write_bcr ) ( unsigned long, int, u16 );
00122         u16 ( *read_rap ) ( unsigned long );
00123         void ( *write_rap ) ( unsigned long, u16 );
00124         void ( *reset ) ( unsigned long );
00125 };
00126 
00127 struct pcnet32_private {
00128         struct pcnet32_init_block init_block __attribute__((aligned(32)));
00129         struct pci_device *pci_dev;
00130         struct net_device *netdev;
00131 
00132         struct io_buffer *rx_iobuf[RX_RING_SIZE];
00133         struct io_buffer *tx_iobuf[TX_RING_SIZE];
00134 
00135         struct pcnet32_rx_desc *rx_base;
00136         struct pcnet32_tx_desc *tx_base;
00137         uint32_t rx_curr;
00138         uint32_t tx_curr;
00139         uint32_t tx_tail;
00140         uint32_t tx_fill_ctr;
00141 
00142         struct pcnet32_access *a;
00143         int options;
00144         unsigned int    mii:1,
00145                         full_duplex:1;
00146 
00147         unsigned short chip_version;
00148 
00149         char irq_enabled;
00150 };
00151 
00152 enum pcnet32_desc_status_bit {
00153         DescOwn         = (1 << 15),
00154         StartOfPacket   = (1 << 9),
00155         EndOfPacket     = (1 << 8)
00156 };
00157 
00158 enum pcnet32_register_content {
00159         /* CSR0 bits - Controller status register */
00160         RxInt           = (1 << 10),
00161         TxInt           = (1 << 9),
00162         InitDone        = (1 << 8),
00163         IntFlag         = (1 << 7),
00164         IntEnable       = (1 << 6),
00165         TxDemand        = (1 << 3),
00166         Stop            = (1 << 2),
00167         Strt            = (1 << 1),
00168         Init            = (1 << 0),
00169 
00170         /* CSR3 bits - Controller status register */
00171         BablMask        = (1 << 14),
00172         MissFrameMask   = (1 << 12),
00173         MemErrMask      = (1 << 11),
00174         RxIntMask       = (1 << 10),
00175         TxIntMask       = (1 << 9),
00176         InitDoneMask    = (1 << 8)
00177 
00178 };
00179 
00180 #endif /* _PCNET32_H_ */