18 #define RTL_BAR_SIZE 0x100 33 #define RTL_DESC_SIZE_MASK 0x3fff 50 #define RTL_RING_ALIGN 256 78 #define RTL_TSD(n) ( 0x10 + 4 * (n) ) 79 #define RTL_TSD_ERTXTH(x) ( (x) << 16 ) 80 #define RTL_TSD_ERTXTH_DEFAULT RTL_TSD_ERTXTH ( 256 / 32 ) 81 #define RTL_TSD_OWN 0x00002000UL 84 #define RTL_TSAD(n) ( 0x20 + 4 * (n) ) 87 #define RTL_TNPDS 0x20 93 #define RTL_NUM_TX_DESC 4 96 #define RTL_RBSTART 0x30 99 #define RTL_RXBUF_LEN 8192 102 #define RTL_RXBUF_PAD 2038 105 #define RTL_RXBUF_ALIGN 16 109 #define RTL_CR_RST 0x10 110 #define RTL_CR_RE 0x08 111 #define RTL_CR_TE 0x04 112 #define RTL_CR_BUFE 0x01 115 #define RTL_RESET_MAX_WAIT_MS 100 118 #define RTL_CAPR 0x38 121 #define RTL_TPPOLL_8169 0x38 122 #define RTL_TPPOLL_NPQ 0x40 126 #define RTL_IRQ_PUN_LINKCHG 0x0020 127 #define RTL_IRQ_TER 0x0008 128 #define RTL_IRQ_TOK 0x0004 129 #define RTL_IRQ_RER 0x0002 130 #define RTL_IRQ_ROK 0x0001 137 #define RTL_TCR_MXDMA(x) ( (x) << 8 ) 138 #define RTL_TCR_MXDMA_MASK RTL_TCR_MXDMA ( 0x7 ) 139 #define RTL_TCR_MXDMA_DEFAULT RTL_TCR_MXDMA ( 0x7 ) 143 #define RTL_RCR_STOP_WORKING 0x01000000UL 144 #define RTL_RCR_RXFTH(x) ( (x) << 13 ) 145 #define RTL_RCR_RXFTH_MASK RTL_RCR_RXFTH ( 0x7 ) 146 #define RTL_RCR_RXFTH_DEFAULT RTL_RCR_RXFTH ( 0x7 ) 147 #define RTL_RCR_RBLEN(x) ( (x) << 11 ) 148 #define RTL_RCR_RBLEN_MASK RTL_RCR_RBLEN ( 0x3 ) 149 #define RTL_RCR_RBLEN_DEFAULT RTL_RCR_RBLEN ( 0 ) 150 #define RTL_RCR_MXDMA(x) ( (x) << 8 ) 151 #define RTL_RCR_MXDMA_MASK RTL_RCR_MXDMA ( 0x7 ) 152 #define RTL_RCR_MXDMA_DEFAULT RTL_RCR_MXDMA ( 0x7 ) 153 #define RTL_RCR_WRAP 0x00000080UL 154 #define RTL_RCR_9356SEL 0x00000040UL 155 #define RTL_RCR_AB 0x00000008UL 156 #define RTL_RCR_AM 0x00000004UL 157 #define RTL_RCR_APM 0x00000002UL 158 #define RTL_RCR_AAP 0x00000001UL 161 #define RTL_9346CR 0x50 162 #define RTL_9346CR_EEM(x) ( (x) << 6 ) 163 #define RTL_9346CR_EEM_EEPROM RTL_9346CR_EEM ( 0x2 ) 164 #define RTL_9346CR_EEM_NORMAL RTL_9346CR_EEM ( 0x0 ) 165 #define RTL_9346CR_EECS 0x08 166 #define RTL_9346CR_EESK 0x04 167 #define RTL_9346CR_EEDI 0x02 168 #define RTL_9346CR_EEDO 0x01 171 #define RTL_EEPROM_ID ( 0x00 / 2 ) 174 #define RTL_EEPROM_ID_MAGIC 0x8129 177 #define RTL_EEPROM_MAC ( 0x0e / 2 ) 180 #define RTL_EEPROM_VPD ( 0x40 / 2 ) 183 #define RTL_EEPROM_VPD_LEN 0x40 186 #define RTL_CONFIG1 0x52 187 #define RTL_CONFIG1_VPD 0x02 191 #define RTL_MSR_TXFCE 0x80 192 #define RTL_MSR_RXFCE 0x40 193 #define RTL_MSR_AUX_STATUS 0x10 194 #define RTL_MSR_SPEED_10 0x08 195 #define RTL_MSR_LINKB 0x04 196 #define RTL_MSR_TXPF 0x02 197 #define RTL_MSR_RXPF 0x01 200 #define RTL_PHYAR 0x60 201 #define RTL_PHYAR_FLAG 0x80000000UL 204 #define RTL_PHYAR_VALUE( flag, reg, data ) ( (flag) | ( (reg) << 16 ) | (data) ) 207 #define RTL_PHYAR_DATA( value ) ( (value) & 0xffff ) 210 #define RTL_MII_MAX_WAIT_US 500 213 #define RTL_PHYSTATUS 0x6c 214 #define RTL_PHYSTATUS_ENTBI 0x80 215 #define RTL_PHYSTATUS_TXFLOW 0x40 216 #define RTL_PHYSTATUS_RXFLOW 0x20 217 #define RTL_PHYSTATUS_1000MF 0x10 218 #define RTL_PHYSTATUS_100M 0x08 219 #define RTL_PHYSTATUS_10M 0x04 220 #define RTL_PHYSTATUS_LINKSTS 0x02 221 #define RTL_PHYSTATUS_FULLDUP 0x01 224 #define RTL_TPPOLL_8139CP 0xd9 230 #define RTL_CPCR 0xe0 231 #define RTL_CPCR_VLAN 0x0040 232 #define RTL_CPCR_DAC 0x0010 233 #define RTL_CPCR_MULRW 0x0008 234 #define RTL_CPCR_CPRX 0x0002 235 #define RTL_CPCR_CPTX 0x0001 238 #define RTL_RDSAR 0xe4 241 #define RTL_NUM_RX_DESC 4 244 #define RTL_RX_MAX_LEN \ 245 ( ETH_FRAME_LEN + 4 + 4 + 4 )
struct realtek_descriptor * desc
Descriptors.
static unsigned int unsigned int reg
struct dma_mapping map
Descriptor ring DMA mapping.
unsigned int prod
Producer index.
SPI bit-bashing interface.
FILE_LICENCE(GPL2_OR_LATER_OR_UBDL)
uint16_t length
Buffer size.
struct nvo_block nvo
Non-volatile options.
int have_phy_regs
PHYAR and PHYSTATUS registers are present.
unsigned long long uint64_t
uint32_t reserved
Reserved.
unsigned int reg
Descriptor start address register.
struct realtek_rx_buffer rxbuf
Receive buffer (legacy mode)
struct mii_device mii
MII device.
struct dma_device * dma
DMA device.
realtek_legacy_status
Legacy mode status bits.
struct realtek_ring rx
Receive descriptor ring.
unsigned int offset
Offset within buffer.
uint16_t count
Number of entries.
Descriptor is owned by NIC.
struct dma_mapping map
Buffer DMA mapping.
size_t len
Length (in bytes)
static void realtek_init_ring(struct realtek_ring *ring, unsigned int count, unsigned int reg)
Initialise descriptor ring.
realtek_descriptor_flags
Packet descriptor flags.
Non-volatile stored options.
A block of non-volatile stored options.
Receive buffer (legacy mode *)
unsigned int cons
Consumer index.
int legacy
Legacy datapath mode.
struct mii_interface mdio
MII interface.
unsigned int tppoll
TPPoll register offset.
uint64_t address
Buffer address.
A Realtek descriptor ring.
First segment descriptor.
struct realtek_ring tx
Transmit descriptor ring.
struct io_buffer * rx_iobuf[RTL_NUM_RX_DESC]
Receive I/O buffers.
#define RTL_NUM_RX_DESC
Number of receive descriptors.
struct spi_bit_basher spibit
SPI bit-bashing interface.