iPXE
sis190.h
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00001 #ifndef __SIS190_H__
00002 #define __SIS190_H__
00003 
00004 FILE_LICENCE ( GPL_ANY );
00005 
00006 #include <stdint.h>
00007 #include <stdio.h>
00008 #include <stdlib.h>
00009 #include <stddef.h>
00010 #include <string.h>
00011 #include <unistd.h>
00012 #include <assert.h>
00013 #include <byteswap.h>
00014 #include <errno.h>
00015 #include <mii.h>
00016 #include <ipxe/ethernet.h>
00017 #include <ipxe/if_ether.h>
00018 #include <ipxe/io.h>
00019 #include <ipxe/iobuf.h>
00020 #include <ipxe/malloc.h>
00021 #include <ipxe/netdevice.h>
00022 #include <ipxe/pci.h>
00023 #include <ipxe/timer.h>
00024 
00025 #define PCI_VENDOR_ID_SI        0x1039
00026 
00027 #define PHY_MAX_ADDR            32
00028 #define PHY_ID_ANY              0x1f
00029 #define MII_REG_ANY             0x1f
00030 
00031 #define DRV_VERSION             "1.3"
00032 #define DRV_NAME                "sis190"
00033 #define SIS190_DRIVER_NAME      DRV_NAME " Gigabit Ethernet driver " DRV_VERSION
00034 #define PFX DRV_NAME ": "
00035 
00036 #define sis190_rx_quota(count, quota)   count
00037 
00038 #define NUM_TX_DESC             8       /* [8..1024] */
00039 #define NUM_RX_DESC             8       /* [8..8192] */
00040 #define TX_RING_BYTES           (NUM_TX_DESC * sizeof(struct TxDesc))
00041 #define RX_RING_BYTES           (NUM_RX_DESC * sizeof(struct RxDesc))
00042 #define RX_BUF_SIZE             1536
00043 #define RX_BUF_MASK             0xfff8
00044 
00045 #define RING_ALIGNMENT          256
00046 
00047 #define SIS190_REGS_SIZE        0x80
00048 
00049 /* Enhanced PHY access register bit definitions */
00050 #define EhnMIIread              0x0000
00051 #define EhnMIIwrite             0x0020
00052 #define EhnMIIdataShift         16
00053 #define EhnMIIpmdShift          6       /* 7016 only */
00054 #define EhnMIIregShift          11
00055 #define EhnMIIreq               0x0010
00056 #define EhnMIInotDone           0x0010
00057 
00058 /* Write/read MMIO register */
00059 #define SIS_W8(reg, val)        writeb ((val), ioaddr + (reg))
00060 #define SIS_W16(reg, val)       writew ((val), ioaddr + (reg))
00061 #define SIS_W32(reg, val)       writel ((val), ioaddr + (reg))
00062 #define SIS_R8(reg)             readb (ioaddr + (reg))
00063 #define SIS_R16(reg)            readw (ioaddr + (reg))
00064 #define SIS_R32(reg)            readl (ioaddr + (reg))
00065 
00066 #define SIS_PCI_COMMIT()        SIS_R32(IntrControl)
00067 
00068 enum sis190_registers {
00069         TxControl               = 0x00,
00070         TxDescStartAddr         = 0x04,
00071         rsv0                    = 0x08, // reserved
00072         TxSts                   = 0x0c, // unused (Control/Status)
00073         RxControl               = 0x10,
00074         RxDescStartAddr         = 0x14,
00075         rsv1                    = 0x18, // reserved
00076         RxSts                   = 0x1c, // unused
00077         IntrStatus              = 0x20,
00078         IntrMask                = 0x24,
00079         IntrControl             = 0x28,
00080         IntrTimer               = 0x2c, // unused (Interrupt Timer)
00081         PMControl               = 0x30, // unused (Power Mgmt Control/Status)
00082         rsv2                    = 0x34, // reserved
00083         ROMControl              = 0x38,
00084         ROMInterface            = 0x3c,
00085         StationControl          = 0x40,
00086         GMIIControl             = 0x44,
00087         GIoCR                   = 0x48, // unused (GMAC IO Compensation)
00088         GIoCtrl                 = 0x4c, // unused (GMAC IO Control)
00089         TxMacControl            = 0x50,
00090         TxLimit                 = 0x54, // unused (Tx MAC Timer/TryLimit)
00091         RGDelay                 = 0x58, // unused (RGMII Tx Internal Delay)
00092         rsv3                    = 0x5c, // reserved
00093         RxMacControl            = 0x60,
00094         RxMacAddr               = 0x62,
00095         RxHashTable             = 0x68,
00096         // Undocumented         = 0x6c,
00097         RxWolCtrl               = 0x70,
00098         RxWolData               = 0x74, // unused (Rx WOL Data Access)
00099         RxMPSControl            = 0x78, // unused (Rx MPS Control)
00100         rsv4                    = 0x7c, // reserved
00101 };
00102 
00103 enum sis190_register_content {
00104         /* IntrStatus */
00105         SoftInt                 = 0x40000000,   // unused
00106         Timeup                  = 0x20000000,   // unused
00107         PauseFrame              = 0x00080000,   // unused
00108         MagicPacket             = 0x00040000,   // unused
00109         WakeupFrame             = 0x00020000,   // unused
00110         LinkChange              = 0x00010000,
00111         RxQEmpty                = 0x00000080,
00112         RxQInt                  = 0x00000040,
00113         TxQ1Empty               = 0x00000020,   // unused
00114         TxQ1Int                 = 0x00000010,
00115         TxQ0Empty               = 0x00000008,   // unused
00116         TxQ0Int                 = 0x00000004,
00117         RxHalt                  = 0x00000002,
00118         TxHalt                  = 0x00000001,
00119 
00120         /* {Rx/Tx}CmdBits */
00121         CmdReset                = 0x10,
00122         CmdRxEnb                = 0x08,         // unused
00123         CmdTxEnb                = 0x01,
00124         RxBufEmpty              = 0x01,         // unused
00125 
00126         /* Cfg9346Bits */
00127         Cfg9346_Lock            = 0x00,         // unused
00128         Cfg9346_Unlock          = 0xc0,         // unused
00129 
00130         /* RxMacControl */
00131         AcceptErr               = 0x20,         // unused
00132         AcceptRunt              = 0x10,         // unused
00133         AcceptBroadcast         = 0x0800,
00134         AcceptMulticast         = 0x0400,
00135         AcceptMyPhys            = 0x0200,
00136         AcceptAllPhys           = 0x0100,
00137 
00138         /* RxConfigBits */
00139         RxCfgFIFOShift          = 13,
00140         RxCfgDMAShift           = 8,            // 0x1a in RxControl ?
00141 
00142         /* TxConfigBits */
00143         TxInterFrameGapShift    = 24,
00144         TxDMAShift              = 8, /* DMA burst value (0-7) is shift this many bits */
00145 
00146         LinkStatus              = 0x02,         // unused
00147         FullDup                 = 0x01,         // unused
00148 
00149         /* TBICSRBit */
00150         TBILinkOK               = 0x02000000,   // unused
00151 };
00152 
00153 struct TxDesc {
00154         volatile u32 PSize;
00155         volatile u32 status;
00156         volatile u32 addr;
00157         volatile u32 size;
00158 };
00159 
00160 struct RxDesc {
00161         volatile u32 PSize;
00162         volatile u32 status;
00163         volatile u32 addr;
00164         volatile u32 size;
00165 };
00166 
00167 enum _DescStatusBit {
00168         /* _Desc.status */
00169         OWNbit          = 0x80000000, // RXOWN/TXOWN
00170         INTbit          = 0x40000000, // RXINT/TXINT
00171         CRCbit          = 0x00020000, // CRCOFF/CRCEN
00172         PADbit          = 0x00010000, // PREADD/PADEN
00173         /* _Desc.size */
00174         RingEnd         = 0x80000000,
00175         /* TxDesc.status */
00176         LSEN            = 0x08000000, // TSO ? -- FR
00177         IPCS            = 0x04000000,
00178         TCPCS           = 0x02000000,
00179         UDPCS           = 0x01000000,
00180         BSTEN           = 0x00800000,
00181         EXTEN           = 0x00400000,
00182         DEFEN           = 0x00200000,
00183         BKFEN           = 0x00100000,
00184         CRSEN           = 0x00080000,
00185         COLEN           = 0x00040000,
00186         THOL3           = 0x30000000,
00187         THOL2           = 0x20000000,
00188         THOL1           = 0x10000000,
00189         THOL0           = 0x00000000,
00190 
00191         WND             = 0x00080000,
00192         TABRT           = 0x00040000,
00193         FIFO            = 0x00020000,
00194         LINK            = 0x00010000,
00195         ColCountMask    = 0x0000ffff,
00196         /* RxDesc.status */
00197         IPON            = 0x20000000,
00198         TCPON           = 0x10000000,
00199         UDPON           = 0x08000000,
00200         Wakup           = 0x00400000,
00201         Magic           = 0x00200000,
00202         Pause           = 0x00100000,
00203         DEFbit          = 0x00200000,
00204         BCAST           = 0x000c0000,
00205         MCAST           = 0x00080000,
00206         UCAST           = 0x00040000,
00207         /* RxDesc.PSize */
00208         TAGON           = 0x80000000,
00209         RxDescCountMask = 0x7f000000, // multi-desc pkt when > 1 ? -- FR
00210         ABORT           = 0x00800000,
00211         SHORT           = 0x00400000,
00212         LIMIT           = 0x00200000,
00213         MIIER           = 0x00100000,
00214         OVRUN           = 0x00080000,
00215         NIBON           = 0x00040000,
00216         COLON           = 0x00020000,
00217         CRCOK           = 0x00010000,
00218         RxSizeMask      = 0x0000ffff
00219         /*
00220         * The asic could apparently do vlan, TSO, jumbo (sis191 only) and
00221         * provide two (unused with Linux) Tx queues. No publicly
00222         * available documentation alas.
00223         */
00224 };
00225 
00226 enum sis190_eeprom_access_register_bits {
00227         EECS    = 0x00000001,   // unused
00228         EECLK   = 0x00000002,   // unused
00229         EEDO    = 0x00000008,   // unused
00230         EEDI    = 0x00000004,   // unused
00231         EEREQ   = 0x00000080,
00232         EEROP   = 0x00000200,
00233         EEWOP   = 0x00000100    // unused
00234 };
00235 
00236 /* EEPROM Addresses */
00237 enum sis190_eeprom_address {
00238         EEPROMSignature = 0x00,
00239         EEPROMCLK       = 0x01, // unused
00240         EEPROMInfo      = 0x02,
00241         EEPROMMACAddr   = 0x03
00242 };
00243 
00244 enum sis190_feature {
00245         F_HAS_RGMII     = 1,
00246         F_PHY_88E1111   = 2,
00247         F_PHY_BCM5461   = 4
00248 };
00249 
00250 struct sis190_private {
00251         void *mmio_addr;
00252         struct pci_device *pci_device;
00253         struct net_device *dev;
00254         u32 cur_rx;
00255         u32 cur_tx;
00256         u32 dirty_rx;
00257         u32 dirty_tx;
00258         u32 rx_dma;
00259         u32 tx_dma;
00260         struct RxDesc *RxDescRing;
00261         struct TxDesc *TxDescRing;
00262         struct io_buffer *Rx_iobuf[NUM_RX_DESC];
00263         struct io_buffer *Tx_iobuf[NUM_TX_DESC];
00264         struct mii_if_info mii_if;
00265         struct list_head first_phy;
00266         u32 features;
00267 };
00268 
00269 struct sis190_phy {
00270         struct list_head list;
00271         int phy_id;
00272         u16 id[2];
00273         u16 status;
00274         u8  type;
00275 };
00276 
00277 enum sis190_phy_type {
00278         UNKNOWN = 0x00,
00279         HOME    = 0x01,
00280         LAN     = 0x02,
00281         MIX     = 0x03
00282 };
00283 
00284 static struct mii_chip_info {
00285         const char *name;
00286         u16 id[2];
00287         unsigned int type;
00288         u32 feature;
00289 } mii_chip_table[] = {
00290         { "Atheros PHY",          { 0x004d, 0xd010 }, LAN, 0 },
00291         { "Atheros PHY AR8012",   { 0x004d, 0xd020 }, LAN, 0 },
00292         { "Broadcom PHY BCM5461", { 0x0020, 0x60c0 }, LAN, F_PHY_BCM5461 },
00293         { "Broadcom PHY AC131",   { 0x0143, 0xbc70 }, LAN, 0 },
00294         { "Agere PHY ET1101B",    { 0x0282, 0xf010 }, LAN, 0 },
00295         { "Marvell PHY 88E1111",  { 0x0141, 0x0cc0 }, LAN, F_PHY_88E1111 },
00296         { "Realtek PHY RTL8201",  { 0x0000, 0x8200 }, LAN, 0 },
00297         { NULL, { 0x00, 0x00 }, 0, 0 }
00298 };
00299 
00300 static void sis190_phy_task(struct sis190_private *tp);
00301 static void sis190_free(struct net_device *dev);
00302 static inline void sis190_init_rxfilter(struct net_device *dev);
00303 
00304 #endif