iPXE
tulip.c
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00001 /* -*- Mode:C; c-basic-offset:4; -*- */
00002 
00003 /*
00004   Tulip and clone Etherboot Driver
00005 
00006   By Marty Connor (mdc@etherboot.org)
00007   Copyright (C) 2001 Entity Cyber, Inc.
00008 
00009   This software may be used and distributed according to the terms
00010   of the GNU Public License, incorporated herein by reference.
00011 
00012   As of April 2001 this driver should support most tulip cards that 
00013   the Linux tulip driver supports because Donald Becker's Linux media 
00014   detection code is now included.
00015 
00016   Based on Ken Yap's Tulip Etherboot Driver and Donald Becker's
00017   Linux Tulip Driver. Supports N-Way speed auto-configuration on
00018   MX98715, MX98715A and MX98725. Support inexpensive PCI 10/100 cards
00019   based on the Macronix MX987x5 chip, such as the SOHOware Fast
00020   model SFA110A, and the LinkSYS model LNE100TX. The NetGear
00021   model FA310X, based on the LC82C168 chip is supported.
00022   The TRENDnet TE100-PCIA NIC which uses a genuine Intel 21143-PD
00023   chipset is supported. Also, Davicom DM9102's.
00024 
00025   Documentation and source code used:
00026   Source for Etherboot driver at
00027   http://etherboot.sourceforge.net/
00028   MX98715A Data Sheet and MX98715A Application Note
00029   on http://www.macronix.com/  (PDF format files)
00030   Source for Linux tulip driver at
00031   http://cesdis.gsfc.nasa.gov/linux/drivers/tulip.html
00032 
00033   Adapted by Ken Yap from
00034   FreeBSD netboot DEC 21143 driver
00035   Author: David Sharp
00036   date: Nov/98
00037 
00038   Some code fragments were taken from verious places, Ken Yap's
00039   etherboot, FreeBSD's if_de.c, and various Linux related files.
00040   DEC's manuals for the 21143 and SROM format were very helpful.
00041   The Linux de driver development page has a number of links to
00042   useful related information.  Have a look at:
00043   ftp://cesdis.gsfc.nasa.gov/pub/linux/drivers/tulip-devel.html
00044 */
00045 
00046 FILE_LICENCE ( GPL_ANY );
00047 
00048 /*********************************************************************/
00049 /* Revision History                                                  */
00050 /*********************************************************************/
00051 
00052 /*
00053   08 Feb 2005  Ramesh Chander chhabaramesh at yahoo.co.in added table entries
00054                for SGThomson STE10/100A
00055   07 Sep 2003  timlegge Multicast Support Added
00056   11 Apr 2001  mdc     [patch to etherboot 4.7.24]
00057      Major rewrite to include Linux tulip driver media detection
00058      code.  This driver should support a lot more cards now.
00059   16 Jul 2000  mdc     0.75b11
00060      Added support for ADMtek 0985 Centaur-P, a "Comet" tulip clone
00061      which is used on the LinkSYS LNE100TX v4.x cards.  We already
00062      support LNE100TX v2.0 cards, which use a different controller.
00063   04 Jul 2000   jam     ?
00064      Added test of status after receiving a packet from the card.
00065      Also uncommented the tulip_disable routine.  Stray packets
00066      seemed to be causing problems.
00067   27 Apr 2000   njl     ?
00068   29 Feb 2000   mdc     0.75b7
00069      Increased reset delay to 3 seconds because Macronix cards seem to
00070      need more reset time before card comes back to a usable state.
00071   26 Feb 2000   mdc     0.75b6
00072      Added a 1 second delay after initializing the transmitter because
00073      some cards seem to need the time or they drop the first packet 
00074      transmitted.
00075   23 Feb 2000   mdc     0.75b5
00076      removed udelay code and used currticks() for more reliable delay
00077      code in reset pause and sanity timeouts.  Added function prototypes
00078      and TX debugging code.
00079   21 Feb 2000   mdc     patch to Etherboot 4.4.3
00080      Incorporated patches from Bob Edwards and Paul Mackerras of 
00081      Linuxcare's OZLabs to deal with inefficiencies in tulip_transmit
00082      and udelay.  We now wait for packet transmission to complete
00083      (or sanity timeout).
00084   04 Feb 2000   Robert.Edwards@anu.edu.au patch to Etherboot 4.4.2
00085      patch to tulip.c that implements the automatic selection of the MII
00086      interface on cards using the Intel/DEC 21143 reference design, in
00087      particular, the TRENDnet TE100-PCIA NIC which uses a genuine Intel
00088      21143-PD chipset.
00089   11 Jan 2000   mdc     0.75b4
00090      Added support for NetGear FA310TX card based on the LC82C168
00091      chip.  This should also support Lite-On LC82C168 boards.
00092      Added simple MII support. Re-arranged code to better modularize
00093      initializations.
00094   04 Dec 1999   mdc     0.75b3
00095      Added preliminary support for LNE100TX PCI cards.  Should work for
00096      PNIC2 cards. No MII support, but single interface (RJ45) tulip
00097      cards seem to not care.
00098   03 Dec 1999   mdc     0.75b2
00099      Renamed from mx987x5 to tulip, merged in original tulip init code
00100      from tulip.c to support other tulip compatible cards.
00101   02 Dec 1999   mdc     0.75b1
00102      Released Beta MX987x5 Driver for code review and testing to netboot
00103      and thinguin mailing lists.
00104 */
00105 
00106 
00107 /*********************************************************************/
00108 /* Declarations                                                      */
00109 /*********************************************************************/
00110 
00111 #include "etherboot.h"
00112 #include "nic.h"
00113 
00114 #include <ipxe/ethernet.h>
00115 #include <ipxe/pci.h>
00116 
00117 /* User settable parameters */
00118 
00119 #define TX_TIME_OUT       2*TICKS_PER_SEC
00120 
00121 /* helpful macros if on a big_endian machine for changing byte order.
00122    not strictly needed on Intel */
00123 #define get_unaligned(ptr) (*(ptr))
00124 #define put_unaligned(val, ptr) ((void)( *(ptr) = (val) ))
00125 #define get_u16(ptr) (*(u16 *)(ptr))
00126 #define virt_to_le32desc(addr)  virt_to_bus(addr)
00127 
00128 #define TULIP_IOTYPE  PCI_USES_MASTER | PCI_USES_IO | PCI_ADDR0
00129 #define TULIP_SIZE 0x80
00130 
00131 /* This is a mysterious value that can be written to CSR11 in the 21040 (only)
00132    to support a pre-NWay full-duplex signaling mechanism using short frames.
00133    No one knows what it should be, but if left at its default value some
00134    10base2(!) packets trigger a full-duplex-request interrupt. */
00135 #define FULL_DUPLEX_MAGIC       0x6969
00136 
00137 static const int csr0 = 0x01A00000 | 0x8000;
00138 
00139 /*  The possible media types that can be set in options[] are: */
00140 #define MEDIA_MASK 31
00141 static const char * const medianame[32] = {
00142     "10baseT", "10base2", "AUI", "100baseTx",
00143     "10baseT-FDX", "100baseTx-FDX", "100baseT4", "100baseFx",
00144     "100baseFx-FDX", "MII 10baseT", "MII 10baseT-FDX", "MII",
00145     "10baseT(forced)", "MII 100baseTx", "MII 100baseTx-FDX", "MII 100baseT4",
00146     "MII 100baseFx-HDX", "MII 100baseFx-FDX", "Home-PNA 1Mbps", "Invalid-19",
00147 };
00148 
00149 /* This much match tulip_tbl[]!  Note 21142 == 21143. */
00150 enum tulip_chips {
00151     DC21040=0, DC21041=1, DC21140=2, DC21142=3, DC21143=3,
00152     LC82C168, MX98713, MX98715, MX98725, AX88141, AX88140, PNIC2, COMET,
00153     COMPEX9881, I21145, XIRCOM, SGThomson,      /*Ramesh Chander*/
00154 };
00155 
00156 enum pci_id_flags_bits {
00157     /* Set PCI command register bits before calling probe1(). */
00158     PCI_USES_IO=1, PCI_USES_MEM=2, PCI_USES_MASTER=4,
00159     /* Read and map the single following PCI BAR. */
00160     PCI_ADDR0=0<<4, PCI_ADDR1=1<<4, PCI_ADDR2=2<<4, PCI_ADDR3=3<<4,
00161     PCI_ADDR_64BITS=0x100, PCI_NO_ACPI_WAKE=0x200, PCI_NO_MIN_LATENCY=0x400,
00162     PCI_UNUSED_IRQ=0x800,
00163 };
00164 
00165 struct pci_id_info {
00166     char *name;
00167     struct match_info {
00168         u32 pci, pci_mask, subsystem, subsystem_mask;
00169         u32 revision, revision_mask;                            /* Only 8 bits. */
00170     } id;
00171     enum pci_id_flags_bits pci_flags;
00172     int io_size;                                /* Needed for I/O region check or ioremap(). */
00173     int drv_flags;                              /* Driver use, intended as capability flags. */
00174 };
00175 
00176 static const struct pci_id_info pci_id_tbl[] = {
00177     { "Digital DC21040 Tulip", { 0x00021011, 0xffffffff, 0, 0, 0, 0 },
00178       TULIP_IOTYPE, 0x80, DC21040 },
00179     { "Digital DC21041 Tulip", { 0x00141011, 0xffffffff, 0, 0, 0, 0 },
00180       TULIP_IOTYPE, 0x80, DC21041 },
00181     { "Digital DS21140A Tulip", { 0x00091011, 0xffffffff, 0,0, 0x20,0xf0 },
00182       TULIP_IOTYPE, 0x80, DC21140 },
00183     { "Digital DS21140 Tulip", { 0x00091011, 0xffffffff, 0, 0, 0, 0 },
00184       TULIP_IOTYPE, 0x80, DC21140 },
00185     { "Digital DS21143 Tulip", { 0x00191011, 0xffffffff, 0,0, 65,0xff },
00186       TULIP_IOTYPE, TULIP_SIZE, DC21142 },
00187     { "Digital DS21142 Tulip", { 0x00191011, 0xffffffff, 0, 0, 0, 0 },
00188       TULIP_IOTYPE, TULIP_SIZE, DC21142 },
00189     { "Kingston KNE110tx (PNIC)", { 0x000211AD, 0xffffffff, 0xf0022646, 0xffffffff, 0, 0 },
00190       TULIP_IOTYPE, 256, LC82C168 },
00191     { "Lite-On 82c168 PNIC", { 0x000211AD, 0xffffffff, 0, 0, 0, 0 },
00192       TULIP_IOTYPE, 256, LC82C168 },
00193     { "Macronix 98713 PMAC", { 0x051210d9, 0xffffffff, 0, 0, 0, 0 },
00194       TULIP_IOTYPE, 256, MX98713 },
00195     { "Macronix 98715 PMAC", { 0x053110d9, 0xffffffff, 0, 0, 0, 0 },
00196       TULIP_IOTYPE, 256, MX98715 },
00197     { "Macronix 98725 PMAC", { 0x053110d9, 0xffffffff, 0, 0, 0, 0 },
00198       TULIP_IOTYPE, 256, MX98725 },
00199     { "ASIX AX88141", { 0x1400125B, 0xffffffff, 0,0, 0x10, 0xf0 },
00200       TULIP_IOTYPE, 128, AX88141 },
00201     { "ASIX AX88140", { 0x1400125B, 0xffffffff, 0, 0, 0, 0 },
00202       TULIP_IOTYPE, 128, AX88140 },
00203     { "Lite-On LC82C115 PNIC-II", { 0xc11511AD, 0xffffffff, 0, 0, 0, 0 },
00204       TULIP_IOTYPE, 256, PNIC2 },
00205     { "ADMtek AN981 Comet", { 0x09811317, 0xffffffff, 0, 0, 0, 0 },
00206       TULIP_IOTYPE, 256, COMET },
00207     { "ADMTek AN983 Comet", { 0x12161113, 0xffffffff, 0, 0, 0, 0 },
00208       TULIP_IOTYPE, 256, COMET },
00209     { "ADMTek Comet AN983b", { 0x95111317, 0xffffffff, 0, 0, 0, 0 },
00210       TULIP_IOTYPE, 256, COMET },
00211     { "ADMtek Centaur-P", { 0x09851317, 0xffffffff, 0, 0, 0, 0 },
00212       TULIP_IOTYPE, 256, COMET },
00213     { "ADMtek Centaur-C", { 0x19851317, 0xffffffff, 0, 0, 0, 0 },
00214       TULIP_IOTYPE, 256, COMET },
00215     { "Compex RL100-TX", { 0x988111F6, 0xffffffff, 0, 0, 0, 0 },
00216       TULIP_IOTYPE, 128, COMPEX9881 },
00217     { "Intel 21145 Tulip", { 0x00398086, 0xffffffff, 0, 0, 0, 0 },
00218       TULIP_IOTYPE, 128, I21145 },
00219     { "Xircom Tulip clone", { 0x0003115d, 0xffffffff, 0, 0, 0, 0 },
00220       TULIP_IOTYPE, 128, XIRCOM },
00221     { "Davicom DM9102", { 0x91021282, 0xffffffff, 0, 0, 0, 0 },
00222       TULIP_IOTYPE, 0x80, DC21140 },
00223     { "Davicom DM9100", { 0x91001282, 0xffffffff, 0, 0, 0, 0 },
00224       TULIP_IOTYPE, 0x80, DC21140 },
00225     { "Macronix mxic-98715 (EN1217)", { 0x12171113, 0xffffffff, 0, 0, 0, 0 },
00226       TULIP_IOTYPE, 256, MX98715 },
00227     { "3Com 3cSOHO100B-TX (ADMtek Centuar)", { 0x930010b7, 0xffffffff, 0, 0, 0, 0 },
00228       TULIP_IOTYPE, TULIP_SIZE, COMET },
00229     { "SG Thomson STE10/100A", { 0x2774104a, 0xffffffff, 0, 0, 0, 0 },
00230       TULIP_IOTYPE, 256, COMET },       /*Ramesh Chander*/
00231     { NULL, { 0, 0, 0, 0, 0, 0 }, 0, 0, 0 },
00232 };
00233 
00234 enum tbl_flag {
00235     HAS_MII=1, HAS_MEDIA_TABLE=2, CSR12_IN_SROM=4, ALWAYS_CHECK_MII=8,
00236     HAS_PWRDWN=0x10, MC_HASH_ONLY=0x20, /* Hash-only multicast filter. */
00237     HAS_PNICNWAY=0x80, HAS_NWAY=0x40,   /* Uses internal NWay xcvr. */
00238     HAS_INTR_MITIGATION=0x100, IS_ASIX=0x200, HAS_8023X=0x400,
00239 };
00240 
00241 /* Note: this table must match  enum tulip_chips  above. */
00242 static struct tulip_chip_table {
00243     char *chip_name;
00244     int flags;
00245 } tulip_tbl[] = {
00246     { "Digital DC21040 Tulip", 0},
00247     { "Digital DC21041 Tulip", HAS_MEDIA_TABLE | HAS_NWAY },
00248     { "Digital DS21140 Tulip", HAS_MII | HAS_MEDIA_TABLE | CSR12_IN_SROM },
00249     { "Digital DS21143 Tulip", HAS_MII | HAS_MEDIA_TABLE | ALWAYS_CHECK_MII 
00250       | HAS_PWRDWN | HAS_NWAY   | HAS_INTR_MITIGATION },
00251     { "Lite-On 82c168 PNIC", HAS_MII | HAS_PNICNWAY },
00252     { "Macronix 98713 PMAC", HAS_MII | HAS_MEDIA_TABLE | CSR12_IN_SROM },
00253     { "Macronix 98715 PMAC", HAS_MEDIA_TABLE },
00254     { "Macronix 98725 PMAC", HAS_MEDIA_TABLE },
00255     { "ASIX AX88140", HAS_MII | HAS_MEDIA_TABLE | CSR12_IN_SROM 
00256       | MC_HASH_ONLY | IS_ASIX },
00257     { "ASIX AX88141", HAS_MII | HAS_MEDIA_TABLE | CSR12_IN_SROM | MC_HASH_ONLY 
00258       | IS_ASIX },
00259     { "Lite-On PNIC-II", HAS_MII | HAS_NWAY | HAS_8023X },
00260     { "ADMtek Comet", HAS_MII | MC_HASH_ONLY },
00261     { "Compex 9881 PMAC",       HAS_MII | HAS_MEDIA_TABLE | CSR12_IN_SROM },
00262     { "Intel DS21145 Tulip", HAS_MII | HAS_MEDIA_TABLE | ALWAYS_CHECK_MII 
00263       | HAS_PWRDWN | HAS_NWAY },
00264     { "Xircom tulip work-alike", HAS_MII | HAS_MEDIA_TABLE | ALWAYS_CHECK_MII 
00265       | HAS_PWRDWN | HAS_NWAY },
00266     { "SGThomson STE10/100A", HAS_MII | MC_HASH_ONLY }, /*Ramesh Chander*/   
00267     { NULL, 0 },
00268 };
00269 
00270 /* A full-duplex map for media types. */
00271 enum MediaIs {
00272     MediaIsFD = 1, MediaAlwaysFD=2, MediaIsMII=4, MediaIsFx=8,
00273     MediaIs100=16};
00274 
00275 static const char media_cap[32] =
00276 {0,0,0,16,  3,19,16,24,  27,4,7,5, 0,20,23,20, 20,31,0,0, };
00277 static u8 t21040_csr13[] = {2,0x0C,8,4,  4,0,0,0, 0,0,0,0, 4,0,0,0};
00278 
00279 /* 21041 transceiver register settings: 10-T, 10-2, AUI, 10-T, 10T-FD */
00280 static u16 t21041_csr13[] = { 0xEF01, 0xEF09, 0xEF09, 0xEF01, 0xEF09, };
00281 static u16 t21041_csr14[] = { 0xFFFF, 0xF7FD, 0xF7FD, 0x7F3F, 0x7F3D, };
00282 static u16 t21041_csr15[] = { 0x0008, 0x0006, 0x000E, 0x0008, 0x0008, };
00283 
00284 /* not used
00285 static u16 t21142_csr13[] = { 0x0001, 0x0009, 0x0009, 0x0000, 0x0001, };
00286 */
00287 static u16 t21142_csr14[] = { 0xFFFF, 0x0705, 0x0705, 0x0000, 0x7F3D, };
00288 /* not used
00289 static u16 t21142_csr15[] = { 0x0008, 0x0006, 0x000E, 0x0008, 0x0008, };
00290 */
00291 
00292 /* Offsets to the Command and Status Registers, "CSRs".  All accesses
00293    must be longword instructions and quadword aligned. */
00294 enum tulip_offsets {
00295     CSR0=0,     CSR1=0x08,  CSR2=0x10,  CSR3=0x18,  CSR4=0x20,  CSR5=0x28,
00296     CSR6=0x30,  CSR7=0x38,  CSR8=0x40,  CSR9=0x48, CSR10=0x50, CSR11=0x58,
00297     CSR12=0x60, CSR13=0x68, CSR14=0x70, CSR15=0x78, CSR16=0x80, CSR20=0xA0
00298 };
00299 
00300 /* The bits in the CSR5 status registers, mostly interrupt sources. */
00301 enum status_bits {
00302     TimerInt=0x800, TPLnkFail=0x1000, TPLnkPass=0x10,
00303     NormalIntr=0x10000, AbnormalIntr=0x8000,
00304     RxJabber=0x200, RxDied=0x100, RxNoBuf=0x80, RxIntr=0x40,
00305     TxFIFOUnderflow=0x20, TxJabber=0x08, TxNoBuf=0x04, TxDied=0x02, TxIntr=0x01,
00306 };
00307 
00308 /* The configuration bits in CSR6. */
00309 enum csr6_mode_bits {
00310         TxOn=0x2000, RxOn=0x0002, FullDuplex=0x0200,
00311         AcceptBroadcast=0x0100, AcceptAllMulticast=0x0080,
00312         AcceptAllPhys=0x0040, AcceptRunt=0x0008,
00313 };
00314 
00315 
00316 enum desc_status_bits {
00317     DescOwnded=0x80000000, RxDescFatalErr=0x8000, RxWholePkt=0x0300,
00318 };
00319 
00320 struct medialeaf {
00321     u8 type;
00322     u8 media;
00323     unsigned char *leafdata;
00324 };
00325 
00326 struct mediatable {
00327     u16 defaultmedia;
00328     u8 leafcount, csr12dir;                             /* General purpose pin directions. */
00329     unsigned has_mii:1, has_nonmii:1, has_reset:6;
00330     u32 csr15dir, csr15val;                             /* 21143 NWay setting. */
00331     struct medialeaf mleaf[0];
00332 };
00333 
00334 struct mediainfo {
00335     struct mediainfo *next;
00336     int info_type;
00337     int index;
00338     unsigned char *info;
00339 };
00340 
00341 /* EEPROM Address width definitions */
00342 #define EEPROM_ADDRLEN 6
00343 #define EEPROM_SIZE    128              /* 2 << EEPROM_ADDRLEN */
00344 
00345 /* The EEPROM commands include the alway-set leading bit. */
00346 #define EE_WRITE_CMD    (5 << addr_len)
00347 #define EE_READ_CMD     (6 << addr_len)
00348 #define EE_ERASE_CMD    (7 << addr_len)
00349 
00350 /* EEPROM_Ctrl bits. */
00351 #define EE_SHIFT_CLK    0x02    /* EEPROM shift clock. */
00352 #define EE_CS           0x01    /* EEPROM chip select. */
00353 #define EE_DATA_WRITE   0x04    /* EEPROM chip data in. */
00354 #define EE_WRITE_0      0x01
00355 #define EE_WRITE_1      0x05
00356 #define EE_DATA_READ    0x08    /* EEPROM chip data out. */
00357 #define EE_ENB          (0x4800 | EE_CS)
00358 
00359 /* Delay between EEPROM clock transitions.  Even at 33Mhz current PCI
00360    implementations don't overrun the EEPROM clock.  We add a bus
00361    turn-around to insure that this remains true.  */
00362 #define eeprom_delay()  inl(ee_addr)
00363 
00364 /* Size of transmit and receive buffers */
00365 #define BUFLEN 1536
00366 
00367 /* Ring-wrap flag in length field, use for last ring entry.
00368    0x01000000 means chain on buffer2 address,
00369    0x02000000 means use the ring start address in CSR2/3.
00370    Note: Some work-alike chips do not function correctly in chained mode.
00371    The ASIX chip works only in chained mode.
00372    Thus we indicate ring mode, but always write the 'next' field for
00373    chained mode as well. */
00374 #define DESC_RING_WRAP 0x02000000
00375 
00376 /* transmit and receive descriptor format */
00377 struct tulip_rx_desc {
00378     volatile u32 status;
00379     u32 length;
00380     u32 buffer1, buffer2;
00381 };
00382 
00383 struct tulip_tx_desc {
00384     volatile u32 status;
00385     u32 length;
00386     u32 buffer1, buffer2;
00387 };
00388 
00389 /*********************************************************************/
00390 /* Global Storage                                                    */
00391 /*********************************************************************/
00392 
00393 static u32 ioaddr;
00394 
00395 struct tulip_private {
00396     int cur_rx;
00397     int chip_id;                        /* index into tulip_tbl[]  */
00398     int pci_id_idx;                     /* index into pci_id_tbl[] */
00399     int revision;
00400     int flags;
00401     unsigned short vendor_id;           /* PCI card vendor code */
00402     unsigned short dev_id;              /* PCI card device code */
00403     unsigned char ehdr[ETH_HLEN];       /* buffer for ethernet header */
00404     const char *nic_name;
00405     unsigned int csr0, csr6;            /* Current CSR0, CSR6 settings. */
00406     unsigned int if_port;
00407     unsigned int full_duplex;         /* Full-duplex operation requested. */
00408     unsigned int full_duplex_lock;
00409     unsigned int medialock;           /* Do not sense media type. */
00410     unsigned int mediasense;          /* Media sensing in progress. */
00411     unsigned int nway, nwayset;     /* 21143 internal NWay. */
00412     unsigned int default_port;
00413     unsigned char eeprom[EEPROM_SIZE];  /* Serial EEPROM contents. */
00414     u8 media_table_storage[(sizeof(struct mediatable) + 32*sizeof(struct medialeaf))];
00415     u16 sym_advertise, mii_advertise;   /* NWay to-advertise. */
00416     struct mediatable *mtable;
00417     u16 lpar;                           /* 21143 Link partner ability. */
00418     u16 advertising[4];                 /* MII advertise, from SROM table. */
00419     signed char phys[4], mii_cnt;       /* MII device addresses. */
00420     int cur_index;                      /* Current media index. */
00421     int saved_if_port;
00422 };
00423 
00424 /* Note: transmit and receive buffers must be longword aligned and
00425    longword divisable */
00426 
00427 #define TX_RING_SIZE    2
00428 #define RX_RING_SIZE    4
00429 struct {
00430     struct tulip_tx_desc tx_ring[TX_RING_SIZE];
00431     unsigned char txb[BUFLEN];
00432     struct tulip_rx_desc rx_ring[RX_RING_SIZE];
00433     unsigned char rxb[RX_RING_SIZE * BUFLEN];
00434     struct tulip_private tpx;
00435 } tulip_bss __shared __attribute__ ((aligned(4)));
00436 #define tx_ring tulip_bss.tx_ring
00437 #define txb tulip_bss.txb
00438 #define rx_ring tulip_bss.rx_ring
00439 #define rxb tulip_bss.rxb
00440 
00441 static struct tulip_private *tp;
00442 
00443 /* Known cards that have old-style EEPROMs.
00444    Writing this table is described at
00445    http://cesdis.gsfc.nasa.gov/linux/drivers/tulip-drivers/tulip-media.html */
00446 static struct fixups {
00447     char *name;
00448     unsigned char addr0, addr1, addr2;
00449     u16 newtable[32];                           /* Max length below. */
00450 } eeprom_fixups[] = {
00451     {"Asante", 0, 0, 0x94, {0x1e00, 0x0000, 0x0800, 0x0100, 0x018c,
00452                             0x0000, 0x0000, 0xe078, 0x0001, 0x0050, 0x0018 }},
00453     {"SMC9332DST", 0, 0, 0xC0, { 0x1e00, 0x0000, 0x0800, 0x041f,
00454                                  0x0000, 0x009E, /* 10baseT */
00455                                  0x0004, 0x009E, /* 10baseT-FD */
00456                                  0x0903, 0x006D, /* 100baseTx */
00457                                  0x0905, 0x006D, /* 100baseTx-FD */ }},
00458     {"Cogent EM100", 0, 0, 0x92, { 0x1e00, 0x0000, 0x0800, 0x063f,
00459                                    0x0107, 0x8021, /* 100baseFx */
00460                                    0x0108, 0x8021, /* 100baseFx-FD */
00461                                    0x0100, 0x009E, /* 10baseT */
00462                                    0x0104, 0x009E, /* 10baseT-FD */
00463                                    0x0103, 0x006D, /* 100baseTx */
00464                                    0x0105, 0x006D, /* 100baseTx-FD */ }},
00465     {"Maxtech NX-110", 0, 0, 0xE8, { 0x1e00, 0x0000, 0x0800, 0x0513,
00466                                      0x1001, 0x009E, /* 10base2, CSR12 0x10*/
00467                                      0x0000, 0x009E, /* 10baseT */
00468                                      0x0004, 0x009E, /* 10baseT-FD */
00469                                      0x0303, 0x006D, /* 100baseTx, CSR12 0x03 */
00470                                      0x0305, 0x006D, /* 100baseTx-FD CSR12 0x03 */}},
00471     {"Accton EN1207", 0, 0, 0xE8, { 0x1e00, 0x0000, 0x0800, 0x051F,
00472                                     0x1B01, 0x0000, /* 10base2,   CSR12 0x1B */
00473                                     0x0B00, 0x009E, /* 10baseT,   CSR12 0x0B */
00474                                     0x0B04, 0x009E, /* 10baseT-FD,CSR12 0x0B */
00475                                     0x1B03, 0x006D, /* 100baseTx, CSR12 0x1B */
00476                                     0x1B05, 0x006D, /* 100baseTx-FD CSR12 0x1B */
00477     }},
00478     {NULL, 0, 0, 0, {}}};
00479 
00480 static const char * block_name[] = {"21140 non-MII", "21140 MII PHY",
00481                                     "21142 Serial PHY", "21142 MII PHY", "21143 SYM PHY", "21143 reset method"};
00482 
00483 
00484 /*********************************************************************/
00485 /* Function Prototypes                                               */
00486 /*********************************************************************/
00487 static int mdio_read(struct nic *nic, int phy_id, int location);
00488 static void mdio_write(struct nic *nic, int phy_id, int location, int value);
00489 static int read_eeprom(unsigned long ioaddr, int location, int addr_len);
00490 static void parse_eeprom(struct nic *nic);
00491 static int tulip_probe(struct nic *nic,struct pci_device *pci);
00492 static void tulip_init_ring(struct nic *nic);
00493 static void tulip_reset(struct nic *nic);
00494 static void tulip_transmit(struct nic *nic, const char *d, unsigned int t,
00495                            unsigned int s, const char *p);
00496 static int tulip_poll(struct nic *nic, int retrieve);
00497 static void tulip_disable(struct nic *nic);
00498 static void nway_start(struct nic *nic);
00499 static void pnic_do_nway(struct nic *nic);
00500 static void select_media(struct nic *nic, int startup);
00501 static void init_media(struct nic *nic);
00502 static void start_link(struct nic *nic);
00503 static int tulip_check_duplex(struct nic *nic);
00504 
00505 static void tulip_wait(unsigned int nticks);
00506 
00507 
00508 /*********************************************************************/
00509 /* Utility Routines                                                  */
00510 /*********************************************************************/
00511 
00512 static void whereami (const char *str)
00513 {
00514     DBGP("%s\n", str);
00515     /* sleep(2); */
00516 }
00517 
00518 static void tulip_wait(unsigned int nticks)
00519 {
00520     unsigned int to = currticks() + nticks;
00521     while (currticks() < to)
00522         /* wait */ ;
00523 }
00524 
00525 
00526 /*********************************************************************/
00527 /* Media Descriptor Code                                             */
00528 /*********************************************************************/
00529 
00530 /* MII transceiver control section.
00531    Read and write the MII registers using software-generated serial
00532    MDIO protocol.  See the MII specifications or DP83840A data sheet
00533    for details. */
00534 
00535 /* The maximum data clock rate is 2.5 Mhz.  The minimum timing is usually
00536    met by back-to-back PCI I/O cycles, but we insert a delay to avoid
00537    "overclocking" issues or future 66Mhz PCI. */
00538 #define mdio_delay() inl(mdio_addr)
00539 
00540 /* Read and write the MII registers using software-generated serial
00541    MDIO protocol.  It is just different enough from the EEPROM protocol
00542    to not share code.  The maxium data clock rate is 2.5 Mhz. */
00543 #define MDIO_SHIFT_CLK  0x10000
00544 #define MDIO_DATA_WRITE0 0x00000
00545 #define MDIO_DATA_WRITE1 0x20000
00546 #define MDIO_ENB                0x00000         /* Ignore the 0x02000 databook setting. */
00547 #define MDIO_ENB_IN             0x40000
00548 #define MDIO_DATA_READ  0x80000
00549 
00550 /* MII transceiver control section.
00551    Read and write the MII registers using software-generated serial
00552    MDIO protocol.  See the MII specifications or DP83840A data sheet
00553    for details. */
00554 
00555 int mdio_read(struct nic *nic __unused, int phy_id, int location)
00556 {
00557     int i;
00558     int read_cmd = (0xf6 << 10) | (phy_id << 5) | location;
00559     int retval = 0;
00560     long mdio_addr = ioaddr + CSR9;
00561 
00562     whereami("mdio_read\n");
00563 
00564     if (tp->chip_id == LC82C168) {
00565         int i = 1000;
00566         outl(0x60020000 + (phy_id<<23) + (location<<18), ioaddr + 0xA0);
00567         inl(ioaddr + 0xA0);
00568         inl(ioaddr + 0xA0);
00569         while (--i > 0)
00570             if ( ! ((retval = inl(ioaddr + 0xA0)) & 0x80000000))
00571                 return retval & 0xffff;
00572         return 0xffff;
00573     }
00574 
00575     if (tp->chip_id == COMET) {
00576         if (phy_id == 1) {
00577             if (location < 7)
00578                 return inl(ioaddr + 0xB4 + (location<<2));
00579             else if (location == 17)
00580                 return inl(ioaddr + 0xD0);
00581             else if (location >= 29 && location <= 31)
00582                 return inl(ioaddr + 0xD4 + ((location-29)<<2));
00583         }
00584         return 0xffff;
00585     }
00586 
00587     /* Establish sync by sending at least 32 logic ones. */
00588     for (i = 32; i >= 0; i--) {
00589         outl(MDIO_ENB | MDIO_DATA_WRITE1, mdio_addr);
00590         mdio_delay();
00591         outl(MDIO_ENB | MDIO_DATA_WRITE1 | MDIO_SHIFT_CLK, mdio_addr);
00592         mdio_delay();
00593     }
00594     /* Shift the read command bits out. */
00595     for (i = 15; i >= 0; i--) {
00596         int dataval = (read_cmd & (1 << i)) ? MDIO_DATA_WRITE1 : 0;
00597 
00598         outl(MDIO_ENB | dataval, mdio_addr);
00599         mdio_delay();
00600         outl(MDIO_ENB | dataval | MDIO_SHIFT_CLK, mdio_addr);
00601         mdio_delay();
00602     }
00603     /* Read the two transition, 16 data, and wire-idle bits. */
00604     for (i = 19; i > 0; i--) {
00605         outl(MDIO_ENB_IN, mdio_addr);
00606         mdio_delay();
00607         retval = (retval << 1) | ((inl(mdio_addr) & MDIO_DATA_READ) ? 1 : 0);
00608         outl(MDIO_ENB_IN | MDIO_SHIFT_CLK, mdio_addr);
00609         mdio_delay();
00610     }
00611     return (retval>>1) & 0xffff;
00612 }
00613 
00614 void mdio_write(struct nic *nic __unused, int phy_id, int location, int value)
00615 {
00616     int i;
00617     int cmd = (0x5002 << 16) | (phy_id << 23) | (location<<18) | value;
00618     long mdio_addr = ioaddr + CSR9;
00619 
00620     whereami("mdio_write\n");
00621 
00622     if (tp->chip_id == LC82C168) {
00623         int i = 1000;
00624         outl(cmd, ioaddr + 0xA0);
00625         do
00626             if ( ! (inl(ioaddr + 0xA0) & 0x80000000))
00627                 break;
00628         while (--i > 0);
00629         return;
00630     }
00631 
00632     if (tp->chip_id == COMET) {
00633         if (phy_id != 1)
00634             return;
00635         if (location < 7)
00636             outl(value, ioaddr + 0xB4 + (location<<2));
00637         else if (location == 17)
00638             outl(value, ioaddr + 0xD0);
00639         else if (location >= 29 && location <= 31)
00640             outl(value, ioaddr + 0xD4 + ((location-29)<<2));
00641         return;
00642     }
00643 
00644     /* Establish sync by sending 32 logic ones. */
00645     for (i = 32; i >= 0; i--) {
00646         outl(MDIO_ENB | MDIO_DATA_WRITE1, mdio_addr);
00647         mdio_delay();
00648         outl(MDIO_ENB | MDIO_DATA_WRITE1 | MDIO_SHIFT_CLK, mdio_addr);
00649         mdio_delay();
00650     }
00651     /* Shift the command bits out. */
00652     for (i = 31; i >= 0; i--) {
00653         int dataval = (cmd & (1 << i)) ? MDIO_DATA_WRITE1 : 0;
00654         outl(MDIO_ENB | dataval, mdio_addr);
00655         mdio_delay();
00656         outl(MDIO_ENB | dataval | MDIO_SHIFT_CLK, mdio_addr);
00657         mdio_delay();
00658     }
00659     /* Clear out extra bits. */
00660     for (i = 2; i > 0; i--) {
00661         outl(MDIO_ENB_IN, mdio_addr);
00662         mdio_delay();
00663         outl(MDIO_ENB_IN | MDIO_SHIFT_CLK, mdio_addr);
00664         mdio_delay();
00665     }
00666 }
00667 
00668 
00669 /*********************************************************************/
00670 /* EEPROM Reading Code                                               */
00671 /*********************************************************************/
00672 /* EEPROM routines adapted from the Linux Tulip Code */
00673 /* Reading a serial EEPROM is a "bit" grungy, but we work our way
00674    through:->.
00675 */
00676 static int read_eeprom(unsigned long ioaddr, int location, int addr_len)
00677 {
00678     int i;
00679     unsigned short retval = 0;
00680     long ee_addr = ioaddr + CSR9;
00681     int read_cmd = location | EE_READ_CMD;
00682 
00683     whereami("read_eeprom\n");
00684 
00685     outl(EE_ENB & ~EE_CS, ee_addr);
00686     outl(EE_ENB, ee_addr);
00687 
00688     /* Shift the read command bits out. */
00689     for (i = 4 + addr_len; i >= 0; i--) {
00690         short dataval = (read_cmd & (1 << i)) ? EE_DATA_WRITE : 0;
00691         outl(EE_ENB | dataval, ee_addr);
00692         eeprom_delay();
00693         outl(EE_ENB | dataval | EE_SHIFT_CLK, ee_addr);
00694         eeprom_delay();
00695     }
00696     outl(EE_ENB, ee_addr);
00697 
00698     for (i = 16; i > 0; i--) {
00699         outl(EE_ENB | EE_SHIFT_CLK, ee_addr);
00700         eeprom_delay();
00701         retval = (retval << 1) | ((inl(ee_addr) & EE_DATA_READ) ? 1 : 0);
00702         outl(EE_ENB, ee_addr);
00703         eeprom_delay();
00704     }
00705 
00706     /* Terminate the EEPROM access. */
00707     outl(EE_ENB & ~EE_CS, ee_addr);
00708     return retval;
00709 }
00710 
00711 
00712 /*********************************************************************/
00713 /* EEPROM Parsing Code                                               */
00714 /*********************************************************************/
00715 static void parse_eeprom(struct nic *nic)
00716 {
00717     unsigned char *p, *ee_data = tp->eeprom;
00718     int new_advertise = 0;
00719     int i;
00720 
00721     whereami("parse_eeprom\n");
00722 
00723     tp->mtable = NULL;
00724     /* Detect an old-style (SA only) EEPROM layout:
00725        memcmp(ee_data, ee_data+16, 8). */
00726     for (i = 0; i < 8; i ++)
00727         if (ee_data[i] != ee_data[16+i])
00728             break;
00729     if (i >= 8) {
00730         /* Do a fix-up based on the vendor half of the station address. */
00731         for (i = 0; eeprom_fixups[i].name; i++) {
00732             if (nic->node_addr[0] == eeprom_fixups[i].addr0
00733                 &&  nic->node_addr[1] == eeprom_fixups[i].addr1
00734                 &&  nic->node_addr[2] == eeprom_fixups[i].addr2) {
00735                 if (nic->node_addr[2] == 0xE8  &&  ee_data[0x1a] == 0x55)
00736                     i++;                /* An Accton EN1207, not an outlaw Maxtech. */
00737                 memcpy(ee_data + 26, eeprom_fixups[i].newtable,
00738                        sizeof(eeprom_fixups[i].newtable));
00739                 DBG("%s: Old format EEPROM on '%s' board.\n%s: Using substitute media control info.\n",
00740                        tp->nic_name, eeprom_fixups[i].name, tp->nic_name);
00741                 break;
00742             }
00743         }
00744         if (eeprom_fixups[i].name == NULL) { /* No fixup found. */
00745             DBG("%s: Old style EEPROM with no media selection information.\n",
00746                    tp->nic_name);
00747             return;
00748         }
00749     }
00750 
00751     if (ee_data[19] > 1) {
00752         DBG("%s:  Multiport cards (%d ports) may not work correctly.\n",
00753                tp->nic_name, ee_data[19]);
00754     }
00755 
00756     p = (void *)ee_data + ee_data[27];
00757 
00758     if (ee_data[27] == 0) {             /* No valid media table. */
00759             DBG2("%s:  No Valid Media Table. ee_data[27] = %hhX\n",
00760                  tp->nic_name, ee_data[27]);
00761     } else if (tp->chip_id == DC21041) {
00762         int media = get_u16(p);
00763         int count = p[2];
00764         p += 3;
00765 
00766         DBG("%s: 21041 Media table, default media %hX (%s).\n",
00767                tp->nic_name, media,
00768                media & 0x0800 ? "Autosense" : medianame[media & 15]);
00769         for (i = 0; i < count; i++) {
00770             unsigned char media_block = *p++;
00771             int media_code = media_block & MEDIA_MASK;
00772             if (media_block & 0x40)
00773                 p += 6;
00774             switch(media_code) {
00775             case 0: new_advertise |= 0x0020; break;
00776             case 4: new_advertise |= 0x0040; break;
00777             }
00778             DBG("%s:  21041 media #%d, %s.\n",
00779                    tp->nic_name, media_code, medianame[media_code]);
00780         }
00781     } else {
00782         unsigned char csr12dir = 0;
00783         int count;
00784         struct mediatable *mtable;
00785         u16 media = get_u16(p);
00786 
00787         p += 2;
00788         if (tp->flags & CSR12_IN_SROM)
00789             csr12dir = *p++;
00790         count = *p++;
00791 
00792         tp->mtable = mtable = (struct mediatable *)&tp->media_table_storage[0];
00793 
00794         mtable->defaultmedia = media;
00795         mtable->leafcount = count;
00796         mtable->csr12dir = csr12dir;
00797         mtable->has_nonmii = mtable->has_mii = mtable->has_reset = 0;
00798         mtable->csr15dir = mtable->csr15val = 0;
00799 
00800         DBG("%s:  EEPROM default media type %s.\n", tp->nic_name,
00801                media & 0x0800 ? "Autosense" : medianame[media & MEDIA_MASK]);
00802 
00803         for (i = 0; i < count; i++) {
00804             struct medialeaf *leaf = &mtable->mleaf[i];
00805 
00806             if ((p[0] & 0x80) == 0) { /* 21140 Compact block. */
00807                 leaf->type = 0;
00808                 leaf->media = p[0] & 0x3f;
00809                 leaf->leafdata = p;
00810                 if ((p[2] & 0x61) == 0x01)      /* Bogus, but Znyx boards do it. */
00811                     mtable->has_mii = 1;
00812                 p += 4;
00813             } else {
00814                 switch(leaf->type = p[1]) {
00815                 case 5:
00816                     mtable->has_reset = i;
00817                     leaf->media = p[2] & 0x0f;
00818                     break;
00819                 case 1: case 3:
00820                     mtable->has_mii = 1;
00821                     leaf->media = 11;
00822                     break;
00823                 case 2:
00824                     if ((p[2] & 0x3f) == 0) {
00825                         u32 base15 = (p[2] & 0x40) ? get_u16(p + 7) : 0x0008;
00826                         u16 *p1 = (u16 *)(p + (p[2] & 0x40 ? 9 : 3));
00827                         mtable->csr15dir = (get_unaligned(p1 + 0)<<16) + base15;
00828                         mtable->csr15val = (get_unaligned(p1 + 1)<<16) + base15;
00829                     }
00830                     /* Fall through. */
00831                 case 0: case 4:
00832                     mtable->has_nonmii = 1;
00833                     leaf->media = p[2] & MEDIA_MASK;
00834                     switch (leaf->media) {
00835                     case 0: new_advertise |= 0x0020; break;
00836                     case 4: new_advertise |= 0x0040; break;
00837                     case 3: new_advertise |= 0x0080; break;
00838                     case 5: new_advertise |= 0x0100; break;
00839                     case 6: new_advertise |= 0x0200; break;
00840                     }
00841                     break;
00842                 default:
00843                     leaf->media = 19;
00844                 }
00845                 leaf->leafdata = p + 2;
00846                 p += (p[0] & 0x3f) + 1;
00847             }
00848             if (leaf->media == 11) {
00849                 unsigned char *bp = leaf->leafdata;
00850                 DBG2("%s:  MII interface PHY %d, setup/reset sequences %d/%d long, capabilities %hhX %hhX.\n",
00851                      tp->nic_name, bp[0], bp[1], bp[2 + bp[1]*2],
00852                      bp[5 + bp[2 + bp[1]*2]*2], bp[4 + bp[2 + bp[1]*2]*2]);
00853             }
00854             DBG("%s:  Index #%d - Media %s (#%d) described "
00855                    "by a %s (%d) block.\n",
00856                    tp->nic_name, i, medianame[leaf->media], leaf->media,
00857                    leaf->type < 6 ? block_name[leaf->type] : "UNKNOWN",
00858                    leaf->type);
00859         }
00860         if (new_advertise)
00861             tp->sym_advertise = new_advertise;
00862     }
00863 }
00864 
00865 
00866 /*********************************************************************/
00867 /* tulip_init_ring - setup the tx and rx descriptors                */
00868 /*********************************************************************/
00869 static void tulip_init_ring(struct nic *nic __unused)
00870 {
00871     int i;
00872 
00873     whereami("tulip_init_ring\n");
00874 
00875     tp->cur_rx = 0;
00876 
00877     for (i = 0; i < RX_RING_SIZE; i++) {
00878         rx_ring[i].status  = cpu_to_le32(0x80000000);
00879         rx_ring[i].length  = cpu_to_le32(BUFLEN);
00880         rx_ring[i].buffer1 = virt_to_le32desc(&rxb[i * BUFLEN]);
00881         rx_ring[i].buffer2 = virt_to_le32desc(&rx_ring[i+1]);
00882     }
00883     /* Mark the last entry as wrapping the ring. */
00884     rx_ring[i-1].length    = cpu_to_le32(DESC_RING_WRAP | BUFLEN);
00885     rx_ring[i-1].buffer2   = virt_to_le32desc(&rx_ring[0]);
00886 
00887     /* We only use 1 transmit buffer, but we use 2 descriptors so
00888        transmit engines have somewhere to point to if they feel the need */
00889 
00890     tx_ring[0].status  = 0x00000000;
00891     tx_ring[0].buffer1 = virt_to_le32desc(&txb[0]);
00892     tx_ring[0].buffer2 = virt_to_le32desc(&tx_ring[1]);
00893 
00894     /* this descriptor should never get used, since it will never be owned
00895        by the machine (status will always == 0) */
00896     tx_ring[1].status  = 0x00000000;
00897     tx_ring[1].buffer1 = virt_to_le32desc(&txb[0]);
00898     tx_ring[1].buffer2 = virt_to_le32desc(&tx_ring[0]);
00899 
00900     /* Mark the last entry as wrapping the ring, though this should never happen */
00901     tx_ring[1].length  = cpu_to_le32(DESC_RING_WRAP | BUFLEN);
00902 }
00903 
00904 
00905 static void set_rx_mode(struct nic *nic __unused) {
00906         int csr6 = inl(ioaddr + CSR6) & ~0x00D5;
00907 
00908         tp->csr6 &= ~0x00D5;
00909  
00910         /* !IFF_PROMISC */
00911         tp->csr6 |= AcceptAllMulticast;
00912         csr6 |= AcceptAllMulticast;
00913 
00914         outl(csr6, ioaddr + CSR6);
00915 
00916         
00917         
00918 }
00919 
00920 /*********************************************************************/
00921 /* eth_reset - Reset adapter                                         */
00922 /*********************************************************************/
00923 static void tulip_reset(struct nic *nic)
00924 {
00925     int i;
00926     unsigned long to;
00927 
00928     whereami("tulip_reset\n");
00929 
00930     /* Stop Tx and RX */
00931     outl(inl(ioaddr + CSR6) & ~0x00002002, ioaddr + CSR6);
00932 
00933     /* On some chip revs we must set the MII/SYM port before the reset!? */
00934     if (tp->mii_cnt  ||  (tp->mtable  &&  tp->mtable->has_mii)) {
00935         outl(0x814C0000, ioaddr + CSR6);
00936     }
00937  
00938     /* Reset the chip, holding bit 0 set at least 50 PCI cycles. */
00939     outl(0x00000001, ioaddr + CSR0);
00940     tulip_wait(1);
00941 
00942     /* turn off reset and set cache align=16lword, burst=unlimit */
00943     outl(tp->csr0, ioaddr + CSR0);
00944 
00945     /*  Wait the specified 50 PCI cycles after a reset */
00946     tulip_wait(1);
00947 
00948     /* set up transmit and receive descriptors */
00949     tulip_init_ring(nic);
00950 
00951     if (tp->chip_id == PNIC2) {
00952         u32 addr_high = (nic->node_addr[1]<<8) + (nic->node_addr[0]<<0);
00953         /* This address setting does not appear to impact chip operation?? */
00954         outl((nic->node_addr[5]<<8) + nic->node_addr[4] +
00955              (nic->node_addr[3]<<24) + (nic->node_addr[2]<<16),
00956              ioaddr + 0xB0);
00957         outl(addr_high + (addr_high<<16), ioaddr + 0xB8);
00958     }
00959 
00960     /* MC_HASH_ONLY boards don't support setup packets */
00961     if (tp->flags & MC_HASH_ONLY) {
00962         u32 addr_low = cpu_to_le32(get_unaligned((u32 *)nic->node_addr));
00963         u32 addr_high = cpu_to_le32(get_unaligned((u16 *)(nic->node_addr+4)));
00964 
00965         /* clear multicast hash filters and setup MAC address filters */
00966         if (tp->flags & IS_ASIX) {
00967             outl(0, ioaddr + CSR13);
00968             outl(addr_low,  ioaddr + CSR14);
00969             outl(1, ioaddr + CSR13);
00970             outl(addr_high, ioaddr + CSR14);
00971             outl(2, ioaddr + CSR13);
00972             outl(0, ioaddr + CSR14);
00973             outl(3, ioaddr + CSR13);
00974             outl(0, ioaddr + CSR14);
00975         } else if (tp->chip_id == COMET) {
00976             outl(addr_low,  ioaddr + 0xA4);
00977             outl(addr_high, ioaddr + 0xA8);
00978             outl(0, ioaddr + 0xAC);
00979             outl(0, ioaddr + 0xB0);
00980         }
00981     } else {
00982         /* for other boards we send a setup packet to initialize
00983            the filters */
00984         u32 tx_flags = 0x08000000 | 192;
00985 
00986         /* construct perfect filter frame with mac address as first match
00987            and broadcast address for all others */
00988         for (i=0; i<192; i++) 
00989             txb[i] = 0xFF;
00990         txb[0] = nic->node_addr[0];
00991         txb[1] = nic->node_addr[1];
00992         txb[4] = nic->node_addr[2];
00993         txb[5] = nic->node_addr[3];
00994         txb[8] = nic->node_addr[4];
00995         txb[9] = nic->node_addr[5];
00996 
00997         tx_ring[0].length  = cpu_to_le32(tx_flags);
00998         tx_ring[0].buffer1 = virt_to_le32desc(&txb[0]);
00999         tx_ring[0].status  = cpu_to_le32(0x80000000);
01000     }
01001 
01002     /* Point to rx and tx descriptors */
01003     outl(virt_to_le32desc(&rx_ring[0]), ioaddr + CSR3);
01004     outl(virt_to_le32desc(&tx_ring[0]), ioaddr + CSR4);
01005 
01006     init_media(nic);
01007 
01008     /* set the chip's operating mode (but don't turn on xmit and recv yet) */
01009     outl((tp->csr6 & ~0x00002002), ioaddr + CSR6);
01010 
01011     /* send setup packet for cards that support it */
01012     if (!(tp->flags & MC_HASH_ONLY)) {
01013         /* enable transmit  wait for completion */
01014         outl(tp->csr6 | 0x00002000, ioaddr + CSR6);
01015         /* immediate transmit demand */
01016         outl(0, ioaddr + CSR1);
01017 
01018         to = currticks() + TX_TIME_OUT;
01019         while ((tx_ring[0].status & 0x80000000) && (currticks() < to))
01020             /* wait */ ;
01021 
01022         if (currticks() >= to) {
01023             DBG ("%s: TX Setup Timeout.\n", tp->nic_name);
01024         }
01025     }
01026 
01027     if (tp->chip_id == LC82C168)
01028         tulip_check_duplex(nic);
01029 
01030     set_rx_mode(nic);   
01031         
01032     /* enable transmit and receive */
01033     outl(tp->csr6 | 0x00002002, ioaddr + CSR6);
01034 }
01035 
01036 
01037 /*********************************************************************/
01038 /* eth_transmit - Transmit a frame                                   */
01039 /*********************************************************************/
01040 static void tulip_transmit(struct nic *nic, const char *d, unsigned int t,
01041                            unsigned int s, const char *p)
01042 {
01043     u16 nstype;
01044     u32 to;
01045     u32 csr6 = inl(ioaddr + CSR6);
01046 
01047     whereami("tulip_transmit\n");
01048 
01049     /* Disable Tx */
01050     outl(csr6 & ~0x00002000, ioaddr + CSR6);
01051 
01052     memcpy(txb, d, ETH_ALEN);
01053     memcpy(txb + ETH_ALEN, nic->node_addr, ETH_ALEN);
01054     nstype = htons((u16) t);
01055     memcpy(txb + 2 * ETH_ALEN, (u8 *)&nstype, 2);
01056     memcpy(txb + ETH_HLEN, p, s);
01057 
01058     s += ETH_HLEN;
01059     s &= 0x0FFF;
01060 
01061     /* pad to minimum packet size */
01062     while (s < ETH_ZLEN)  
01063         txb[s++] = '\0';
01064 
01065     DBG2("%s: sending %d bytes ethtype %hX\n", tp->nic_name, s, t);
01066         
01067     /* setup the transmit descriptor */
01068     /* 0x60000000 = no interrupt on completion */
01069     tx_ring[0].length = cpu_to_le32(0x60000000 | s);
01070     tx_ring[0].status = cpu_to_le32(0x80000000);
01071 
01072     /* Point to transmit descriptor */
01073     outl(virt_to_le32desc(&tx_ring[0]), ioaddr + CSR4);
01074 
01075     /* Enable Tx */
01076     outl(csr6 | 0x00002000, ioaddr + CSR6);
01077     /* immediate transmit demand */
01078     outl(0, ioaddr + CSR1);
01079 
01080     to = currticks() + TX_TIME_OUT;
01081     while ((tx_ring[0].status & 0x80000000) && (currticks() < to))
01082         /* wait */ ;
01083 
01084     if (currticks() >= to) {
01085         DBG ("TX Timeout!\n");
01086     }
01087 
01088     /* Disable Tx */
01089     outl(csr6 & ~0x00002000, ioaddr + CSR6);
01090 }
01091 
01092 /*********************************************************************/
01093 /* eth_poll - Wait for a frame                                       */
01094 /*********************************************************************/
01095 static int tulip_poll(struct nic *nic, int retrieve)
01096 {
01097 
01098     whereami("tulip_poll\n");
01099 
01100     /* no packet waiting. packet still owned by NIC */
01101     if (rx_ring[tp->cur_rx].status & 0x80000000)
01102         return 0;
01103 
01104     if ( ! retrieve ) return 1;
01105 
01106     whereami("tulip_poll got one\n");
01107 
01108     nic->packetlen = (rx_ring[tp->cur_rx].status & 0x3FFF0000) >> 16;
01109 
01110     /* if we get a corrupted packet. throw it away and move on */
01111     if (rx_ring[tp->cur_rx].status & 0x00008000) {
01112         /* return the descriptor and buffer to receive ring */
01113         rx_ring[tp->cur_rx].status = 0x80000000;
01114         tp->cur_rx = (tp->cur_rx + 1) % RX_RING_SIZE;
01115         return 0;
01116     }
01117 
01118     /* copy packet to working buffer */
01119     memcpy(nic->packet, rxb + tp->cur_rx * BUFLEN, nic->packetlen);
01120 
01121     /* return the descriptor and buffer to receive ring */
01122     rx_ring[tp->cur_rx].status = 0x80000000;
01123     tp->cur_rx = (tp->cur_rx + 1) % RX_RING_SIZE;
01124 
01125     return 1;
01126 }
01127 
01128 /*********************************************************************/
01129 /* eth_disable - Disable the interface                               */
01130 /*********************************************************************/
01131 static void tulip_disable ( struct nic *nic ) {
01132 
01133     whereami("tulip_disable\n");
01134 
01135     tulip_reset(nic);
01136 
01137     /* disable interrupts */
01138     outl(0x00000000, ioaddr + CSR7);
01139 
01140     /* Stop the chip's Tx and Rx processes. */
01141     outl(inl(ioaddr + CSR6) & ~0x00002002, ioaddr + CSR6);
01142 
01143     /* Clear the missed-packet counter. */
01144     inl(ioaddr + CSR8);
01145 }
01146 
01147 /*********************************************************************/
01148 /*IRQ - Enable, Disable, or Force interrupts                         */
01149 /*********************************************************************/
01150 static void tulip_irq(struct nic *nic __unused, irq_action_t action __unused)
01151 {
01152   switch ( action ) {
01153   case DISABLE :
01154     break;
01155   case ENABLE :
01156     break;
01157   case FORCE :
01158     break;
01159   }
01160 }
01161 
01162 static struct nic_operations tulip_operations = {
01163         .connect        = dummy_connect,
01164         .poll           = tulip_poll,
01165         .transmit       = tulip_transmit,
01166         .irq            = tulip_irq,
01167 
01168 };
01169 
01170 /*********************************************************************/
01171 /* eth_probe - Look for an adapter                                   */
01172 /*********************************************************************/
01173 static int tulip_probe ( struct nic *nic, struct pci_device *pci ) {
01174 
01175     u32 i;
01176     u8  chip_rev;
01177     u8 ee_data[EEPROM_SIZE];
01178     unsigned short sum;
01179     int chip_idx;
01180     static unsigned char last_phys_addr[ETH_ALEN] = {0x00, 'L', 'i', 'n', 'u', 'x'};
01181 
01182     if (pci->ioaddr == 0)
01183         return 0;
01184 
01185     ioaddr         = pci->ioaddr;
01186     nic->ioaddr    = pci->ioaddr & ~3;
01187     nic->irqno     = 0;
01188 
01189     /* point to private storage */
01190     tp = &tulip_bss.tpx;
01191 
01192     tp->vendor_id  = pci->vendor;
01193     tp->dev_id     = pci->device;
01194     tp->nic_name   = pci->id->name;
01195 
01196     tp->if_port = 0;
01197     tp->default_port = 0;
01198 
01199     adjust_pci_device(pci);
01200 
01201     /* disable interrupts */
01202     outl(0x00000000, ioaddr + CSR7);
01203 
01204     /* Stop the chip's Tx and Rx processes. */
01205     outl(inl(ioaddr + CSR6) & ~0x00002002, ioaddr + CSR6);
01206 
01207     /* Clear the missed-packet counter. */
01208     inl(ioaddr + CSR8);
01209 
01210     DBG("\n");                /* so we start on a fresh line */
01211     whereami("tulip_probe\n");
01212 
01213     DBG2 ("%s: Looking for Tulip Chip: Vendor=%hX  Device=%hX\n", tp->nic_name,
01214           tp->vendor_id, tp->dev_id);
01215 
01216     /* Figure out which chip we're dealing with */
01217     i = 0;
01218     chip_idx = -1;
01219   
01220     while (pci_id_tbl[i].name) {
01221         if ( (((u32) tp->dev_id << 16) | tp->vendor_id) == 
01222              (pci_id_tbl[i].id.pci & pci_id_tbl[i].id.pci_mask) ) {
01223             chip_idx = pci_id_tbl[i].drv_flags;
01224             break;
01225         }
01226         i++;
01227     }
01228 
01229     if (chip_idx == -1) {
01230         DBG ("%s: Unknown Tulip Chip: Vendor=%hX  Device=%hX\n", tp->nic_name,
01231                 tp->vendor_id, tp->dev_id);
01232         return 0;
01233     }
01234 
01235     tp->pci_id_idx = i;
01236     tp->flags = tulip_tbl[chip_idx].flags;
01237 
01238     DBG2 ("%s: tp->pci_id_idx == %d,  name == %s\n", tp->nic_name,
01239           tp->pci_id_idx, pci_id_tbl[tp->pci_id_idx].name);
01240     DBG2 ("%s: chip_idx == %d, name == %s\n", tp->nic_name, chip_idx,
01241           tulip_tbl[chip_idx].chip_name);
01242   
01243     /* Bring the 21041/21143 out of sleep mode.
01244        Caution: Snooze mode does not work with some boards! */
01245     if (tp->flags & HAS_PWRDWN)
01246         pci_write_config_dword(pci, 0x40, 0x00000000);
01247 
01248     if (inl(ioaddr + CSR5) == 0xFFFFFFFF) {
01249         DBG("%s: The Tulip chip at %X is not functioning.\n",
01250                tp->nic_name, (unsigned int) ioaddr);
01251         return 0;
01252     }
01253    
01254     pci_read_config_byte(pci, PCI_REVISION, &chip_rev);
01255 
01256     DBG("%s: [chip: %s] rev %d at %hX\n", tp->nic_name,
01257            tulip_tbl[chip_idx].chip_name, chip_rev, (unsigned int) ioaddr);
01258     DBG("%s: Vendor=%hX  Device=%hX", tp->nic_name, tp->vendor_id, tp->dev_id);
01259 
01260     if (chip_idx == DC21041  &&  inl(ioaddr + CSR9) & 0x8000) {
01261         DBG(" 21040 compatible mode.");
01262         chip_idx = DC21040;
01263     }
01264 
01265     DBG("\n");
01266 
01267     /* The SROM/EEPROM interface varies dramatically. */
01268     sum = 0;
01269     if (chip_idx == DC21040) {
01270         outl(0, ioaddr + CSR9);         /* Reset the pointer with a dummy write. */
01271         for (i = 0; i < ETH_ALEN; i++) {
01272             int value, boguscnt = 100000;
01273             do
01274                 value = inl(ioaddr + CSR9);
01275             while (value < 0  && --boguscnt > 0);
01276             nic->node_addr[i] = value;
01277             sum += value & 0xff;
01278         }
01279     } else if (chip_idx == LC82C168) {
01280         for (i = 0; i < 3; i++) {
01281             int value, boguscnt = 100000;
01282             outl(0x600 | i, ioaddr + 0x98);
01283             do
01284                 value = inl(ioaddr + CSR9);
01285             while (value < 0  && --boguscnt > 0);
01286             put_unaligned(le16_to_cpu(value), ((u16*)nic->node_addr) + i);
01287             sum += value & 0xffff;
01288         }
01289     } else if (chip_idx == COMET) {
01290         /* No need to read the EEPROM. */
01291         put_unaligned(inl(ioaddr + 0xA4), (u32 *)nic->node_addr);
01292         put_unaligned(inl(ioaddr + 0xA8), (u16 *)(nic->node_addr + 4));
01293         for (i = 0; i < ETH_ALEN; i ++)
01294             sum += nic->node_addr[i];
01295     } else {
01296         /* A serial EEPROM interface, we read now and sort it out later. */
01297         int sa_offset = 0;
01298         int ee_addr_size = read_eeprom(ioaddr, 0xff, 8) & 0x40000 ? 8 : 6;
01299 
01300         for (i = 0; i < sizeof(ee_data)/2; i++)
01301             ((u16 *)ee_data)[i] =
01302                 le16_to_cpu(read_eeprom(ioaddr, i, ee_addr_size));
01303 
01304         /* DEC now has a specification (see Notes) but early board makers
01305            just put the address in the first EEPROM locations. */
01306         /* This does  memcmp(eedata, eedata+16, 8) */
01307         for (i = 0; i < 8; i ++)
01308             if (ee_data[i] != ee_data[16+i])
01309                 sa_offset = 20;
01310         if (ee_data[0] == 0xff  &&  ee_data[1] == 0xff &&  ee_data[2] == 0) {
01311             sa_offset = 2;              /* Grrr, damn Matrox boards. */
01312         }
01313         for (i = 0; i < ETH_ALEN; i ++) {
01314             nic->node_addr[i] = ee_data[i + sa_offset];
01315             sum += ee_data[i + sa_offset];
01316         }
01317     }
01318     /* Lite-On boards have the address byte-swapped. */
01319     if ((nic->node_addr[0] == 0xA0  ||  nic->node_addr[0] == 0xC0)
01320         &&  nic->node_addr[1] == 0x00)
01321         for (i = 0; i < ETH_ALEN; i+=2) {
01322             char tmp = nic->node_addr[i];
01323             nic->node_addr[i] = nic->node_addr[i+1];
01324             nic->node_addr[i+1] = tmp;
01325         }
01326 
01327     if (sum == 0  || sum == ETH_ALEN*0xff) {
01328         DBG("%s: EEPROM not present!\n", tp->nic_name);
01329         for (i = 0; i < ETH_ALEN-1; i++)
01330             nic->node_addr[i] = last_phys_addr[i];
01331         nic->node_addr[i] = last_phys_addr[i] + 1;
01332     }
01333 
01334     for (i = 0; i < ETH_ALEN; i++)
01335         last_phys_addr[i] = nic->node_addr[i];
01336 
01337     DBG ( "%s: %s at ioaddr %hX\n", tp->nic_name, eth_ntoa ( nic->node_addr ), 
01338           (unsigned int) ioaddr );
01339 
01340     tp->chip_id = chip_idx;
01341     tp->revision = chip_rev;
01342     tp->csr0 = csr0;
01343 
01344     /* BugFixes: The 21143-TD hangs with PCI Write-and-Invalidate cycles.
01345        And the ASIX must have a burst limit or horrible things happen. */
01346     if (chip_idx == DC21143  &&  chip_rev == 65)
01347         tp->csr0 &= ~0x01000000;
01348     else if (tp->flags & IS_ASIX)
01349         tp->csr0 |= 0x2000;
01350 
01351     if (media_cap[tp->default_port] & MediaIsMII) {
01352         static const u16 media2advert[] = { 0x20, 0x40, 0x03e0, 0x60,
01353                                             0x80, 0x100, 0x200 };
01354         tp->mii_advertise = media2advert[tp->default_port - 9];
01355         tp->mii_advertise |= (tp->flags & HAS_8023X); /* Matching bits! */
01356     }
01357 
01358     /* This is logically part of the probe routine, but too complex
01359        to write inline. */
01360     if (tp->flags & HAS_MEDIA_TABLE) {
01361         memcpy(tp->eeprom, ee_data, sizeof(tp->eeprom));
01362         parse_eeprom(nic);
01363     }
01364 
01365     start_link(nic);
01366 
01367     /* reset the device and make ready for tx and rx of packets */
01368     tulip_reset(nic);
01369     nic->nic_op = &tulip_operations;
01370 
01371     /* give the board a chance to reset before returning */
01372     tulip_wait(4*TICKS_PER_SEC);
01373 
01374     return 1;
01375 }
01376 
01377 static void start_link(struct nic *nic)
01378 {
01379     int i;
01380 
01381     whereami("start_link\n");
01382 
01383     if ((tp->flags & ALWAYS_CHECK_MII) ||
01384         (tp->mtable  &&  tp->mtable->has_mii) ||
01385         ( ! tp->mtable  &&  (tp->flags & HAS_MII))) {
01386         unsigned int phy, phy_idx;
01387         if (tp->mtable  &&  tp->mtable->has_mii) {
01388             for (i = 0; i < tp->mtable->leafcount; i++)
01389                 if (tp->mtable->mleaf[i].media == 11) {
01390                     tp->cur_index = i;
01391                     tp->saved_if_port = tp->if_port;
01392                     select_media(nic, 2);
01393                     tp->if_port = tp->saved_if_port;
01394                     break;
01395                 }
01396         }
01397 
01398         /* Find the connected MII xcvrs. */
01399         for (phy = 0, phy_idx = 0; phy < 32 && phy_idx < sizeof(tp->phys);
01400              phy++) {
01401             int mii_status = mdio_read(nic, phy, 1);
01402             if ((mii_status & 0x8301) == 0x8001 ||
01403                 ((mii_status & 0x8000) == 0  && (mii_status & 0x7800) != 0)) {
01404                 int mii_reg0 = mdio_read(nic, phy, 0);
01405                 int mii_advert = mdio_read(nic, phy, 4);
01406                 int to_advert;
01407 
01408                 if (tp->mii_advertise)
01409                     to_advert = tp->mii_advertise;
01410                 else if (tp->advertising[phy_idx])
01411                     to_advert = tp->advertising[phy_idx];
01412                 else                    /* Leave unchanged. */
01413                     tp->mii_advertise = to_advert = mii_advert;
01414 
01415                 tp->phys[phy_idx++] = phy;
01416                 DBG("%s:  MII transceiver %d config %hX status %hX advertising %hX.\n",
01417                        tp->nic_name, phy, mii_reg0, mii_status, mii_advert);
01418                                 /* Fixup for DLink with miswired PHY. */
01419                 if (mii_advert != to_advert) {
01420                     DBG("%s:  Advertising %hX on PHY %d previously advertising %hX.\n",
01421                            tp->nic_name, to_advert, phy, mii_advert);
01422                     mdio_write(nic, phy, 4, to_advert);
01423                 }
01424                                 /* Enable autonegotiation: some boards default to off. */
01425                 mdio_write(nic, phy, 0, mii_reg0 |
01426                            (tp->full_duplex ? 0x1100 : 0x1000) |
01427                            (media_cap[tp->default_port]&MediaIs100 ? 0x2000:0));
01428             }
01429         }
01430         tp->mii_cnt = phy_idx;
01431         if (tp->mtable  &&  tp->mtable->has_mii  &&  phy_idx == 0) {
01432             DBG("%s: ***WARNING***: No MII transceiver found!\n",
01433                    tp->nic_name);
01434             tp->phys[0] = 1;
01435         }
01436     }
01437 
01438     /* Reset the xcvr interface and turn on heartbeat. */
01439     switch (tp->chip_id) {
01440     case DC21040:
01441         outl(0x00000000, ioaddr + CSR13);
01442         outl(0x00000004, ioaddr + CSR13);
01443         break;
01444     case DC21041:
01445         /* This is nway_start(). */
01446         if (tp->sym_advertise == 0)
01447             tp->sym_advertise = 0x0061;
01448         outl(0x00000000, ioaddr + CSR13);
01449         outl(0xFFFFFFFF, ioaddr + CSR14);
01450         outl(0x00000008, ioaddr + CSR15); /* Listen on AUI also. */
01451         outl(inl(ioaddr + CSR6) | 0x0200, ioaddr + CSR6);
01452         outl(0x0000EF01, ioaddr + CSR13);
01453         break;
01454     case DC21140: default:
01455         if (tp->mtable)
01456             outl(tp->mtable->csr12dir | 0x100, ioaddr + CSR12);
01457         break;
01458     case DC21142:
01459     case PNIC2:
01460         if (tp->mii_cnt  ||  media_cap[tp->if_port] & MediaIsMII) {
01461             outl(0x82020000, ioaddr + CSR6);
01462             outl(0x0000, ioaddr + CSR13);
01463             outl(0x0000, ioaddr + CSR14);
01464             outl(0x820E0000, ioaddr + CSR6);
01465         } else
01466             nway_start(nic);
01467         break;
01468     case LC82C168:
01469         if ( ! tp->mii_cnt) {
01470             tp->nway = 1;
01471             tp->nwayset = 0;
01472             outl(0x00420000, ioaddr + CSR6);
01473             outl(0x30, ioaddr + CSR12);
01474             outl(0x0001F078, ioaddr + 0xB8);
01475             outl(0x0201F078, ioaddr + 0xB8); /* Turn on autonegotiation. */
01476         }
01477         break;
01478     case MX98713: case COMPEX9881:
01479         outl(0x00000000, ioaddr + CSR6);
01480         outl(0x000711C0, ioaddr + CSR14); /* Turn on NWay. */
01481         outl(0x00000001, ioaddr + CSR13);
01482         break;
01483     case MX98715: case MX98725:
01484         outl(0x01a80000, ioaddr + CSR6);
01485         outl(0xFFFFFFFF, ioaddr + CSR14);
01486         outl(0x00001000, ioaddr + CSR12);
01487         break;
01488     case COMET:
01489         /* No initialization necessary. */
01490         break;
01491     }
01492 }
01493 
01494 static void nway_start(struct nic *nic __unused)
01495 {
01496     int csr14 = ((tp->sym_advertise & 0x0780) << 9)  |
01497         ((tp->sym_advertise&0x0020)<<1) | 0xffbf;
01498 
01499     whereami("nway_start\n");
01500 
01501     tp->if_port = 0;
01502     tp->nway = tp->mediasense = 1;
01503     tp->nwayset = tp->lpar = 0;
01504     if (tp->chip_id == PNIC2) {
01505         tp->csr6 = 0x01000000 | (tp->sym_advertise & 0x0040 ? 0x0200 : 0);
01506         return;
01507     }
01508     DBG2("%s: Restarting internal NWay autonegotiation, %X.\n",
01509          tp->nic_name, csr14);
01510     outl(0x0001, ioaddr + CSR13);
01511     outl(csr14, ioaddr + CSR14);
01512     tp->csr6 = 0x82420000 | (tp->sym_advertise & 0x0040 ? 0x0200 : 0);
01513     outl(tp->csr6, ioaddr + CSR6);
01514     if (tp->mtable  &&  tp->mtable->csr15dir) {
01515         outl(tp->mtable->csr15dir, ioaddr + CSR15);
01516         outl(tp->mtable->csr15val, ioaddr + CSR15);
01517     } else if (tp->chip_id != PNIC2)
01518         outw(0x0008, ioaddr + CSR15);
01519     if (tp->chip_id == DC21041)                 /* Trigger NWAY. */
01520         outl(0xEF01, ioaddr + CSR12);
01521     else
01522         outl(0x1301, ioaddr + CSR12);
01523 }
01524 
01525 static void init_media(struct nic *nic)
01526 {
01527     int i;
01528 
01529     whereami("init_media\n");
01530 
01531     tp->saved_if_port = tp->if_port;
01532     if (tp->if_port == 0)
01533         tp->if_port = tp->default_port;
01534 
01535     /* Allow selecting a default media. */
01536     i = 0;
01537     if (tp->mtable == NULL)
01538         goto media_picked;
01539     if (tp->if_port) {
01540         int looking_for = media_cap[tp->if_port] & MediaIsMII ? 11 :
01541             (tp->if_port == 12 ? 0 : tp->if_port);
01542         for (i = 0; i < tp->mtable->leafcount; i++)
01543             if (tp->mtable->mleaf[i].media == looking_for) {
01544                 DBG("%s: Using user-specified media %s.\n",
01545                        tp->nic_name, medianame[tp->if_port]);
01546                 goto media_picked;
01547             }
01548     }
01549     if ((tp->mtable->defaultmedia & 0x0800) == 0) {
01550         int looking_for = tp->mtable->defaultmedia & 15;
01551         for (i = 0; i < tp->mtable->leafcount; i++)
01552             if (tp->mtable->mleaf[i].media == looking_for) {
01553                 DBG("%s: Using EEPROM-set media %s.\n",
01554                        tp->nic_name, medianame[looking_for]);
01555                 goto media_picked;
01556             }
01557     }
01558     /* Start sensing first non-full-duplex media. */
01559     for (i = tp->mtable->leafcount - 1;
01560          (media_cap[tp->mtable->mleaf[i].media] & MediaAlwaysFD) && i > 0; i--)
01561         ;
01562  media_picked:
01563 
01564     tp->csr6 = 0;
01565     tp->cur_index = i;
01566     tp->nwayset = 0;
01567 
01568     if (tp->if_port) {
01569         if (tp->chip_id == DC21143  &&  media_cap[tp->if_port] & MediaIsMII) {
01570             /* We must reset the media CSRs when we force-select MII mode. */
01571             outl(0x0000, ioaddr + CSR13);
01572             outl(0x0000, ioaddr + CSR14);
01573             outl(0x0008, ioaddr + CSR15);
01574         }
01575         select_media(nic, 1);
01576         return;
01577     }
01578     switch(tp->chip_id) {
01579     case DC21041:
01580         /* tp->nway = 1;*/
01581         nway_start(nic);
01582         break;
01583     case DC21142:
01584         if (tp->mii_cnt) {
01585             select_media(nic, 1);
01586             DBG2("%s: Using MII transceiver %d, status %hX.\n",
01587                  tp->nic_name, tp->phys[0], mdio_read(nic, tp->phys[0], 1));
01588             outl(0x82020000, ioaddr + CSR6);
01589             tp->csr6 = 0x820E0000;
01590             tp->if_port = 11;
01591             outl(0x0000, ioaddr + CSR13);
01592             outl(0x0000, ioaddr + CSR14);
01593         } else
01594             nway_start(nic);
01595         break;
01596     case PNIC2:
01597         nway_start(nic);
01598         break;
01599     case LC82C168:
01600         if (tp->mii_cnt) {
01601             tp->if_port = 11;
01602             tp->csr6 = 0x814C0000 | (tp->full_duplex ? 0x0200 : 0);
01603             outl(0x0001, ioaddr + CSR15);
01604         } else if (inl(ioaddr + CSR5) & TPLnkPass)
01605             pnic_do_nway(nic);
01606         else {
01607             /* Start with 10mbps to do autonegotiation. */
01608             outl(0x32, ioaddr + CSR12);
01609             tp->csr6 = 0x00420000;
01610             outl(0x0001B078, ioaddr + 0xB8);
01611             outl(0x0201B078, ioaddr + 0xB8);
01612         }
01613         break;
01614     case MX98713: case COMPEX9881:
01615         tp->if_port = 0;
01616         tp->csr6 = 0x01880000 | (tp->full_duplex ? 0x0200 : 0);
01617         outl(0x0f370000 | inw(ioaddr + 0x80), ioaddr + 0x80);
01618         break;
01619     case MX98715: case MX98725:
01620         /* Provided by BOLO, Macronix - 12/10/1998. */
01621         tp->if_port = 0;
01622         tp->csr6 = 0x01a80200;
01623         outl(0x0f370000 | inw(ioaddr + 0x80), ioaddr + 0x80);
01624         outl(0x11000 | inw(ioaddr + 0xa0), ioaddr + 0xa0);
01625         break;
01626     case COMET:
01627         /* Enable automatic Tx underrun recovery */
01628         outl(inl(ioaddr + 0x88) | 1, ioaddr + 0x88);
01629         tp->if_port = 0;
01630         tp->csr6 = 0x00040000;
01631         break;
01632     case AX88140: case AX88141:
01633         tp->csr6 = tp->mii_cnt ? 0x00040100 : 0x00000100;
01634         break;
01635     default:
01636         select_media(nic, 1);
01637     }
01638 }
01639 
01640 static void pnic_do_nway(struct nic *nic __unused)
01641 {
01642     u32 phy_reg = inl(ioaddr + 0xB8);
01643     u32 new_csr6 = tp->csr6 & ~0x40C40200;
01644 
01645     whereami("pnic_do_nway\n");
01646 
01647     if (phy_reg & 0x78000000) { /* Ignore baseT4 */
01648         if (phy_reg & 0x20000000)               tp->if_port = 5;
01649         else if (phy_reg & 0x40000000)  tp->if_port = 3;
01650         else if (phy_reg & 0x10000000)  tp->if_port = 4;
01651         else if (phy_reg & 0x08000000)  tp->if_port = 0;
01652         tp->nwayset = 1;
01653         new_csr6 = (tp->if_port & 1) ? 0x01860000 : 0x00420000;
01654         outl(0x32 | (tp->if_port & 1), ioaddr + CSR12);
01655         if (tp->if_port & 1)
01656             outl(0x1F868, ioaddr + 0xB8);
01657         if (phy_reg & 0x30000000) {
01658             tp->full_duplex = 1;
01659             new_csr6 |= 0x00000200;
01660         }
01661         DBG2("%s: PNIC autonegotiated status %X, %s.\n",
01662              tp->nic_name, phy_reg, medianame[tp->if_port]);
01663         if (tp->csr6 != new_csr6) {
01664             tp->csr6 = new_csr6;
01665             outl(tp->csr6 | 0x0002, ioaddr + CSR6);     /* Restart Tx */
01666             outl(tp->csr6 | 0x2002, ioaddr + CSR6);
01667         }
01668     }
01669 }
01670 
01671 /* Set up the transceiver control registers for the selected media type. */
01672 static void select_media(struct nic *nic, int startup)
01673 {
01674     struct mediatable *mtable = tp->mtable;
01675     u32 new_csr6;
01676     int i;
01677 
01678     whereami("select_media\n");
01679 
01680     if (mtable) {
01681         struct medialeaf *mleaf = &mtable->mleaf[tp->cur_index];
01682         unsigned char *p = mleaf->leafdata;
01683         switch (mleaf->type) {
01684         case 0:                                 /* 21140 non-MII xcvr. */
01685             DBG2("%s: Using a 21140 non-MII transceiver"
01686                  " with control setting %hhX.\n",
01687                  tp->nic_name, p[1]);
01688             tp->if_port = p[0];
01689             if (startup)
01690                 outl(mtable->csr12dir | 0x100, ioaddr + CSR12);
01691             outl(p[1], ioaddr + CSR12);
01692             new_csr6 = 0x02000000 | ((p[2] & 0x71) << 18);
01693             break;
01694         case 2: case 4: {
01695             u16 setup[5];
01696             u32 csr13val, csr14val, csr15dir, csr15val;
01697             for (i = 0; i < 5; i++)
01698                 setup[i] = get_u16(&p[i*2 + 1]);
01699 
01700             tp->if_port = p[0] & 15;
01701             if (media_cap[tp->if_port] & MediaAlwaysFD)
01702                 tp->full_duplex = 1;
01703 
01704             if (startup && mtable->has_reset) {
01705                 struct medialeaf *rleaf = &mtable->mleaf[mtable->has_reset];
01706                 unsigned char *rst = rleaf->leafdata;
01707                 DBG2("%s: Resetting the transceiver.\n",
01708                      tp->nic_name);
01709                 for (i = 0; i < rst[0]; i++)
01710                     outl(get_u16(rst + 1 + (i<<1)) << 16, ioaddr + CSR15);
01711             }
01712             DBG2("%s: 21143 non-MII %s transceiver control %hX/%hX.\n",
01713                  tp->nic_name, medianame[tp->if_port], setup[0], setup[1]);
01714             if (p[0] & 0x40) {  /* SIA (CSR13-15) setup values are provided. */
01715                 csr13val = setup[0];
01716                 csr14val = setup[1];
01717                 csr15dir = (setup[3]<<16) | setup[2];
01718                 csr15val = (setup[4]<<16) | setup[2];
01719                 outl(0, ioaddr + CSR13);
01720                 outl(csr14val, ioaddr + CSR14);
01721                 outl(csr15dir, ioaddr + CSR15); /* Direction */
01722                 outl(csr15val, ioaddr + CSR15); /* Data */
01723                 outl(csr13val, ioaddr + CSR13);
01724             } else {
01725                 csr13val = 1;
01726                 csr14val = 0x0003FF7F;
01727                 csr15dir = (setup[0]<<16) | 0x0008;
01728                 csr15val = (setup[1]<<16) | 0x0008;
01729                 if (tp->if_port <= 4)
01730                     csr14val = t21142_csr14[tp->if_port];
01731                 if (startup) {
01732                     outl(0, ioaddr + CSR13);
01733                     outl(csr14val, ioaddr + CSR14);
01734                 }
01735                 outl(csr15dir, ioaddr + CSR15); /* Direction */
01736                 outl(csr15val, ioaddr + CSR15); /* Data */
01737                 if (startup) outl(csr13val, ioaddr + CSR13);
01738             }
01739             DBG2("%s:  Setting CSR15 to %X/%X.\n",
01740                  tp->nic_name, csr15dir, csr15val);
01741             if (mleaf->type == 4)
01742                 new_csr6 = 0x82020000 | ((setup[2] & 0x71) << 18);
01743             else
01744                 new_csr6 = 0x82420000;
01745             break;
01746         }
01747         case 1: case 3: {
01748             int phy_num = p[0];
01749             int init_length = p[1];
01750             u16 *misc_info;
01751 
01752             tp->if_port = 11;
01753             new_csr6 = 0x020E0000;
01754             if (mleaf->type == 3) {     /* 21142 */
01755                 u16 *init_sequence = (u16*)(p+2);
01756                 u16 *reset_sequence = &((u16*)(p+3))[init_length];
01757                 int reset_length = p[2 + init_length*2];
01758                 misc_info = reset_sequence + reset_length;
01759                 if (startup)
01760                     for (i = 0; i < reset_length; i++)
01761                         outl(get_u16(&reset_sequence[i]) << 16, ioaddr + CSR15);
01762                 for (i = 0; i < init_length; i++)
01763                     outl(get_u16(&init_sequence[i]) << 16, ioaddr + CSR15);
01764             } else {
01765                 u8 *init_sequence = p + 2;
01766                 u8 *reset_sequence = p + 3 + init_length;
01767                 int reset_length = p[2 + init_length];
01768                 misc_info = (u16*)(reset_sequence + reset_length);
01769                 if (startup) {
01770                     outl(mtable->csr12dir | 0x100, ioaddr + CSR12);
01771                     for (i = 0; i < reset_length; i++)
01772                         outl(reset_sequence[i], ioaddr + CSR12);
01773                 }
01774                 for (i = 0; i < init_length; i++)
01775                     outl(init_sequence[i], ioaddr + CSR12);
01776             }
01777             tp->advertising[phy_num] = get_u16(&misc_info[1]) | 1;
01778             if (startup < 2) {
01779                 if (tp->mii_advertise == 0)
01780                     tp->mii_advertise = tp->advertising[phy_num];
01781                 DBG2("%s:  Advertising %hX on MII %d.\n",
01782                      tp->nic_name, tp->mii_advertise, tp->phys[phy_num]);
01783                 mdio_write(nic, tp->phys[phy_num], 4, tp->mii_advertise);
01784             }
01785             break;
01786         }
01787         default:
01788             DBG("%s:  Invalid media table selection %d.\n",
01789                    tp->nic_name, mleaf->type);
01790             new_csr6 = 0x020E0000;
01791         }
01792         DBG2("%s: Using media type %s, CSR12 is %hhX.\n",
01793              tp->nic_name, medianame[tp->if_port],
01794              inl(ioaddr + CSR12) & 0xff);
01795     } else if (tp->chip_id == DC21041) {
01796         int port = tp->if_port <= 4 ? tp->if_port : 0;
01797         DBG2("%s: 21041 using media %s, CSR12 is %hX.\n",
01798              tp->nic_name, medianame[port == 3 ? 12: port],
01799              inl(ioaddr + CSR12));
01800         outl(0x00000000, ioaddr + CSR13); /* Reset the serial interface */
01801         outl(t21041_csr14[port], ioaddr + CSR14);
01802         outl(t21041_csr15[port], ioaddr + CSR15);
01803         outl(t21041_csr13[port], ioaddr + CSR13);
01804         new_csr6 = 0x80020000;
01805     } else if (tp->chip_id == LC82C168) {
01806         if (startup && ! tp->medialock)
01807             tp->if_port = tp->mii_cnt ? 11 : 0;
01808         DBG2("%s: PNIC PHY status is %hX, media %s.\n",
01809              tp->nic_name, inl(ioaddr + 0xB8), medianame[tp->if_port]);
01810         if (tp->mii_cnt) {
01811             new_csr6 = 0x810C0000;
01812             outl(0x0001, ioaddr + CSR15);
01813             outl(0x0201B07A, ioaddr + 0xB8);
01814         } else if (startup) {
01815             /* Start with 10mbps to do autonegotiation. */
01816             outl(0x32, ioaddr + CSR12);
01817             new_csr6 = 0x00420000;
01818             outl(0x0001B078, ioaddr + 0xB8);
01819             outl(0x0201B078, ioaddr + 0xB8);
01820         } else if (tp->if_port == 3  ||  tp->if_port == 5) {
01821             outl(0x33, ioaddr + CSR12);
01822             new_csr6 = 0x01860000;
01823             /* Trigger autonegotiation. */
01824             outl(startup ? 0x0201F868 : 0x0001F868, ioaddr + 0xB8);
01825         } else {
01826             outl(0x32, ioaddr + CSR12);
01827             new_csr6 = 0x00420000;
01828             outl(0x1F078, ioaddr + 0xB8);
01829         }
01830     } else if (tp->chip_id == DC21040) {                                        /* 21040 */
01831         /* Turn on the xcvr interface. */
01832         int csr12 = inl(ioaddr + CSR12);
01833         DBG2("%s: 21040 media type is %s, CSR12 is %hhX.\n",
01834              tp->nic_name, medianame[tp->if_port], csr12);
01835         if (media_cap[tp->if_port] & MediaAlwaysFD)
01836             tp->full_duplex = 1;
01837         new_csr6 = 0x20000;
01838         /* Set the full duplux match frame. */
01839         outl(FULL_DUPLEX_MAGIC, ioaddr + CSR11);
01840         outl(0x00000000, ioaddr + CSR13); /* Reset the serial interface */
01841         if (t21040_csr13[tp->if_port] & 8) {
01842             outl(0x0705, ioaddr + CSR14);
01843             outl(0x0006, ioaddr + CSR15);
01844         } else {
01845             outl(0xffff, ioaddr + CSR14);
01846             outl(0x0000, ioaddr + CSR15);
01847         }
01848         outl(0x8f01 | t21040_csr13[tp->if_port], ioaddr + CSR13);
01849     } else {                                    /* Unknown chip type with no media table. */
01850         if (tp->default_port == 0)
01851             tp->if_port = tp->mii_cnt ? 11 : 3;
01852         if (media_cap[tp->if_port] & MediaIsMII) {
01853             new_csr6 = 0x020E0000;
01854         } else if (media_cap[tp->if_port] & MediaIsFx) {
01855             new_csr6 = 0x028600000;
01856         } else
01857             new_csr6 = 0x038600000;
01858         DBG2("%s: No media description table, assuming "
01859              "%s transceiver, CSR12 %hhX.\n",
01860              tp->nic_name, medianame[tp->if_port],
01861              inl(ioaddr + CSR12));
01862     }
01863 
01864     tp->csr6 = new_csr6 | (tp->csr6 & 0xfdff) | (tp->full_duplex ? 0x0200 : 0);
01865     return;
01866 }
01867 
01868 /*
01869   Check the MII negotiated duplex and change the CSR6 setting if
01870   required.
01871   Return 0 if everything is OK.
01872   Return < 0 if the transceiver is missing or has no link beat.
01873 */
01874 static int tulip_check_duplex(struct nic *nic)
01875 {
01876         unsigned int bmsr, lpa, negotiated, new_csr6;
01877 
01878         bmsr = mdio_read(nic, tp->phys[0], 1);
01879         lpa = mdio_read(nic, tp->phys[0], 5);
01880 
01881         DBG2("%s: MII status %#x, Link partner report %#x.\n",
01882              tp->nic_name, bmsr, lpa);
01883 
01884         if (bmsr == 0xffff)
01885                 return -2;
01886         if ((bmsr & 4) == 0) { 
01887                 int new_bmsr = mdio_read(nic, tp->phys[0], 1); 
01888                 if ((new_bmsr & 4) == 0) { 
01889                         DBG2("%s: No link beat on the MII interface,"
01890                              " status %#x.\n", tp->nic_name,
01891                              new_bmsr);
01892                         return -1;
01893                 }
01894         }
01895         tp->full_duplex = lpa & 0x140;
01896 
01897         new_csr6 = tp->csr6;
01898         negotiated = lpa & tp->advertising[0];
01899 
01900         if(negotiated & 0x380) new_csr6 &= ~0x400000; 
01901         else                   new_csr6 |= 0x400000;
01902         if (tp->full_duplex)   new_csr6 |= 0x200; 
01903         else                   new_csr6 &= ~0x200;
01904 
01905         if (new_csr6 != tp->csr6) {
01906                 tp->csr6 = new_csr6;
01907 
01908                 DBG("%s: Setting %s-duplex based on MII"
01909                     "#%d link partner capability of %#x.\n",
01910                     tp->nic_name,
01911                     tp->full_duplex ? "full" : "half",
01912                     tp->phys[0], lpa);
01913                 return 1;
01914         }
01915 
01916         return 0;
01917 }
01918 
01919 static struct pci_device_id tulip_nics[] = {
01920 PCI_ROM(0x1011, 0x0002, "dc21040",     "Digital Tulip", 0),
01921 PCI_ROM(0x1011, 0x0009, "ds21140",     "Digital Tulip Fast", 0),
01922 PCI_ROM(0x1011, 0x0014, "dc21041",     "Digital Tulip+", 0),
01923 PCI_ROM(0x1011, 0x0019, "ds21142",     "Digital Tulip 21142", 0),
01924 PCI_ROM(0x10b7, 0x9300, "3csoho100b-tx","3ComSOHO100B-TX", 0),
01925 PCI_ROM(0x10b9, 0x5261, "ali1563",     "ALi 1563 integrated ethernet", 0),
01926 PCI_ROM(0x10d9, 0x0512, "mx98713",     "Macronix MX987x3", 0),
01927 PCI_ROM(0x10d9, 0x0531, "mx98715",     "Macronix MX987x5", 0),
01928 PCI_ROM(0x1113, 0x1217, "mxic-98715",  "Macronix MX987x5", 0),
01929 PCI_ROM(0x11ad, 0xc115, "lc82c115",    "LinkSys LNE100TX", 0),
01930 PCI_ROM(0x11ad, 0x0002, "82c168",      "Netgear FA310TX", 0),
01931 PCI_ROM(0x1282, 0x9100, "dm9100",      "Davicom 9100", 0),
01932 PCI_ROM(0x1282, 0x9102, "dm9102",      "Davicom 9102", 0),
01933 PCI_ROM(0x1282, 0x9009, "dm9009",      "Davicom 9009", 0),
01934 PCI_ROM(0x1282, 0x9132, "dm9132",      "Davicom 9132", 0),
01935 PCI_ROM(0x1317, 0x0985, "centaur-p",   "ADMtek Centaur-P", 0),
01936 PCI_ROM(0x1317, 0x0981, "an981",       "ADMtek AN981 Comet", 0),                /* ADMTek Centaur-P (stmicro) */
01937 PCI_ROM(0x1113, 0x1216, "an983",       "ADMTek AN983 Comet", 0),
01938 PCI_ROM(0x1317, 0x9511, "an983b",      "ADMTek Comet 983b", 0),
01939 PCI_ROM(0x1317, 0x1985, "centaur-c",   "ADMTek Centaur-C", 0),
01940 PCI_ROM(0x8086, 0x0039, "intel21145",  "Intel Tulip", 0),
01941 PCI_ROM(0x125b, 0x1400, "ax88140",     "ASIX AX88140", 0),
01942 PCI_ROM(0x11f6, 0x9881, "rl100tx",     "Compex RL100-TX", 0),
01943 PCI_ROM(0x115d, 0x0003, "xircomtulip", "Xircom Tulip", 0),
01944 PCI_ROM(0x104a, 0x0981, "tulip-0981",  "Tulip 0x104a 0x0981", 0),
01945 PCI_ROM(0x104a, 0x2774, "SGThomson-STE10100A", "Tulip 0x104a 0x2774", 0),       /*Modified by Ramesh Chander*/
01946 PCI_ROM(0x1113, 0x9511, "tulip-9511",  "Tulip 0x1113 0x9511", 0),
01947 PCI_ROM(0x1186, 0x1561, "tulip-1561",  "Tulip 0x1186 0x1561", 0),
01948 PCI_ROM(0x1259, 0xa120, "tulip-a120",  "Tulip 0x1259 0xa120", 0),
01949 PCI_ROM(0x13d1, 0xab02, "tulip-ab02",  "Tulip 0x13d1 0xab02", 0),
01950 PCI_ROM(0x13d1, 0xab03, "tulip-ab03",  "Tulip 0x13d1 0xab03", 0),
01951 PCI_ROM(0x13d1, 0xab08, "tulip-ab08",  "Tulip 0x13d1 0xab08", 0),
01952 PCI_ROM(0x14f1, 0x1803, "lanfinity",   "Conexant LANfinity", 0),
01953 PCI_ROM(0x1626, 0x8410, "tulip-8410",  "Tulip 0x1626 0x8410", 0),
01954 PCI_ROM(0x1737, 0xab08, "tulip-1737-ab08","Tulip 0x1737 0xab08", 0),
01955 PCI_ROM(0x1737, 0xab09, "tulip-ab09",  "Tulip 0x1737 0xab09", 0),
01956 };
01957 
01958 PCI_DRIVER ( tulip_driver, tulip_nics, PCI_NO_CLASS );
01959 
01960 DRIVER ( "Tulip", nic_driver, pci_driver, tulip_driver,
01961          tulip_probe, tulip_disable );
01962 
01963 /*
01964  * Local variables:
01965  *  c-basic-offset: 8
01966  *  c-indent-level: 8
01967  *  tab-width: 8
01968  * End:
01969  */