iPXE
Macros | Enumerations | Functions
amd8111e.h File Reference

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Macros

#define _AMD811E_H
#define ASF_STAT   0x00 /* ASF status register */
#define CHIPID   0x04 /* Chip ID regsiter */
#define MIB_DATA   0x10 /* MIB data register */
#define MIB_ADDR   0x14 /* MIB address register */
#define STAT0   0x30 /* Status0 register */
#define INT0   0x38 /* Interrupt0 register */
#define INTEN0   0x40 /* Interrupt0 enable register*/
#define CMD0   0x48 /* Command0 register */
#define CMD2   0x50 /* Command2 register */
#define CMD3   0x54 /* Command3 resiter */
#define CMD7   0x64 /* Command7 register */
#define CTRL1   0x6C /* Control1 register */
#define CTRL2   0x70 /* Control2 register */
#define XMT_RING_LIMIT   0x7C /* Transmit ring limit register */
#define AUTOPOLL0   0x88 /* Auto-poll0 register */
#define AUTOPOLL1   0x8A /* Auto-poll1 register */
#define AUTOPOLL2   0x8C /* Auto-poll2 register */
#define AUTOPOLL3   0x8E /* Auto-poll3 register */
#define AUTOPOLL4   0x90 /* Auto-poll4 register */
#define AUTOPOLL5   0x92 /* Auto-poll5 register */
#define AP_VALUE   0x98 /* Auto-poll value register */
#define DLY_INT_A   0xA8 /* Group A delayed interrupt register */
#define DLY_INT_B   0xAC /* Group B delayed interrupt register */
#define FLOW_CONTROL   0xC8 /* Flow control register */
#define PHY_ACCESS   0xD0 /* PHY access register */
#define STVAL   0xD8 /* Software timer value register */
#define XMT_RING_BASE_ADDR0   0x100 /* Transmit ring0 base addr register */
#define XMT_RING_BASE_ADDR1   0x108 /* Transmit ring1 base addr register */
#define XMT_RING_BASE_ADDR2   0x110 /* Transmit ring2 base addr register */
#define XMT_RING_BASE_ADDR3   0x118 /* Transmit ring2 base addr register */
#define RCV_RING_BASE_ADDR0   0x120 /* Transmit ring0 base addr register */
#define PMAT0   0x190 /* OnNow pattern register0 */
#define PMAT1   0x194 /* OnNow pattern register1 */
#define XMT_RING_LEN0   0x140 /* Transmit Ring0 length register */
#define XMT_RING_LEN1   0x144 /* Transmit Ring1 length register */
#define XMT_RING_LEN2   0x148 /* Transmit Ring2 length register */
#define XMT_RING_LEN3   0x14C /* Transmit Ring3 length register */
#define RCV_RING_LEN0   0x150 /* Receive Ring0 length register */
#define SRAM_SIZE   0x178 /* SRAM size register */
#define SRAM_BOUNDARY   0x17A /* SRAM boundary register */
#define PADR   0x160 /* Physical address register */
#define IFS1   0x18C /* Inter-frame spacing Part1 register */
#define IFS   0x18D /* Inter-frame spacing register */
#define IPG   0x18E /* Inter-frame gap register */
#define LADRF   0x168 /* Logical address filter register */
#define PHY_SPEED_10   0x2
#define PHY_SPEED_100   0x3
#define rcv_miss_pkts   0x00
#define rcv_octets   0x01
#define rcv_broadcast_pkts   0x02
#define rcv_multicast_pkts   0x03
#define rcv_undersize_pkts   0x04
#define rcv_oversize_pkts   0x05
#define rcv_fragments   0x06
#define rcv_jabbers   0x07
#define rcv_unicast_pkts   0x08
#define rcv_alignment_errors   0x09
#define rcv_fcs_errors   0x0A
#define rcv_good_octets   0x0B
#define rcv_mac_ctrl   0x0C
#define rcv_flow_ctrl   0x0D
#define rcv_pkts_64_octets   0x0E
#define rcv_pkts_65to127_octets   0x0F
#define rcv_pkts_128to255_octets   0x10
#define rcv_pkts_256to511_octets   0x11
#define rcv_pkts_512to1023_octets   0x12
#define rcv_pkts_1024to1518_octets   0x13
#define rcv_unsupported_opcode   0x14
#define rcv_symbol_errors   0x15
#define rcv_drop_pkts_ring1   0x16
#define rcv_drop_pkts_ring2   0x17
#define rcv_drop_pkts_ring3   0x18
#define rcv_drop_pkts_ring4   0x19
#define rcv_jumbo_pkts   0x1A
#define xmt_underrun_pkts   0x20
#define xmt_octets   0x21
#define xmt_packets   0x22
#define xmt_broadcast_pkts   0x23
#define xmt_multicast_pkts   0x24
#define xmt_collisions   0x25
#define xmt_unicast_pkts   0x26
#define xmt_one_collision   0x27
#define xmt_multiple_collision   0x28
#define xmt_deferred_transmit   0x29
#define xmt_late_collision   0x2A
#define xmt_excessive_defer   0x2B
#define xmt_loss_carrier   0x2C
#define xmt_excessive_collision   0x2D
#define xmt_back_pressure   0x2E
#define xmt_flow_ctrl   0x2F
#define xmt_pkts_64_octets   0x30
#define xmt_pkts_65to127_octets   0x31
#define xmt_pkts_128to255_octets   0x32
#define xmt_pkts_256to511_octets   0x33
#define xmt_pkts_512to1023_octets   0x34
#define xmt_pkts_1024to1518_octet   0x35
#define xmt_oversize_pkts   0x36
#define xmt_jumbo_pkts   0x37
#define DEFAULT_IPG   0x60
#define IFS1_DELTA   36
#define IPG_CONVERGE_JIFFIES   (HZ/2)
#define IPG_STABLE_TIME   5
#define MIN_IPG   96
#define MAX_IPG   255
#define IPG_STEP   16
#define CSTATE   1
#define SSTATE   2
#define RESET_RX_FLAGS   0x0000
#define TT_MASK   0x000c
#define TCC_MASK   0x0003
#define AMD8111E_REG_DUMP_LEN   13*sizeof(u32)
#define CRC32   0xedb88320
#define INITCRC   0xFFFFFFFF
#define amd8111e_writeq(_UlData, _memMap)

Enumerations

enum  STAT_ASF_BITS { ASF_INIT_DONE = (1 << 1) , ASF_INIT_PRESENT = (1 << 0) }
enum  MIB_ADDR_BITS { MIB_CMD_ACTIVE = (1 << 15 ) , MIB_RD_CMD = (1 << 13 ) , MIB_CLEAR = (1 << 12 ) , MIB_ADDRESS }
enum  STAT0_BITS {
  PMAT_DET = (1 << 12) , MP_DET = (1 << 11) , LC_DET = (1 << 10) , SPEED_MASK = (1 << 9)|(1 << 8)|(1 << 7) ,
  FULL_DPLX = (1 << 6) , LINK_STATS = (1 << 5) , AUTONEG_COMPLETE = (1 << 4) , MIIPD = (1 << 3) ,
  RX_SUSPENDED = (1 << 2) , TX_SUSPENDED = (1 << 1) , RUNNING = (1 << 0)
}
enum  INT0_BITS {
  INTR = (1 << 31) , PCSINT = (1 << 28) , LCINT = (1 << 27) , APINT5 = (1 << 26) ,
  APINT4 = (1 << 25) , APINT3 = (1 << 24) , TINT_SUM = (1 << 23) , APINT2 = (1 << 22) ,
  APINT1 = (1 << 21) , APINT0 = (1 << 20) , MIIPDTINT = (1 << 19) , MCCINT = (1 << 17) ,
  MREINT = (1 << 16) , RINT_SUM = (1 << 15) , SPNDINT = (1 << 14) , MPINT = (1 << 13) ,
  SINT = (1 << 12) , TINT3 = (1 << 11) , TINT2 = (1 << 10) , TINT1 = (1 << 9) ,
  TINT0 = (1 << 8) , UINT = (1 << 7) , STINT = (1 << 4) , RINT0 = (1 << 0)
}
enum  VAL_BITS { VAL3 = (1 << 31) , VAL2 = (1 << 23) , VAL1 = (1 << 15) , VAL0 = (1 << 7) }
enum  INTEN0_BITS {
  LCINTEN = (1 << 27) , APINT5EN = (1 << 26) , APINT4EN = (1 << 25) , APINT3EN = (1 << 24) ,
  APINT2EN = (1 << 22) , APINT1EN = (1 << 21) , APINT0EN = (1 << 20) , MIIPDTINTEN = (1 << 19) ,
  MCCIINTEN = (1 << 18) , MCCINTEN = (1 << 17) , MREINTEN = (1 << 16) , SPNDINTEN = (1 << 14) ,
  MPINTEN = (1 << 13) , TINTEN3 = (1 << 11) , SINTEN = (1 << 12) , TINTEN2 = (1 << 10) ,
  TINTEN1 = (1 << 9) , TINTEN0 = (1 << 8) , STINTEN = (1 << 4) , RINTEN0 = (1 << 0) ,
  INTEN0_CLEAR = 0x1F7F7F1F
}
enum  CMD0_BITS {
  RDMD0 = (1 << 16) , TDMD3 = (1 << 11) , TDMD2 = (1 << 10) , TDMD1 = (1 << 9) ,
  TDMD0 = (1 << 8) , UINTCMD = (1 << 6) , RX_FAST_SPND = (1 << 5) , TX_FAST_SPND = (1 << 4) ,
  RX_SPND = (1 << 3) , TX_SPND = (1 << 2) , INTREN = (1 << 1) , RUN = (1 << 0) ,
  CMD0_CLEAR = 0x000F0F7F
}
enum  CMD2_BITS {
  CONDUIT_MODE = (1 << 29) , RPA = (1 << 19) , DRCVPA = (1 << 18) , DRCVBC = (1 << 17) ,
  PROM = (1 << 16) , ASTRP_RCV = (1 << 13) , RCV_DROP0 = (1 << 12) , EMBA = (1 << 11) ,
  DXMT2PD = (1 << 10) , LTINTEN = (1 << 9) , DXMTFCS = (1 << 8) , APAD_XMT = (1 << 6) ,
  DRTY = (1 << 5) , INLOOP = (1 << 4) , EXLOOP = (1 << 3) , REX_RTRY = (1 << 2) ,
  REX_UFLO = (1 << 1) , REX_LCOL = (1 << 0) , CMD2_CLEAR = 0x3F7F3F7F
}
enum  CMD3_BITS {
  ASF_INIT_DONE_ALIAS = (1 << 29) , JUMBO = (1 << 21) , VSIZE = (1 << 20) , VLONLY = (1 << 19) ,
  VL_TAG_DEL = (1 << 18) , EN_PMGR = (1 << 14) , INTLEVEL = (1 << 13) , FORCE_FULL_DUPLEX = (1 << 12) ,
  FORCE_LINK_STATUS = (1 << 11) , APEP = (1 << 10) , MPPLBA = (1 << 9) , RESET_PHY_PULSE = (1 << 2) ,
  RESET_PHY = (1 << 1) , PHY_RST_POL = (1 << 0)
}
enum  CMD7_BITS {
  PMAT_SAVE_MATCH = (1 << 4) , PMAT_MODE = (1 << 3) , MPEN_SW = (1 << 1) , LCMODE_SW = (1 << 0) ,
  CMD7_CLEAR = 0x0000001B
}
enum  CTRL1_BITS {
  RESET_PHY_WIDTH = (0xF << 16) | (0xF<< 20) , XMTSP_MASK = (1 << 9) | (1 << 8) , XMTSP_128 = (1 << 9) , XMTSP_64 = (1 << 8) ,
  CACHE_ALIGN = (1 << 4) , BURST_LIMIT_MASK = (0xF << 0 ) , CTRL1_DEFAULT = 0x00010111
}
enum  CTRL2_BITS {
  FMDC_MASK = (1 << 9)|(1 << 8) , XPHYRST = (1 << 7) , XPHYANE = (1 << 6) , XPHYFD = (1 << 5) ,
  XPHYSP = (1 << 4) | (1 << 3) , APDW_MASK = (1 << 2) | (1 << 1) | (1 << 0)
}
enum  XMT_RING_LIMIT_BITS { XMT_RING2_LIMIT = (0xFF << 16) , XMT_RING1_LIMIT = (0xFF << 8) , XMT_RING0_LIMIT = (0xFF << 0) }
enum  AUTOPOLL0_BITS { AP_REG0_EN = (1 << 15) , AP_REG0_ADDR_MASK = (0xF << 8) |(1 << 12) , AP_PHY0_ADDR_MASK = (0xF << 0) |(1 << 4) }
enum  AUTOPOLL1_BITS {
  AP_REG1_EN = (1 << 15) , AP_REG1_ADDR_MASK = (0xF << 8) |(1 << 12) , AP_PRE_SUP1 = (1 << 6) , AP_PHY1_DFLT = (1 << 5) ,
  AP_PHY1_ADDR_MASK = (0xF << 0) |(1 << 4)
}
enum  AUTOPOLL2_BITS {
  AP_REG2_EN = (1 << 15) , AP_REG2_ADDR_MASK = (0xF << 8) |(1 << 12) , AP_PRE_SUP2 = (1 << 6) , AP_PHY2_DFLT = (1 << 5) ,
  AP_PHY2_ADDR_MASK = (0xF << 0) |(1 << 4)
}
enum  AUTOPOLL3_BITS {
  AP_REG3_EN = (1 << 15) , AP_REG3_ADDR_MASK = (0xF << 8) |(1 << 12) , AP_PRE_SUP3 = (1 << 6) , AP_PHY3_DFLT = (1 << 5) ,
  AP_PHY3_ADDR_MASK = (0xF << 0) |(1 << 4)
}
enum  AUTOPOLL4_BITS {
  AP_REG4_EN = (1 << 15) , AP_REG4_ADDR_MASK = (0xF << 8) |(1 << 12) , AP_PRE_SUP4 = (1 << 6) , AP_PHY4_DFLT = (1 << 5) ,
  AP_PHY4_ADDR_MASK = (0xF << 0) |(1 << 4)
}
enum  AUTOPOLL5_BITS {
  AP_REG5_EN = (1 << 15) , AP_REG5_ADDR_MASK = (0xF << 8) |(1 << 12) , AP_PRE_SUP5 = (1 << 6) , AP_PHY5_DFLT = (1 << 5) ,
  AP_PHY5_ADDR_MASK = (0xF << 0) |(1 << 4)
}
enum  AP_VALUE_BITS { AP_VAL_ACTIVE = (1 << 31) , AP_VAL_RD_CMD = ( 1 << 29) , AP_ADDR = (1 << 18)|(1 << 17)|(1 << 16) , AP_VAL }
enum  DLY_INT_A_BITS {
  DLY_INT_A_R3 = (1 << 31) , DLY_INT_A_R2 = (1 << 30) , DLY_INT_A_R1 = (1 << 29) , DLY_INT_A_R0 = (1 << 28) ,
  DLY_INT_A_T3 = (1 << 27) , DLY_INT_A_T2 = (1 << 26) , DLY_INT_A_T1 = (1 << 25) , DLY_INT_A_T0 = ( 1 << 24) ,
  EVENT_COUNT_A = (0xF << 16) | (0x1 << 20) , MAX_DELAY_TIME_A
}
enum  DLY_INT_B_BITS {
  DLY_INT_B_R3 = (1 << 31) , DLY_INT_B_R2 = (1 << 30) , DLY_INT_B_R1 = (1 << 29) , DLY_INT_B_R0 = (1 << 28) ,
  DLY_INT_B_T3 = (1 << 27) , DLY_INT_B_T2 = (1 << 26) , DLY_INT_B_T1 = (1 << 25) , DLY_INT_B_T0 = ( 1 << 24) ,
  EVENT_COUNT_B = (0xF << 16) | (0x1 << 20) , MAX_DELAY_TIME_B
}
enum  FLOW_CONTROL_BITS {
  PAUSE_LEN_CHG = (1 << 30) , FTPE = (1 << 22) , FRPE = (1 << 21) , NAPA = (1 << 20) ,
  NPA = (1 << 19) , FIXP = ( 1 << 18) , FCCMD = ( 1 << 16) , PAUSE_LEN = (0xF << 0) | (0xF << 4) |( 0xF << 8) | (0xF << 12)
}
enum  PHY_ACCESS_BITS {
  PHY_CMD_ACTIVE = (1 << 31) , PHY_WR_CMD = (1 << 30) , PHY_RD_CMD = (1 << 29) , PHY_RD_ERR = (1 << 28) ,
  PHY_PRE_SUP = (1 << 27) , PHY_ADDR , PHY_REG_ADDR = (1 << 16) | (1 << 17) | (1 << 18)| (1 << 19) | (1 << 20) , PHY_DATA
}
enum  PMAT0_BITS {
  PMR_ACTIVE = (1 << 31) , PMR_WR_CMD = (1 << 30) , PMR_RD_CMD = (1 << 29) , PMR_BANK = (1 <<28) ,
  PMR_ADDR , PMR_B4 = (0xF << 0) | (0xF << 4)
}
enum  PMAT1_BITS { PMR_B3 = (0xF << 24) | (0xF <<28) , PMR_B2 = (0xF << 16) |(0xF << 20) , PMR_B1 = (0xF << 8) | (0xF <<12) , PMR_B0 = (0xF << 0)|(0xF << 4) }
enum  TX_FLAG_BITS {
  OWN_BIT = (1 << 15) , ADD_FCS_BIT = (1 << 13) , LTINT_BIT = (1 << 12) , STP_BIT = (1 << 9) ,
  ENP_BIT = (1 << 8) , KILL_BIT = (1 << 6) , TCC_VLAN_INSERT = (1 << 1) , TCC_VLAN_REPLACE = (1 << 1) |( 1<< 0)
}
enum  RX_FLAG_BITS {
  ERR_BIT = (1 << 14) , FRAM_BIT = (1 << 13) , OFLO_BIT = (1 << 12) , CRC_BIT = (1 << 11) ,
  PAM_BIT = (1 << 6) , LAFM_BIT = (1 << 5) , BAM_BIT = (1 << 4) , TT_VLAN_TAGGED = (1 << 3) |(1 << 2) ,
  TT_PRTY_TAGGED = (1 << 3)
}
enum  EXT_PHY_OPTION {
  SPEED_AUTONEG , SPEED10_HALF , SPEED10_FULL , SPEED100_HALF ,
  SPEED100_FULL
}

Functions

 FILE_LICENCE (GPL2_OR_LATER_OR_UBDL)

Macro Definition Documentation

◆ _AMD811E_H

#define _AMD811E_H

Definition at line 46 of file amd8111e.h.

◆ ASF_STAT

#define ASF_STAT   0x00 /* ASF status register */

Definition at line 59 of file amd8111e.h.

◆ CHIPID

#define CHIPID   0x04 /* Chip ID regsiter */

Definition at line 60 of file amd8111e.h.

◆ MIB_DATA

#define MIB_DATA   0x10 /* MIB data register */

Definition at line 61 of file amd8111e.h.

◆ MIB_ADDR

#define MIB_ADDR   0x14 /* MIB address register */

Definition at line 62 of file amd8111e.h.

Referenced by amd8111e_init_hw_default().

◆ STAT0

#define STAT0   0x30 /* Status0 register */

Definition at line 63 of file amd8111e.h.

Referenced by amd8111e_poll_link(), and amd8111e_wait_link().

◆ INT0

#define INT0   0x38 /* Interrupt0 register */

Definition at line 64 of file amd8111e.h.

Referenced by amd8111e_disable_interrupt(), and amd8111e_init_hw_default().

◆ INTEN0

#define INTEN0   0x40 /* Interrupt0 enable register*/

Definition at line 65 of file amd8111e.h.

Referenced by amd8111e_disable_interrupt(), amd8111e_enable_interrupt(), and amd8111e_init_hw_default().

◆ CMD0

#define CMD0   0x48 /* Command0 register */

Definition at line 66 of file amd8111e.h.

Referenced by amd8111e_disable_interrupt(), amd8111e_enable_interrupt(), amd8111e_force_interrupt(), amd8111e_init_hw_default(), amd8111e_poll(), amd8111e_start(), and amd8111e_transmit().

◆ CMD2

#define CMD2   0x50 /* Command2 register */

Definition at line 67 of file amd8111e.h.

Referenced by amd8111e_init_hw_default(), and amd8111e_start().

◆ CMD3

#define CMD3   0x54 /* Command3 resiter */

Definition at line 68 of file amd8111e.h.

Referenced by amd8111e_start().

◆ CMD7

#define CMD7   0x64 /* Command7 register */

Definition at line 69 of file amd8111e.h.

Referenced by amd8111e_init_hw_default().

◆ CTRL1

#define CTRL1   0x6C /* Control1 register */

Definition at line 71 of file amd8111e.h.

Referenced by amd8111e_init_hw_default(), and amd8111e_start().

◆ CTRL2

#define CTRL2   0x70 /* Control2 register */

Definition at line 72 of file amd8111e.h.

Referenced by amd8111e_start().

◆ XMT_RING_LIMIT

#define XMT_RING_LIMIT   0x7C /* Transmit ring limit register */

Definition at line 74 of file amd8111e.h.

Referenced by amd8111e_init_hw_default().

◆ AUTOPOLL0

#define AUTOPOLL0   0x88 /* Auto-poll0 register */

Definition at line 76 of file amd8111e.h.

Referenced by amd8111e_start().

◆ AUTOPOLL1

#define AUTOPOLL1   0x8A /* Auto-poll1 register */

Definition at line 77 of file amd8111e.h.

◆ AUTOPOLL2

#define AUTOPOLL2   0x8C /* Auto-poll2 register */

Definition at line 78 of file amd8111e.h.

◆ AUTOPOLL3

#define AUTOPOLL3   0x8E /* Auto-poll3 register */

Definition at line 79 of file amd8111e.h.

◆ AUTOPOLL4

#define AUTOPOLL4   0x90 /* Auto-poll4 register */

Definition at line 80 of file amd8111e.h.

◆ AUTOPOLL5

#define AUTOPOLL5   0x92 /* Auto-poll5 register */

Definition at line 81 of file amd8111e.h.

◆ AP_VALUE

#define AP_VALUE   0x98 /* Auto-poll value register */

Definition at line 83 of file amd8111e.h.

◆ DLY_INT_A

#define DLY_INT_A   0xA8 /* Group A delayed interrupt register */

Definition at line 84 of file amd8111e.h.

Referenced by amd8111e_init_hw_default().

◆ DLY_INT_B

#define DLY_INT_B   0xAC /* Group B delayed interrupt register */

Definition at line 85 of file amd8111e.h.

Referenced by amd8111e_init_hw_default().

◆ FLOW_CONTROL

#define FLOW_CONTROL   0xC8 /* Flow control register */

Definition at line 87 of file amd8111e.h.

Referenced by amd8111e_init_hw_default().

◆ PHY_ACCESS

#define PHY_ACCESS   0xD0 /* PHY access register */

Definition at line 88 of file amd8111e.h.

Referenced by amd8111e_read_phy().

◆ STVAL

#define STVAL   0xD8 /* Software timer value register */

Definition at line 90 of file amd8111e.h.

Referenced by amd8111e_init_hw_default().

◆ XMT_RING_BASE_ADDR0

#define XMT_RING_BASE_ADDR0   0x100 /* Transmit ring0 base addr register */

Definition at line 92 of file amd8111e.h.

Referenced by amd8111e_init_hw_default(), and amd8111e_start().

◆ XMT_RING_BASE_ADDR1

#define XMT_RING_BASE_ADDR1   0x108 /* Transmit ring1 base addr register */

Definition at line 93 of file amd8111e.h.

Referenced by amd8111e_init_hw_default().

◆ XMT_RING_BASE_ADDR2

#define XMT_RING_BASE_ADDR2   0x110 /* Transmit ring2 base addr register */

Definition at line 94 of file amd8111e.h.

Referenced by amd8111e_init_hw_default().

◆ XMT_RING_BASE_ADDR3

#define XMT_RING_BASE_ADDR3   0x118 /* Transmit ring2 base addr register */

Definition at line 95 of file amd8111e.h.

Referenced by amd8111e_init_hw_default().

◆ RCV_RING_BASE_ADDR0

#define RCV_RING_BASE_ADDR0   0x120 /* Transmit ring0 base addr register */

Definition at line 97 of file amd8111e.h.

Referenced by amd8111e_init_hw_default(), and amd8111e_start().

◆ PMAT0

#define PMAT0   0x190 /* OnNow pattern register0 */

Definition at line 99 of file amd8111e.h.

◆ PMAT1

#define PMAT1   0x194 /* OnNow pattern register1 */

Definition at line 100 of file amd8111e.h.

◆ XMT_RING_LEN0

#define XMT_RING_LEN0   0x140 /* Transmit Ring0 length register */

Definition at line 104 of file amd8111e.h.

Referenced by amd8111e_init_hw_default(), and amd8111e_start().

◆ XMT_RING_LEN1

#define XMT_RING_LEN1   0x144 /* Transmit Ring1 length register */

Definition at line 105 of file amd8111e.h.

Referenced by amd8111e_init_hw_default().

◆ XMT_RING_LEN2

#define XMT_RING_LEN2   0x148 /* Transmit Ring2 length register */

Definition at line 106 of file amd8111e.h.

Referenced by amd8111e_init_hw_default().

◆ XMT_RING_LEN3

#define XMT_RING_LEN3   0x14C /* Transmit Ring3 length register */

Definition at line 107 of file amd8111e.h.

Referenced by amd8111e_init_hw_default().

◆ RCV_RING_LEN0

#define RCV_RING_LEN0   0x150 /* Receive Ring0 length register */

Definition at line 109 of file amd8111e.h.

Referenced by amd8111e_init_hw_default(), and amd8111e_start().

◆ SRAM_SIZE

#define SRAM_SIZE   0x178 /* SRAM size register */

Definition at line 111 of file amd8111e.h.

Referenced by amd8111e_init_hw_default().

◆ SRAM_BOUNDARY

#define SRAM_BOUNDARY   0x17A /* SRAM boundary register */

Definition at line 112 of file amd8111e.h.

◆ PADR

#define PADR   0x160 /* Physical address register */

Definition at line 116 of file amd8111e.h.

Referenced by amd8111e_get_mac_address(), and amd8111e_start().

◆ IFS1

#define IFS1   0x18C /* Inter-frame spacing Part1 register */

Definition at line 118 of file amd8111e.h.

Referenced by amd8111e_start().

◆ IFS

#define IFS   0x18D /* Inter-frame spacing register */

Definition at line 119 of file amd8111e.h.

◆ IPG

#define IPG   0x18E /* Inter-frame gap register */

Definition at line 120 of file amd8111e.h.

Referenced by amd8111e_start().

◆ LADRF

#define LADRF   0x168 /* Logical address filter register */

Definition at line 123 of file amd8111e.h.

Referenced by amd8111e_init_hw_default().

◆ PHY_SPEED_10

#define PHY_SPEED_10   0x2

Definition at line 160 of file amd8111e.h.

◆ PHY_SPEED_100

#define PHY_SPEED_100   0x3

Definition at line 161 of file amd8111e.h.

Referenced by amd8111e_poll_link().

◆ rcv_miss_pkts

#define rcv_miss_pkts   0x00

Definition at line 517 of file amd8111e.h.

◆ rcv_octets

#define rcv_octets   0x01

Definition at line 518 of file amd8111e.h.

◆ rcv_broadcast_pkts

#define rcv_broadcast_pkts   0x02

Definition at line 519 of file amd8111e.h.

◆ rcv_multicast_pkts

#define rcv_multicast_pkts   0x03

Definition at line 520 of file amd8111e.h.

◆ rcv_undersize_pkts

#define rcv_undersize_pkts   0x04

Definition at line 521 of file amd8111e.h.

◆ rcv_oversize_pkts

#define rcv_oversize_pkts   0x05

Definition at line 522 of file amd8111e.h.

◆ rcv_fragments

#define rcv_fragments   0x06

Definition at line 523 of file amd8111e.h.

◆ rcv_jabbers

#define rcv_jabbers   0x07

Definition at line 524 of file amd8111e.h.

◆ rcv_unicast_pkts

#define rcv_unicast_pkts   0x08

Definition at line 525 of file amd8111e.h.

◆ rcv_alignment_errors

#define rcv_alignment_errors   0x09

Definition at line 526 of file amd8111e.h.

◆ rcv_fcs_errors

#define rcv_fcs_errors   0x0A

Definition at line 527 of file amd8111e.h.

◆ rcv_good_octets

#define rcv_good_octets   0x0B

Definition at line 528 of file amd8111e.h.

◆ rcv_mac_ctrl

#define rcv_mac_ctrl   0x0C

Definition at line 529 of file amd8111e.h.

◆ rcv_flow_ctrl

#define rcv_flow_ctrl   0x0D

Definition at line 530 of file amd8111e.h.

◆ rcv_pkts_64_octets

#define rcv_pkts_64_octets   0x0E

Definition at line 531 of file amd8111e.h.

◆ rcv_pkts_65to127_octets

#define rcv_pkts_65to127_octets   0x0F

Definition at line 532 of file amd8111e.h.

◆ rcv_pkts_128to255_octets

#define rcv_pkts_128to255_octets   0x10

Definition at line 533 of file amd8111e.h.

◆ rcv_pkts_256to511_octets

#define rcv_pkts_256to511_octets   0x11

Definition at line 534 of file amd8111e.h.

◆ rcv_pkts_512to1023_octets

#define rcv_pkts_512to1023_octets   0x12

Definition at line 535 of file amd8111e.h.

◆ rcv_pkts_1024to1518_octets

#define rcv_pkts_1024to1518_octets   0x13

Definition at line 536 of file amd8111e.h.

◆ rcv_unsupported_opcode

#define rcv_unsupported_opcode   0x14

Definition at line 537 of file amd8111e.h.

◆ rcv_symbol_errors

#define rcv_symbol_errors   0x15

Definition at line 538 of file amd8111e.h.

◆ rcv_drop_pkts_ring1

#define rcv_drop_pkts_ring1   0x16

Definition at line 539 of file amd8111e.h.

◆ rcv_drop_pkts_ring2

#define rcv_drop_pkts_ring2   0x17

Definition at line 540 of file amd8111e.h.

◆ rcv_drop_pkts_ring3

#define rcv_drop_pkts_ring3   0x18

Definition at line 541 of file amd8111e.h.

◆ rcv_drop_pkts_ring4

#define rcv_drop_pkts_ring4   0x19

Definition at line 542 of file amd8111e.h.

◆ rcv_jumbo_pkts

#define rcv_jumbo_pkts   0x1A

Definition at line 543 of file amd8111e.h.

◆ xmt_underrun_pkts

#define xmt_underrun_pkts   0x20

Definition at line 545 of file amd8111e.h.

◆ xmt_octets

#define xmt_octets   0x21

Definition at line 546 of file amd8111e.h.

◆ xmt_packets

#define xmt_packets   0x22

Definition at line 547 of file amd8111e.h.

◆ xmt_broadcast_pkts

#define xmt_broadcast_pkts   0x23

Definition at line 548 of file amd8111e.h.

◆ xmt_multicast_pkts

#define xmt_multicast_pkts   0x24

Definition at line 549 of file amd8111e.h.

◆ xmt_collisions

#define xmt_collisions   0x25

Definition at line 550 of file amd8111e.h.

◆ xmt_unicast_pkts

#define xmt_unicast_pkts   0x26

Definition at line 551 of file amd8111e.h.

◆ xmt_one_collision

#define xmt_one_collision   0x27

Definition at line 552 of file amd8111e.h.

◆ xmt_multiple_collision

#define xmt_multiple_collision   0x28

Definition at line 553 of file amd8111e.h.

◆ xmt_deferred_transmit

#define xmt_deferred_transmit   0x29

Definition at line 554 of file amd8111e.h.

◆ xmt_late_collision

#define xmt_late_collision   0x2A

Definition at line 555 of file amd8111e.h.

◆ xmt_excessive_defer

#define xmt_excessive_defer   0x2B

Definition at line 556 of file amd8111e.h.

◆ xmt_loss_carrier

#define xmt_loss_carrier   0x2C

Definition at line 557 of file amd8111e.h.

◆ xmt_excessive_collision

#define xmt_excessive_collision   0x2D

Definition at line 558 of file amd8111e.h.

◆ xmt_back_pressure

#define xmt_back_pressure   0x2E

Definition at line 559 of file amd8111e.h.

◆ xmt_flow_ctrl

#define xmt_flow_ctrl   0x2F

Definition at line 560 of file amd8111e.h.

◆ xmt_pkts_64_octets

#define xmt_pkts_64_octets   0x30

Definition at line 561 of file amd8111e.h.

◆ xmt_pkts_65to127_octets

#define xmt_pkts_65to127_octets   0x31

Definition at line 562 of file amd8111e.h.

◆ xmt_pkts_128to255_octets

#define xmt_pkts_128to255_octets   0x32

Definition at line 563 of file amd8111e.h.

◆ xmt_pkts_256to511_octets

#define xmt_pkts_256to511_octets   0x33

Definition at line 564 of file amd8111e.h.

◆ xmt_pkts_512to1023_octets

#define xmt_pkts_512to1023_octets   0x34

Definition at line 565 of file amd8111e.h.

◆ xmt_pkts_1024to1518_octet

#define xmt_pkts_1024to1518_octet   0x35

Definition at line 566 of file amd8111e.h.

◆ xmt_oversize_pkts

#define xmt_oversize_pkts   0x36

Definition at line 567 of file amd8111e.h.

◆ xmt_jumbo_pkts

#define xmt_jumbo_pkts   0x37

Definition at line 568 of file amd8111e.h.

◆ DEFAULT_IPG

#define DEFAULT_IPG   0x60

Definition at line 571 of file amd8111e.h.

Referenced by amd8111e_start().

◆ IFS1_DELTA

#define IFS1_DELTA   36

Definition at line 572 of file amd8111e.h.

Referenced by amd8111e_start().

◆ IPG_CONVERGE_JIFFIES

#define IPG_CONVERGE_JIFFIES   (HZ/2)

Definition at line 573 of file amd8111e.h.

◆ IPG_STABLE_TIME

#define IPG_STABLE_TIME   5

Definition at line 574 of file amd8111e.h.

◆ MIN_IPG

#define MIN_IPG   96

Definition at line 575 of file amd8111e.h.

◆ MAX_IPG

#define MAX_IPG   255

Definition at line 576 of file amd8111e.h.

◆ IPG_STEP

#define IPG_STEP   16

Definition at line 577 of file amd8111e.h.

◆ CSTATE

#define CSTATE   1

Definition at line 578 of file amd8111e.h.

◆ SSTATE

#define SSTATE   2

Definition at line 579 of file amd8111e.h.

◆ RESET_RX_FLAGS

#define RESET_RX_FLAGS   0x0000

Definition at line 608 of file amd8111e.h.

◆ TT_MASK

#define TT_MASK   0x000c

Definition at line 609 of file amd8111e.h.

◆ TCC_MASK

#define TCC_MASK   0x0003

Definition at line 610 of file amd8111e.h.

◆ AMD8111E_REG_DUMP_LEN

#define AMD8111E_REG_DUMP_LEN   13*sizeof(u32)

Definition at line 613 of file amd8111e.h.

◆ CRC32

#define CRC32   0xedb88320

Definition at line 616 of file amd8111e.h.

◆ INITCRC

#define INITCRC   0xFFFFFFFF

Definition at line 617 of file amd8111e.h.

◆ amd8111e_writeq

#define amd8111e_writeq ( _UlData,
_memMap )
Value:
writel(*(u32*)(&_UlData), _memMap); \
writel(*(u32*)((u8*)(&_UlData)+4), _memMap+4)
u8
#define u8
Definition igbvf_osdep.h:40
u32
#define u32
Definition vga.h:21
writel
#define writel
Definition w89c840.c:160

Definition at line 621 of file amd8111e.h.

621#define amd8111e_writeq(_UlData,_memMap) \
622 writel(*(u32*)(&_UlData), _memMap); \
623 writel(*(u32*)((u8*)(&_UlData)+4), _memMap+4)

Enumeration Type Documentation

◆ STAT_ASF_BITS

enum STAT_ASF_BITS
Enumerator
ASF_INIT_DONE 
ASF_INIT_PRESENT 

Definition at line 127 of file amd8111e.h.

127 {
128
129 ASF_INIT_DONE = (1 << 1),
130 ASF_INIT_PRESENT = (1 << 0),
131
132}STAT_ASF_BITS;
STAT_ASF_BITS
STAT_ASF_BITS
Definition amd8111e.h:127
ASF_INIT_PRESENT
@ ASF_INIT_PRESENT
Definition amd8111e.h:130
ASF_INIT_DONE
@ ASF_INIT_DONE
Definition amd8111e.h:129

◆ MIB_ADDR_BITS

enum MIB_ADDR_BITS
Enumerator
MIB_CMD_ACTIVE 
MIB_RD_CMD 
MIB_CLEAR 
MIB_ADDRESS 

Definition at line 134 of file amd8111e.h.

134 {
135
136 MIB_CMD_ACTIVE = (1 << 15 ),
137 MIB_RD_CMD = (1 << 13 ),
138 MIB_CLEAR = (1 << 12 ),
139 MIB_ADDRESS = (1 << 0) | (1 << 1) | (1 << 2) | (1 << 3)|
140 (1 << 4) | (1 << 5),
141}MIB_ADDR_BITS;
MIB_ADDR_BITS
MIB_ADDR_BITS
Definition amd8111e.h:134
MIB_RD_CMD
@ MIB_RD_CMD
Definition amd8111e.h:137
MIB_CLEAR
@ MIB_CLEAR
Definition amd8111e.h:138
MIB_CMD_ACTIVE
@ MIB_CMD_ACTIVE
Definition amd8111e.h:136
MIB_ADDRESS
@ MIB_ADDRESS
Definition amd8111e.h:139

◆ STAT0_BITS

enum STAT0_BITS
Enumerator
PMAT_DET 
MP_DET 
LC_DET 
SPEED_MASK 
FULL_DPLX 
LINK_STATS 
AUTONEG_COMPLETE 
MIIPD 
RX_SUSPENDED 
TX_SUSPENDED 
RUNNING 

Definition at line 144 of file amd8111e.h.

144 {
145
146 PMAT_DET = (1 << 12),
147 MP_DET = (1 << 11),
148 LC_DET = (1 << 10),
149 SPEED_MASK = (1 << 9)|(1 << 8)|(1 << 7),
150 FULL_DPLX = (1 << 6),
151 LINK_STATS = (1 << 5),
152 AUTONEG_COMPLETE = (1 << 4),
153 MIIPD = (1 << 3),
154 RX_SUSPENDED = (1 << 2),
155 TX_SUSPENDED = (1 << 1),
156 RUNNING = (1 << 0),
157
158}STAT0_BITS;
STAT0_BITS
STAT0_BITS
Definition amd8111e.h:144
RX_SUSPENDED
@ RX_SUSPENDED
Definition amd8111e.h:154
RUNNING
@ RUNNING
Definition amd8111e.h:156
FULL_DPLX
@ FULL_DPLX
Definition amd8111e.h:150
MIIPD
@ MIIPD
Definition amd8111e.h:153
LINK_STATS
@ LINK_STATS
Definition amd8111e.h:151
SPEED_MASK
@ SPEED_MASK
Definition amd8111e.h:149
MP_DET
@ MP_DET
Definition amd8111e.h:147
AUTONEG_COMPLETE
@ AUTONEG_COMPLETE
Definition amd8111e.h:152
TX_SUSPENDED
@ TX_SUSPENDED
Definition amd8111e.h:155
PMAT_DET
@ PMAT_DET
Definition amd8111e.h:146
LC_DET
@ LC_DET
Definition amd8111e.h:148

◆ INT0_BITS

enum INT0_BITS
Enumerator
INTR 
PCSINT 
LCINT 
APINT5 
APINT4 
APINT3 
TINT_SUM 
APINT2 
APINT1 
APINT0 
MIIPDTINT 
MCCINT 
MREINT 
RINT_SUM 
SPNDINT 
MPINT 
SINT 
TINT3 
TINT2 
TINT1 
TINT0 
UINT 
STINT 
RINT0 

Definition at line 164 of file amd8111e.h.

164 {
165
166 INTR = (1 << 31),
167 PCSINT = (1 << 28),
168 LCINT = (1 << 27),
169 APINT5 = (1 << 26),
170 APINT4 = (1 << 25),
171 APINT3 = (1 << 24),
172 TINT_SUM = (1 << 23),
173 APINT2 = (1 << 22),
174 APINT1 = (1 << 21),
175 APINT0 = (1 << 20),
176 MIIPDTINT = (1 << 19),
177 MCCINT = (1 << 17),
178 MREINT = (1 << 16),
179 RINT_SUM = (1 << 15),
180 SPNDINT = (1 << 14),
181 MPINT = (1 << 13),
182 SINT = (1 << 12),
183 TINT3 = (1 << 11),
184 TINT2 = (1 << 10),
185 TINT1 = (1 << 9),
186 TINT0 = (1 << 8),
187 UINT = (1 << 7),
188 STINT = (1 << 4),
189 RINT0 = (1 << 0),
190
191}INT0_BITS;
INT0_BITS
INT0_BITS
Definition amd8111e.h:164
RINT_SUM
@ RINT_SUM
Definition amd8111e.h:179
MREINT
@ MREINT
Definition amd8111e.h:178
INTR
@ INTR
Definition amd8111e.h:166
PCSINT
@ PCSINT
Definition amd8111e.h:167
TINT1
@ TINT1
Definition amd8111e.h:185
MIIPDTINT
@ MIIPDTINT
Definition amd8111e.h:176
APINT5
@ APINT5
Definition amd8111e.h:169
APINT0
@ APINT0
Definition amd8111e.h:175
APINT3
@ APINT3
Definition amd8111e.h:171
APINT2
@ APINT2
Definition amd8111e.h:173
STINT
@ STINT
Definition amd8111e.h:188
UINT
@ UINT
Definition amd8111e.h:187
RINT0
@ RINT0
Definition amd8111e.h:189
TINT0
@ TINT0
Definition amd8111e.h:186
TINT2
@ TINT2
Definition amd8111e.h:184
MPINT
@ MPINT
Definition amd8111e.h:181
TINT3
@ TINT3
Definition amd8111e.h:183
APINT4
@ APINT4
Definition amd8111e.h:170
MCCINT
@ MCCINT
Definition amd8111e.h:177
LCINT
@ LCINT
Definition amd8111e.h:168
SINT
@ SINT
Definition amd8111e.h:182
SPNDINT
@ SPNDINT
Definition amd8111e.h:180
TINT_SUM
@ TINT_SUM
Definition amd8111e.h:172
APINT1
@ APINT1
Definition amd8111e.h:174

◆ VAL_BITS

enum VAL_BITS
Enumerator
VAL3 
VAL2 
VAL1 
VAL0 

Definition at line 193 of file amd8111e.h.

193 {
194
195 VAL3 = (1 << 31), /* VAL bit for byte 3 */
196 VAL2 = (1 << 23), /* VAL bit for byte 2 */
197 VAL1 = (1 << 15), /* VAL bit for byte 1 */
198 VAL0 = (1 << 7), /* VAL bit for byte 0 */
199
200}VAL_BITS;
VAL_BITS
VAL_BITS
Definition amd8111e.h:193
VAL2
@ VAL2
Definition amd8111e.h:196
VAL3
@ VAL3
Definition amd8111e.h:195
VAL1
@ VAL1
Definition amd8111e.h:197
VAL0
@ VAL0
Definition amd8111e.h:198

◆ INTEN0_BITS

enum INTEN0_BITS
Enumerator
LCINTEN 
APINT5EN 
APINT4EN 
APINT3EN 
APINT2EN 
APINT1EN 
APINT0EN 
MIIPDTINTEN 
MCCIINTEN 
MCCINTEN 
MREINTEN 
SPNDINTEN 
MPINTEN 
TINTEN3 
SINTEN 
TINTEN2 
TINTEN1 
TINTEN0 
STINTEN 
RINTEN0 
INTEN0_CLEAR 

Definition at line 202 of file amd8111e.h.

202 {
203
204 /* VAL3 */
205 LCINTEN = (1 << 27),
206 APINT5EN = (1 << 26),
207 APINT4EN = (1 << 25),
208 APINT3EN = (1 << 24),
209 /* VAL2 */
210 APINT2EN = (1 << 22),
211 APINT1EN = (1 << 21),
212 APINT0EN = (1 << 20),
213 MIIPDTINTEN = (1 << 19),
214 MCCIINTEN = (1 << 18),
215 MCCINTEN = (1 << 17),
216 MREINTEN = (1 << 16),
217 /* VAL1 */
218 SPNDINTEN = (1 << 14),
219 MPINTEN = (1 << 13),
220 TINTEN3 = (1 << 11),
221 SINTEN = (1 << 12),
222 TINTEN2 = (1 << 10),
223 TINTEN1 = (1 << 9),
224 TINTEN0 = (1 << 8),
225 /* VAL0 */
226 STINTEN = (1 << 4),
227 RINTEN0 = (1 << 0),
228
229 INTEN0_CLEAR = 0x1F7F7F1F, /* Command style register */
230
231}INTEN0_BITS;
INTEN0_BITS
INTEN0_BITS
Definition amd8111e.h:202
APINT3EN
@ APINT3EN
Definition amd8111e.h:208
INTEN0_CLEAR
@ INTEN0_CLEAR
Definition amd8111e.h:229
APINT5EN
@ APINT5EN
Definition amd8111e.h:206
TINTEN2
@ TINTEN2
Definition amd8111e.h:222
TINTEN0
@ TINTEN0
Definition amd8111e.h:224
APINT4EN
@ APINT4EN
Definition amd8111e.h:207
APINT2EN
@ APINT2EN
Definition amd8111e.h:210
APINT0EN
@ APINT0EN
Definition amd8111e.h:212
LCINTEN
@ LCINTEN
Definition amd8111e.h:205
TINTEN1
@ TINTEN1
Definition amd8111e.h:223
MCCINTEN
@ MCCINTEN
Definition amd8111e.h:215
MCCIINTEN
@ MCCIINTEN
Definition amd8111e.h:214
MPINTEN
@ MPINTEN
Definition amd8111e.h:219
APINT1EN
@ APINT1EN
Definition amd8111e.h:211
STINTEN
@ STINTEN
Definition amd8111e.h:226
RINTEN0
@ RINTEN0
Definition amd8111e.h:227
TINTEN3
@ TINTEN3
Definition amd8111e.h:220
SINTEN
@ SINTEN
Definition amd8111e.h:221
MIIPDTINTEN
@ MIIPDTINTEN
Definition amd8111e.h:213
MREINTEN
@ MREINTEN
Definition amd8111e.h:216
SPNDINTEN
@ SPNDINTEN
Definition amd8111e.h:218

◆ CMD0_BITS

enum CMD0_BITS
Enumerator
RDMD0 
TDMD3 
TDMD2 
TDMD1 
TDMD0 
UINTCMD 
RX_FAST_SPND 
TX_FAST_SPND 
RX_SPND 
TX_SPND 
INTREN 
RUN 
CMD0_CLEAR 

Definition at line 233 of file amd8111e.h.

233 {
234 /* VAL2 */
235 RDMD0 = (1 << 16),
236 /* VAL1 */
237 TDMD3 = (1 << 11),
238 TDMD2 = (1 << 10),
239 TDMD1 = (1 << 9),
240 TDMD0 = (1 << 8),
241 /* VAL0 */
242 UINTCMD = (1 << 6),
243 RX_FAST_SPND = (1 << 5),
244 TX_FAST_SPND = (1 << 4),
245 RX_SPND = (1 << 3),
246 TX_SPND = (1 << 2),
247 INTREN = (1 << 1),
248 RUN = (1 << 0),
249
250 CMD0_CLEAR = 0x000F0F7F, /* Command style register */
251
252}CMD0_BITS;
CMD0_BITS
CMD0_BITS
Definition amd8111e.h:233
RX_SPND
@ RX_SPND
Definition amd8111e.h:245
TDMD1
@ TDMD1
Definition amd8111e.h:239
INTREN
@ INTREN
Definition amd8111e.h:247
RUN
@ RUN
Definition amd8111e.h:248
TDMD3
@ TDMD3
Definition amd8111e.h:237
RDMD0
@ RDMD0
Definition amd8111e.h:235
TDMD0
@ TDMD0
Definition amd8111e.h:240
TX_SPND
@ TX_SPND
Definition amd8111e.h:246
TDMD2
@ TDMD2
Definition amd8111e.h:238
TX_FAST_SPND
@ TX_FAST_SPND
Definition amd8111e.h:244
RX_FAST_SPND
@ RX_FAST_SPND
Definition amd8111e.h:243
UINTCMD
@ UINTCMD
Definition amd8111e.h:242
CMD0_CLEAR
@ CMD0_CLEAR
Definition amd8111e.h:250

◆ CMD2_BITS

enum CMD2_BITS
Enumerator
CONDUIT_MODE 
RPA 
DRCVPA 
DRCVBC 
PROM 
ASTRP_RCV 
RCV_DROP0 
EMBA 
DXMT2PD 
LTINTEN 
DXMTFCS 
APAD_XMT 
DRTY 
INLOOP 
EXLOOP 
REX_RTRY 
REX_UFLO 
REX_LCOL 
CMD2_CLEAR 

Definition at line 254 of file amd8111e.h.

254 {
255
256 /* VAL3 */
257 CONDUIT_MODE = (1 << 29),
258 /* VAL2 */
259 RPA = (1 << 19),
260 DRCVPA = (1 << 18),
261 DRCVBC = (1 << 17),
262 PROM = (1 << 16),
263 /* VAL1 */
264 ASTRP_RCV = (1 << 13),
265 RCV_DROP0 = (1 << 12),
266 EMBA = (1 << 11),
267 DXMT2PD = (1 << 10),
268 LTINTEN = (1 << 9),
269 DXMTFCS = (1 << 8),
270 /* VAL0 */
271 APAD_XMT = (1 << 6),
272 DRTY = (1 << 5),
273 INLOOP = (1 << 4),
274 EXLOOP = (1 << 3),
275 REX_RTRY = (1 << 2),
276 REX_UFLO = (1 << 1),
277 REX_LCOL = (1 << 0),
278
279 CMD2_CLEAR = 0x3F7F3F7F, /* Command style register */
280
281}CMD2_BITS;
CMD2_BITS
CMD2_BITS
Definition amd8111e.h:254
RPA
@ RPA
Definition amd8111e.h:259
LTINTEN
@ LTINTEN
Definition amd8111e.h:268
DXMTFCS
@ DXMTFCS
Definition amd8111e.h:269
DRCVBC
@ DRCVBC
Definition amd8111e.h:261
DRTY
@ DRTY
Definition amd8111e.h:272
EMBA
@ EMBA
Definition amd8111e.h:266
CONDUIT_MODE
@ CONDUIT_MODE
Definition amd8111e.h:257
RCV_DROP0
@ RCV_DROP0
Definition amd8111e.h:265
EXLOOP
@ EXLOOP
Definition amd8111e.h:274
INLOOP
@ INLOOP
Definition amd8111e.h:273
REX_RTRY
@ REX_RTRY
Definition amd8111e.h:275
PROM
@ PROM
Definition amd8111e.h:262
REX_LCOL
@ REX_LCOL
Definition amd8111e.h:277
ASTRP_RCV
@ ASTRP_RCV
Definition amd8111e.h:264
REX_UFLO
@ REX_UFLO
Definition amd8111e.h:276
DRCVPA
@ DRCVPA
Definition amd8111e.h:260
CMD2_CLEAR
@ CMD2_CLEAR
Definition amd8111e.h:279
APAD_XMT
@ APAD_XMT
Definition amd8111e.h:271
DXMT2PD
@ DXMT2PD
Definition amd8111e.h:267

◆ CMD3_BITS

enum CMD3_BITS
Enumerator
ASF_INIT_DONE_ALIAS 
JUMBO 
VSIZE 
VLONLY 
VL_TAG_DEL 
EN_PMGR 
INTLEVEL 
FORCE_FULL_DUPLEX 
FORCE_LINK_STATUS 
APEP 
MPPLBA 
RESET_PHY_PULSE 
RESET_PHY 
PHY_RST_POL 

Definition at line 283 of file amd8111e.h.

283 {
284
285 /* VAL3 */
286 ASF_INIT_DONE_ALIAS = (1 << 29),
287 /* VAL2 */
288 JUMBO = (1 << 21),
289 VSIZE = (1 << 20),
290 VLONLY = (1 << 19),
291 VL_TAG_DEL = (1 << 18),
292 /* VAL1 */
293 EN_PMGR = (1 << 14),
294 INTLEVEL = (1 << 13),
295 FORCE_FULL_DUPLEX = (1 << 12),
296 FORCE_LINK_STATUS = (1 << 11),
297 APEP = (1 << 10),
298 MPPLBA = (1 << 9),
299 /* VAL0 */
300 RESET_PHY_PULSE = (1 << 2),
301 RESET_PHY = (1 << 1),
302 PHY_RST_POL = (1 << 0),
303
304}CMD3_BITS;
CMD3_BITS
CMD3_BITS
Definition amd8111e.h:283
VL_TAG_DEL
@ VL_TAG_DEL
Definition amd8111e.h:291
EN_PMGR
@ EN_PMGR
Definition amd8111e.h:293
JUMBO
@ JUMBO
Definition amd8111e.h:288
RESET_PHY
@ RESET_PHY
Definition amd8111e.h:301
VSIZE
@ VSIZE
Definition amd8111e.h:289
INTLEVEL
@ INTLEVEL
Definition amd8111e.h:294
ASF_INIT_DONE_ALIAS
@ ASF_INIT_DONE_ALIAS
Definition amd8111e.h:286
MPPLBA
@ MPPLBA
Definition amd8111e.h:298
PHY_RST_POL
@ PHY_RST_POL
Definition amd8111e.h:302
RESET_PHY_PULSE
@ RESET_PHY_PULSE
Definition amd8111e.h:300
APEP
@ APEP
Definition amd8111e.h:297
FORCE_LINK_STATUS
@ FORCE_LINK_STATUS
Definition amd8111e.h:296
FORCE_FULL_DUPLEX
@ FORCE_FULL_DUPLEX
Definition amd8111e.h:295
VLONLY
@ VLONLY
Definition amd8111e.h:290

◆ CMD7_BITS

enum CMD7_BITS
Enumerator
PMAT_SAVE_MATCH 
PMAT_MODE 
MPEN_SW 
LCMODE_SW 
CMD7_CLEAR 

Definition at line 307 of file amd8111e.h.

307 {
308
309 /* VAL0 */
310 PMAT_SAVE_MATCH = (1 << 4),
311 PMAT_MODE = (1 << 3),
312 MPEN_SW = (1 << 1),
313 LCMODE_SW = (1 << 0),
314
315 CMD7_CLEAR = 0x0000001B /* Command style register */
316
317}CMD7_BITS;
CMD7_BITS
CMD7_BITS
Definition amd8111e.h:307
PMAT_MODE
@ PMAT_MODE
Definition amd8111e.h:311
MPEN_SW
@ MPEN_SW
Definition amd8111e.h:312
PMAT_SAVE_MATCH
@ PMAT_SAVE_MATCH
Definition amd8111e.h:310
CMD7_CLEAR
@ CMD7_CLEAR
Definition amd8111e.h:315
LCMODE_SW
@ LCMODE_SW
Definition amd8111e.h:313

◆ CTRL1_BITS

enum CTRL1_BITS
Enumerator
RESET_PHY_WIDTH 
XMTSP_MASK 
XMTSP_128 
XMTSP_64 
CACHE_ALIGN 
BURST_LIMIT_MASK 
CTRL1_DEFAULT 

Definition at line 320 of file amd8111e.h.

320 {
321
322 RESET_PHY_WIDTH = (0xF << 16) | (0xF<< 20), /* 0x00FF0000 */
323 XMTSP_MASK = (1 << 9) | (1 << 8), /* 9:8 */
324 XMTSP_128 = (1 << 9), /* 9 */
325 XMTSP_64 = (1 << 8),
326 CACHE_ALIGN = (1 << 4),
327 BURST_LIMIT_MASK = (0xF << 0 ),
328 CTRL1_DEFAULT = 0x00010111,
329
330}CTRL1_BITS;
CTRL1_BITS
CTRL1_BITS
Definition amd8111e.h:320
CTRL1_DEFAULT
@ CTRL1_DEFAULT
Definition amd8111e.h:328
XMTSP_128
@ XMTSP_128
Definition amd8111e.h:324
XMTSP_MASK
@ XMTSP_MASK
Definition amd8111e.h:323
CACHE_ALIGN
@ CACHE_ALIGN
Definition amd8111e.h:326
XMTSP_64
@ XMTSP_64
Definition amd8111e.h:325
BURST_LIMIT_MASK
@ BURST_LIMIT_MASK
Definition amd8111e.h:327
RESET_PHY_WIDTH
@ RESET_PHY_WIDTH
Definition amd8111e.h:322

◆ CTRL2_BITS

enum CTRL2_BITS
Enumerator
FMDC_MASK 
XPHYRST 
XPHYANE 
XPHYFD 
XPHYSP 
APDW_MASK 

Definition at line 332 of file amd8111e.h.

332 {
333
334 FMDC_MASK = (1 << 9)|(1 << 8), /* 9:8 */
335 XPHYRST = (1 << 7),
336 XPHYANE = (1 << 6),
337 XPHYFD = (1 << 5),
338 XPHYSP = (1 << 4) | (1 << 3), /* 4:3 */
339 APDW_MASK = (1 << 2) | (1 << 1) | (1 << 0), /* 2:0 */
340
341}CTRL2_BITS;
CTRL2_BITS
CTRL2_BITS
Definition amd8111e.h:332
APDW_MASK
@ APDW_MASK
Definition amd8111e.h:339
XPHYFD
@ XPHYFD
Definition amd8111e.h:337
XPHYRST
@ XPHYRST
Definition amd8111e.h:335
XPHYANE
@ XPHYANE
Definition amd8111e.h:336
XPHYSP
@ XPHYSP
Definition amd8111e.h:338
FMDC_MASK
@ FMDC_MASK
Definition amd8111e.h:334

◆ XMT_RING_LIMIT_BITS

enum XMT_RING_LIMIT_BITS
Enumerator
XMT_RING2_LIMIT 
XMT_RING1_LIMIT 
XMT_RING0_LIMIT 

Definition at line 344 of file amd8111e.h.

344 {
345
346 XMT_RING2_LIMIT = (0xFF << 16), /* 23:16 */
347 XMT_RING1_LIMIT = (0xFF << 8), /* 15:8 */
348 XMT_RING0_LIMIT = (0xFF << 0), /* 7:0 */
349
350}XMT_RING_LIMIT_BITS;
XMT_RING_LIMIT_BITS
XMT_RING_LIMIT_BITS
Definition amd8111e.h:344
XMT_RING2_LIMIT
@ XMT_RING2_LIMIT
Definition amd8111e.h:346
XMT_RING1_LIMIT
@ XMT_RING1_LIMIT
Definition amd8111e.h:347
XMT_RING0_LIMIT
@ XMT_RING0_LIMIT
Definition amd8111e.h:348

◆ AUTOPOLL0_BITS

enum AUTOPOLL0_BITS
Enumerator
AP_REG0_EN 
AP_REG0_ADDR_MASK 
AP_PHY0_ADDR_MASK 

Definition at line 352 of file amd8111e.h.

352 {
353
354 AP_REG0_EN = (1 << 15),
355 AP_REG0_ADDR_MASK = (0xF << 8) |(1 << 12),/* 12:8 */
356 AP_PHY0_ADDR_MASK = (0xF << 0) |(1 << 4),/* 4:0 */
357
358}AUTOPOLL0_BITS;
AUTOPOLL0_BITS
AUTOPOLL0_BITS
Definition amd8111e.h:352
AP_REG0_EN
@ AP_REG0_EN
Definition amd8111e.h:354
AP_REG0_ADDR_MASK
@ AP_REG0_ADDR_MASK
Definition amd8111e.h:355
AP_PHY0_ADDR_MASK
@ AP_PHY0_ADDR_MASK
Definition amd8111e.h:356

◆ AUTOPOLL1_BITS

enum AUTOPOLL1_BITS
Enumerator
AP_REG1_EN 
AP_REG1_ADDR_MASK 
AP_PRE_SUP1 
AP_PHY1_DFLT 
AP_PHY1_ADDR_MASK 

Definition at line 361 of file amd8111e.h.

361 {
362
363 AP_REG1_EN = (1 << 15),
364 AP_REG1_ADDR_MASK = (0xF << 8) |(1 << 12),/* 12:8 */
365 AP_PRE_SUP1 = (1 << 6),
366 AP_PHY1_DFLT = (1 << 5),
367 AP_PHY1_ADDR_MASK = (0xF << 0) |(1 << 4),/* 4:0 */
368
369}AUTOPOLL1_BITS;
AUTOPOLL1_BITS
AUTOPOLL1_BITS
Definition amd8111e.h:361
AP_PHY1_DFLT
@ AP_PHY1_DFLT
Definition amd8111e.h:366
AP_REG1_ADDR_MASK
@ AP_REG1_ADDR_MASK
Definition amd8111e.h:364
AP_REG1_EN
@ AP_REG1_EN
Definition amd8111e.h:363
AP_PHY1_ADDR_MASK
@ AP_PHY1_ADDR_MASK
Definition amd8111e.h:367
AP_PRE_SUP1
@ AP_PRE_SUP1
Definition amd8111e.h:365

◆ AUTOPOLL2_BITS

enum AUTOPOLL2_BITS
Enumerator
AP_REG2_EN 
AP_REG2_ADDR_MASK 
AP_PRE_SUP2 
AP_PHY2_DFLT 
AP_PHY2_ADDR_MASK 

Definition at line 372 of file amd8111e.h.

372 {
373
374 AP_REG2_EN = (1 << 15),
375 AP_REG2_ADDR_MASK = (0xF << 8) |(1 << 12),/* 12:8 */
376 AP_PRE_SUP2 = (1 << 6),
377 AP_PHY2_DFLT = (1 << 5),
378 AP_PHY2_ADDR_MASK = (0xF << 0) |(1 << 4),/* 4:0 */
379
380}AUTOPOLL2_BITS;
AUTOPOLL2_BITS
AUTOPOLL2_BITS
Definition amd8111e.h:372
AP_PRE_SUP2
@ AP_PRE_SUP2
Definition amd8111e.h:376
AP_PHY2_DFLT
@ AP_PHY2_DFLT
Definition amd8111e.h:377
AP_REG2_EN
@ AP_REG2_EN
Definition amd8111e.h:374
AP_REG2_ADDR_MASK
@ AP_REG2_ADDR_MASK
Definition amd8111e.h:375
AP_PHY2_ADDR_MASK
@ AP_PHY2_ADDR_MASK
Definition amd8111e.h:378

◆ AUTOPOLL3_BITS

enum AUTOPOLL3_BITS
Enumerator
AP_REG3_EN 
AP_REG3_ADDR_MASK 
AP_PRE_SUP3 
AP_PHY3_DFLT 
AP_PHY3_ADDR_MASK 

Definition at line 382 of file amd8111e.h.

382 {
383
384 AP_REG3_EN = (1 << 15),
385 AP_REG3_ADDR_MASK = (0xF << 8) |(1 << 12),/* 12:8 */
386 AP_PRE_SUP3 = (1 << 6),
387 AP_PHY3_DFLT = (1 << 5),
388 AP_PHY3_ADDR_MASK = (0xF << 0) |(1 << 4),/* 4:0 */
389
390}AUTOPOLL3_BITS;
AUTOPOLL3_BITS
AUTOPOLL3_BITS
Definition amd8111e.h:382
AP_PHY3_DFLT
@ AP_PHY3_DFLT
Definition amd8111e.h:387
AP_PHY3_ADDR_MASK
@ AP_PHY3_ADDR_MASK
Definition amd8111e.h:388
AP_REG3_EN
@ AP_REG3_EN
Definition amd8111e.h:384
AP_PRE_SUP3
@ AP_PRE_SUP3
Definition amd8111e.h:386
AP_REG3_ADDR_MASK
@ AP_REG3_ADDR_MASK
Definition amd8111e.h:385

◆ AUTOPOLL4_BITS

enum AUTOPOLL4_BITS
Enumerator
AP_REG4_EN 
AP_REG4_ADDR_MASK 
AP_PRE_SUP4 
AP_PHY4_DFLT 
AP_PHY4_ADDR_MASK 

Definition at line 393 of file amd8111e.h.

393 {
394
395 AP_REG4_EN = (1 << 15),
396 AP_REG4_ADDR_MASK = (0xF << 8) |(1 << 12),/* 12:8 */
397 AP_PRE_SUP4 = (1 << 6),
398 AP_PHY4_DFLT = (1 << 5),
399 AP_PHY4_ADDR_MASK = (0xF << 0) |(1 << 4),/* 4:0 */
400
401}AUTOPOLL4_BITS;
AUTOPOLL4_BITS
AUTOPOLL4_BITS
Definition amd8111e.h:393
AP_REG4_EN
@ AP_REG4_EN
Definition amd8111e.h:395
AP_REG4_ADDR_MASK
@ AP_REG4_ADDR_MASK
Definition amd8111e.h:396
AP_PRE_SUP4
@ AP_PRE_SUP4
Definition amd8111e.h:397
AP_PHY4_DFLT
@ AP_PHY4_DFLT
Definition amd8111e.h:398
AP_PHY4_ADDR_MASK
@ AP_PHY4_ADDR_MASK
Definition amd8111e.h:399

◆ AUTOPOLL5_BITS

enum AUTOPOLL5_BITS
Enumerator
AP_REG5_EN 
AP_REG5_ADDR_MASK 
AP_PRE_SUP5 
AP_PHY5_DFLT 
AP_PHY5_ADDR_MASK 

Definition at line 404 of file amd8111e.h.

404 {
405
406 AP_REG5_EN = (1 << 15),
407 AP_REG5_ADDR_MASK = (0xF << 8) |(1 << 12),/* 12:8 */
408 AP_PRE_SUP5 = (1 << 6),
409 AP_PHY5_DFLT = (1 << 5),
410 AP_PHY5_ADDR_MASK = (0xF << 0) |(1 << 4),/* 4:0 */
411
412}AUTOPOLL5_BITS;
AUTOPOLL5_BITS
AUTOPOLL5_BITS
Definition amd8111e.h:404
AP_REG5_ADDR_MASK
@ AP_REG5_ADDR_MASK
Definition amd8111e.h:407
AP_PHY5_ADDR_MASK
@ AP_PHY5_ADDR_MASK
Definition amd8111e.h:410
AP_PHY5_DFLT
@ AP_PHY5_DFLT
Definition amd8111e.h:409
AP_REG5_EN
@ AP_REG5_EN
Definition amd8111e.h:406
AP_PRE_SUP5
@ AP_PRE_SUP5
Definition amd8111e.h:408

◆ AP_VALUE_BITS

enum AP_VALUE_BITS
Enumerator
AP_VAL_ACTIVE 
AP_VAL_RD_CMD 
AP_ADDR 
AP_VAL 

Definition at line 418 of file amd8111e.h.

418 {
419
420 AP_VAL_ACTIVE = (1 << 31),
421 AP_VAL_RD_CMD = ( 1 << 29),
422 AP_ADDR = (1 << 18)|(1 << 17)|(1 << 16), /* 18:16 */
423 AP_VAL = (0xF << 0) | (0xF << 4) |( 0xF << 8) |
424 (0xF << 12), /* 15:0 */
425
426}AP_VALUE_BITS;
AP_VALUE_BITS
AP_VALUE_BITS
Definition amd8111e.h:418
AP_VAL
@ AP_VAL
Definition amd8111e.h:423
AP_VAL_RD_CMD
@ AP_VAL_RD_CMD
Definition amd8111e.h:421
AP_VAL_ACTIVE
@ AP_VAL_ACTIVE
Definition amd8111e.h:420
AP_ADDR
@ AP_ADDR
Definition amd8111e.h:422

◆ DLY_INT_A_BITS

enum DLY_INT_A_BITS
Enumerator
DLY_INT_A_R3 
DLY_INT_A_R2 
DLY_INT_A_R1 
DLY_INT_A_R0 
DLY_INT_A_T3 
DLY_INT_A_T2 
DLY_INT_A_T1 
DLY_INT_A_T0 
EVENT_COUNT_A 
MAX_DELAY_TIME_A 

Definition at line 428 of file amd8111e.h.

428 {
429
430 DLY_INT_A_R3 = (1 << 31),
431 DLY_INT_A_R2 = (1 << 30),
432 DLY_INT_A_R1 = (1 << 29),
433 DLY_INT_A_R0 = (1 << 28),
434 DLY_INT_A_T3 = (1 << 27),
435 DLY_INT_A_T2 = (1 << 26),
436 DLY_INT_A_T1 = (1 << 25),
437 DLY_INT_A_T0 = ( 1 << 24),
438 EVENT_COUNT_A = (0xF << 16) | (0x1 << 20),/* 20:16 */
439 MAX_DELAY_TIME_A = (0xF << 0) | (0xF << 4) | (1 << 8)|
440 (1 << 9) | (1 << 10), /* 10:0 */
441
442}DLY_INT_A_BITS;
DLY_INT_A_BITS
DLY_INT_A_BITS
Definition amd8111e.h:428
DLY_INT_A_R3
@ DLY_INT_A_R3
Definition amd8111e.h:430
DLY_INT_A_T2
@ DLY_INT_A_T2
Definition amd8111e.h:435
DLY_INT_A_T1
@ DLY_INT_A_T1
Definition amd8111e.h:436
DLY_INT_A_R2
@ DLY_INT_A_R2
Definition amd8111e.h:431
MAX_DELAY_TIME_A
@ MAX_DELAY_TIME_A
Definition amd8111e.h:439
EVENT_COUNT_A
@ EVENT_COUNT_A
Definition amd8111e.h:438
DLY_INT_A_T0
@ DLY_INT_A_T0
Definition amd8111e.h:437
DLY_INT_A_T3
@ DLY_INT_A_T3
Definition amd8111e.h:434
DLY_INT_A_R0
@ DLY_INT_A_R0
Definition amd8111e.h:433
DLY_INT_A_R1
@ DLY_INT_A_R1
Definition amd8111e.h:432

◆ DLY_INT_B_BITS

enum DLY_INT_B_BITS
Enumerator
DLY_INT_B_R3 
DLY_INT_B_R2 
DLY_INT_B_R1 
DLY_INT_B_R0 
DLY_INT_B_T3 
DLY_INT_B_T2 
DLY_INT_B_T1 
DLY_INT_B_T0 
EVENT_COUNT_B 
MAX_DELAY_TIME_B 

Definition at line 444 of file amd8111e.h.

444 {
445
446 DLY_INT_B_R3 = (1 << 31),
447 DLY_INT_B_R2 = (1 << 30),
448 DLY_INT_B_R1 = (1 << 29),
449 DLY_INT_B_R0 = (1 << 28),
450 DLY_INT_B_T3 = (1 << 27),
451 DLY_INT_B_T2 = (1 << 26),
452 DLY_INT_B_T1 = (1 << 25),
453 DLY_INT_B_T0 = ( 1 << 24),
454 EVENT_COUNT_B = (0xF << 16) | (0x1 << 20),/* 20:16 */
455 MAX_DELAY_TIME_B = (0xF << 0) | (0xF << 4) | (1 << 8)|
456 (1 << 9) | (1 << 10), /* 10:0 */
457}DLY_INT_B_BITS;
DLY_INT_B_BITS
DLY_INT_B_BITS
Definition amd8111e.h:444
DLY_INT_B_T3
@ DLY_INT_B_T3
Definition amd8111e.h:450
DLY_INT_B_T0
@ DLY_INT_B_T0
Definition amd8111e.h:453
EVENT_COUNT_B
@ EVENT_COUNT_B
Definition amd8111e.h:454
DLY_INT_B_T1
@ DLY_INT_B_T1
Definition amd8111e.h:452
DLY_INT_B_R3
@ DLY_INT_B_R3
Definition amd8111e.h:446
DLY_INT_B_T2
@ DLY_INT_B_T2
Definition amd8111e.h:451
DLY_INT_B_R1
@ DLY_INT_B_R1
Definition amd8111e.h:448
MAX_DELAY_TIME_B
@ MAX_DELAY_TIME_B
Definition amd8111e.h:455
DLY_INT_B_R2
@ DLY_INT_B_R2
Definition amd8111e.h:447
DLY_INT_B_R0
@ DLY_INT_B_R0
Definition amd8111e.h:449

◆ FLOW_CONTROL_BITS

enum FLOW_CONTROL_BITS
Enumerator
PAUSE_LEN_CHG 
FTPE 
FRPE 
NAPA 
NPA 
FIXP 
FCCMD 
PAUSE_LEN 

Definition at line 461 of file amd8111e.h.

461 {
462
463 PAUSE_LEN_CHG = (1 << 30),
464 FTPE = (1 << 22),
465 FRPE = (1 << 21),
466 NAPA = (1 << 20),
467 NPA = (1 << 19),
468 FIXP = ( 1 << 18),
469 FCCMD = ( 1 << 16),
470 PAUSE_LEN = (0xF << 0) | (0xF << 4) |( 0xF << 8) | (0xF << 12), /* 15:0 */
471
472}FLOW_CONTROL_BITS;
FLOW_CONTROL_BITS
FLOW_CONTROL_BITS
Definition amd8111e.h:461
NPA
@ NPA
Definition amd8111e.h:467
FCCMD
@ FCCMD
Definition amd8111e.h:469
PAUSE_LEN
@ PAUSE_LEN
Definition amd8111e.h:470
FTPE
@ FTPE
Definition amd8111e.h:464
FIXP
@ FIXP
Definition amd8111e.h:468
PAUSE_LEN_CHG
@ PAUSE_LEN_CHG
Definition amd8111e.h:463
NAPA
@ NAPA
Definition amd8111e.h:466
FRPE
@ FRPE
Definition amd8111e.h:465

◆ PHY_ACCESS_BITS

enum PHY_ACCESS_BITS
Enumerator
PHY_CMD_ACTIVE 
PHY_WR_CMD 
PHY_RD_CMD 
PHY_RD_ERR 
PHY_PRE_SUP 
PHY_ADDR 
PHY_REG_ADDR 
PHY_DATA 

Definition at line 475 of file amd8111e.h.

475 {
476
477 PHY_CMD_ACTIVE = (1 << 31),
478 PHY_WR_CMD = (1 << 30),
479 PHY_RD_CMD = (1 << 29),
480 PHY_RD_ERR = (1 << 28),
481 PHY_PRE_SUP = (1 << 27),
482 PHY_ADDR = (1 << 21) | (1 << 22) | (1 << 23)|
483 (1 << 24) |(1 << 25),/* 25:21 */
484 PHY_REG_ADDR = (1 << 16) | (1 << 17) | (1 << 18)| (1 << 19) | (1 << 20),/* 20:16 */
485 PHY_DATA = (0xF << 0)|(0xF << 4) |(0xF << 8)|
486 (0xF << 12),/* 15:0 */
487
488}PHY_ACCESS_BITS;
PHY_ACCESS_BITS
PHY_ACCESS_BITS
Definition amd8111e.h:475
PHY_RD_CMD
@ PHY_RD_CMD
Definition amd8111e.h:479
PHY_CMD_ACTIVE
@ PHY_CMD_ACTIVE
Definition amd8111e.h:477
PHY_REG_ADDR
@ PHY_REG_ADDR
Definition amd8111e.h:484
PHY_RD_ERR
@ PHY_RD_ERR
Definition amd8111e.h:480
PHY_DATA
@ PHY_DATA
Definition amd8111e.h:485
PHY_WR_CMD
@ PHY_WR_CMD
Definition amd8111e.h:478
PHY_PRE_SUP
@ PHY_PRE_SUP
Definition amd8111e.h:481
PHY_ADDR
@ PHY_ADDR
Definition amd8111e.h:482

◆ PMAT0_BITS

enum PMAT0_BITS
Enumerator
PMR_ACTIVE 
PMR_WR_CMD 
PMR_RD_CMD 
PMR_BANK 
PMR_ADDR 
PMR_B4 

Definition at line 492 of file amd8111e.h.

492 {
493 PMR_ACTIVE = (1 << 31),
494 PMR_WR_CMD = (1 << 30),
495 PMR_RD_CMD = (1 << 29),
496 PMR_BANK = (1 <<28),
497 PMR_ADDR = (0xF << 16)|(1 << 20)|(1 << 21)|
498 (1 << 22),/* 22:16 */
499 PMR_B4 = (0xF << 0) | (0xF << 4),/* 15:0 */
500}PMAT0_BITS;
PMAT0_BITS
PMAT0_BITS
Definition amd8111e.h:492
PMR_RD_CMD
@ PMR_RD_CMD
Definition amd8111e.h:495
PMR_B4
@ PMR_B4
Definition amd8111e.h:499
PMR_BANK
@ PMR_BANK
Definition amd8111e.h:496
PMR_WR_CMD
@ PMR_WR_CMD
Definition amd8111e.h:494
PMR_ADDR
@ PMR_ADDR
Definition amd8111e.h:497
PMR_ACTIVE
@ PMR_ACTIVE
Definition amd8111e.h:493

◆ PMAT1_BITS

enum PMAT1_BITS
Enumerator
PMR_B3 
PMR_B2 
PMR_B1 
PMR_B0 

Definition at line 504 of file amd8111e.h.

504 {
505 PMR_B3 = (0xF << 24) | (0xF <<28),/* 31:24 */
506 PMR_B2 = (0xF << 16) |(0xF << 20),/* 23:16 */
507 PMR_B1 = (0xF << 8) | (0xF <<12), /* 15:8 */
508 PMR_B0 = (0xF << 0)|(0xF << 4),/* 7:0 */
509}PMAT1_BITS;
PMAT1_BITS
PMAT1_BITS
Definition amd8111e.h:504
PMR_B3
@ PMR_B3
Definition amd8111e.h:505
PMR_B2
@ PMR_B2
Definition amd8111e.h:506
PMR_B1
@ PMR_B1
Definition amd8111e.h:507
PMR_B0
@ PMR_B0
Definition amd8111e.h:508

◆ TX_FLAG_BITS

enum TX_FLAG_BITS
Enumerator
OWN_BIT 
ADD_FCS_BIT 
LTINT_BIT 
STP_BIT 
ENP_BIT 
KILL_BIT 
TCC_VLAN_INSERT 
TCC_VLAN_REPLACE 

Definition at line 582 of file amd8111e.h.

582 {
583
584 OWN_BIT = (1 << 15),
585 ADD_FCS_BIT = (1 << 13),
586 LTINT_BIT = (1 << 12),
587 STP_BIT = (1 << 9),
588 ENP_BIT = (1 << 8),
589 KILL_BIT = (1 << 6),
590 TCC_VLAN_INSERT = (1 << 1),
591 TCC_VLAN_REPLACE = (1 << 1) |( 1<< 0),
592
593}TX_FLAG_BITS;
TX_FLAG_BITS
TX_FLAG_BITS
Definition amd8111e.h:582
ENP_BIT
@ ENP_BIT
Definition amd8111e.h:588
OWN_BIT
@ OWN_BIT
Definition amd8111e.h:584
TCC_VLAN_REPLACE
@ TCC_VLAN_REPLACE
Definition amd8111e.h:591
LTINT_BIT
@ LTINT_BIT
Definition amd8111e.h:586
KILL_BIT
@ KILL_BIT
Definition amd8111e.h:589
ADD_FCS_BIT
@ ADD_FCS_BIT
Definition amd8111e.h:585
STP_BIT
@ STP_BIT
Definition amd8111e.h:587
TCC_VLAN_INSERT
@ TCC_VLAN_INSERT
Definition amd8111e.h:590

◆ RX_FLAG_BITS

enum RX_FLAG_BITS
Enumerator
ERR_BIT 
FRAM_BIT 
OFLO_BIT 
CRC_BIT 
PAM_BIT 
LAFM_BIT 
BAM_BIT 
TT_VLAN_TAGGED 
TT_PRTY_TAGGED 

Definition at line 595 of file amd8111e.h.

595 {
596 ERR_BIT = (1 << 14),
597 FRAM_BIT = (1 << 13),
598 OFLO_BIT = (1 << 12),
599 CRC_BIT = (1 << 11),
600 PAM_BIT = (1 << 6),
601 LAFM_BIT = (1 << 5),
602 BAM_BIT = (1 << 4),
603 TT_VLAN_TAGGED = (1 << 3) |(1 << 2),/* 0x000 */
604 TT_PRTY_TAGGED = (1 << 3),/* 0x0008 */
605
606}RX_FLAG_BITS;
RX_FLAG_BITS
RX_FLAG_BITS
Definition amd8111e.h:595
CRC_BIT
@ CRC_BIT
Definition amd8111e.h:599
LAFM_BIT
@ LAFM_BIT
Definition amd8111e.h:601
BAM_BIT
@ BAM_BIT
Definition amd8111e.h:602
OFLO_BIT
@ OFLO_BIT
Definition amd8111e.h:598
PAM_BIT
@ PAM_BIT
Definition amd8111e.h:600
TT_VLAN_TAGGED
@ TT_VLAN_TAGGED
Definition amd8111e.h:603
TT_PRTY_TAGGED
@ TT_PRTY_TAGGED
Definition amd8111e.h:604
ERR_BIT
@ ERR_BIT
Definition amd8111e.h:596
FRAM_BIT
@ FRAM_BIT
Definition amd8111e.h:597

◆ EXT_PHY_OPTION

enum EXT_PHY_OPTION
Enumerator
SPEED_AUTONEG 
SPEED10_HALF 
SPEED10_FULL 
SPEED100_HALF 
SPEED100_FULL 

Definition at line 626 of file amd8111e.h.

626 {
627 SPEED_AUTONEG,
628 SPEED10_HALF,
629 SPEED10_FULL,
630 SPEED100_HALF,
631 SPEED100_FULL,
632}EXT_PHY_OPTION;
EXT_PHY_OPTION
EXT_PHY_OPTION
Definition amd8111e.h:626
SPEED_AUTONEG
@ SPEED_AUTONEG
Definition amd8111e.h:627
SPEED100_FULL
@ SPEED100_FULL
Definition amd8111e.h:631
SPEED10_FULL
@ SPEED10_FULL
Definition amd8111e.h:629
SPEED100_HALF
@ SPEED100_HALF
Definition amd8111e.h:630
SPEED10_HALF
@ SPEED10_HALF
Definition amd8111e.h:628

Function Documentation

◆ FILE_LICENCE()

FILE_LICENCE ( GPL2_OR_LATER_OR_UBDL )
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