74 #define XMT_RING_LIMIT 0x7C 76 #define AUTOPOLL0 0x88 77 #define AUTOPOLL1 0x8A 78 #define AUTOPOLL2 0x8C 79 #define AUTOPOLL3 0x8E 80 #define AUTOPOLL4 0x90 81 #define AUTOPOLL5 0x92 84 #define DLY_INT_A 0xA8 85 #define DLY_INT_B 0xAC 87 #define FLOW_CONTROL 0xC8 88 #define PHY_ACCESS 0xD0 92 #define XMT_RING_BASE_ADDR0 0x100 93 #define XMT_RING_BASE_ADDR1 0x108 94 #define XMT_RING_BASE_ADDR2 0x110 95 #define XMT_RING_BASE_ADDR3 0x118 97 #define RCV_RING_BASE_ADDR0 0x120 104 #define XMT_RING_LEN0 0x140 105 #define XMT_RING_LEN1 0x144 106 #define XMT_RING_LEN2 0x148 107 #define XMT_RING_LEN3 0x14C 109 #define RCV_RING_LEN0 0x150 111 #define SRAM_SIZE 0x178 112 #define SRAM_BOUNDARY 0x17A 160 #define PHY_SPEED_10 0x2 161 #define PHY_SPEED_100 0x3 423 AP_VAL = (0xF << 0) | (0xF << 4) |( 0xF << 8) |
440 (1 << 9) | (1 << 10),
456 (1 << 9) | (1 << 10),
470 PAUSE_LEN = (0xF << 0) | (0xF << 4) |( 0xF << 8) | (0xF << 12),
483 (1 << 24) |(1 << 25),
484 PHY_REG_ADDR = (1 << 16) | (1 << 17) | (1 << 18)| (1 << 19) | (1 << 20),
517 #define rcv_miss_pkts 0x00 518 #define rcv_octets 0x01 519 #define rcv_broadcast_pkts 0x02 520 #define rcv_multicast_pkts 0x03 521 #define rcv_undersize_pkts 0x04 522 #define rcv_oversize_pkts 0x05 523 #define rcv_fragments 0x06 524 #define rcv_jabbers 0x07 525 #define rcv_unicast_pkts 0x08 526 #define rcv_alignment_errors 0x09 527 #define rcv_fcs_errors 0x0A 528 #define rcv_good_octets 0x0B 529 #define rcv_mac_ctrl 0x0C 530 #define rcv_flow_ctrl 0x0D 531 #define rcv_pkts_64_octets 0x0E 532 #define rcv_pkts_65to127_octets 0x0F 533 #define rcv_pkts_128to255_octets 0x10 534 #define rcv_pkts_256to511_octets 0x11 535 #define rcv_pkts_512to1023_octets 0x12 536 #define rcv_pkts_1024to1518_octets 0x13 537 #define rcv_unsupported_opcode 0x14 538 #define rcv_symbol_errors 0x15 539 #define rcv_drop_pkts_ring1 0x16 540 #define rcv_drop_pkts_ring2 0x17 541 #define rcv_drop_pkts_ring3 0x18 542 #define rcv_drop_pkts_ring4 0x19 543 #define rcv_jumbo_pkts 0x1A 545 #define xmt_underrun_pkts 0x20 546 #define xmt_octets 0x21 547 #define xmt_packets 0x22 548 #define xmt_broadcast_pkts 0x23 549 #define xmt_multicast_pkts 0x24 550 #define xmt_collisions 0x25 551 #define xmt_unicast_pkts 0x26 552 #define xmt_one_collision 0x27 553 #define xmt_multiple_collision 0x28 554 #define xmt_deferred_transmit 0x29 555 #define xmt_late_collision 0x2A 556 #define xmt_excessive_defer 0x2B 557 #define xmt_loss_carrier 0x2C 558 #define xmt_excessive_collision 0x2D 559 #define xmt_back_pressure 0x2E 560 #define xmt_flow_ctrl 0x2F 561 #define xmt_pkts_64_octets 0x30 562 #define xmt_pkts_65to127_octets 0x31 563 #define xmt_pkts_128to255_octets 0x32 564 #define xmt_pkts_256to511_octets 0x33 565 #define xmt_pkts_512to1023_octets 0x34 566 #define xmt_pkts_1024to1518_octet 0x35 567 #define xmt_oversize_pkts 0x36 568 #define xmt_jumbo_pkts 0x37 571 #define DEFAULT_IPG 0x60 572 #define IFS1_DELTA 36 573 #define IPG_CONVERGE_JIFFIES (HZ/2) 574 #define IPG_STABLE_TIME 5 608 #define RESET_RX_FLAGS 0x0000 609 #define TT_MASK 0x000c 610 #define TCC_MASK 0x0003 613 #define AMD8111E_REG_DUMP_LEN 13*sizeof(u32) 616 #define CRC32 0xedb88320 617 #define INITCRC 0xFFFFFFFF 621 #define amd8111e_writeq(_UlData,_memMap) \ 622 writel(*(u32*)(&_UlData), _memMap); \ 623 writel(*(u32*)((u8*)(&_UlData)+4), _memMap+4)
FILE_LICENCE(GPL2_OR_LATER_OR_UBDL)