40 #define ATL_BAR_SIZE 0x10000 41 #define ATL2_BAR_SIZE 0x40000 42 #define ATL_RING_SIZE 64 43 #define ATL_RING_ALIGN 128 44 #define ATL_RX_MAX_LEN 2048 46 #define ATL_IRQ_TX 0x00000001U 47 #define ATL_IRQ_RX 0x00000002U 50 #define ATL_IRQ_STAT_REG 0x00002000U 53 #define ATL_IRQ_CTRL 0x00002300U 54 #define ATL_IRQ_CTRL_COR_EN 0x00000080U 55 #define ATL_IRQ_CTRL_REG_RST_DIS 0x20000000U 58 #define ATL_IRQ_MAP_REG1 0x00002100U 60 #define ATL_IRQ_MAP_REG1_RX0_EN 0x00008000U 61 #define ATL_IRQ_MAP_REG1_RX0 0x00000100U 63 #define ATL_IRQ_MAP_REG1_TX0_EN 0x80000000U 64 #define ATL_IRQ_MAP_REG1_TX0 0x00000000U 67 #define ATL_TX_IRQ_CTRL 0x00007B40U 68 #define ATL_TX_IRQ_CTRL_WB_EN 0x00000002U 71 #define ATL_RX_IRQ_CTRL 0x00005A30U 72 #define ATL_RX_IRQ_CTRL_WB_EN 0x00000004U 74 #define ATL_GLB_CTRL 0x00000000U 76 #define ATL_PCI_CTRL 0x00001000U 77 #define ATL_PCI_CTRL_RST_DIS 0x20000000U 79 #define ATL_RX_CTRL 0x00005000U 80 #define ATL_RX_CTRL_RST_DIS 0x20000000U 81 #define ATL_TX_CTRL 0x00007000U 82 #define ATL_TX_CTRL_RST_DIS 0x20000000U 85 #define ATL_RPF2_CTRL 0x00005040U 86 #define ATL_RPF2_CTRL_EN 0x000F0000U 87 #define ATL2_RPF_NEW_EN_ADR_EN 0x00000001U 88 #define ATL2_RPF_NEW_EN_ADR 0x5104 90 #define ATL_RPF_CTRL1 0x00005100U 91 #define ATL_RPF_CTRL1_BRC_EN 0x00000001U 92 #define ATL_RPF_CTRL1_L2_PROMISC 0x00000008U 93 #define ATL_RPF_CTRL1_ACTION 0x00001000U 94 #define ATL_RPF_CTRL1_BRC_TSH 0x00010000U 96 #define ATL_RPF_CTRL2 0x00005280U 97 #define ATL_RPF_CTRL2_VLAN_PROMISC 0x00000002U 99 #define ATL_RPB_CTRL_DIS 0x0 100 #define ATL_RPB_CTRL 0x00005700U 101 #define ATL_RPB_CTRL_EN 0x00000001U 102 #define ATL_RPB_CTRL_FC 0x00000010U 103 #define ATL_RPB_CTRL_TC_MODE 0x00000100U 105 #define ATL_RPB0_CTRL1 0x00005710U 106 #define ATL_RPB0_CTRL1_SIZE 0x00000140U 108 #define ATL_RPB0_CTRL2 0x00005714U 111 #define ATL_RPB0_CTRL2_LOW_TSH 0x00000C00U 113 #define ATL_RPB0_CTRL2_HIGH_TSH 0x1C000000U 114 #define ATL_RPB0_CTRL2_FC_EN 0x80000000U 116 #define ATL_RX_DMA_DESC_BUF_SIZE 0x00005b18U 117 #define ATL_RX_DMA_DESC_ADDR 0x00005b00U 120 #define ATL_TPO2_CTRL 0x00007040U 121 #define ATL_TPO2_EN 0x00010000U 123 #define ATL_TPB_CTRL_DIS 0x0 124 #define ATL_TPB_CTRL 0x00007900U 125 #define ATL_TPB_CTRL_EN 0x00000001U 126 #define ATL_TPB_CTRL_PAD_EN 0x00000004U 127 #define ATL_TPB_CTRL_TC_MODE 0x00000100U 129 #define ATL_TPB0_CTRL1 0x00007910U 130 #define ATL_TPB0_CTRL1_SIZE 0x000000A0U 132 #define ATL_TPB0_CTRL2 0x00007914U 134 #define ATL_TPB0_CTRL2_LOW_TSH 0x00000600U 136 #define ATL_TPB0_CTRL2_HIGH_TSH 0x0E000000U 138 #define ATL_TX_DMA_DESC_ADDR 0x00007c00U 141 #define ATL_RING_TX_CTRL 0x00007c08U 142 #define ATL_RING_TX_CTRL_EN 0x80000000U 144 #define ATL_RING_RX_CTRL 0x00005b08U 145 #define ATL_RING_RX_CTRL_EN 0x80000000U 147 #define ATL_RING_TAIL 0x00007c10U 148 #define ATL_RING_TAIL_PTR 0x00005b10U 151 #define ATL_ITR_MSKS_DIS 0x0 152 #define ATL_ITR_MSKS 0x00002060U 153 #define ATL_ITR_MSKS_LSW 0x0000000CU 154 #define ATL_ITR_MSKC 0x00002070U 155 #define ATL_ITR_MSKC_LSW 0x0000000CU 158 #define ATL_LINK_ADV 0x00000368U 159 #define ATL_SHUT_LINK 0x0 160 #define ATL_LINK_ADV_AUTONEG 0xF20U 162 #define ATL_LINK_ST 0x00000370U 165 #define ATL_SEM_RAM 0x000003a8U 166 #define ATL_SEM_RAM_RESET 0X1 169 #define ATL_MBOX_ADDR 0x00000360U 170 #define ATL_MBOX_CTRL1 0x00000200U 171 #define ATL_MBOX_CTRL1_START_MBOX_OPT 0x8000 173 #define ATL_MBOX_CTRL3 0x00000208U 174 #define ATL_MBOX_CTRL5 0x0000020cU 176 #define ATL_FLAG_A1 0x1 177 #define ATL_FLAG_A2 0x2 180 #define ATL_WRITE_REG( VAL, REG ) writel( VAL, nic->regs + (REG) ) 181 #define ATL_READ_REG( REG ) readl( nic->regs + (REG) ) 189 #define ATL_DESC_TX_DX_TYPE_VALUE 0x1 191 #define ATL_DESC_TX_DX_EOP_VALUE 0x1 192 #define ATL_DESC_TX_EOP_MASK 0x00200000 193 #define ATL_DESC_TX_EOP_OFFSET 21 195 #define ATL_DESC_TX_CMD_MASK 0x3FC00000UL 196 #define ATL_DESC_TX_CMD_OFFSET 22 197 #define ATL_DESC_TX_CMD_VALUE 0x22 199 #define ATL_DESC_TX_BUF_LEN_MASK 0x000FFFF0 200 #define ATL_DESC_TX_BUF_LEN_OFFSET 5 202 #define ATL_DESC_TX_PAY_LEN_MASK 0xFFFFC000 203 #define ATL_DESC_TX_PAY_LEN_OFFSET 14 211 #define ATL_TX_DESC_STATUS_DD 0x00100000UL 226 #define ATL_RX_DESC_STATUS_DD 0x0001UL 227 #define ATL_RX_DESC_STATUS_EOP 0x0002UL An aQuanita network card.
int(* get_link)(struct atl_nic *nic)
struct io_buffer * iobufs[ATL_RING_SIZE]
unsigned long long uint64_t
uint8_t mac[ETH_ALEN]
MAC address.
struct atl_hw_ops * hw_ops
int(* reset)(struct atl_nic *nic)
int(* get_mac)(struct atl_nic *, uint8_t *mac)
struct atl_ring __attribute__
struct dma_mapping map
Descriptor ring DMA mapping.
int(* start)(struct atl_nic *nic)
int(* stop)(struct atl_nic *nic)
struct dma_device * dma
DMA device.
unsigned int port
Port number (for multi-port devices)