iPXE
ar9003_phy.h
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1 /*
2  * Copyright (c) 2010-2011 Atheros Communications, Inc.
3  *
4  * Permission to use, copy, modify, and/or distribute this software for any
5  * purpose with or without fee is hereby granted, provided that the above
6  * copyright notice and this permission notice appear in all copies.
7  *
8  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15  */
16 
17 #ifndef AR9003_PHY_H
18 #define AR9003_PHY_H
19 
20 /*
21  * Channel Register Map
22  */
23 #define AR_CHAN_BASE 0x9800
24 
25 #define AR_PHY_TIMING1 (AR_CHAN_BASE + 0x0)
26 #define AR_PHY_TIMING2 (AR_CHAN_BASE + 0x4)
27 #define AR_PHY_TIMING3 (AR_CHAN_BASE + 0x8)
28 #define AR_PHY_TIMING4 (AR_CHAN_BASE + 0xc)
29 #define AR_PHY_TIMING5 (AR_CHAN_BASE + 0x10)
30 #define AR_PHY_TIMING6 (AR_CHAN_BASE + 0x14)
31 #define AR_PHY_TIMING11 (AR_CHAN_BASE + 0x18)
32 #define AR_PHY_SPUR_REG (AR_CHAN_BASE + 0x1c)
33 #define AR_PHY_RX_IQCAL_CORR_B0 (AR_CHAN_BASE + 0xdc)
34 #define AR_PHY_TX_IQCAL_CONTROL_3 (AR_CHAN_BASE + 0xb0)
35 
36 #define AR_PHY_TIMING11_SPUR_FREQ_SD 0x3FF00000
37 #define AR_PHY_TIMING11_SPUR_FREQ_SD_S 20
38 
39 #define AR_PHY_TIMING11_SPUR_DELTA_PHASE 0x000FFFFF
40 #define AR_PHY_TIMING11_SPUR_DELTA_PHASE_S 0
41 
42 #define AR_PHY_TIMING11_USE_SPUR_FILTER_IN_AGC 0x40000000
43 #define AR_PHY_TIMING11_USE_SPUR_FILTER_IN_AGC_S 30
44 
45 #define AR_PHY_TIMING11_USE_SPUR_FILTER_IN_SELFCOR 0x80000000
46 #define AR_PHY_TIMING11_USE_SPUR_FILTER_IN_SELFCOR_S 31
47 
48 #define AR_PHY_SPUR_REG_ENABLE_NF_RSSI_SPUR_MIT 0x4000000
49 #define AR_PHY_SPUR_REG_ENABLE_NF_RSSI_SPUR_MIT_S 26
50 
51 #define AR_PHY_SPUR_REG_ENABLE_MASK_PPM 0x20000 /* bins move with freq offset */
52 #define AR_PHY_SPUR_REG_ENABLE_MASK_PPM_S 17
53 #define AR_PHY_SPUR_REG_SPUR_RSSI_THRESH 0x000000FF
54 #define AR_PHY_SPUR_REG_SPUR_RSSI_THRESH_S 0
55 #define AR_PHY_SPUR_REG_EN_VIT_SPUR_RSSI 0x00000100
56 #define AR_PHY_SPUR_REG_EN_VIT_SPUR_RSSI_S 8
57 #define AR_PHY_SPUR_REG_MASK_RATE_CNTL 0x03FC0000
58 #define AR_PHY_SPUR_REG_MASK_RATE_CNTL_S 18
59 
60 #define AR_PHY_RX_IQCAL_CORR_B0_LOOPBACK_IQCORR_EN 0x20000000
61 #define AR_PHY_RX_IQCAL_CORR_B0_LOOPBACK_IQCORR_EN_S 29
62 
63 #define AR_PHY_TX_IQCAL_CONTROL_3_IQCORR_EN 0x80000000
64 #define AR_PHY_TX_IQCAL_CONTROL_3_IQCORR_EN_S 31
65 
66 #define AR_PHY_FIND_SIG_LOW (AR_CHAN_BASE + 0x20)
67 
68 #define AR_PHY_SFCORR (AR_CHAN_BASE + 0x24)
69 #define AR_PHY_SFCORR_LOW (AR_CHAN_BASE + 0x28)
70 #define AR_PHY_SFCORR_EXT (AR_CHAN_BASE + 0x2c)
71 
72 #define AR_PHY_EXT_CCA (AR_CHAN_BASE + 0x30)
73 #define AR_PHY_RADAR_0 (AR_CHAN_BASE + 0x34)
74 #define AR_PHY_RADAR_1 (AR_CHAN_BASE + 0x38)
75 #define AR_PHY_RADAR_EXT (AR_CHAN_BASE + 0x3c)
76 #define AR_PHY_MULTICHAIN_CTRL (AR_CHAN_BASE + 0x80)
77 #define AR_PHY_PERCHAIN_CSD (AR_CHAN_BASE + 0x84)
78 
79 #define AR_PHY_TX_PHASE_RAMP_0 (AR_CHAN_BASE + 0xd0)
80 #define AR_PHY_ADC_GAIN_DC_CORR_0 (AR_CHAN_BASE + 0xd4)
81 #define AR_PHY_IQ_ADC_MEAS_0_B0 (AR_CHAN_BASE + 0xc0)
82 #define AR_PHY_IQ_ADC_MEAS_1_B0 (AR_CHAN_BASE + 0xc4)
83 #define AR_PHY_IQ_ADC_MEAS_2_B0 (AR_CHAN_BASE + 0xc8)
84 #define AR_PHY_IQ_ADC_MEAS_3_B0 (AR_CHAN_BASE + 0xcc)
85 
86 /* The following registers changed position from AR9300 1.0 to AR9300 2.0 */
87 #define AR_PHY_TX_PHASE_RAMP_0_9300_10 (AR_CHAN_BASE + 0xd0 - 0x10)
88 #define AR_PHY_ADC_GAIN_DC_CORR_0_9300_10 (AR_CHAN_BASE + 0xd4 - 0x10)
89 #define AR_PHY_IQ_ADC_MEAS_0_B0_9300_10 (AR_CHAN_BASE + 0xc0 + 0x8)
90 #define AR_PHY_IQ_ADC_MEAS_1_B0_9300_10 (AR_CHAN_BASE + 0xc4 + 0x8)
91 #define AR_PHY_IQ_ADC_MEAS_2_B0_9300_10 (AR_CHAN_BASE + 0xc8 + 0x8)
92 #define AR_PHY_IQ_ADC_MEAS_3_B0_9300_10 (AR_CHAN_BASE + 0xcc + 0x8)
93 
94 #define AR_PHY_TX_CRC (AR_CHAN_BASE + 0xa0)
95 #define AR_PHY_TST_DAC_CONST (AR_CHAN_BASE + 0xa4)
96 #define AR_PHY_SPUR_REPORT_0 (AR_CHAN_BASE + 0xa8)
97 #define AR_PHY_CHAN_INFO_TAB_0 (AR_CHAN_BASE + 0x300)
98 
99 /*
100  * Channel Field Definitions
101  */
102 #define AR_PHY_TIMING2_USE_FORCE_PPM 0x00001000
103 #define AR_PHY_TIMING2_FORCE_PPM_VAL 0x00000fff
104 #define AR_PHY_TIMING3_DSC_MAN 0xFFFE0000
105 #define AR_PHY_TIMING3_DSC_MAN_S 17
106 #define AR_PHY_TIMING3_DSC_EXP 0x0001E000
107 #define AR_PHY_TIMING3_DSC_EXP_S 13
108 #define AR_PHY_TIMING4_IQCAL_LOG_COUNT_MAX 0xF000
109 #define AR_PHY_TIMING4_IQCAL_LOG_COUNT_MAX_S 12
110 #define AR_PHY_TIMING4_DO_CAL 0x10000
111 
112 #define AR_PHY_TIMING4_ENABLE_PILOT_MASK 0x10000000
113 #define AR_PHY_TIMING4_ENABLE_PILOT_MASK_S 28
114 #define AR_PHY_TIMING4_ENABLE_CHAN_MASK 0x20000000
115 #define AR_PHY_TIMING4_ENABLE_CHAN_MASK_S 29
116 
117 #define AR_PHY_TIMING4_ENABLE_SPUR_FILTER 0x40000000
118 #define AR_PHY_TIMING4_ENABLE_SPUR_FILTER_S 30
119 #define AR_PHY_TIMING4_ENABLE_SPUR_RSSI 0x80000000
120 #define AR_PHY_TIMING4_ENABLE_SPUR_RSSI_S 31
121 
122 #define AR_PHY_NEW_ADC_GAIN_CORR_ENABLE 0x40000000
123 #define AR_PHY_NEW_ADC_DC_OFFSET_CORR_ENABLE 0x80000000
124 #define AR_PHY_SFCORR_LOW_USE_SELF_CORR_LOW 0x00000001
125 #define AR_PHY_SFCORR_LOW_M2COUNT_THR_LOW 0x00003F00
126 #define AR_PHY_SFCORR_LOW_M2COUNT_THR_LOW_S 8
127 #define AR_PHY_SFCORR_LOW_M1_THRESH_LOW 0x001FC000
128 #define AR_PHY_SFCORR_LOW_M1_THRESH_LOW_S 14
129 #define AR_PHY_SFCORR_LOW_M2_THRESH_LOW 0x0FE00000
130 #define AR_PHY_SFCORR_LOW_M2_THRESH_LOW_S 21
131 #define AR_PHY_SFCORR_M2COUNT_THR 0x0000001F
132 #define AR_PHY_SFCORR_M2COUNT_THR_S 0
133 #define AR_PHY_SFCORR_M1_THRESH 0x00FE0000
134 #define AR_PHY_SFCORR_M1_THRESH_S 17
135 #define AR_PHY_SFCORR_M2_THRESH 0x7F000000
136 #define AR_PHY_SFCORR_M2_THRESH_S 24
137 #define AR_PHY_SFCORR_EXT_M1_THRESH 0x0000007F
138 #define AR_PHY_SFCORR_EXT_M1_THRESH_S 0
139 #define AR_PHY_SFCORR_EXT_M2_THRESH 0x00003F80
140 #define AR_PHY_SFCORR_EXT_M2_THRESH_S 7
141 #define AR_PHY_SFCORR_EXT_M1_THRESH_LOW 0x001FC000
142 #define AR_PHY_SFCORR_EXT_M1_THRESH_LOW_S 14
143 #define AR_PHY_SFCORR_EXT_M2_THRESH_LOW 0x0FE00000
144 #define AR_PHY_SFCORR_EXT_M2_THRESH_LOW_S 21
145 #define AR_PHY_SFCORR_EXT_SPUR_SUBCHANNEL_SD 0x10000000
146 #define AR_PHY_SFCORR_EXT_SPUR_SUBCHANNEL_SD_S 28
147 #define AR_PHY_SFCORR_SPUR_SUBCHNL_SD_S 28
148 #define AR_PHY_EXT_CCA_THRESH62 0x007F0000
149 #define AR_PHY_EXT_CCA_THRESH62_S 16
150 #define AR_PHY_EXT_MINCCA_PWR 0x01FF0000
151 #define AR_PHY_EXT_MINCCA_PWR_S 16
152 #define AR_PHY_EXT_CYCPWR_THR1 0x0000FE00L
153 #define AR_PHY_EXT_CYCPWR_THR1_S 9
154 #define AR_PHY_TIMING5_CYCPWR_THR1 0x000000FE
155 #define AR_PHY_TIMING5_CYCPWR_THR1_S 1
156 #define AR_PHY_TIMING5_CYCPWR_THR1_ENABLE 0x00000001
157 #define AR_PHY_TIMING5_CYCPWR_THR1_ENABLE_S 0
158 #define AR_PHY_TIMING5_CYCPWR_THR1A 0x007F0000
159 #define AR_PHY_TIMING5_CYCPWR_THR1A_S 16
160 #define AR_PHY_TIMING5_RSSI_THR1A (0x7F << 16)
161 #define AR_PHY_TIMING5_RSSI_THR1A_S 16
162 #define AR_PHY_TIMING5_RSSI_THR1A_ENA (0x1 << 15)
163 #define AR_PHY_RADAR_0_ENA 0x00000001
164 #define AR_PHY_RADAR_0_FFT_ENA 0x80000000
165 #define AR_PHY_RADAR_0_INBAND 0x0000003e
166 #define AR_PHY_RADAR_0_INBAND_S 1
167 #define AR_PHY_RADAR_0_PRSSI 0x00000FC0
168 #define AR_PHY_RADAR_0_PRSSI_S 6
169 #define AR_PHY_RADAR_0_HEIGHT 0x0003F000
170 #define AR_PHY_RADAR_0_HEIGHT_S 12
171 #define AR_PHY_RADAR_0_RRSSI 0x00FC0000
172 #define AR_PHY_RADAR_0_RRSSI_S 18
173 #define AR_PHY_RADAR_0_FIRPWR 0x7F000000
174 #define AR_PHY_RADAR_0_FIRPWR_S 24
175 #define AR_PHY_RADAR_1_RELPWR_ENA 0x00800000
176 #define AR_PHY_RADAR_1_USE_FIR128 0x00400000
177 #define AR_PHY_RADAR_1_RELPWR_THRESH 0x003F0000
178 #define AR_PHY_RADAR_1_RELPWR_THRESH_S 16
179 #define AR_PHY_RADAR_1_BLOCK_CHECK 0x00008000
180 #define AR_PHY_RADAR_1_MAX_RRSSI 0x00004000
181 #define AR_PHY_RADAR_1_RELSTEP_CHECK 0x00002000
182 #define AR_PHY_RADAR_1_RELSTEP_THRESH 0x00001F00
183 #define AR_PHY_RADAR_1_RELSTEP_THRESH_S 8
184 #define AR_PHY_RADAR_1_MAXLEN 0x000000FF
185 #define AR_PHY_RADAR_1_MAXLEN_S 0
186 #define AR_PHY_RADAR_EXT_ENA 0x00004000
187 #define AR_PHY_RADAR_DC_PWR_THRESH 0x007f8000
188 #define AR_PHY_RADAR_DC_PWR_THRESH_S 15
189 #define AR_PHY_RADAR_LB_DC_CAP 0x7f800000
190 #define AR_PHY_RADAR_LB_DC_CAP_S 23
191 #define AR_PHY_FIND_SIG_LOW_FIRSTEP_LOW (0x3f << 6)
192 #define AR_PHY_FIND_SIG_LOW_FIRSTEP_LOW_S 6
193 #define AR_PHY_FIND_SIG_LOW_FIRPWR (0x7f << 12)
194 #define AR_PHY_FIND_SIG_LOW_FIRPWR_S 12
195 #define AR_PHY_FIND_SIG_LOW_FIRPWR_SIGN_BIT 19
196 #define AR_PHY_FIND_SIG_LOW_RELSTEP 0x1f
197 #define AR_PHY_FIND_SIG_LOW_RELSTEP_S 0
198 #define AR_PHY_FIND_SIG_LOW_RELSTEP_SIGN_BIT 5
199 #define AR_PHY_CHAN_INFO_TAB_S2_READ 0x00000008
200 #define AR_PHY_CHAN_INFO_TAB_S2_READ_S 3
201 #define AR_PHY_RX_IQCAL_CORR_IQCORR_Q_Q_COFF 0x0000007F
202 #define AR_PHY_RX_IQCAL_CORR_IQCORR_Q_Q_COFF_S 0
203 #define AR_PHY_RX_IQCAL_CORR_IQCORR_Q_I_COFF 0x00003F80
204 #define AR_PHY_RX_IQCAL_CORR_IQCORR_Q_I_COFF_S 7
205 #define AR_PHY_RX_IQCAL_CORR_IQCORR_ENABLE 0x00004000
206 #define AR_PHY_RX_IQCAL_CORR_LOOPBACK_IQCORR_Q_Q_COFF 0x003f8000
207 #define AR_PHY_RX_IQCAL_CORR_LOOPBACK_IQCORR_Q_Q_COFF_S 15
208 #define AR_PHY_RX_IQCAL_CORR_LOOPBACK_IQCORR_Q_I_COFF 0x1fc00000
209 #define AR_PHY_RX_IQCAL_CORR_LOOPBACK_IQCORR_Q_I_COFF_S 22
210 
211 /*
212  * MRC Register Map
213  */
214 #define AR_MRC_BASE 0x9c00
215 
216 #define AR_PHY_TIMING_3A (AR_MRC_BASE + 0x0)
217 #define AR_PHY_LDPC_CNTL1 (AR_MRC_BASE + 0x4)
218 #define AR_PHY_LDPC_CNTL2 (AR_MRC_BASE + 0x8)
219 #define AR_PHY_PILOT_SPUR_MASK (AR_MRC_BASE + 0xc)
220 #define AR_PHY_CHAN_SPUR_MASK (AR_MRC_BASE + 0x10)
221 #define AR_PHY_SGI_DELTA (AR_MRC_BASE + 0x14)
222 #define AR_PHY_ML_CNTL_1 (AR_MRC_BASE + 0x18)
223 #define AR_PHY_ML_CNTL_2 (AR_MRC_BASE + 0x1c)
224 #define AR_PHY_TST_ADC (AR_MRC_BASE + 0x20)
225 
226 #define AR_PHY_PILOT_SPUR_MASK_CF_PILOT_MASK_IDX_A 0x00000FE0
227 #define AR_PHY_PILOT_SPUR_MASK_CF_PILOT_MASK_IDX_A_S 5
228 #define AR_PHY_PILOT_SPUR_MASK_CF_PILOT_MASK_A 0x1F
229 #define AR_PHY_PILOT_SPUR_MASK_CF_PILOT_MASK_A_S 0
230 
231 #define AR_PHY_CHAN_SPUR_MASK_CF_CHAN_MASK_IDX_A 0x00000FE0
232 #define AR_PHY_CHAN_SPUR_MASK_CF_CHAN_MASK_IDX_A_S 5
233 #define AR_PHY_CHAN_SPUR_MASK_CF_CHAN_MASK_A 0x1F
234 #define AR_PHY_CHAN_SPUR_MASK_CF_CHAN_MASK_A_S 0
235 
236 /*
237  * MRC Feild Definitions
238  */
239 #define AR_PHY_SGI_DSC_MAN 0x0007FFF0
240 #define AR_PHY_SGI_DSC_MAN_S 4
241 #define AR_PHY_SGI_DSC_EXP 0x0000000F
242 #define AR_PHY_SGI_DSC_EXP_S 0
243 /*
244  * BBB Register Map
245  */
246 #define AR_BBB_BASE 0x9d00
247 
248 /*
249  * AGC Register Map
250  */
251 #define AR_AGC_BASE 0x9e00
252 
253 #define AR_PHY_SETTLING (AR_AGC_BASE + 0x0)
254 #define AR_PHY_FORCEMAX_GAINS_0 (AR_AGC_BASE + 0x4)
255 #define AR_PHY_GAINS_MINOFF0 (AR_AGC_BASE + 0x8)
256 #define AR_PHY_DESIRED_SZ (AR_AGC_BASE + 0xc)
257 #define AR_PHY_FIND_SIG (AR_AGC_BASE + 0x10)
258 #define AR_PHY_AGC (AR_AGC_BASE + 0x14)
259 #define AR_PHY_EXT_ATTEN_CTL_0 (AR_AGC_BASE + 0x18)
260 #define AR_PHY_CCA_0 (AR_AGC_BASE + 0x1c)
261 #define AR_PHY_EXT_CCA0 (AR_AGC_BASE + 0x20)
262 #define AR_PHY_RESTART (AR_AGC_BASE + 0x24)
263 
264 /*
265  * Antenna Diversity settings
266  */
267 #define AR_PHY_MC_GAIN_CTRL (AR_AGC_BASE + 0x28)
268 #define AR_ANT_DIV_CTRL_ALL 0x7e000000
269 #define AR_ANT_DIV_CTRL_ALL_S 25
270 #define AR_ANT_DIV_ENABLE 0x1000000
271 #define AR_ANT_DIV_ENABLE_S 24
272 
273 
274 #define AR_PHY_9485_ANT_FAST_DIV_BIAS 0x00007e00
275 #define AR_PHY_9485_ANT_FAST_DIV_BIAS_S 9
276 #define AR_PHY_9485_ANT_DIV_LNADIV 0x01000000
277 #define AR_PHY_9485_ANT_DIV_LNADIV_S 24
278 #define AR_PHY_9485_ANT_DIV_ALT_LNACONF 0x06000000
279 #define AR_PHY_9485_ANT_DIV_ALT_LNACONF_S 25
280 #define AR_PHY_9485_ANT_DIV_MAIN_LNACONF 0x18000000
281 #define AR_PHY_9485_ANT_DIV_MAIN_LNACONF_S 27
282 #define AR_PHY_9485_ANT_DIV_ALT_GAINTB 0x20000000
283 #define AR_PHY_9485_ANT_DIV_ALT_GAINTB_S 29
284 #define AR_PHY_9485_ANT_DIV_MAIN_GAINTB 0x40000000
285 #define AR_PHY_9485_ANT_DIV_MAIN_GAINTB_S 30
286 
287 #define AR_PHY_9485_ANT_DIV_LNA1_MINUS_LNA2 0x0
288 #define AR_PHY_9485_ANT_DIV_LNA2 0x1
289 #define AR_PHY_9485_ANT_DIV_LNA1 0x2
290 #define AR_PHY_9485_ANT_DIV_LNA1_PLUS_LNA2 0x3
291 
292 #define AR_PHY_EXTCHN_PWRTHR1 (AR_AGC_BASE + 0x2c)
293 #define AR_PHY_EXT_CHN_WIN (AR_AGC_BASE + 0x30)
294 #define AR_PHY_20_40_DET_THR (AR_AGC_BASE + 0x34)
295 #define AR_PHY_RIFS_SRCH (AR_AGC_BASE + 0x38)
296 #define AR_PHY_PEAK_DET_CTRL_1 (AR_AGC_BASE + 0x3c)
297 #define AR_PHY_PEAK_DET_CTRL_2 (AR_AGC_BASE + 0x40)
298 #define AR_PHY_RX_GAIN_BOUNDS_1 (AR_AGC_BASE + 0x44)
299 #define AR_PHY_RX_GAIN_BOUNDS_2 (AR_AGC_BASE + 0x48)
300 #define AR_PHY_RSSI_0 (AR_AGC_BASE + 0x180)
301 #define AR_PHY_SPUR_CCK_REP0 (AR_AGC_BASE + 0x184)
302 
303 #define AR_PHY_CCK_DETECT (AR_AGC_BASE + 0x1c0)
304 #define AR_FAST_DIV_ENABLE 0x2000
305 #define AR_FAST_DIV_ENABLE_S 13
306 
307 #define AR_PHY_DAG_CTRLCCK (AR_AGC_BASE + 0x1c4)
308 #define AR_PHY_IQCORR_CTRL_CCK (AR_AGC_BASE + 0x1c8)
309 
310 #define AR_PHY_CCK_SPUR_MIT (AR_AGC_BASE + 0x1cc)
311 #define AR_PHY_CCK_SPUR_MIT_SPUR_RSSI_THR 0x000001fe
312 #define AR_PHY_CCK_SPUR_MIT_SPUR_RSSI_THR_S 1
313 #define AR_PHY_CCK_SPUR_MIT_SPUR_FILTER_TYPE 0x60000000
314 #define AR_PHY_CCK_SPUR_MIT_SPUR_FILTER_TYPE_S 29
315 #define AR_PHY_CCK_SPUR_MIT_USE_CCK_SPUR_MIT 0x00000001
316 #define AR_PHY_CCK_SPUR_MIT_USE_CCK_SPUR_MIT_S 0
317 #define AR_PHY_CCK_SPUR_MIT_CCK_SPUR_FREQ 0x1ffffe00
318 #define AR_PHY_CCK_SPUR_MIT_CCK_SPUR_FREQ_S 9
319 
320 #define AR_PHY_MRC_CCK_CTRL (AR_AGC_BASE + 0x1d0)
321 #define AR_PHY_MRC_CCK_ENABLE 0x00000001
322 #define AR_PHY_MRC_CCK_ENABLE_S 0
323 #define AR_PHY_MRC_CCK_MUX_REG 0x00000002
324 #define AR_PHY_MRC_CCK_MUX_REG_S 1
325 
326 #define AR_PHY_RX_OCGAIN (AR_AGC_BASE + 0x200)
327 
328 #define AR_PHY_CCA_NOM_VAL_9300_2GHZ -110
329 #define AR_PHY_CCA_NOM_VAL_9300_5GHZ -115
330 #define AR_PHY_CCA_MIN_GOOD_VAL_9300_2GHZ -125
331 #define AR_PHY_CCA_MIN_GOOD_VAL_9300_5GHZ -125
332 #define AR_PHY_CCA_MAX_GOOD_VAL_9300_2GHZ -95
333 #define AR_PHY_CCA_MAX_GOOD_VAL_9300_5GHZ -100
334 
335 /*
336  * AGC Field Definitions
337  */
338 #define AR_PHY_EXT_ATTEN_CTL_RXTX_MARGIN 0x00FC0000
339 #define AR_PHY_EXT_ATTEN_CTL_RXTX_MARGIN_S 18
340 #define AR_PHY_EXT_ATTEN_CTL_BSW_MARGIN 0x00003C00
341 #define AR_PHY_EXT_ATTEN_CTL_BSW_MARGIN_S 10
342 #define AR_PHY_EXT_ATTEN_CTL_BSW_ATTEN 0x0000001F
343 #define AR_PHY_EXT_ATTEN_CTL_BSW_ATTEN_S 0
344 #define AR_PHY_EXT_ATTEN_CTL_XATTEN2_MARGIN 0x003E0000
345 #define AR_PHY_EXT_ATTEN_CTL_XATTEN2_MARGIN_S 17
346 #define AR_PHY_EXT_ATTEN_CTL_XATTEN1_MARGIN 0x0001F000
347 #define AR_PHY_EXT_ATTEN_CTL_XATTEN1_MARGIN_S 12
348 #define AR_PHY_EXT_ATTEN_CTL_XATTEN2_DB 0x00000FC0
349 #define AR_PHY_EXT_ATTEN_CTL_XATTEN2_DB_S 6
350 #define AR_PHY_EXT_ATTEN_CTL_XATTEN1_DB 0x0000003F
351 #define AR_PHY_EXT_ATTEN_CTL_XATTEN1_DB_S 0
352 #define AR_PHY_RXGAIN_TXRX_ATTEN 0x0003F000
353 #define AR_PHY_RXGAIN_TXRX_ATTEN_S 12
354 #define AR_PHY_RXGAIN_TXRX_RF_MAX 0x007C0000
355 #define AR_PHY_RXGAIN_TXRX_RF_MAX_S 18
356 #define AR9280_PHY_RXGAIN_TXRX_ATTEN 0x00003F80
357 #define AR9280_PHY_RXGAIN_TXRX_ATTEN_S 7
358 #define AR9280_PHY_RXGAIN_TXRX_MARGIN 0x001FC000
359 #define AR9280_PHY_RXGAIN_TXRX_MARGIN_S 14
360 #define AR_PHY_SETTLING_SWITCH 0x00003F80
361 #define AR_PHY_SETTLING_SWITCH_S 7
362 #define AR_PHY_DESIRED_SZ_ADC 0x000000FF
363 #define AR_PHY_DESIRED_SZ_ADC_S 0
364 #define AR_PHY_DESIRED_SZ_PGA 0x0000FF00
365 #define AR_PHY_DESIRED_SZ_PGA_S 8
366 #define AR_PHY_DESIRED_SZ_TOT_DES 0x0FF00000
367 #define AR_PHY_DESIRED_SZ_TOT_DES_S 20
368 #define AR_PHY_MINCCA_PWR 0x1FF00000
369 #define AR_PHY_MINCCA_PWR_S 20
370 #define AR_PHY_CCA_THRESH62 0x0007F000
371 #define AR_PHY_CCA_THRESH62_S 12
372 #define AR9280_PHY_MINCCA_PWR 0x1FF00000
373 #define AR9280_PHY_MINCCA_PWR_S 20
374 #define AR9280_PHY_CCA_THRESH62 0x000FF000
375 #define AR9280_PHY_CCA_THRESH62_S 12
376 #define AR_PHY_EXT_CCA0_THRESH62 0x000000FF
377 #define AR_PHY_EXT_CCA0_THRESH62_S 0
378 #define AR_PHY_CCK_DETECT_WEAK_SIG_THR_CCK 0x0000003F
379 #define AR_PHY_CCK_DETECT_WEAK_SIG_THR_CCK_S 0
380 #define AR_PHY_CCK_DETECT_ANT_SWITCH_TIME 0x00001FC0
381 #define AR_PHY_CCK_DETECT_ANT_SWITCH_TIME_S 6
382 #define AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV 0x2000
383 
384 #define AR_PHY_DAG_CTRLCCK_EN_RSSI_THR 0x00000200
385 #define AR_PHY_DAG_CTRLCCK_EN_RSSI_THR_S 9
386 #define AR_PHY_DAG_CTRLCCK_RSSI_THR 0x0001FC00
387 #define AR_PHY_DAG_CTRLCCK_RSSI_THR_S 10
388 
389 #define AR_PHY_RIFS_INIT_DELAY 0x3ff0000
390 #define AR_PHY_AGC_COARSE_LOW 0x00007F80
391 #define AR_PHY_AGC_COARSE_LOW_S 7
392 #define AR_PHY_AGC_COARSE_HIGH 0x003F8000
393 #define AR_PHY_AGC_COARSE_HIGH_S 15
394 #define AR_PHY_AGC_COARSE_PWR_CONST 0x0000007F
395 #define AR_PHY_AGC_COARSE_PWR_CONST_S 0
396 #define AR_PHY_FIND_SIG_FIRSTEP 0x0003F000
397 #define AR_PHY_FIND_SIG_FIRSTEP_S 12
398 #define AR_PHY_FIND_SIG_FIRPWR 0x03FC0000
399 #define AR_PHY_FIND_SIG_FIRPWR_S 18
400 #define AR_PHY_FIND_SIG_FIRPWR_SIGN_BIT 25
401 #define AR_PHY_FIND_SIG_RELPWR (0x1f << 6)
402 #define AR_PHY_FIND_SIG_RELPWR_S 6
403 #define AR_PHY_FIND_SIG_RELPWR_SIGN_BIT 11
404 #define AR_PHY_FIND_SIG_RELSTEP 0x1f
405 #define AR_PHY_FIND_SIG_RELSTEP_S 0
406 #define AR_PHY_FIND_SIG_RELSTEP_SIGN_BIT 5
407 #define AR_PHY_RESTART_DIV_GC 0x001C0000
408 #define AR_PHY_RESTART_DIV_GC_S 18
409 #define AR_PHY_RESTART_ENA 0x01
410 #define AR_PHY_DC_RESTART_DIS 0x40000000
411 
412 #define AR_PHY_TPC_OLPC_GAIN_DELTA_PAL_ON 0xFF000000
413 #define AR_PHY_TPC_OLPC_GAIN_DELTA_PAL_ON_S 24
414 #define AR_PHY_TPC_OLPC_GAIN_DELTA 0x00FF0000
415 #define AR_PHY_TPC_OLPC_GAIN_DELTA_S 16
416 
417 #define AR_PHY_TPC_6_ERROR_EST_MODE 0x03000000
418 #define AR_PHY_TPC_6_ERROR_EST_MODE_S 24
419 
420 /*
421  * SM Register Map
422  */
423 #define AR_SM_BASE 0xa200
424 
425 #define AR_PHY_D2_CHIP_ID (AR_SM_BASE + 0x0)
426 #define AR_PHY_GEN_CTRL (AR_SM_BASE + 0x4)
427 #define AR_PHY_MODE (AR_SM_BASE + 0x8)
428 #define AR_PHY_ACTIVE (AR_SM_BASE + 0xc)
429 #define AR_PHY_SPUR_MASK_A (AR_SM_BASE + 0x20)
430 #define AR_PHY_SPUR_MASK_B (AR_SM_BASE + 0x24)
431 #define AR_PHY_SPECTRAL_SCAN (AR_SM_BASE + 0x28)
432 #define AR_PHY_RADAR_BW_FILTER (AR_SM_BASE + 0x2c)
433 #define AR_PHY_SEARCH_START_DELAY (AR_SM_BASE + 0x30)
434 #define AR_PHY_MAX_RX_LEN (AR_SM_BASE + 0x34)
435 #define AR_PHY_FRAME_CTL (AR_SM_BASE + 0x38)
436 #define AR_PHY_RFBUS_REQ (AR_SM_BASE + 0x3c)
437 #define AR_PHY_RFBUS_GRANT (AR_SM_BASE + 0x40)
438 #define AR_PHY_RIFS (AR_SM_BASE + 0x44)
439 #define AR_PHY_RX_CLR_DELAY (AR_SM_BASE + 0x50)
440 #define AR_PHY_RX_DELAY (AR_SM_BASE + 0x54)
441 
442 #define AR_PHY_XPA_TIMING_CTL (AR_SM_BASE + 0x64)
443 #define AR_PHY_MISC_PA_CTL (AR_SM_BASE + 0x80)
444 #define AR_PHY_SWITCH_CHAIN_0 (AR_SM_BASE + 0x84)
445 #define AR_PHY_SWITCH_COM (AR_SM_BASE + 0x88)
446 #define AR_PHY_SWITCH_COM_2 (AR_SM_BASE + 0x8c)
447 #define AR_PHY_RX_CHAINMASK (AR_SM_BASE + 0xa0)
448 #define AR_PHY_CAL_CHAINMASK (AR_SM_BASE + 0xc0)
449 #define AR_PHY_CALMODE (AR_SM_BASE + 0xc8)
450 #define AR_PHY_FCAL_1 (AR_SM_BASE + 0xcc)
451 #define AR_PHY_FCAL_2_0 (AR_SM_BASE + 0xd0)
452 #define AR_PHY_DFT_TONE_CTL_0 (AR_SM_BASE + 0xd4)
453 #define AR_PHY_CL_CAL_CTL (AR_SM_BASE + 0xd8)
454 #define AR_PHY_CL_TAB_0 (AR_SM_BASE + 0x100)
455 #define AR_PHY_SYNTH_CONTROL (AR_SM_BASE + 0x140)
456 #define AR_PHY_ADDAC_CLK_SEL (AR_SM_BASE + 0x144)
457 #define AR_PHY_PLL_CTL (AR_SM_BASE + 0x148)
458 #define AR_PHY_ANALOG_SWAP (AR_SM_BASE + 0x14c)
459 #define AR_PHY_ADDAC_PARA_CTL (AR_SM_BASE + 0x150)
460 #define AR_PHY_XPA_CFG (AR_SM_BASE + 0x158)
461 
462 #define AR_PHY_SPUR_MASK_A_CF_PUNC_MASK_IDX_A 0x0001FC00
463 #define AR_PHY_SPUR_MASK_A_CF_PUNC_MASK_IDX_A_S 10
464 #define AR_PHY_SPUR_MASK_A_CF_PUNC_MASK_A 0x3FF
465 #define AR_PHY_SPUR_MASK_A_CF_PUNC_MASK_A_S 0
466 
467 #define AR_PHY_TEST (AR_SM_BASE + 0x160)
468 
469 #define AR_PHY_TEST_BBB_OBS_SEL 0x780000
470 #define AR_PHY_TEST_BBB_OBS_SEL_S 19
471 
472 #define AR_PHY_TEST_RX_OBS_SEL_BIT5_S 23
473 #define AR_PHY_TEST_RX_OBS_SEL_BIT5 (1 << AR_PHY_TEST_RX_OBS_SEL_BIT5_S)
474 
475 #define AR_PHY_TEST_CHAIN_SEL 0xC0000000
476 #define AR_PHY_TEST_CHAIN_SEL_S 30
477 
478 #define AR_PHY_TEST_CTL_STATUS (AR_SM_BASE + 0x164)
479 #define AR_PHY_TEST_CTL_TSTDAC_EN 0x1
480 #define AR_PHY_TEST_CTL_TSTDAC_EN_S 0
481 #define AR_PHY_TEST_CTL_TX_OBS_SEL 0x1C
482 #define AR_PHY_TEST_CTL_TX_OBS_SEL_S 2
483 #define AR_PHY_TEST_CTL_TX_OBS_MUX_SEL 0x60
484 #define AR_PHY_TEST_CTL_TX_OBS_MUX_SEL_S 5
485 #define AR_PHY_TEST_CTL_TSTADC_EN 0x100
486 #define AR_PHY_TEST_CTL_TSTADC_EN_S 8
487 #define AR_PHY_TEST_CTL_RX_OBS_SEL 0x3C00
488 #define AR_PHY_TEST_CTL_RX_OBS_SEL_S 10
489 
490 
491 #define AR_PHY_TSTDAC (AR_SM_BASE + 0x168)
492 
493 #define AR_PHY_CHAN_STATUS (AR_SM_BASE + 0x16c)
494 
495 #define AR_PHY_CHAN_INFO_MEMORY (AR_SM_BASE + 0x170)
496 #define AR_PHY_CHAN_INFO_MEMORY_CHANINFOMEM_S2_READ 0x00000008
497 #define AR_PHY_CHAN_INFO_MEMORY_CHANINFOMEM_S2_READ_S 3
498 
499 #define AR_PHY_CHNINFO_NOISEPWR (AR_SM_BASE + 0x174)
500 #define AR_PHY_CHNINFO_GAINDIFF (AR_SM_BASE + 0x178)
501 #define AR_PHY_CHNINFO_FINETIM (AR_SM_BASE + 0x17c)
502 #define AR_PHY_CHAN_INFO_GAIN_0 (AR_SM_BASE + 0x180)
503 #define AR_PHY_SCRAMBLER_SEED (AR_SM_BASE + 0x190)
504 #define AR_PHY_CCK_TX_CTRL (AR_SM_BASE + 0x194)
505 
506 #define AR_PHY_HEAVYCLIP_CTL (AR_SM_BASE + 0x1a4)
507 #define AR_PHY_HEAVYCLIP_20 (AR_SM_BASE + 0x1a8)
508 #define AR_PHY_HEAVYCLIP_40 (AR_SM_BASE + 0x1ac)
509 #define AR_PHY_ILLEGAL_TXRATE (AR_SM_BASE + 0x1b0)
510 
511 #define AR_PHY_POWER_TX_RATE(_d) (AR_SM_BASE + 0x1c0 + ((_d) << 2))
512 
513 #define AR_PHY_PWRTX_MAX (AR_SM_BASE + 0x1f0)
514 #define AR_PHY_POWER_TX_SUB (AR_SM_BASE + 0x1f4)
515 
516 #define AR_PHY_TPC_1 (AR_SM_BASE + 0x1f8)
517 #define AR_PHY_TPC_1_FORCED_DAC_GAIN 0x0000003e
518 #define AR_PHY_TPC_1_FORCED_DAC_GAIN_S 1
519 #define AR_PHY_TPC_1_FORCE_DAC_GAIN 0x00000001
520 #define AR_PHY_TPC_1_FORCE_DAC_GAIN_S 0
521 
522 #define AR_PHY_TPC_4_B0 (AR_SM_BASE + 0x204)
523 #define AR_PHY_TPC_5_B0 (AR_SM_BASE + 0x208)
524 #define AR_PHY_TPC_6_B0 (AR_SM_BASE + 0x20c)
525 
526 #define AR_PHY_TPC_11_B0 (AR_SM_BASE + 0x220)
527 #define AR_PHY_TPC_11_B1 (AR_SM1_BASE + 0x220)
528 #define AR_PHY_TPC_11_B2 (AR_SM2_BASE + 0x220)
529 #define AR_PHY_TPC_11_OLPC_GAIN_DELTA 0x00ff0000
530 #define AR_PHY_TPC_11_OLPC_GAIN_DELTA_S 16
531 
532 #define AR_PHY_TPC_12 (AR_SM_BASE + 0x224)
533 #define AR_PHY_TPC_12_DESIRED_SCALE_HT40_5 0x3e000000
534 #define AR_PHY_TPC_12_DESIRED_SCALE_HT40_5_S 25
535 
536 #define AR_PHY_TPC_18 (AR_SM_BASE + 0x23c)
537 #define AR_PHY_TPC_18_THERM_CAL_VALUE 0x000000ff
538 #define AR_PHY_TPC_18_THERM_CAL_VALUE_S 0
539 #define AR_PHY_TPC_18_VOLT_CAL_VALUE 0x0000ff00
540 #define AR_PHY_TPC_18_VOLT_CAL_VALUE_S 8
541 
542 #define AR_PHY_TPC_19 (AR_SM_BASE + 0x240)
543 #define AR_PHY_TPC_19_ALPHA_VOLT 0x001f0000
544 #define AR_PHY_TPC_19_ALPHA_VOLT_S 16
545 #define AR_PHY_TPC_19_ALPHA_THERM 0xff
546 #define AR_PHY_TPC_19_ALPHA_THERM_S 0
547 
548 #define AR_PHY_TX_FORCED_GAIN (AR_SM_BASE + 0x258)
549 #define AR_PHY_TX_FORCED_GAIN_FORCE_TX_GAIN 0x00000001
550 #define AR_PHY_TX_FORCED_GAIN_FORCE_TX_GAIN_S 0
551 #define AR_PHY_TX_FORCED_GAIN_FORCED_TXBB1DBGAIN 0x0000000e
552 #define AR_PHY_TX_FORCED_GAIN_FORCED_TXBB1DBGAIN_S 1
553 #define AR_PHY_TX_FORCED_GAIN_FORCED_TXBB6DBGAIN 0x00000030
554 #define AR_PHY_TX_FORCED_GAIN_FORCED_TXBB6DBGAIN_S 4
555 #define AR_PHY_TX_FORCED_GAIN_FORCED_TXMXRGAIN 0x000003c0
556 #define AR_PHY_TX_FORCED_GAIN_FORCED_TXMXRGAIN_S 6
557 #define AR_PHY_TX_FORCED_GAIN_FORCED_PADRVGNA 0x00003c00
558 #define AR_PHY_TX_FORCED_GAIN_FORCED_PADRVGNA_S 10
559 #define AR_PHY_TX_FORCED_GAIN_FORCED_PADRVGNB 0x0003c000
560 #define AR_PHY_TX_FORCED_GAIN_FORCED_PADRVGNB_S 14
561 #define AR_PHY_TX_FORCED_GAIN_FORCED_PADRVGNC 0x003c0000
562 #define AR_PHY_TX_FORCED_GAIN_FORCED_PADRVGNC_S 18
563 #define AR_PHY_TX_FORCED_GAIN_FORCED_PADRVGND 0x00c00000
564 #define AR_PHY_TX_FORCED_GAIN_FORCED_PADRVGND_S 22
565 #define AR_PHY_TX_FORCED_GAIN_FORCED_ENABLE_PAL 0x01000000
566 #define AR_PHY_TX_FORCED_GAIN_FORCED_ENABLE_PAL_S 24
567 
568 
569 #define AR_PHY_PDADC_TAB_0 (AR_SM_BASE + 0x280)
570 
571 #define AR_PHY_TXGAIN_TABLE (AR_SM_BASE + 0x300)
572 
573 #define AR_PHY_TX_IQCAL_CONTROL_1 (AR_SM_BASE + AR_SREV_9485(ah) ? \
574  0x3c8 : 0x448)
575 #define AR_PHY_TX_IQCAL_START (AR_SM_BASE + AR_SREV_9485(ah) ? \
576  0x3c4 : 0x440)
577 #define AR_PHY_TX_IQCAL_STATUS_B0 (AR_SM_BASE + AR_SREV_9485(ah) ? \
578  0x3f0 : 0x48c)
579 #define AR_PHY_TX_IQCAL_CORR_COEFF_B0(_i) (AR_SM_BASE + \
580  (AR_SREV_9485(ah) ? \
581  0x3d0 : 0x450) + ((_i) << 2))
582 
583 #define AR_PHY_WATCHDOG_STATUS (AR_SM_BASE + 0x5c0)
584 #define AR_PHY_WATCHDOG_CTL_1 (AR_SM_BASE + 0x5c4)
585 #define AR_PHY_WATCHDOG_CTL_2 (AR_SM_BASE + 0x5c8)
586 #define AR_PHY_WATCHDOG_CTL (AR_SM_BASE + 0x5cc)
587 #define AR_PHY_ONLY_WARMRESET (AR_SM_BASE + 0x5d0)
588 #define AR_PHY_ONLY_CTL (AR_SM_BASE + 0x5d4)
589 #define AR_PHY_ECO_CTRL (AR_SM_BASE + 0x5dc)
590 
591 #define AR_PHY_BB_THERM_ADC_1 (AR_SM_BASE + 0x248)
592 #define AR_PHY_BB_THERM_ADC_1_INIT_THERM 0x000000ff
593 #define AR_PHY_BB_THERM_ADC_1_INIT_THERM_S 0
594 
595 #define AR_PHY_BB_THERM_ADC_4 (AR_SM_BASE + 0x254)
596 #define AR_PHY_BB_THERM_ADC_4_LATEST_THERM_VALUE 0x000000ff
597 #define AR_PHY_BB_THERM_ADC_4_LATEST_THERM_VALUE_S 0
598 #define AR_PHY_BB_THERM_ADC_4_LATEST_VOLT_VALUE 0x0000ff00
599 #define AR_PHY_BB_THERM_ADC_4_LATEST_VOLT_VALUE_S 8
600 
601 
602 #define AR_PHY_65NM_CH0_SYNTH4 0x1608c
603 #define AR_PHY_SYNTH4_LONG_SHIFT_SELECT 0x00000002
604 #define AR_PHY_SYNTH4_LONG_SHIFT_SELECT_S 1
605 #define AR_PHY_65NM_CH0_SYNTH7 0x16098
606 #define AR_PHY_65NM_CH0_BIAS1 0x160c0
607 #define AR_PHY_65NM_CH0_BIAS2 0x160c4
608 #define AR_PHY_65NM_CH0_BIAS4 0x160cc
609 #define AR_PHY_65NM_CH0_RXTX4 0x1610c
610 #define AR_PHY_65NM_CH0_THERM (AR_SREV_9300(ah) ? 0x16290 : 0x1628c)
611 
612 #define AR_PHY_65NM_CH0_THERM_LOCAL 0x80000000
613 #define AR_PHY_65NM_CH0_THERM_LOCAL_S 31
614 #define AR_PHY_65NM_CH0_THERM_START 0x20000000
615 #define AR_PHY_65NM_CH0_THERM_START_S 29
616 #define AR_PHY_65NM_CH0_THERM_SAR_ADC_OUT 0x0000ff00
617 #define AR_PHY_65NM_CH0_THERM_SAR_ADC_OUT_S 8
618 
619 #define AR_PHY_65NM_CH0_RXTX1 0x16100
620 #define AR_PHY_65NM_CH0_RXTX2 0x16104
621 #define AR_PHY_65NM_CH1_RXTX1 0x16500
622 #define AR_PHY_65NM_CH1_RXTX2 0x16504
623 #define AR_PHY_65NM_CH2_RXTX1 0x16900
624 #define AR_PHY_65NM_CH2_RXTX2 0x16904
625 
626 #define AR_CH0_TOP2 (AR_SREV_9485(ah) ? 0x00016284 : 0x0001628c)
627 #define AR_CH0_TOP2_XPABIASLVL 0xf000
628 #define AR_CH0_TOP2_XPABIASLVL_S 12
629 
630 #define AR_CH0_XTAL (AR_SREV_9485(ah) ? 0x16290 : 0x16294)
631 #define AR_CH0_XTAL_CAPINDAC 0x7f000000
632 #define AR_CH0_XTAL_CAPINDAC_S 24
633 #define AR_CH0_XTAL_CAPOUTDAC 0x00fe0000
634 #define AR_CH0_XTAL_CAPOUTDAC_S 17
635 
636 #define AR_PHY_PMU1 0x16c40
637 #define AR_PHY_PMU1_PWD 0x1
638 #define AR_PHY_PMU1_PWD_S 0
639 
640 #define AR_PHY_PMU2 0x16c44
641 #define AR_PHY_PMU2_PGM 0x00200000
642 #define AR_PHY_PMU2_PGM_S 21
643 
644 #define AR_PHY_RX1DB_BIQUAD_LONG_SHIFT 0x00380000
645 #define AR_PHY_RX1DB_BIQUAD_LONG_SHIFT_S 19
646 #define AR_PHY_RX6DB_BIQUAD_LONG_SHIFT 0x00c00000
647 #define AR_PHY_RX6DB_BIQUAD_LONG_SHIFT_S 22
648 #define AR_PHY_LNAGAIN_LONG_SHIFT 0xe0000000
649 #define AR_PHY_LNAGAIN_LONG_SHIFT_S 29
650 #define AR_PHY_MXRGAIN_LONG_SHIFT 0x03000000
651 #define AR_PHY_MXRGAIN_LONG_SHIFT_S 24
652 #define AR_PHY_VGAGAIN_LONG_SHIFT 0x1c000000
653 #define AR_PHY_VGAGAIN_LONG_SHIFT_S 26
654 #define AR_PHY_SCFIR_GAIN_LONG_SHIFT 0x00000001
655 #define AR_PHY_SCFIR_GAIN_LONG_SHIFT_S 0
656 #define AR_PHY_MANRXGAIN_LONG_SHIFT 0x00000002
657 #define AR_PHY_MANRXGAIN_LONG_SHIFT_S 1
658 
659 /*
660  * SM Field Definitions
661  */
662 #define AR_PHY_CL_CAL_ENABLE 0x00000002
663 #define AR_PHY_PARALLEL_CAL_ENABLE 0x00000001
664 #define AR_PHY_TPCRG1_PD_CAL_ENABLE 0x00400000
665 #define AR_PHY_TPCRG1_PD_CAL_ENABLE_S 22
666 
667 #define AR_PHY_ADDAC_PARACTL_OFF_PWDADC 0x00008000
668 
669 #define AR_PHY_FCAL20_CAP_STATUS_0 0x01f00000
670 #define AR_PHY_FCAL20_CAP_STATUS_0_S 20
671 
672 #define AR_PHY_RFBUS_REQ_EN 0x00000001 /* request for RF bus */
673 #define AR_PHY_RFBUS_GRANT_EN 0x00000001 /* RF bus granted */
674 #define AR_PHY_GC_TURBO_MODE 0x00000001 /* set turbo mode bits */
675 #define AR_PHY_GC_TURBO_SHORT 0x00000002 /* set short symbols to turbo mode setting */
676 #define AR_PHY_GC_DYN2040_EN 0x00000004 /* enable dyn 20/40 mode */
677 #define AR_PHY_GC_DYN2040_PRI_ONLY 0x00000008 /* dyn 20/40 - primary only */
678 #define AR_PHY_GC_DYN2040_PRI_CH 0x00000010 /* dyn 20/40 - primary ch offset (0=+10MHz, 1=-10MHz)*/
679 #define AR_PHY_GC_DYN2040_PRI_CH_S 4
680 #define AR_PHY_GC_DYN2040_EXT_CH 0x00000020 /* dyn 20/40 - ext ch spacing (0=20MHz/ 1=25MHz) */
681 #define AR_PHY_GC_HT_EN 0x00000040 /* ht enable */
682 #define AR_PHY_GC_SHORT_GI_40 0x00000080 /* allow short GI for HT 40 */
683 #define AR_PHY_GC_WALSH 0x00000100 /* walsh spatial spreading for 2 chains,2 streams TX */
684 #define AR_PHY_GC_SINGLE_HT_LTF1 0x00000200 /* single length (4us) 1st HT long training symbol */
685 #define AR_PHY_GC_GF_DETECT_EN 0x00000400 /* enable Green Field detection. Only affects rx, not tx */
686 #define AR_PHY_GC_ENABLE_DAC_FIFO 0x00000800 /* fifo between bb and dac */
687 #define AR_PHY_RX_DELAY_DELAY 0x00003FFF /* delay from wakeup to rx ena */
688 
689 #define AR_PHY_CALMODE_IQ 0x00000000
690 #define AR_PHY_CALMODE_ADC_GAIN 0x00000001
691 #define AR_PHY_CALMODE_ADC_DC_PER 0x00000002
692 #define AR_PHY_CALMODE_ADC_DC_INIT 0x00000003
693 #define AR_PHY_SWAP_ALT_CHAIN 0x00000040
694 #define AR_PHY_MODE_OFDM 0x00000000
695 #define AR_PHY_MODE_CCK 0x00000001
696 #define AR_PHY_MODE_DYNAMIC 0x00000004
697 #define AR_PHY_MODE_DYNAMIC_S 2
698 #define AR_PHY_MODE_HALF 0x00000020
699 #define AR_PHY_MODE_QUARTER 0x00000040
700 #define AR_PHY_MAC_CLK_MODE 0x00000080
701 #define AR_PHY_MODE_DYN_CCK_DISABLE 0x00000100
702 #define AR_PHY_MODE_SVD_HALF 0x00000200
703 #define AR_PHY_ACTIVE_EN 0x00000001
704 #define AR_PHY_ACTIVE_DIS 0x00000000
705 #define AR_PHY_FORCE_XPA_CFG 0x000000001
706 #define AR_PHY_FORCE_XPA_CFG_S 0
707 #define AR_PHY_XPA_TIMING_CTL_TX_END_XPAB_OFF 0xFF000000
708 #define AR_PHY_XPA_TIMING_CTL_TX_END_XPAB_OFF_S 24
709 #define AR_PHY_XPA_TIMING_CTL_TX_END_XPAA_OFF 0x00FF0000
710 #define AR_PHY_XPA_TIMING_CTL_TX_END_XPAA_OFF_S 16
711 #define AR_PHY_XPA_TIMING_CTL_FRAME_XPAB_ON 0x0000FF00
712 #define AR_PHY_XPA_TIMING_CTL_FRAME_XPAB_ON_S 8
713 #define AR_PHY_XPA_TIMING_CTL_FRAME_XPAA_ON 0x000000FF
714 #define AR_PHY_XPA_TIMING_CTL_FRAME_XPAA_ON_S 0
715 #define AR_PHY_TX_END_TO_A2_RX_ON 0x00FF0000
716 #define AR_PHY_TX_END_TO_A2_RX_ON_S 16
717 #define AR_PHY_TX_END_DATA_START 0x000000FF
718 #define AR_PHY_TX_END_DATA_START_S 0
719 #define AR_PHY_TX_END_PA_ON 0x0000FF00
720 #define AR_PHY_TX_END_PA_ON_S 8
721 #define AR_PHY_TPCRG5_PD_GAIN_OVERLAP 0x0000000F
722 #define AR_PHY_TPCRG5_PD_GAIN_OVERLAP_S 0
723 #define AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_1 0x000003F0
724 #define AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_1_S 4
725 #define AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_2 0x0000FC00
726 #define AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_2_S 10
727 #define AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_3 0x003F0000
728 #define AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_3_S 16
729 #define AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_4 0x0FC00000
730 #define AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_4_S 22
731 #define AR_PHY_TPCRG1_NUM_PD_GAIN 0x0000c000
732 #define AR_PHY_TPCRG1_NUM_PD_GAIN_S 14
733 #define AR_PHY_TPCRG1_PD_GAIN_1 0x00030000
734 #define AR_PHY_TPCRG1_PD_GAIN_1_S 16
735 #define AR_PHY_TPCRG1_PD_GAIN_2 0x000C0000
736 #define AR_PHY_TPCRG1_PD_GAIN_2_S 18
737 #define AR_PHY_TPCRG1_PD_GAIN_3 0x00300000
738 #define AR_PHY_TPCRG1_PD_GAIN_3_S 20
739 #define AR_PHY_TPCGR1_FORCED_DAC_GAIN 0x0000003e
740 #define AR_PHY_TPCGR1_FORCED_DAC_GAIN_S 1
741 #define AR_PHY_TPCGR1_FORCE_DAC_GAIN 0x00000001
742 #define AR_PHY_TXGAIN_FORCE 0x00000001
743 #define AR_PHY_TXGAIN_FORCE_S 0
744 #define AR_PHY_TXGAIN_FORCED_PADVGNRA 0x00003c00
745 #define AR_PHY_TXGAIN_FORCED_PADVGNRA_S 10
746 #define AR_PHY_TXGAIN_FORCED_PADVGNRB 0x0003c000
747 #define AR_PHY_TXGAIN_FORCED_PADVGNRB_S 14
748 #define AR_PHY_TXGAIN_FORCED_PADVGNRD 0x00c00000
749 #define AR_PHY_TXGAIN_FORCED_PADVGNRD_S 22
750 #define AR_PHY_TXGAIN_FORCED_TXMXRGAIN 0x000003c0
751 #define AR_PHY_TXGAIN_FORCED_TXMXRGAIN_S 6
752 #define AR_PHY_TXGAIN_FORCED_TXBB1DBGAIN 0x0000000e
753 #define AR_PHY_TXGAIN_FORCED_TXBB1DBGAIN_S 1
754 
755 #define AR_PHY_POWER_TX_RATE1 0x9934
756 #define AR_PHY_POWER_TX_RATE2 0x9938
757 #define AR_PHY_POWER_TX_RATE_MAX 0x993c
758 #define AR_PHY_POWER_TX_RATE_MAX_TPC_ENABLE 0x00000040
759 #define PHY_AGC_CLR 0x10000000
760 #define RFSILENT_BB 0x00002000
761 #define AR_PHY_CHAN_INFO_GAIN_DIFF_PPM_MASK 0xFFF
762 #define AR_PHY_CHAN_INFO_GAIN_DIFF_PPM_SIGNED_BIT 0x800
763 #define AR_PHY_CHAN_INFO_GAIN_DIFF_UPPER_LIMIT 320
764 #define AR_PHY_CHAN_INFO_MEMORY_CAPTURE_MASK 0x0001
765 #define AR_PHY_RX_DELAY_DELAY 0x00003FFF
766 #define AR_PHY_CCK_TX_CTRL_JAPAN 0x00000010
767 #define AR_PHY_SPECTRAL_SCAN_ENABLE 0x00000001
768 #define AR_PHY_SPECTRAL_SCAN_ENABLE_S 0
769 #define AR_PHY_SPECTRAL_SCAN_ACTIVE 0x00000002
770 #define AR_PHY_SPECTRAL_SCAN_ACTIVE_S 1
771 #define AR_PHY_SPECTRAL_SCAN_FFT_PERIOD 0x000000F0
772 #define AR_PHY_SPECTRAL_SCAN_FFT_PERIOD_S 4
773 #define AR_PHY_SPECTRAL_SCAN_PERIOD 0x0000FF00
774 #define AR_PHY_SPECTRAL_SCAN_PERIOD_S 8
775 #define AR_PHY_SPECTRAL_SCAN_COUNT 0x00FF0000
776 #define AR_PHY_SPECTRAL_SCAN_COUNT_S 16
777 #define AR_PHY_SPECTRAL_SCAN_SHORT_REPEAT 0x01000000
778 #define AR_PHY_SPECTRAL_SCAN_SHORT_REPEAT_S 24
779 #define AR_PHY_CHANNEL_STATUS_RX_CLEAR 0x00000004
780 #define AR_PHY_TX_IQCAL_CONTROL_1_IQCORR_I_Q_COFF_DELPT 0x01fc0000
781 #define AR_PHY_TX_IQCAL_CONTROL_1_IQCORR_I_Q_COFF_DELPT_S 18
782 #define AR_PHY_TX_IQCAL_START_DO_CAL 0x00000001
783 #define AR_PHY_TX_IQCAL_START_DO_CAL_S 0
784 
785 #define AR_PHY_TX_IQCAL_STATUS_FAILED 0x00000001
786 #define AR_PHY_CALIBRATED_GAINS_0 0x3e
787 #define AR_PHY_CALIBRATED_GAINS_0_S 1
788 
789 #define AR_PHY_TX_IQCAL_CORR_COEFF_00_COEFF_TABLE 0x00003fff
790 #define AR_PHY_TX_IQCAL_CORR_COEFF_00_COEFF_TABLE_S 0
791 #define AR_PHY_TX_IQCAL_CORR_COEFF_01_COEFF_TABLE 0x0fffc000
792 #define AR_PHY_TX_IQCAL_CORR_COEFF_01_COEFF_TABLE_S 14
793 
794 #define AR_PHY_65NM_CH0_RXTX4_THERM_ON 0x10000000
795 #define AR_PHY_65NM_CH0_RXTX4_THERM_ON_S 28
796 
797 /*
798  * Channel 1 Register Map
799  */
800 #define AR_CHAN1_BASE 0xa800
801 
802 #define AR_PHY_EXT_CCA_1 (AR_CHAN1_BASE + 0x30)
803 #define AR_PHY_TX_PHASE_RAMP_1 (AR_CHAN1_BASE + 0xd0)
804 #define AR_PHY_ADC_GAIN_DC_CORR_1 (AR_CHAN1_BASE + 0xd4)
805 
806 #define AR_PHY_SPUR_REPORT_1 (AR_CHAN1_BASE + 0xa8)
807 #define AR_PHY_CHAN_INFO_TAB_1 (AR_CHAN1_BASE + 0x300)
808 #define AR_PHY_RX_IQCAL_CORR_B1 (AR_CHAN1_BASE + 0xdc)
809 
810 /*
811  * Channel 1 Field Definitions
812  */
813 #define AR_PHY_CH1_EXT_MINCCA_PWR 0x01FF0000
814 #define AR_PHY_CH1_EXT_MINCCA_PWR_S 16
815 
816 /*
817  * AGC 1 Register Map
818  */
819 #define AR_AGC1_BASE 0xae00
820 
821 #define AR_PHY_FORCEMAX_GAINS_1 (AR_AGC1_BASE + 0x4)
822 #define AR_PHY_EXT_ATTEN_CTL_1 (AR_AGC1_BASE + 0x18)
823 #define AR_PHY_CCA_1 (AR_AGC1_BASE + 0x1c)
824 #define AR_PHY_CCA_CTRL_1 (AR_AGC1_BASE + 0x20)
825 #define AR_PHY_RSSI_1 (AR_AGC1_BASE + 0x180)
826 #define AR_PHY_SPUR_CCK_REP_1 (AR_AGC1_BASE + 0x184)
827 #define AR_PHY_RX_OCGAIN_2 (AR_AGC1_BASE + 0x200)
828 
829 /*
830  * AGC 1 Field Definitions
831  */
832 #define AR_PHY_CH1_MINCCA_PWR 0x1FF00000
833 #define AR_PHY_CH1_MINCCA_PWR_S 20
834 
835 /*
836  * SM 1 Register Map
837  */
838 #define AR_SM1_BASE 0xb200
839 
840 #define AR_PHY_SWITCH_CHAIN_1 (AR_SM1_BASE + 0x84)
841 #define AR_PHY_FCAL_2_1 (AR_SM1_BASE + 0xd0)
842 #define AR_PHY_DFT_TONE_CTL_1 (AR_SM1_BASE + 0xd4)
843 #define AR_PHY_CL_TAB_1 (AR_SM1_BASE + 0x100)
844 #define AR_PHY_CHAN_INFO_GAIN_1 (AR_SM1_BASE + 0x180)
845 #define AR_PHY_TPC_4_B1 (AR_SM1_BASE + 0x204)
846 #define AR_PHY_TPC_5_B1 (AR_SM1_BASE + 0x208)
847 #define AR_PHY_TPC_6_B1 (AR_SM1_BASE + 0x20c)
848 #define AR_PHY_TPC_11_B1 (AR_SM1_BASE + 0x220)
849 #define AR_PHY_PDADC_TAB_1 (AR_SM1_BASE + 0x240)
850 #define AR_PHY_TX_IQCAL_STATUS_B1 (AR_SM1_BASE + 0x48c)
851 #define AR_PHY_TX_IQCAL_CORR_COEFF_B1(_i) (AR_SM_BASE + 0x450 + ((_i) << 2))
852 
853 /*
854  * Channel 2 Register Map
855  */
856 #define AR_CHAN2_BASE 0xb800
857 
858 #define AR_PHY_EXT_CCA_2 (AR_CHAN2_BASE + 0x30)
859 #define AR_PHY_TX_PHASE_RAMP_2 (AR_CHAN2_BASE + 0xd0)
860 #define AR_PHY_ADC_GAIN_DC_CORR_2 (AR_CHAN2_BASE + 0xd4)
861 
862 #define AR_PHY_SPUR_REPORT_2 (AR_CHAN2_BASE + 0xa8)
863 #define AR_PHY_CHAN_INFO_TAB_2 (AR_CHAN2_BASE + 0x300)
864 #define AR_PHY_RX_IQCAL_CORR_B2 (AR_CHAN2_BASE + 0xdc)
865 
866 /*
867  * Channel 2 Field Definitions
868  */
869 #define AR_PHY_CH2_EXT_MINCCA_PWR 0x01FF0000
870 #define AR_PHY_CH2_EXT_MINCCA_PWR_S 16
871 /*
872  * AGC 2 Register Map
873  */
874 #define AR_AGC2_BASE 0xbe00
875 
876 #define AR_PHY_FORCEMAX_GAINS_2 (AR_AGC2_BASE + 0x4)
877 #define AR_PHY_EXT_ATTEN_CTL_2 (AR_AGC2_BASE + 0x18)
878 #define AR_PHY_CCA_2 (AR_AGC2_BASE + 0x1c)
879 #define AR_PHY_CCA_CTRL_2 (AR_AGC2_BASE + 0x20)
880 #define AR_PHY_RSSI_2 (AR_AGC2_BASE + 0x180)
881 
882 /*
883  * AGC 2 Field Definitions
884  */
885 #define AR_PHY_CH2_MINCCA_PWR 0x1FF00000
886 #define AR_PHY_CH2_MINCCA_PWR_S 20
887 
888 /*
889  * SM 2 Register Map
890  */
891 #define AR_SM2_BASE 0xc200
892 
893 #define AR_PHY_SWITCH_CHAIN_2 (AR_SM2_BASE + 0x84)
894 #define AR_PHY_FCAL_2_2 (AR_SM2_BASE + 0xd0)
895 #define AR_PHY_DFT_TONE_CTL_2 (AR_SM2_BASE + 0xd4)
896 #define AR_PHY_CL_TAB_2 (AR_SM2_BASE + 0x100)
897 #define AR_PHY_CHAN_INFO_GAIN_2 (AR_SM2_BASE + 0x180)
898 #define AR_PHY_TPC_4_B2 (AR_SM2_BASE + 0x204)
899 #define AR_PHY_TPC_5_B2 (AR_SM2_BASE + 0x208)
900 #define AR_PHY_TPC_6_B2 (AR_SM2_BASE + 0x20c)
901 #define AR_PHY_TPC_11_B2 (AR_SM2_BASE + 0x220)
902 #define AR_PHY_PDADC_TAB_2 (AR_SM2_BASE + 0x240)
903 #define AR_PHY_TX_IQCAL_STATUS_B2 (AR_SM2_BASE + 0x48c)
904 #define AR_PHY_TX_IQCAL_CORR_COEFF_B2(_i) (AR_SM2_BASE + 0x450 + ((_i) << 2))
905 
906 #define AR_PHY_TX_IQCAL_STATUS_B2_FAILED 0x00000001
907 
908 /*
909  * AGC 3 Register Map
910  */
911 #define AR_AGC3_BASE 0xce00
912 
913 #define AR_PHY_RSSI_3 (AR_AGC3_BASE + 0x180)
914 
915 /*
916  * Misc helper defines
917  */
918 #define AR_PHY_CHAIN_OFFSET (AR_CHAN1_BASE - AR_CHAN_BASE)
919 
920 #define AR_PHY_NEW_ADC_DC_GAIN_CORR(_i) (AR_PHY_ADC_GAIN_DC_CORR_0 + (AR_PHY_CHAIN_OFFSET * (_i)))
921 #define AR_PHY_NEW_ADC_DC_GAIN_CORR_9300_10(_i) (AR_PHY_ADC_GAIN_DC_CORR_0_9300_10 + (AR_PHY_CHAIN_OFFSET * (_i)))
922 #define AR_PHY_SWITCH_CHAIN(_i) (AR_PHY_SWITCH_CHAIN_0 + (AR_PHY_CHAIN_OFFSET * (_i)))
923 #define AR_PHY_EXT_ATTEN_CTL(_i) (AR_PHY_EXT_ATTEN_CTL_0 + (AR_PHY_CHAIN_OFFSET * (_i)))
924 
925 #define AR_PHY_RXGAIN(_i) (AR_PHY_FORCEMAX_GAINS_0 + (AR_PHY_CHAIN_OFFSET * (_i)))
926 #define AR_PHY_TPCRG5(_i) (AR_PHY_TPC_5_B0 + (AR_PHY_CHAIN_OFFSET * (_i)))
927 #define AR_PHY_PDADC_TAB(_i) (AR_PHY_PDADC_TAB_0 + (AR_PHY_CHAIN_OFFSET * (_i)))
928 
929 #define AR_PHY_CAL_MEAS_0(_i) (AR_PHY_IQ_ADC_MEAS_0_B0 + (AR_PHY_CHAIN_OFFSET * (_i)))
930 #define AR_PHY_CAL_MEAS_1(_i) (AR_PHY_IQ_ADC_MEAS_1_B0 + (AR_PHY_CHAIN_OFFSET * (_i)))
931 #define AR_PHY_CAL_MEAS_2(_i) (AR_PHY_IQ_ADC_MEAS_2_B0 + (AR_PHY_CHAIN_OFFSET * (_i)))
932 #define AR_PHY_CAL_MEAS_3(_i) (AR_PHY_IQ_ADC_MEAS_3_B0 + (AR_PHY_CHAIN_OFFSET * (_i)))
933 #define AR_PHY_CAL_MEAS_0_9300_10(_i) (AR_PHY_IQ_ADC_MEAS_0_B0_9300_10 + (AR_PHY_CHAIN_OFFSET * (_i)))
934 #define AR_PHY_CAL_MEAS_1_9300_10(_i) (AR_PHY_IQ_ADC_MEAS_1_B0_9300_10 + (AR_PHY_CHAIN_OFFSET * (_i)))
935 #define AR_PHY_CAL_MEAS_2_9300_10(_i) (AR_PHY_IQ_ADC_MEAS_2_B0_9300_10 + (AR_PHY_CHAIN_OFFSET * (_i)))
936 #define AR_PHY_CAL_MEAS_3_9300_10(_i) (AR_PHY_IQ_ADC_MEAS_3_B0_9300_10 + (AR_PHY_CHAIN_OFFSET * (_i)))
937 
938 #define AR_PHY_WATCHDOG_NON_IDLE_ENABLE 0x00000001
939 #define AR_PHY_WATCHDOG_IDLE_ENABLE 0x00000002
940 #define AR_PHY_WATCHDOG_IDLE_MASK 0xFFFF0000
941 #define AR_PHY_WATCHDOG_NON_IDLE_MASK 0x0000FFFC
942 
943 #define AR_PHY_WATCHDOG_RST_ENABLE 0x00000002
944 #define AR_PHY_WATCHDOG_IRQ_ENABLE 0x00000004
945 #define AR_PHY_WATCHDOG_CNTL2_MASK 0xFFFFFFF9
946 
947 #define AR_PHY_WATCHDOG_INFO 0x00000007
948 #define AR_PHY_WATCHDOG_INFO_S 0
949 #define AR_PHY_WATCHDOG_DET_HANG 0x00000008
950 #define AR_PHY_WATCHDOG_DET_HANG_S 3
951 #define AR_PHY_WATCHDOG_RADAR_SM 0x000000F0
952 #define AR_PHY_WATCHDOG_RADAR_SM_S 4
953 #define AR_PHY_WATCHDOG_RX_OFDM_SM 0x00000F00
954 #define AR_PHY_WATCHDOG_RX_OFDM_SM_S 8
955 #define AR_PHY_WATCHDOG_RX_CCK_SM 0x0000F000
956 #define AR_PHY_WATCHDOG_RX_CCK_SM_S 12
957 #define AR_PHY_WATCHDOG_TX_OFDM_SM 0x000F0000
958 #define AR_PHY_WATCHDOG_TX_OFDM_SM_S 16
959 #define AR_PHY_WATCHDOG_TX_CCK_SM 0x00F00000
960 #define AR_PHY_WATCHDOG_TX_CCK_SM_S 20
961 #define AR_PHY_WATCHDOG_AGC_SM 0x0F000000
962 #define AR_PHY_WATCHDOG_AGC_SM_S 24
963 #define AR_PHY_WATCHDOG_SRCH_SM 0xF0000000
964 #define AR_PHY_WATCHDOG_SRCH_SM_S 28
965 
966 #define AR_PHY_WATCHDOG_STATUS_CLR 0x00000008
967 
968 /*
969  * PAPRD registers
970  */
971 #define AR_PHY_XPA_TIMING_CTL (AR_SM_BASE + 0x64)
972 
973 #define AR_PHY_PAPRD_AM2AM (AR_CHAN_BASE + 0xe4)
974 #define AR_PHY_PAPRD_AM2AM_MASK 0x01ffffff
975 #define AR_PHY_PAPRD_AM2AM_MASK_S 0
976 
977 #define AR_PHY_PAPRD_AM2PM (AR_CHAN_BASE + 0xe8)
978 #define AR_PHY_PAPRD_AM2PM_MASK 0x01ffffff
979 #define AR_PHY_PAPRD_AM2PM_MASK_S 0
980 
981 #define AR_PHY_PAPRD_HT40 (AR_CHAN_BASE + 0xec)
982 #define AR_PHY_PAPRD_HT40_MASK 0x01ffffff
983 #define AR_PHY_PAPRD_HT40_MASK_S 0
984 
985 #define AR_PHY_PAPRD_CTRL0_B0 (AR_CHAN_BASE + 0xf0)
986 #define AR_PHY_PAPRD_CTRL0_B1 (AR_CHAN1_BASE + 0xf0)
987 #define AR_PHY_PAPRD_CTRL0_B2 (AR_CHAN2_BASE + 0xf0)
988 #define AR_PHY_PAPRD_CTRL0_PAPRD_ENABLE 0x00000001
989 #define AR_PHY_PAPRD_CTRL0_PAPRD_ENABLE_S 0
990 #define AR_PHY_PAPRD_CTRL0_USE_SINGLE_TABLE_MASK 0x00000002
991 #define AR_PHY_PAPRD_CTRL0_USE_SINGLE_TABLE_MASK_S 1
992 #define AR_PHY_PAPRD_CTRL0_PAPRD_MAG_THRSH 0xf8000000
993 #define AR_PHY_PAPRD_CTRL0_PAPRD_MAG_THRSH_S 27
994 
995 #define AR_PHY_PAPRD_CTRL1_B0 (AR_CHAN_BASE + 0xf4)
996 #define AR_PHY_PAPRD_CTRL1_B1 (AR_CHAN1_BASE + 0xf4)
997 #define AR_PHY_PAPRD_CTRL1_B2 (AR_CHAN2_BASE + 0xf4)
998 #define AR_PHY_PAPRD_CTRL1_ADAPTIVE_SCALING_ENA 0x00000001
999 #define AR_PHY_PAPRD_CTRL1_ADAPTIVE_SCALING_ENA_S 0
1000 #define AR_PHY_PAPRD_CTRL1_ADAPTIVE_AM2AM_ENABLE 0x00000002
1001 #define AR_PHY_PAPRD_CTRL1_ADAPTIVE_AM2AM_ENABLE_S 1
1002 #define AR_PHY_PAPRD_CTRL1_ADAPTIVE_AM2PM_ENABLE 0x00000004
1003 #define AR_PHY_PAPRD_CTRL1_ADAPTIVE_AM2PM_ENABLE_S 2
1004 #define AR_PHY_PAPRD_CTRL1_PAPRD_POWER_AT_AM2AM_CAL 0x000001f8
1005 #define AR_PHY_PAPRD_CTRL1_PAPRD_POWER_AT_AM2AM_CAL_S 3
1006 #define AR_PHY_PAPRD_CTRL1_PA_GAIN_SCALE_FACT_MASK 0x0001fe00
1007 #define AR_PHY_PAPRD_CTRL1_PA_GAIN_SCALE_FACT_MASK_S 9
1008 #define AR_PHY_PAPRD_CTRL1_PAPRD_MAG_SCALE_FACT 0x0ffe0000
1009 #define AR_PHY_PAPRD_CTRL1_PAPRD_MAG_SCALE_FACT_S 17
1010 
1011 #define AR_PHY_PAPRD_TRAINER_CNTL1 (AR_SM_BASE + \
1012  (AR_SREV_9485(ah) ? \
1013  0x580 : 0x490))
1014 #define AR_PHY_PAPRD_TRAINER_CNTL1_CF_CF_PAPRD_TRAIN_ENABLE 0x00000001
1015 #define AR_PHY_PAPRD_TRAINER_CNTL1_CF_CF_PAPRD_TRAIN_ENABLE_S 0
1016 #define AR_PHY_PAPRD_TRAINER_CNTL1_CF_PAPRD_AGC2_SETTLING 0x0000007e
1017 #define AR_PHY_PAPRD_TRAINER_CNTL1_CF_PAPRD_AGC2_SETTLING_S 1
1018 #define AR_PHY_PAPRD_TRAINER_CNTL1_CF_PAPRD_IQCORR_ENABLE 0x00000100
1019 #define AR_PHY_PAPRD_TRAINER_CNTL1_CF_PAPRD_IQCORR_ENABLE_S 8
1020 #define AR_PHY_PAPRD_TRAINER_CNTL1_CF_PAPRD_RX_BB_GAIN_FORCE 0x00000200
1021 #define AR_PHY_PAPRD_TRAINER_CNTL1_CF_PAPRD_RX_BB_GAIN_FORCE_S 9
1022 #define AR_PHY_PAPRD_TRAINER_CNTL1_CF_PAPRD_TX_GAIN_FORCE 0x00000400
1023 #define AR_PHY_PAPRD_TRAINER_CNTL1_CF_PAPRD_TX_GAIN_FORCE_S 10
1024 #define AR_PHY_PAPRD_TRAINER_CNTL1_CF_PAPRD_LB_ENABLE 0x00000800
1025 #define AR_PHY_PAPRD_TRAINER_CNTL1_CF_PAPRD_LB_ENABLE_S 11
1026 #define AR_PHY_PAPRD_TRAINER_CNTL1_CF_PAPRD_LB_SKIP 0x0003f000
1027 #define AR_PHY_PAPRD_TRAINER_CNTL1_CF_PAPRD_LB_SKIP_S 12
1028 
1029 #define AR_PHY_PAPRD_TRAINER_CNTL2 (AR_SM_BASE + \
1030  (AR_SREV_9485(ah) ? \
1031  0x584 : 0x494))
1032 #define AR_PHY_PAPRD_TRAINER_CNTL2_CF_PAPRD_INIT_RX_BB_GAIN 0xFFFFFFFF
1033 #define AR_PHY_PAPRD_TRAINER_CNTL2_CF_PAPRD_INIT_RX_BB_GAIN_S 0
1034 
1035 #define AR_PHY_PAPRD_TRAINER_CNTL3 (AR_SM_BASE + \
1036  (AR_SREV_9485(ah) ? \
1037  0x588 : 0x498))
1038 #define AR_PHY_PAPRD_TRAINER_CNTL3_CF_PAPRD_ADC_DESIRED_SIZE 0x0000003f
1039 #define AR_PHY_PAPRD_TRAINER_CNTL3_CF_PAPRD_ADC_DESIRED_SIZE_S 0
1040 #define AR_PHY_PAPRD_TRAINER_CNTL3_CF_PAPRD_QUICK_DROP 0x00000fc0
1041 #define AR_PHY_PAPRD_TRAINER_CNTL3_CF_PAPRD_QUICK_DROP_S 6
1042 #define AR_PHY_PAPRD_TRAINER_CNTL3_CF_PAPRD_MIN_LOOPBACK_DEL 0x0001f000
1043 #define AR_PHY_PAPRD_TRAINER_CNTL3_CF_PAPRD_MIN_LOOPBACK_DEL_S 12
1044 #define AR_PHY_PAPRD_TRAINER_CNTL3_CF_PAPRD_NUM_CORR_STAGES 0x000e0000
1045 #define AR_PHY_PAPRD_TRAINER_CNTL3_CF_PAPRD_NUM_CORR_STAGES_S 17
1046 #define AR_PHY_PAPRD_TRAINER_CNTL3_CF_PAPRD_COARSE_CORR_LEN 0x00f00000
1047 #define AR_PHY_PAPRD_TRAINER_CNTL3_CF_PAPRD_COARSE_CORR_LEN_S 20
1048 #define AR_PHY_PAPRD_TRAINER_CNTL3_CF_PAPRD_FINE_CORR_LEN 0x0f000000
1049 #define AR_PHY_PAPRD_TRAINER_CNTL3_CF_PAPRD_FINE_CORR_LEN_S 24
1050 #define AR_PHY_PAPRD_TRAINER_CNTL3_CF_PAPRD_BBTXMIX_DISABLE 0x20000000
1051 #define AR_PHY_PAPRD_TRAINER_CNTL3_CF_PAPRD_BBTXMIX_DISABLE_S 29
1052 
1053 #define AR_PHY_PAPRD_TRAINER_CNTL4 (AR_SM_BASE + \
1054  (AR_SREV_9485(ah) ? \
1055  0x58c : 0x49c))
1056 #define AR_PHY_PAPRD_TRAINER_CNTL4_CF_PAPRD_NUM_TRAIN_SAMPLES 0x03ff0000
1057 #define AR_PHY_PAPRD_TRAINER_CNTL4_CF_PAPRD_NUM_TRAIN_SAMPLES_S 16
1058 #define AR_PHY_PAPRD_TRAINER_CNTL4_CF_PAPRD_SAFETY_DELTA 0x0000f000
1059 #define AR_PHY_PAPRD_TRAINER_CNTL4_CF_PAPRD_SAFETY_DELTA_S 12
1060 #define AR_PHY_PAPRD_TRAINER_CNTL4_CF_PAPRD_MIN_CORR 0x00000fff
1061 #define AR_PHY_PAPRD_TRAINER_CNTL4_CF_PAPRD_MIN_CORR_S 0
1062 
1063 #define AR_PHY_PAPRD_PRE_POST_SCALE_0_B0 (AR_CHAN_BASE + 0x100)
1064 #define AR_PHY_PAPRD_PRE_POST_SCALE_1_B0 (AR_CHAN_BASE + 0x104)
1065 #define AR_PHY_PAPRD_PRE_POST_SCALE_2_B0 (AR_CHAN_BASE + 0x108)
1066 #define AR_PHY_PAPRD_PRE_POST_SCALE_3_B0 (AR_CHAN_BASE + 0x10c)
1067 #define AR_PHY_PAPRD_PRE_POST_SCALE_4_B0 (AR_CHAN_BASE + 0x110)
1068 #define AR_PHY_PAPRD_PRE_POST_SCALE_5_B0 (AR_CHAN_BASE + 0x114)
1069 #define AR_PHY_PAPRD_PRE_POST_SCALE_6_B0 (AR_CHAN_BASE + 0x118)
1070 #define AR_PHY_PAPRD_PRE_POST_SCALE_7_B0 (AR_CHAN_BASE + 0x11c)
1071 #define AR_PHY_PAPRD_PRE_POST_SCALING 0x3FFFF
1072 #define AR_PHY_PAPRD_PRE_POST_SCALING_S 0
1073 
1074 #define AR_PHY_PAPRD_TRAINER_STAT1 (AR_SM_BASE + 0x4a0)
1075 #define AR_PHY_PAPRD_TRAINER_STAT1_PAPRD_TRAIN_DONE 0x00000001
1076 #define AR_PHY_PAPRD_TRAINER_STAT1_PAPRD_TRAIN_DONE_S 0
1077 #define AR_PHY_PAPRD_TRAINER_STAT1_PAPRD_TRAIN_INCOMPLETE 0x00000002
1078 #define AR_PHY_PAPRD_TRAINER_STAT1_PAPRD_TRAIN_INCOMPLETE_S 1
1079 #define AR_PHY_PAPRD_TRAINER_STAT1_PAPRD_CORR_ERR 0x00000004
1080 #define AR_PHY_PAPRD_TRAINER_STAT1_PAPRD_CORR_ERR_S 2
1081 #define AR_PHY_PAPRD_TRAINER_STAT1_PAPRD_TRAIN_ACTIVE 0x00000008
1082 #define AR_PHY_PAPRD_TRAINER_STAT1_PAPRD_TRAIN_ACTIVE_S 3
1083 #define AR_PHY_PAPRD_TRAINER_STAT1_PAPRD_RX_GAIN_IDX 0x000001f0
1084 #define AR_PHY_PAPRD_TRAINER_STAT1_PAPRD_RX_GAIN_IDX_S 4
1085 #define AR_PHY_PAPRD_TRAINER_STAT1_PAPRD_AGC2_PWR 0x0001fe00
1086 #define AR_PHY_PAPRD_TRAINER_STAT1_PAPRD_AGC2_PWR_S 9
1087 
1088 #define AR_PHY_PAPRD_TRAINER_STAT2 (AR_SM_BASE + 0x4a4)
1089 #define AR_PHY_PAPRD_TRAINER_STAT2_PAPRD_FINE_VAL 0x0000ffff
1090 #define AR_PHY_PAPRD_TRAINER_STAT2_PAPRD_FINE_VAL_S 0
1091 #define AR_PHY_PAPRD_TRAINER_STAT2_PAPRD_COARSE_IDX 0x001f0000
1092 #define AR_PHY_PAPRD_TRAINER_STAT2_PAPRD_COARSE_IDX_S 16
1093 #define AR_PHY_PAPRD_TRAINER_STAT2_PAPRD_FINE_IDX 0x00600000
1094 #define AR_PHY_PAPRD_TRAINER_STAT2_PAPRD_FINE_IDX_S 21
1095 
1096 #define AR_PHY_PAPRD_TRAINER_STAT3 (AR_SM_BASE + 0x4a8)
1097 #define AR_PHY_PAPRD_TRAINER_STAT3_PAPRD_TRAIN_SAMPLES_CNT 0x000fffff
1098 #define AR_PHY_PAPRD_TRAINER_STAT3_PAPRD_TRAIN_SAMPLES_CNT_S 0
1099 
1100 #define AR_PHY_PAPRD_MEM_TAB_B0 (AR_CHAN_BASE + 0x120)
1101 #define AR_PHY_PAPRD_MEM_TAB_B1 (AR_CHAN1_BASE + 0x120)
1102 #define AR_PHY_PAPRD_MEM_TAB_B2 (AR_CHAN2_BASE + 0x120)
1103 
1104 #define AR_PHY_PA_GAIN123_B0 (AR_CHAN_BASE + 0xf8)
1105 #define AR_PHY_PA_GAIN123_B1 (AR_CHAN1_BASE + 0xf8)
1106 #define AR_PHY_PA_GAIN123_B2 (AR_CHAN2_BASE + 0xf8)
1107 #define AR_PHY_PA_GAIN123_PA_GAIN1 0x3FF
1108 #define AR_PHY_PA_GAIN123_PA_GAIN1_S 0
1109 
1110 #define AR_PHY_POWERTX_RATE5 (AR_SM_BASE + 0x1d0)
1111 #define AR_PHY_POWERTX_RATE5_POWERTXHT20_0 0x3F
1112 #define AR_PHY_POWERTX_RATE5_POWERTXHT20_0_S 0
1113 
1114 #define AR_PHY_POWERTX_RATE6 (AR_SM_BASE + 0x1d4)
1115 #define AR_PHY_POWERTX_RATE6_POWERTXHT20_5 0x3F00
1116 #define AR_PHY_POWERTX_RATE6_POWERTXHT20_5_S 8
1117 
1118 #define AR_PHY_POWERTX_RATE8 (AR_SM_BASE + 0x1dc)
1119 #define AR_PHY_POWERTX_RATE8_POWERTXHT40_5 0x3F00
1120 #define AR_PHY_POWERTX_RATE8_POWERTXHT40_5_S 8
1121 
1122 void ar9003_hw_set_chain_masks(struct ath_hw *ah, u8 rx, u8 tx);
1123 
1124 #endif /* AR9003_PHY_H */
Definition: hw.h:656
void ar9003_hw_set_chain_masks(struct ath_hw *ah, u8 rx, u8 tx)
uint32_t rx
Maximum number of receive queues.
Definition: intelvf.h:16
uint32_t tx
Maximum number of transmit queues.
Definition: intelvf.h:14
uint8_t ah
Definition: registers.h:85
uint8_t u8
Definition: stdint.h:19