iPXE
hw.h
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1 /*
2  * Copyright (c) 2008-2011 Atheros Communications Inc.
3  *
4  * Modified for iPXE by Scott K Logan <logans@cottsay.net> July 2011
5  * Original from Linux kernel 3.0.1
6  *
7  * Permission to use, copy, modify, and/or distribute this software for any
8  * purpose with or without fee is hereby granted, provided that the above
9  * copyright notice and this permission notice appear in all copies.
10  *
11  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
12  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
13  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
14  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
15  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
16  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
17  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
18  */
19 
20 #ifndef HW_H
21 #define HW_H
22 
23 FILE_LICENCE ( BSD2 );
24 
25 #include <errno.h>
26 
27 #include "mac.h"
28 #include "ani.h"
29 #include "eeprom.h"
30 #include "calib.h"
31 #include "reg.h"
32 #include "phy.h"
33 
34 #include "../regd.h"
35 
36 /* Keep all ath9k files under one errfile ID */
37 #undef ERRFILE
38 #define ERRFILE ERRFILE_ath9k
39 
40 #define ATHEROS_VENDOR_ID 0x168c
41 
42 #define AR5416_DEVID_PCI 0x0023
43 #define AR5416_DEVID_PCIE 0x0024
44 #define AR9160_DEVID_PCI 0x0027
45 #define AR9280_DEVID_PCI 0x0029
46 #define AR9280_DEVID_PCIE 0x002a
47 #define AR9285_DEVID_PCIE 0x002b
48 #define AR2427_DEVID_PCIE 0x002c
49 #define AR9287_DEVID_PCI 0x002d
50 #define AR9287_DEVID_PCIE 0x002e
51 #define AR9300_DEVID_PCIE 0x0030
52 #define AR9300_DEVID_AR9340 0x0031
53 #define AR9300_DEVID_AR9485_PCIE 0x0032
54 
55 #define AR5416_AR9100_DEVID 0x000b
56 
57 #define AR_SUBVENDOR_ID_NOG 0x0e11
58 #define AR_SUBVENDOR_ID_NEW_A 0x7065
59 #define AR5416_MAGIC 0x19641014
60 
61 #define AR9280_COEX2WIRE_SUBSYSID 0x309b
62 #define AT9285_COEX3WIRE_SA_SUBSYSID 0x30aa
63 #define AT9285_COEX3WIRE_DA_SUBSYSID 0x30ab
64 
65 #define AR9300_NUM_BT_WEIGHTS 4
66 #define AR9300_NUM_WLAN_WEIGHTS 4
67 
68 #define ATH_AMPDU_LIMIT_MAX (64 * 1024 - 1)
69 
70 #define ATH_DEFAULT_NOISE_FLOOR -95
71 
72 #define ATH9K_RSSI_BAD -128
73 
74 #define ATH9K_NUM_CHANNELS 38
75 
76 /* Register read/write primitives */
77 #define REG_WRITE(_ah, _reg, _val) \
78  (_ah)->reg_ops.write((_ah), (_val), (_reg))
79 
80 #define REG_READ(_ah, _reg) \
81  (_ah)->reg_ops.read((_ah), (_reg))
82 
83 #define REG_READ_MULTI(_ah, _addr, _val, _cnt) \
84  (_ah)->reg_ops.multi_read((_ah), (_addr), (_val), (_cnt))
85 
86 #define REG_RMW(_ah, _reg, _set, _clr) \
87  (_ah)->reg_ops.rmw((_ah), (_reg), (_set), (_clr))
88 
89 #define ENABLE_REGWRITE_BUFFER(_ah) \
90  do { \
91  if ((_ah)->reg_ops.enable_write_buffer) \
92  (_ah)->reg_ops.enable_write_buffer((_ah)); \
93  } while (0)
94 
95 #define REGWRITE_BUFFER_FLUSH(_ah) \
96  do { \
97  if ((_ah)->reg_ops.write_flush) \
98  (_ah)->reg_ops.write_flush((_ah)); \
99  } while (0)
100 
101 #define SM(_v, _f) (((_v) << _f##_S) & _f)
102 #define MS(_v, _f) (((_v) & _f) >> _f##_S)
103 #define REG_RMW_FIELD(_a, _r, _f, _v) \
104  REG_RMW(_a, _r, (((_v) << _f##_S) & _f), (_f))
105 #define REG_READ_FIELD(_a, _r, _f) \
106  (((REG_READ(_a, _r) & _f) >> _f##_S))
107 #define REG_SET_BIT(_a, _r, _f) \
108  REG_RMW(_a, _r, (_f), 0)
109 #define REG_CLR_BIT(_a, _r, _f) \
110  REG_RMW(_a, _r, 0, (_f))
111 
112 #define DO_DELAY(x) do { \
113  if (((++(x) % 64) == 0) && \
114  (ath9k_hw_common(ah)->bus_ops->ath_bus_type \
115  != ATH_USB)) \
116  udelay(1); \
117  } while (0)
118 
119 #define REG_WRITE_ARRAY(iniarray, column, regWr) \
120  ath9k_hw_write_array(ah, iniarray, column, &(regWr))
121 
122 #define AR_GPIO_OUTPUT_MUX_AS_OUTPUT 0
123 #define AR_GPIO_OUTPUT_MUX_AS_PCIE_ATTENTION_LED 1
124 #define AR_GPIO_OUTPUT_MUX_AS_PCIE_POWER_LED 2
125 #define AR_GPIO_OUTPUT_MUX_AS_TX_FRAME 3
126 #define AR_GPIO_OUTPUT_MUX_AS_RX_CLEAR_EXTERNAL 4
127 #define AR_GPIO_OUTPUT_MUX_AS_MAC_NETWORK_LED 5
128 #define AR_GPIO_OUTPUT_MUX_AS_MAC_POWER_LED 6
129 
130 #define AR_GPIOD_MASK 0x00001FFF
131 #define AR_GPIO_BIT(_gpio) (1 << (_gpio))
132 
133 #define BASE_ACTIVATE_DELAY 100
134 #define RTC_PLL_SETTLE_DELAY (AR_SREV_9340(ah) ? 1000 : 100)
135 #define COEF_SCALE_S 24
136 #define HT40_CHANNEL_CENTER_SHIFT 10
137 
138 #define ATH9K_ANTENNA0_CHAINMASK 0x1
139 #define ATH9K_ANTENNA1_CHAINMASK 0x2
140 
141 #define ATH9K_NUM_DMA_DEBUG_REGS 8
142 #define ATH9K_NUM_QUEUES 10
143 
144 #define MAX_RATE_POWER 63
145 #define AH_WAIT_TIMEOUT 100000 /* (us) */
146 #define AH_TSF_WRITE_TIMEOUT 100 /* (us) */
147 #define AH_TIME_QUANTUM 10
148 #define AR_KEYTABLE_SIZE 128
149 #define POWER_UP_TIME 10000
150 #define SPUR_RSSI_THRESH 40
151 
152 #define CAB_TIMEOUT_VAL 10
153 #define BEACON_TIMEOUT_VAL 10
154 #define MIN_BEACON_TIMEOUT_VAL 1
155 #define SLEEP_SLOP 3
156 
157 #define INIT_CONFIG_STATUS 0x00000000
158 #define INIT_RSSI_THR 0x00000700
159 #define INIT_BCON_CNTRL_REG 0x00000000
160 
161 #define TU_TO_USEC(_tu) ((_tu) << 10)
162 
163 #define ATH9K_HW_RX_HP_QDEPTH 16
164 #define ATH9K_HW_RX_LP_QDEPTH 128
165 
166 #define PAPRD_GAIN_TABLE_ENTRIES 32
167 #define PAPRD_TABLE_SZ 24
168 
171 };
172 
178 };
179 
196 };
197 
199  u32 hw_caps; /* ATH9K_HW_CAP_* from ath9k_hw_caps */
213 };
214 
219  int ack_6mb;
235 #define SPUR_DISABLE 0
236 #define SPUR_ENABLE_IOCTL 1
237 #define SPUR_ENABLE_EEPROM 2
238 #define AR_SPUR_5413_1 1640
239 #define AR_SPUR_5413_2 1200
240 #define AR_NO_SPUR 0x8000
241 #define AR_BASE_FREQ_2GHZ 2300
242 #define AR_BASE_FREQ_5GHZ 4900
243 #define AR_SPUR_FEEQ_BOUND_HT40 19
244 #define AR_SPUR_FEEQ_BOUND_HT20 10
245  int spurmode;
248  u16 ani_poll_interval; /* ANI poll interval in ms */
249 };
250 
251 enum ath9k_int {
252  ATH9K_INT_RX = 0x00000001,
253  ATH9K_INT_RXDESC = 0x00000002,
254  ATH9K_INT_RXHP = 0x00000001,
255  ATH9K_INT_RXLP = 0x00000002,
256  ATH9K_INT_RXNOFRM = 0x00000008,
257  ATH9K_INT_RXEOL = 0x00000010,
258  ATH9K_INT_RXORN = 0x00000020,
259  ATH9K_INT_TX = 0x00000040,
260  ATH9K_INT_TXDESC = 0x00000080,
261  ATH9K_INT_TIM_TIMER = 0x00000100,
262  ATH9K_INT_BB_WATCHDOG = 0x00000400,
263  ATH9K_INT_TXURN = 0x00000800,
264  ATH9K_INT_MIB = 0x00001000,
265  ATH9K_INT_RXPHY = 0x00004000,
266  ATH9K_INT_RXKCM = 0x00008000,
267  ATH9K_INT_SWBA = 0x00010000,
268  ATH9K_INT_BMISS = 0x00040000,
269  ATH9K_INT_BNR = 0x00100000,
270  ATH9K_INT_TIM = 0x00200000,
271  ATH9K_INT_DTIM = 0x00400000,
272  ATH9K_INT_DTIMSYNC = 0x00800000,
273  ATH9K_INT_GPIO = 0x01000000,
274  ATH9K_INT_CABEND = 0x02000000,
275  ATH9K_INT_TSFOOR = 0x04000000,
276  ATH9K_INT_GENTIMER = 0x08000000,
277  ATH9K_INT_CST = 0x10000000,
278  ATH9K_INT_GTT = 0x20000000,
279  ATH9K_INT_FATAL = 0x40000000,
280  ATH9K_INT_GLOBAL = 0x80000000,
292  ATH9K_INT_MIB |
298  ATH9K_INT_NOCARD = 0xffffffff
299 };
300 
301 #define CHANNEL_CW_INT 0x00002
302 #define CHANNEL_CCK 0x00020
303 #define CHANNEL_OFDM 0x00040
304 #define CHANNEL_2GHZ 0x00080
305 #define CHANNEL_5GHZ 0x00100
306 #define CHANNEL_PASSIVE 0x00200
307 #define CHANNEL_DYN 0x00400
308 #define CHANNEL_HALF 0x04000
309 #define CHANNEL_QUARTER 0x08000
310 #define CHANNEL_HT20 0x10000
311 #define CHANNEL_HT40PLUS 0x20000
312 #define CHANNEL_HT40MINUS 0x40000
313 
314 #define CHANNEL_A (CHANNEL_5GHZ|CHANNEL_OFDM)
315 #define CHANNEL_B (CHANNEL_2GHZ|CHANNEL_CCK)
316 #define CHANNEL_G (CHANNEL_2GHZ|CHANNEL_OFDM)
317 #define CHANNEL_G_HT20 (CHANNEL_2GHZ|CHANNEL_HT20)
318 #define CHANNEL_A_HT20 (CHANNEL_5GHZ|CHANNEL_HT20)
319 #define CHANNEL_G_HT40PLUS (CHANNEL_2GHZ|CHANNEL_HT40PLUS)
320 #define CHANNEL_G_HT40MINUS (CHANNEL_2GHZ|CHANNEL_HT40MINUS)
321 #define CHANNEL_A_HT40PLUS (CHANNEL_5GHZ|CHANNEL_HT40PLUS)
322 #define CHANNEL_A_HT40MINUS (CHANNEL_5GHZ|CHANNEL_HT40MINUS)
323 #define CHANNEL_ALL \
324  (CHANNEL_OFDM| \
325  CHANNEL_CCK| \
326  CHANNEL_2GHZ | \
327  CHANNEL_5GHZ | \
328  CHANNEL_HT20 | \
329  CHANNEL_HT40PLUS | \
330  CHANNEL_HT40MINUS)
331 
344 };
345 
353 };
354 
355 #define IS_CHAN_G(_c) ((((_c)->channelFlags & (CHANNEL_G)) == CHANNEL_G) || \
356  (((_c)->channelFlags & CHANNEL_G_HT20) == CHANNEL_G_HT20) || \
357  (((_c)->channelFlags & CHANNEL_G_HT40PLUS) == CHANNEL_G_HT40PLUS) || \
358  (((_c)->channelFlags & CHANNEL_G_HT40MINUS) == CHANNEL_G_HT40MINUS))
359 #define IS_CHAN_OFDM(_c) (((_c)->channelFlags & CHANNEL_OFDM) != 0)
360 #define IS_CHAN_5GHZ(_c) (((_c)->channelFlags & CHANNEL_5GHZ) != 0)
361 #define IS_CHAN_2GHZ(_c) (((_c)->channelFlags & CHANNEL_2GHZ) != 0)
362 #define IS_CHAN_HALF_RATE(_c) (((_c)->channelFlags & CHANNEL_HALF) != 0)
363 #define IS_CHAN_QUARTER_RATE(_c) (((_c)->channelFlags & CHANNEL_QUARTER) != 0)
364 #define IS_CHAN_A_FAST_CLOCK(_ah, _c) \
365  ((((_c)->channelFlags & CHANNEL_5GHZ) != 0) && \
366  ((_ah)->caps.hw_caps & ATH9K_HW_CAP_FASTCLOCK))
367 
368 /* These macros check chanmode and not channelFlags */
369 #define IS_CHAN_B(_c) ((_c)->chanmode == CHANNEL_B)
370 #define IS_CHAN_HT20(_c) (((_c)->chanmode == CHANNEL_A_HT20) || \
371  ((_c)->chanmode == CHANNEL_G_HT20))
372 #define IS_CHAN_HT40(_c) (((_c)->chanmode == CHANNEL_A_HT40PLUS) || \
373  ((_c)->chanmode == CHANNEL_A_HT40MINUS) || \
374  ((_c)->chanmode == CHANNEL_G_HT40PLUS) || \
375  ((_c)->chanmode == CHANNEL_G_HT40MINUS))
376 #define IS_CHAN_HT(_c) (IS_CHAN_HT20((_c)) || IS_CHAN_HT40((_c)))
377 
383 };
384 
391 };
392 
397 };
398 
403 };
404 
409 #define ATH9K_BEACON_PERIOD 0x0000ffff
410 #define ATH9K_TSFOOR_THRESHOLD 0x00004240 /* 16k us */
419 };
420 
421 struct chan_centers {
425 };
426 
427 enum {
431 };
432 
444 };
445 
446 /* Generic TSF timer definitions */
447 
448 #define ATH_MAX_GEN_TIMER 16
449 
450 #define AR_GENTMR_BIT(_index) (1 << (_index))
451 
452 /*
453  * Using de Bruijin sequence to look up 1's index in a 32 bit number
454  * debruijn32 = 0000 0111 0111 1100 1011 0101 0011 0001
455  */
456 #define debruijn32 0x077CB531U
457 
463 };
464 
466  void (*trigger)(void *arg);
467  void (*overflow)(void *arg);
468  void *arg;
470 };
471 
475  union {
476  unsigned long timer_bits;
478  } timer_mask;
479 };
480 
489 };
490 
491 /**
492  * struct ath_hw_radar_conf - radar detection initialization parameters
493  *
494  * @pulse_inband: threshold for checking the ratio of in-band power
495  * to total power for short radar pulses (half dB steps)
496  * @pulse_inband_step: threshold for checking an in-band power to total
497  * power ratio increase for short radar pulses (half dB steps)
498  * @pulse_height: threshold for detecting the beginning of a short
499  * radar pulse (dB step)
500  * @pulse_rssi: threshold for detecting if a short radar pulse is
501  * gone (dB step)
502  * @pulse_maxlen: maximum pulse length (0.8 us steps)
503  *
504  * @radar_rssi: RSSI threshold for starting long radar detection (dB steps)
505  * @radar_inband: threshold for checking the ratio of in-band power
506  * to total power for long radar pulses (half dB steps)
507  * @fir_power: threshold for detecting the end of a long radar pulse (dB)
508  *
509  * @ext_channel: enable extension channel radar detection
510  */
512  unsigned int pulse_inband;
513  unsigned int pulse_inband_step;
514  unsigned int pulse_height;
515  unsigned int pulse_rssi;
516  unsigned int pulse_maxlen;
517 
518  unsigned int radar_rssi;
519  unsigned int radar_inband;
521 
523 };
524 
525 /**
526  * struct ath_hw_private_ops - callbacks used internally by hardware code
527  *
528  * This structure contains private callbacks designed to only be used internally
529  * by the hardware core.
530  *
531  * @init_cal_settings: setup types of calibrations supported
532  * @init_cal: starts actual calibration
533  *
534  * @init_mode_regs: Initializes mode registers
535  * @init_mode_gain_regs: Initialize TX/RX gain registers
536  *
537  * @rf_set_freq: change frequency
538  * @spur_mitigate_freq: spur mitigation
539  * @rf_alloc_ext_banks:
540  * @rf_free_ext_banks:
541  * @set_rf_regs:
542  * @compute_pll_control: compute the PLL control value to use for
543  * AR_RTC_PLL_CONTROL for a given channel
544  * @setup_calibration: set up calibration
545  * @iscal_supported: used to query if a type of calibration is supported
546  *
547  * @ani_cache_ini_regs: cache the values for ANI from the initial
548  * register settings through the register initialization.
549  */
551  /* Calibration ops */
552  void (*init_cal_settings)(struct ath_hw *ah);
553  int (*init_cal)(struct ath_hw *ah, struct ath9k_channel *chan);
554 
555  void (*init_mode_regs)(struct ath_hw *ah);
556  void (*init_mode_gain_regs)(struct ath_hw *ah);
557  void (*setup_calibration)(struct ath_hw *ah,
558  struct ath9k_cal_list *currCal);
559 
560  /* PHY ops */
561  int (*rf_set_freq)(struct ath_hw *ah,
562  struct ath9k_channel *chan);
563  void (*spur_mitigate_freq)(struct ath_hw *ah,
564  struct ath9k_channel *chan);
565  int (*rf_alloc_ext_banks)(struct ath_hw *ah);
566  void (*rf_free_ext_banks)(struct ath_hw *ah);
567  int (*set_rf_regs)(struct ath_hw *ah,
568  struct ath9k_channel *chan,
569  u16 modesIndex);
570  void (*set_channel_regs)(struct ath_hw *ah, struct ath9k_channel *chan);
571  void (*init_bb)(struct ath_hw *ah,
572  struct ath9k_channel *chan);
573  int (*process_ini)(struct ath_hw *ah, struct ath9k_channel *chan);
574  void (*olc_init)(struct ath_hw *ah);
575  void (*set_rfmode)(struct ath_hw *ah, struct ath9k_channel *chan);
576  void (*mark_phy_inactive)(struct ath_hw *ah);
577  void (*set_delta_slope)(struct ath_hw *ah, struct ath9k_channel *chan);
578  int (*rfbus_req)(struct ath_hw *ah);
579  void (*rfbus_done)(struct ath_hw *ah);
580  void (*restore_chainmask)(struct ath_hw *ah);
581  void (*set_diversity)(struct ath_hw *ah, int value);
583  struct ath9k_channel *chan);
584  int (*ani_control)(struct ath_hw *ah, enum ath9k_ani_cmd cmd,
585  int param);
586  void (*do_getnf)(struct ath_hw *ah, int16_t nfarray[NUM_NF_READINGS]);
587  void (*set_radar_params)(struct ath_hw *ah,
588  struct ath_hw_radar_conf *conf);
589 
590  /* ANI */
591  void (*ani_cache_ini_regs)(struct ath_hw *ah);
592 };
593 
594 /**
595  * struct ath_hw_ops - callbacks used by hardware code and driver code
596  *
597  * This structure contains callbacks designed to to be used internally by
598  * hardware code and also by the lower level driver.
599  *
600  * @config_pci_powersave:
601  * @calibrate: periodic calibration for NF, ANI, IQ, ADC gain, ADC-DC
602  */
603 struct ath_hw_ops {
604  void (*config_pci_powersave)(struct ath_hw *ah,
605  int restore,
606  int power_off);
607  void (*rx_enable)(struct ath_hw *ah);
608  void (*set_desc_link)(void *ds, u32 link);
609  void (*get_desc_link)(void *ds, u32 **link);
610  int (*calibrate)(struct ath_hw *ah,
611  struct ath9k_channel *chan,
612  u8 rxchainmask,
613  int longcal);
614  int (*get_isr)(struct ath_hw *ah, enum ath9k_int *masked);
615  void (*fill_txdesc)(struct ath_hw *ah, void *ds, u32 seglen,
616  int is_firstseg, int is_is_lastseg,
617  const void *ds0, u32 buf_addr,
618  unsigned int qcu);
619  int (*proc_txdesc)(struct ath_hw *ah, void *ds,
620  struct ath_tx_status *ts);
621  void (*set11n_txdesc)(struct ath_hw *ah, void *ds,
622  u32 pktLen, enum ath9k_pkt_type type,
623  u32 txPower, u32 keyIx,
624  enum ath9k_key_type keyType,
625  u32 flags);
626  void (*set11n_ratescenario)(struct ath_hw *ah, void *ds,
627  void *lastds,
628  u32 durUpdateEn, u32 rtsctsRate,
629  u32 rtsctsDuration,
630  struct ath9k_11n_rate_series series[],
631  u32 nseries, u32 flags);
632  void (*set11n_aggr_first)(struct ath_hw *ah, void *ds,
633  u32 aggrLen);
634  void (*set11n_aggr_middle)(struct ath_hw *ah, void *ds,
635  u32 numDelims);
636  void (*set11n_aggr_last)(struct ath_hw *ah, void *ds);
637  void (*clr11n_aggr)(struct ath_hw *ah, void *ds);
638  void (*set_clrdmask)(struct ath_hw *ah, void *ds, int val);
639  void (*antdiv_comb_conf_get)(struct ath_hw *ah,
640  struct ath_hw_antcomb_conf *antconf);
641  void (*antdiv_comb_conf_set)(struct ath_hw *ah,
642  struct ath_hw_antcomb_conf *antconf);
643 
644 };
645 
650 };
651 
652 /* ah_flags */
653 #define AH_USE_EEPROM 0x1
654 #define AH_UNPLUGGED 0x2 /* The card has been physically removed. */
655 
656 struct ath_hw {
657  struct ath_ops reg_ops;
658 
666 
667  union {
672  } eeprom;
673  const struct eeprom_ops *eep_ops;
674 
680 
688 
690 
692 
697 
699  int ah_ier;
709 
710  /* Calibration */
719 #define totalPowerMeasI meas0.unsign
720 #define totalPowerMeasQ meas1.unsign
721 #define totalIqCorrMeas meas2.sign
722 #define totalAdcIOddPhase meas0.unsign
723 #define totalAdcIEvenPhase meas1.unsign
724 #define totalAdcQOddPhase meas2.unsign
725 #define totalAdcQEvenPhase meas3.unsign
726 #define totalAdcDcOffsetIOddPhase meas0.sign
727 #define totalAdcDcOffsetIEvenPhase meas1.sign
728 #define totalAdcDcOffsetQOddPhase meas2.sign
729 #define totalAdcDcOffsetQEvenPhase meas3.sign
730  union {
733  } meas0;
734  union {
737  } meas1;
738  union {
741  } meas2;
742  union {
745  } meas3;
747 
750  enum {
755 
756  /* Private to hardware code */
758  /* Accessed by the lower level driver */
759  struct ath_hw_ops ops;
760 
761  /* Used to program the radio on non single-chip devices */
771 
776 
777  /* ANI */
781  int coarse_high[5];
782  int coarse_low[5];
783  int firpwr[5];
785 
789 
791 
795  int led_pin;
798 
824 
829 
833 
835  void *ts_start;
840 
841  unsigned int paprd_target_power;
842  unsigned int paprd_training_power;
843  unsigned int paprd_ratemask;
844  unsigned int paprd_ratemask_ht40;
848  /*
849  * Store the permanent value of Reg 0x4004in WARegVal
850  * so we dont have to R/M/W. We should not be reading
851  * this register when in sleep states.
852  */
854 
855  /* Enterprise mode cap */
857 
859 };
860 
861 struct ath_bus_ops {
863  void (*read_cachesize)(struct ath_common *common, int *csz);
864  int (*eeprom_read)(struct ath_common *common, u32 off, u16 *data);
865  void (*bt_coex_prep)(struct ath_common *common);
866  void (*extn_synch_en)(struct ath_common *common);
867 };
868 
869 static inline struct ath_common *ath9k_hw_common(struct ath_hw *ah)
870 {
871  return &ah->common;
872 }
873 
874 static inline struct ath_regulatory *ath9k_hw_regulatory(struct ath_hw *ah)
875 {
876  return &(ath9k_hw_common(ah)->regulatory);
877 }
878 
879 static inline struct ath_hw_private_ops *ath9k_hw_private_ops(struct ath_hw *ah)
880 {
881  return &ah->private_ops;
882 }
883 
884 static inline struct ath_hw_ops *ath9k_hw_ops(struct ath_hw *ah)
885 {
886  return &ah->ops;
887 }
888 
889 static inline u8 get_streams(int mask)
890 {
891  return !!(mask & BIT(0)) + !!(mask & BIT(1)) + !!(mask & BIT(2));
892 }
893 
894 /* Initialization, Detach, Reset */
895 const char *ath9k_hw_probe(u16 vendorid, u16 devid);
896 void ath9k_hw_deinit(struct ath_hw *ah);
897 int ath9k_hw_init(struct ath_hw *ah);
898 int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan,
899  struct ath9k_hw_cal_data *caldata, int bChannelChange);
900 int ath9k_hw_fill_cap_info(struct ath_hw *ah);
901 u32 ath9k_regd_get_ctl(struct ath_regulatory *reg, struct ath9k_channel *chan);
902 
903 /* GPIO / RFKILL / Antennae */
904 void ath9k_hw_cfg_gpio_input(struct ath_hw *ah, u32 gpio);
906 void ath9k_hw_cfg_output(struct ath_hw *ah, u32 gpio,
907  u32 ah_signal_type);
908 void ath9k_hw_set_gpio(struct ath_hw *ah, u32 gpio, u32 val);
910 void ath9k_hw_setantenna(struct ath_hw *ah, u32 antenna);
911 
912 /* General Operation */
913 int ath9k_hw_wait(struct ath_hw *ah, u32 reg, u32 mask, u32 val, u32 timeout);
914 void ath9k_hw_write_array(struct ath_hw *ah, struct ar5416IniArray *array,
915  int column, unsigned int *writecnt);
918  u8 phy, int kbps,
919  u32 frameLen, u16 rateix, int shortPreamble);
921  struct ath9k_channel *chan,
922  struct chan_centers *centers);
924 void ath9k_hw_setrxfilter(struct ath_hw *ah, u32 bits);
925 int ath9k_hw_phy_disable(struct ath_hw *ah);
926 int ath9k_hw_disable(struct ath_hw *ah);
927 void ath9k_hw_set_txpowerlimit(struct ath_hw *ah, u32 limit, int test);
928 void ath9k_hw_setopmode(struct ath_hw *ah);
929 void ath9k_hw_setmcastfilter(struct ath_hw *ah, u32 filter0, u32 filter1);
930 void ath9k_hw_setbssidmask(struct ath_hw *ah);
931 void ath9k_hw_write_associd(struct ath_hw *ah);
934 void ath9k_hw_set11nmac2040(struct ath_hw *ah);
935 int ath9k_hw_check_alive(struct ath_hw *ah);
936 
937 int ath9k_hw_setpower(struct ath_hw *ah, enum ath9k_power_mode mode);
938 
939 void ath9k_hw_name(struct ath_hw *ah, char *hw_name, size_t len);
940 
941 /* HTC */
942 void ath9k_hw_htc_resetinit(struct ath_hw *ah);
943 
944 /* PHY */
945 void ath9k_hw_get_delta_slope_vals(struct ath_hw *ah, u32 coef_scaled,
946  u32 *coef_mantissa, u32 *coef_exponent);
947 
948 /*
949  * Code Specific to AR5008, AR9001 or AR9002,
950  * we stuff these here to avoid callbacks for AR9003.
951  */
953 int ar9002_hw_rf_claim(struct ath_hw *ah);
957 
958 /*
959  * Code specific to AR9003, we stuff these here to avoid callbacks
960  * for older families
961  */
963 
964 /* Hardware family op attach helpers */
965 void ar5008_hw_attach_phy_ops(struct ath_hw *ah);
966 void ar9002_hw_attach_phy_ops(struct ath_hw *ah);
967 void ar9003_hw_attach_phy_ops(struct ath_hw *ah);
968 
969 void ar9002_hw_attach_calib_ops(struct ath_hw *ah);
970 void ar9003_hw_attach_calib_ops(struct ath_hw *ah);
971 
972 void ar9002_hw_attach_ops(struct ath_hw *ah);
973 void ar9003_hw_attach_ops(struct ath_hw *ah);
974 
975 void ar9002_hw_load_ani_reg(struct ath_hw *ah, struct ath9k_channel *chan);
976 /*
977  * ANI work can be shared between all families but a next
978  * generation implementation of ANI will be used only for AR9003 only
979  * for now as the other families still need to be tested with the same
980  * next generation ANI. Feel free to start testing it though for the
981  * older families (AR5008, AR9001, AR9002) by using modparam_force_new_ani.
982  */
983 extern int modparam_force_new_ani;
984 void ath9k_ani_reset(struct ath_hw *ah, int is_scanning);
985 void ath9k_hw_proc_mib_event(struct ath_hw *ah);
986 void ath9k_hw_ani_monitor(struct ath_hw *ah, struct ath9k_channel *chan);
987 
988 #define ATH_PCIE_CAP_LINK_CTRL 0x70
989 #define ATH_PCIE_CAP_LINK_L0S 1
990 #define ATH_PCIE_CAP_LINK_L1 2
991 
992 #define ATH9K_CLOCK_RATE_CCK 22
993 #define ATH9K_CLOCK_RATE_5GHZ_OFDM 40
994 #define ATH9K_CLOCK_RATE_2GHZ_OFDM 44
995 #define ATH9K_CLOCK_FAST_RATE_5GHZ_OFDM 44
996 
997 #endif
void ath9k_hw_setmcastfilter(struct ath_hw *ah, u32 filter0, u32 filter1)
Definition: ath9k_hw.c:1958
#define AR9300_MAX_CHAINS
Definition: ar9003_eeprom.h:49
struct ar5416IniArray iniBank0
Definition: hw.h:801
u32 bs_intval
Definition: hw.h:408
u8 index
Definition: hw.h:469
int pcieSerDesWrite
Definition: hw.h:222
uint16_t u16
Definition: stdint.h:21
u32 rfkill_polarity
Definition: hw.h:686
void(* set_delta_slope)(struct ath_hw *ah, struct ath9k_channel *chan)
Definition: hw.h:577
u32 ent_mode
Definition: hw.h:856
u32 proc_phyerr
Definition: hw.h:778
u32 * analogBank7Data
Definition: hw.h:768
u32 txurn_interrupt_mask
Definition: hw.h:706
u8 fast_div_bias
Definition: hw.h:484
int PDADCdelta
Definition: hw.h:794
u16 channel
Definition: hw.h:333
FILE_LICENCE(BSD2)
struct ar5416IniArray iniModes_normal_power_tx_gain_9271
Definition: hw.h:823
u16 channel
Definition: hw.h:349
u32 chanmode
Definition: hw.h:351
u8 paprd_gain_table_index[PAPRD_GAIN_TABLE_ENTRIES]
Definition: hw.h:847
Definition: hw.h:656
struct ath_hw_private_ops private_ops
Definition: hw.h:757
void ath9k_hw_setbssidmask(struct ath_hw *ah)
u16 synth_center
Definition: hw.h:422
u32 intr_txqs
Definition: hw.h:786
int16_t s16
Definition: stdint.h:20
void(* overflow)(void *arg)
Definition: hw.h:467
struct ath_regulatory regulatory
Definition: ath.h:222
int coarse_low[5]
Definition: hw.h:782
void(* read_cachesize)(struct ath_common *common, int *csz)
Definition: hw.h:863
int ar9002_hw_rf_claim(struct ath_hw *ah)
u8 ts_size
Definition: hw.h:839
u16 ts_tail
Definition: hw.h:838
void ath9k_hw_set_gpio(struct ath_hw *ah, u32 gpio, u32 val)
Definition: ath9k_hw.c:1850
u32 enable_ani
Definition: hw.h:231
int spurmode
Definition: hw.h:245
int ath9k_hw_disable(struct ath_hw *ah)
Definition: ath9k_hw.c:1925
struct ath9k_channel * curchan
Definition: hw.h:665
u32 gpio_mask
Definition: hw.h:796
unsigned int paprd_ratemask_ht40
Definition: hw.h:844
u32 globaltxtimeout
Definition: hw.h:775
void(* init_bb)(struct ath_hw *ah, struct ath9k_channel *chan)
Definition: hw.h:571
void ath9k_hw_cfg_output(struct ath_hw *ah, u32 gpio, u32 ah_signal_type)
Definition: ath9k_hw.c:1829
int serialize_regmode
Definition: hw.h:232
struct ar5416IniArray iniRadio[ATH_INI_NUM_SPLIT]
Definition: hw.h:827
u32 pcie_waen
Definition: hw.h:224
void ath9k_hw_write_array(struct ath_hw *ah, struct ar5416IniArray *array, int column, unsigned int *writecnt)
Definition: ath9k_hw.c:111
s16 nominal
Definition: hw.h:649
u32 * analogBank0Data
Definition: hw.h:762
enum ath9k_int imask
Definition: hw.h:700
ath_bus_type
Definition: ath.h:124
u32 misc_mode
Definition: hw.h:749
u16 analog5GhzRev
Definition: hw.h:440
Error codes.
void ath9k_hw_setopmode(struct ath_hw *ah)
Definition: ath9k_hw.c:1953
void(* rx_enable)(struct ath_hw *ah)
Definition: hw.h:607
struct ar5416IniArray iniBB[ATH_INI_NUM_SPLIT]
Definition: hw.h:826
void(* rf_free_ext_banks)(struct ath_hw *ah)
Definition: hw.h:566
int sw_beacon_response_time
Definition: hw.h:217
u8 txpower_limit
Definition: hw.h:772
u16 rts_aggr_limit
Definition: hw.h:200
int(* eeprom_read)(struct ath_common *common, u32 off, u16 *data)
Definition: hw.h:864
#define ATH_MAX_GEN_TIMER
Definition: hw.h:448
#define AR_EEPROM_MODAL_SPURS
Definition: eeprom.h:25
void ar5008_hw_attach_phy_ops(struct ath_hw *ah)
struct ath9k_hw_version hw_version
Definition: hw.h:661
uint8_t type
Type.
Definition: ena.h:16
struct ar5416IniArray iniBank1
Definition: hw.h:803
void(* init_cal_settings)(struct ath_hw *ah)
Definition: hw.h:552
void(* spur_mitigate_freq)(struct ath_hw *ah, struct ath9k_channel *chan)
Definition: hw.h:563
int sw_mgmt_crypto
Definition: hw.h:675
u16 ext_center
Definition: hw.h:424
struct ar5416IniArray iniCommon
Definition: hw.h:800
void ath9k_hw_ani_monitor(struct ath_hw *ah, struct ath9k_channel *chan)
u8 pcie_powersave_enable
Definition: hw.h:221
struct ar5416IniArray iniModesAdditional_40M
Definition: hw.h:813
u16 tx_trig_level
Definition: hw.h:679
int ah_ier
Definition: hw.h:699
ath9k_int
Definition: hw.h:251
enum ath9k_power_mode power_mode
Definition: hw.h:691
u32 * analogBank6Data
Definition: hw.h:766
u32 ath9k_hw_reverse_bits(u32 val, u32 n)
Definition: ath9k_hw.c:125
int(* rf_alloc_ext_banks)(struct ath_hw *ah)
Definition: hw.h:565
int32_t CalValid
Definition: hw.h:335
struct ath_gen_timer_table hw_gen_timers
Definition: hw.h:832
void(* olc_init)(struct ath_hw *ah)
Definition: hw.h:574
struct ath_hw_ops ops
Definition: hw.h:759
u32 cck_trig_low
Definition: hw.h:230
void ath9k_hw_htc_resetinit(struct ath_hw *ah)
u16 bs_bmissthreshold
Definition: hw.h:416
struct ar5416IniArray iniModes_9271_ANI_reg
Definition: hw.h:821
void ath9k_hw_setrxfilter(struct ath_hw *ah, u32 bits)
Definition: ath9k_hw.c:1893
u32 bs_tsfoor_threshold
Definition: hw.h:418
void(* rfbus_done)(struct ath_hw *ah)
Definition: hw.h:579
struct ar5416IniArray iniSOC[ATH_INI_NUM_SPLIT]
Definition: hw.h:828
unsigned int paprd_training_power
Definition: hw.h:842
#define ATH9K_NUM_CHANNELS
Definition: hw.h:74
struct ar5416IniArray iniCommon_normal_cck_fir_coeff_9271
Definition: hw.h:819
struct ar5416_eeprom_4k map4k
Definition: hw.h:669
struct ath_hw_private_ops - callbacks used internally by hardware code
Definition: hw.h:550
int is_monitoring
Definition: hw.h:677
union ath_hw::@28 meas1
struct ar5416IniArray iniModesTxGain
Definition: hw.h:815
void * arg
Definition: hw.h:468
void(* clr11n_aggr)(struct ath_hw *ah, void *ds)
Definition: hw.h:637
u32 txok_interrupt_mask
Definition: hw.h:702
#define PAPRD_TABLE_SZ
Definition: hw.h:167
struct ar5416IniArray iniBank6
Definition: hw.h:806
void(* setup_calibration)(struct ath_hw *ah, struct ath9k_cal_list *currCal)
Definition: hw.h:557
struct ath_ops - Register read/write operations
Definition: ath.h:182
u32 ofdm_trig_high
Definition: hw.h:228
int ath9k_hw_check_alive(struct ath_hw *ah)
Definition: ath9k_hw.c:1189
int pcie_lcr_extsync_en
Definition: hw.h:212
struct net80211_channel * chan
Definition: hw.h:347
u32 channelFlags
Definition: hw.h:350
void ath9k_hw_deinit(struct ath_hw *ah)
Definition: ath9k_hw.c:850
u16 subsysid
Definition: hw.h:442
ath9k_tp_scale
Definition: hw.h:385
void ath9k_hw_name(struct ath_hw *ah, char *hw_name, size_t len)
Definition: ath9k_hw.c:2045
int firpwr[5]
Definition: hw.h:783
int ath9k_hw_fill_cap_info(struct ath_hw *ah)
Definition: ath9k_hw.c:1569
struct ar5416IniArray iniCckfirJapan2484
Definition: hw.h:818
struct ath9k_cal_list adcgain_caldata
Definition: hw.h:713
u32 gen_timer_index[32]
Definition: hw.h:473
struct ar5416IniArray iniBank7
Definition: hw.h:808
void(* extn_synch_en)(struct ath_common *common)
Definition: hw.h:866
struct ar5416IniArray iniBank6TPC
Definition: hw.h:807
u32 bs_nexttbtt
Definition: hw.h:406
void(* antdiv_comb_conf_set)(struct ath_hw *ah, struct ath_hw_antcomb_conf *antconf)
Definition: hw.h:641
void(* mark_phy_inactive)(struct ath_hw *ah)
Definition: hw.h:576
u32 aniperiod
Definition: hw.h:779
void(* set11n_aggr_last)(struct ath_hw *ah, void *ds)
Definition: hw.h:636
void ath9k_hw_write_associd(struct ath_hw *ah)
Definition: ath9k_hw.c:1964
const struct eeprom_ops * eep_ops
Definition: hw.h:673
int ath9k_hw_phy_disable(struct ath_hw *ah)
Definition: ath9k_hw.c:1916
pseudo_bit_t gpio[0x00001]
Definition: arbel.h:30
int(* get_isr)(struct ath_hw *ah, enum ath9k_int *masked)
Definition: hw.h:614
unsigned int pulse_maxlen
Definition: hw.h:516
void ar9003_hw_attach_ops(struct ath_hw *ah)
int htc_reset_init
Definition: hw.h:689
void ar9002_hw_attach_phy_ops(struct ath_hw *ah)
#define PAPRD_GAIN_TABLE_ENTRIES
Definition: hw.h:166
u32 txdesc_interrupt_mask
Definition: hw.h:704
int ext_channel
Definition: hw.h:522
struct ath9k_cal_list iq_caldata
Definition: hw.h:712
ath_usb_dev
Definition: reg.h:885
void ar9002_hw_cck_chan14_spread(struct ath_hw *ah)
u8 max_txtrig_level
Definition: hw.h:247
int nfcal_pending
Definition: hw.h:339
u16 analog2GhzRev
Definition: hw.h:441
uint32_t array
Array number.
Definition: edd.h:30
int(* process_ini)(struct ath_hw *ah, struct ath9k_channel *chan)
Definition: hw.h:573
struct ar5416Stats stats
Definition: hw.h:695
struct ar9287_eeprom map9287
Definition: hw.h:670
struct ath9k_cal_list adcdc_caldata
Definition: hw.h:714
ath9k_key_type
Definition: mac.h:664
struct ath9k_pacal_info pacal_info
Definition: hw.h:694
u32 txerr_interrupt_mask
Definition: hw.h:703
u32 imrs2_reg
Definition: hw.h:701
void(* bt_coex_prep)(struct ath_common *common)
Definition: hw.h:865
ath9k_power_mode
Definition: hw.h:378
u32 * bank6Temp
Definition: hw.h:770
struct ar5416IniArray iniModes
Definition: hw.h:799
void ar9003_hw_attach_calib_ops(struct ath_hw *ah)
void ar9002_hw_enable_wep_aggregation(struct ath_hw *ah)
unsigned int pulse_inband_step
Definition: hw.h:513
unsigned int pulse_height
Definition: hw.h:514
struct ar5416IniArray iniModes_9271_1_0_only
Definition: hw.h:816
ath_hw_txq_subtype
Definition: hw.h:169
static struct ath_regulatory * ath9k_hw_regulatory(struct ath_hw *ah)
Definition: hw.h:874
#define u32
Definition: vga.h:21
int(* set_rf_regs)(struct ath_hw *ah, struct ath9k_channel *chan, u16 modesIndex)
Definition: hw.h:567
struct ath9k_tx_queue_info txq[ATH9K_NUM_TX_QUEUES]
Definition: hw.h:696
unsigned int radar_rssi
Definition: hw.h:518
u32 WARegVal
Definition: hw.h:853
ser_reg_mode
Definition: hw.h:393
u32 link
Link to next descriptor.
Definition: ar9003_mac.h:68
void(* ani_cache_ini_regs)(struct ath_hw *ah)
Definition: hw.h:591
void ath9k_hw_set_txpowerlimit(struct ath_hw *ah, u32 limit, int test)
Definition: ath9k_hw.c:1937
signed char int8_t
Definition: stdint.h:15
void(* trigger)(void *arg)
Definition: hw.h:466
u32 pa_table[AR9300_MAX_CHAINS][PAPRD_TABLE_SZ]
Definition: hw.h:342
int8_t iCoff
Definition: hw.h:336
struct ath9k_ops_config config
Definition: hw.h:662
int need_an_top2_fixup
Definition: hw.h:678
struct ar5416IniArray iniCommon_japan_2484_cck_fir_coeff_9271
Definition: hw.h:820
int totalSizeDesired[5]
Definition: hw.h:780
u32 intr_gen_timer_trigger
Definition: hw.h:830
int fir_power
Definition: hw.h:520
int paprd_table_write_done
Definition: hw.h:845
void ath9k_hw_get_channel_centers(struct ath_hw *ah, struct ath9k_channel *chan, struct chan_centers *centers)
u32 * analogBank1Data
Definition: hw.h:763
int rx_intr_mitigation
Definition: hw.h:233
struct ath_ops reg_ops
Definition: hw.h:657
struct ar5416IniArray iniBank2
Definition: hw.h:804
pseudo_bit_t value[0x00020]
Definition: arbel.h:13
u16 ani_poll_interval
Definition: hw.h:248
void(* set11n_ratescenario)(struct ath_hw *ah, void *ds, void *lastds, u32 durUpdateEn, u32 rtsctsRate, u32 rtsctsDuration, struct ath9k_11n_rate_series series[], u32 nseries, u32 flags)
Definition: hw.h:626
int ath9k_hw_setpower(struct ath_hw *ah, enum ath9k_power_mode mode)
Definition: ath9k_hw.c:1532
struct ath_gen_timer * timers[ATH_MAX_GEN_TIMER]
Definition: hw.h:474
u32 * analogBank6TPCData
Definition: hw.h:767
uint16_t limit
Limit.
Definition: librm.h:250
struct ar5416IniArray iniPcieSerdesLowPower
Definition: hw.h:811
struct ar5416IniArray iniBB_RfGain
Definition: hw.h:802
void(* init_mode_regs)(struct ath_hw *ah)
Definition: hw.h:555
unsigned long timer_bits
Definition: hw.h:476
unsigned int paprd_ratemask
Definition: hw.h:843
u32 nf_regs[6]
Definition: hw.h:681
static unsigned int unsigned int reg
Definition: intel.h:245
struct ath_hw_radar_conf - radar detection initialization parameters
Definition: hw.h:511
u32 bs_sleepduration
Definition: hw.h:417
u32 originalGain[22]
Definition: hw.h:792
struct hv_monitor_parameter param[4][32]
Parameters.
Definition: hyperv.h:24
Structure encapsulating the complete state of an 802.11 device.
Definition: net80211.h:786
u32 ath9k_hw_gpio_get(struct ath_hw *ah, u32 gpio)
Definition: ath9k_hw.c:1802
int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan, struct ath9k_hw_cal_data *caldata, int bChannelChange)
Definition: ath9k_hw.c:1216
An 802.11 RF channel.
Definition: net80211.h:385
struct ath_hw_ops - callbacks used by hardware code and driver code
Definition: hw.h:603
uint32_t column[4]
Viewed as an array of four-byte columns.
Definition: aes.h:14
void(* set11n_txdesc)(struct ath_hw *ah, void *ds, u32 pktLen, enum ath9k_pkt_type type, u32 txPower, u32 keyIx, enum ath9k_key_type keyType, u32 flags)
Definition: hw.h:621
int(* calibrate)(struct ath_hw *ah, struct ath9k_channel *chan, u8 rxchainmask, int longcal)
Definition: hw.h:610
u32 macVersion
Definition: hw.h:437
u32 gpio_val
Definition: hw.h:797
void ath9k_hw_init_global_settings(struct ath_hw *ah)
Definition: ath9k_hw.c:812
#define ATH9K_NUM_TX_QUEUES
Definition: mac.h:580
static struct ath_common * ath9k_hw_common(struct ath_hw *ah)
Definition: hw.h:869
void ar9002_hw_load_ani_reg(struct ath_hw *ah, struct ath9k_channel *chan)
struct ar5416IniArray iniCckfirNormal
Definition: hw.h:817
union ath_hw::@30 meas3
void ath9k_hw_get_delta_slope_vals(struct ath_hw *ah, u32 coef_scaled, u32 *coef_mantissa, u32 *coef_exponent)
void(* config_pci_powersave)(struct ath_hw *ah, int restore, int power_off)
Definition: hw.h:604
struct ar5416IniArray iniModes_high_power_tx_gain_9271
Definition: hw.h:822
void(* init_mode_gain_regs)(struct ath_hw *ah)
Definition: hw.h:556
void ath9k_hw_setantenna(struct ath_hw *ah, u32 antenna)
Definition: ath9k_hw.c:1871
u32 supp_cals
Definition: hw.h:711
int nfcal_interference
Definition: hw.h:340
unsigned int radar_inband
Definition: hw.h:519
struct ath9k_cal_list * cal_list_last
Definition: hw.h:717
u32 atim_window
Definition: hw.h:708
u8 analog_shiftreg
Definition: hw.h:225
union ath_hw::@26 eeprom
void(* set_clrdmask)(struct ath_hw *ah, void *ds, int val)
Definition: hw.h:638
enum ath9k_ani_cmd ani_function
Definition: hw.h:784
unsigned int pulse_rssi
Definition: hw.h:515
u8 rxchainmask
Definition: hw.h:788
u16 spurchans[AR_EEPROM_MODAL_SPURS][2]
Definition: hw.h:246
int coarse_high[5]
Definition: hw.h:781
struct ib_cm_common common
Definition: ib_mad.h:11
void ath9k_hw_set11nmac2040(struct ath_hw *ah)
Definition: ath9k_hw.c:1973
uint32_t ds
Definition: librm.h:254
s16 min
Definition: hw.h:648
void(* set_rfmode)(struct ath_hw *ah, struct ath9k_channel *chan)
Definition: hw.h:575
int ath9k_hw_init(struct ath_hw *ah)
Definition: ath9k_hw.c:569
struct net80211_device * dev
Definition: hw.h:659
int modparam_force_new_ani
void __asmcall int val
Definition: setjmp.h:28
u32 * analogBank3Data
Definition: hw.h:765
int16_t curchan_rad_index
Definition: hw.h:698
void(* set_diversity)(struct ath_hw *ah, int value)
Definition: hw.h:581
enum ath_bus_type ath_bus_type
Definition: hw.h:862
union ath_gen_timer_table::@25 timer_mask
#define AR5416_MAX_CHAINS
Definition: eeprom.h:159
unsigned int paprd_target_power
Definition: hw.h:841
u16 devid
Definition: hw.h:435
int ack_6mb
Definition: hw.h:219
void ar9002_hw_attach_calib_ops(struct ath_hw *ah)
enum ath_hw::@31 enable_32kHz_clock
u32 ah_flags
Definition: hw.h:687
s16 noisefloor
Definition: hw.h:352
struct ar9300_eeprom ar9300_eep
Definition: hw.h:671
u16 subvendorid
Definition: hw.h:436
static struct ath_hw_ops * ath9k_hw_ops(struct ath_hw *ah)
Definition: hw.h:884
struct ath9k_cal_list tempCompCalData
Definition: hw.h:715
void ath9k_hw_proc_mib_event(struct ath_hw *ah)
int(* proc_txdesc)(struct ath_hw *ah, void *ds, struct ath_tx_status *ts)
Definition: hw.h:619
void ar9002_hw_attach_ops(struct ath_hw *ah)
ath9k_ani_cmd
Definition: ani.h:80
int(* rfbus_req)(struct ath_hw *ah)
Definition: hw.h:578
struct ath_nf_limits nf_2g
Definition: hw.h:682
#define BIT(nr)
Definition: ath.h:32
struct ath_nf_limits nf_5g
Definition: hw.h:683
signed int int32_t
Definition: stdint.h:17
void ar9003_hw_attach_phy_ops(struct ath_hw *ah)
int chip_fullsleep
Definition: hw.h:707
void(* set11n_aggr_middle)(struct ath_hw *ah, void *ds, u32 numDelims)
Definition: hw.h:634
u32 ts_paddr_start
Definition: hw.h:836
struct ar5416IniArray iniModesAdditional
Definition: hw.h:812
void ar9003_hw_disable_phy_restart(struct ath_hw *ah)
u32 * analogBank2Data
Definition: hw.h:764
static volatile void * bits
Definition: bitops.h:27
int initPDADC
Definition: hw.h:793
uint32_t len
Length.
Definition: ena.h:14
struct ar9003_txs * ts_ring
Definition: hw.h:834
struct ar5416AniState ani
Definition: hw.h:348
int lna1_lna2_delta
Definition: hw.h:487
struct ath9k_hw_capabilities caps
Definition: hw.h:663
u8 paprd_disable
Definition: hw.h:226
u32 txeol_interrupt_mask
Definition: hw.h:705
int8_t qCoff
Definition: hw.h:337
u32 cwm_ignore_extcca
Definition: hw.h:220
u16 pcie_lcr_offset
Definition: hw.h:211
struct ar5416IniArray iniAddac
Definition: hw.h:809
void ath9k_hw_cfg_gpio_input(struct ath_hw *ah, u32 gpio)
Definition: ath9k_hw.c:1783
int is_pciexpress
Definition: hw.h:676
u16 rfsilent
Definition: hw.h:684
#define NUM_NF_READINGS
Definition: calib.h:30
void ar9002_hw_update_async_fifo(struct ath_hw *ah)
struct ar5416IniArray iniMac[ATH_INI_NUM_SPLIT]
Definition: hw.h:825
u32 channelFlags
Definition: hw.h:334
u16 phyRev
Definition: hw.h:439
int(* ani_control)(struct ath_hw *ah, enum ath9k_ani_cmd cmd, int param)
Definition: hw.h:584
u32 ath9k_hw_getdefantenna(struct ath_hw *ah)
Definition: ath9k_hw.c:1866
int paprd_done
Definition: hw.h:338
int led_pin
Definition: hw.h:795
u32 magic
Definition: hw.h:434
union ath_hw::@29 meas2
int additional_swba_backoff
Definition: hw.h:218
void(* antdiv_comb_conf_get)(struct ath_hw *ah, struct ath_hw_antcomb_conf *antconf)
Definition: hw.h:639
const char * ath9k_hw_probe(u16 vendorid, u16 devid)
int(* rf_set_freq)(struct ath_hw *ah, struct ath9k_channel *chan)
Definition: hw.h:561
u32 ath9k_regd_get_ctl(struct ath_regulatory *reg, struct ath9k_channel *chan)
Definition: ath9k_hw.c:867
void(* set11n_aggr_first)(struct ath_hw *ah, void *ds, u32 aggrLen)
Definition: hw.h:632
u32 intr_gen_timer_thresh
Definition: hw.h:831
void(* set_channel_regs)(struct ath_hw *ah, struct ath9k_channel *chan)
Definition: hw.h:570
u16 ath9k_hw_computetxtime(struct ath_hw *ah, u8 phy, int kbps, u32 frameLen, u16 rateix, int shortPreamble)
Definition: ath9k_hw.c:137
struct ath_common common
Definition: hw.h:660
unsigned int pulse_inband
Definition: hw.h:512
struct ath9k_cal_list * cal_list
Definition: hw.h:716
s16 max
Definition: hw.h:647
u8 main_lna_conf
Definition: hw.h:482
uint8_t ah
Definition: registers.h:85
ath_ini_subsys
Definition: hw.h:173
void timeout(int)
u32 sta_id1_defaults
Definition: hw.h:748
u32(* compute_pll_control)(struct ath_hw *ah, struct ath9k_channel *chan)
Definition: hw.h:582
unsigned int n
Definition: entropy.h:159
void * ts_start
Definition: hw.h:835
void(* set_radar_params)(struct ath_hw *ah, struct ath_hw_radar_conf *conf)
Definition: hw.h:587
u16 bs_cfpperiod
Definition: hw.h:412
int is_clk_25mhz
Definition: hw.h:858
struct ath9k_channel channels[ATH9K_NUM_CHANNELS]
Definition: hw.h:664
signed short int16_t
Definition: stdint.h:16
static struct ath_hw_private_ops * ath9k_hw_private_ops(struct ath_hw *ah)
Definition: hw.h:879
struct arbelprm_port_state_change_st data
Message.
Definition: arbel.h:12
u16 macRev
Definition: hw.h:438
struct ath_hw_radar_conf radar_conf
Definition: hw.h:790
void(* do_getnf)(struct ath_hw *ah, int16_t nfarray[NUM_NF_READINGS])
Definition: hw.h:586
struct ar5416_eeprom_def def
Definition: hw.h:668
u8 txchainmask
Definition: hw.h:787
int coverage_class
Definition: hw.h:773
u32 * addac5416_21
Definition: hw.h:769
void(* restore_chainmask)(struct ath_hw *ah)
Definition: hw.h:580
ath9k_pkt_type
Definition: mac.h:604
struct ath9k_hw_cal_data * caldata
Definition: hw.h:693
u32 bs_cfpnext
Definition: hw.h:414
void ath9k_ani_reset(struct ath_hw *ah, int is_scanning)
Definition: ath9k_ani.c:466
u32 ofdm_trig_low
Definition: hw.h:227
void(* fill_txdesc)(struct ath_hw *ah, void *ds, u32 seglen, int is_firstseg, int is_is_lastseg, const void *ds0, u32 buf_addr, unsigned int qcu)
Definition: hw.h:615
struct ar5416IniArray iniPcieSerdes
Definition: hw.h:810
u32 ts_paddr_end
Definition: hw.h:837
u16 small_signal_gain[AR9300_MAX_CHAINS]
Definition: hw.h:341
u32 cck_trig_high
Definition: hw.h:229
enum ath_usb_dev usbdev
Definition: hw.h:443
u32 ar9003_get_pll_sqsum_dvc(struct ath_hw *ah)
Definition: ath9k_hw.c:609
ath9k_hw_caps
Definition: hw.h:180
struct golan_eqe_cmd cmd
Definition: CIB_PRM.h:29
u16 bs_cfpmaxduration
Definition: hw.h:413
ath9k_rx_qtype
Definition: hw.h:399
u32 unsign[AR5416_MAX_CHAINS]
Definition: hw.h:731
struct ar5416IniArray iniBank3
Definition: hw.h:805
u8 pcie_clock_req
Definition: hw.h:223
void(* get_desc_link)(void *ds, u32 **link)
Definition: hw.h:609
static u8 get_streams(int mask)
Definition: hw.h:889
struct ath9k_cal_list * cal_list_curr
Definition: hw.h:718
u32 rfkill_gpio
Definition: hw.h:685
uint8_t u8
Definition: stdint.h:19
static int test
Definition: epic100.c:73
u32 bs_nextdtim
Definition: hw.h:407
int tx_intr_mitigation
Definition: hw.h:234
uint32_t u32
Definition: stdint.h:23
struct ar5416IniArray iniModesRxGain
Definition: hw.h:814
u32 ath9k_hw_getrxfilter(struct ath_hw *ah)
Definition: ath9k_hw.c:1880
int(* init_cal)(struct ath_hw *ah, struct ath9k_channel *chan)
Definition: hw.h:553
u32 bs_dtimperiod
Definition: hw.h:411
u32 paprd_gain_table_entries[PAPRD_GAIN_TABLE_ENTRIES]
Definition: hw.h:846
union ath_hw::@27 meas0
void ar9002_hw_enable_async_fifo(struct ath_hw *ah)
u16 bs_timoffset
Definition: hw.h:415
struct ath9k_nfcal_hist nfCalHist[NUM_NF_READINGS]
Definition: hw.h:343
int32_t sign[AR5416_MAX_CHAINS]
Definition: hw.h:732
u16 cal_samples
Definition: hw.h:746
int ath9k_hw_wait(struct ath_hw *ah, u32 reg, u32 mask, u32 val, u32 timeout)
Definition: ath9k_hw.c:93
int dma_beacon_response_time
Definition: hw.h:216
uint8_t flags
Flags.
Definition: ena.h:18
void(* set_desc_link)(void *ds, u32 link)
Definition: hw.h:608
u32 slottime
Definition: hw.h:774
u16 ctl_center
Definition: hw.h:423