iPXE
ath9k_ar9003_phy.c
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1 /*
2  * Copyright (c) 2010-2011 Atheros Communications Inc.
3  *
4  * Modified for iPXE by Scott K Logan <logans@cottsay.net> July 2011
5  * Original from Linux kernel 3.0.1
6  *
7  * Permission to use, copy, modify, and/or distribute this software for any
8  * purpose with or without fee is hereby granted, provided that the above
9  * copyright notice and this permission notice appear in all copies.
10  *
11  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
12  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
13  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
14  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
15  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
16  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
17  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
18  */
19 
20 #include <ipxe/io.h>
21 
22 #include "hw.h"
23 #include "ar9003_phy.h"
24 
25 static const int firstep_table[] =
26 /* level: 0 1 2 3 4 5 6 7 8 */
27  { -4, -2, 0, 2, 4, 6, 8, 10, 12 }; /* lvl 0-8, default 2 */
28 
29 static const int cycpwrThr1_table[] =
30 /* level: 0 1 2 3 4 5 6 7 8 */
31  { -6, -4, -2, 0, 2, 4, 6, 8 }; /* lvl 0-7, default 3 */
32 
33 /*
34  * register values to turn OFDM weak signal detection OFF
35  */
36 static const int m1ThreshLow_off = 127;
37 static const int m2ThreshLow_off = 127;
38 static const int m1Thresh_off = 127;
39 static const int m2Thresh_off = 127;
40 static const int m2CountThr_off = 31;
41 static const int m2CountThrLow_off = 63;
42 static const int m1ThreshLowExt_off = 127;
43 static const int m2ThreshLowExt_off = 127;
44 static const int m1ThreshExt_off = 127;
45 static const int m2ThreshExt_off = 127;
46 
47 /**
48  * ar9003_hw_set_channel - set channel on single-chip device
49  * @ah: atheros hardware structure
50  * @chan:
51  *
52  * This is the function to change channel on single-chip devices, that is
53  * all devices after ar9280.
54  *
55  * This function takes the channel value in MHz and sets
56  * hardware channel value. Assumes writes have been enabled to analog bus.
57  *
58  * Actual Expression,
59  *
60  * For 2GHz channel,
61  * Channel Frequency = (3/4) * freq_ref * (chansel[8:0] + chanfrac[16:0]/2^17)
62  * (freq_ref = 40MHz)
63  *
64  * For 5GHz channel,
65  * Channel Frequency = (3/2) * freq_ref * (chansel[8:0] + chanfrac[16:0]/2^10)
66  * (freq_ref = 40MHz/(24>>amodeRefSel))
67  *
68  * For 5GHz channels which are 5MHz spaced,
69  * Channel Frequency = (3/2) * freq_ref * (chansel[8:0] + chanfrac[16:0]/2^17)
70  * (freq_ref = 40MHz)
71  */
72 static int ar9003_hw_set_channel(struct ath_hw *ah, struct ath9k_channel *chan)
73 {
74  u16 bMode, fracMode = 0, aModeRefSel = 0;
75  u32 freq, channelSel = 0, reg32 = 0;
76  struct chan_centers centers;
77  int loadSynthChannel;
78 
79  ath9k_hw_get_channel_centers(ah, chan, &centers);
80  freq = centers.synth_center;
81 
82  if (freq < 4800) { /* 2 GHz, fractional mode */
83  if (AR_SREV_9485(ah)) {
84  u32 chan_frac;
85 
86  /*
87  * freq_ref = 40 / (refdiva >> amoderefsel); where refdiva=1 and amoderefsel=0
88  * ndiv = ((chan_mhz * 4) / 3) / freq_ref;
89  * chansel = int(ndiv), chanfrac = (ndiv - chansel) * 0x20000
90  */
91  channelSel = (freq * 4) / 120;
92  chan_frac = (((freq * 4) % 120) * 0x20000) / 120;
93  channelSel = (channelSel << 17) | chan_frac;
94  } else if (AR_SREV_9340(ah)) {
95  if (ah->is_clk_25mhz) {
96  u32 chan_frac;
97 
98  channelSel = (freq * 2) / 75;
99  chan_frac = (((freq * 2) % 75) * 0x20000) / 75;
100  channelSel = (channelSel << 17) | chan_frac;
101  } else
102  channelSel = CHANSEL_2G(freq) >> 1;
103  } else
104  channelSel = CHANSEL_2G(freq);
105  /* Set to 2G mode */
106  bMode = 1;
107  } else {
108  if (AR_SREV_9340(ah) && ah->is_clk_25mhz) {
109  u32 chan_frac;
110 
111  channelSel = (freq * 2) / 75;
112  chan_frac = ((freq % 75) * 0x20000) / 75;
113  channelSel = (channelSel << 17) | chan_frac;
114  } else {
115  channelSel = CHANSEL_5G(freq);
116  /* Doubler is ON, so, divide channelSel by 2. */
117  channelSel >>= 1;
118  }
119  /* Set to 5G mode */
120  bMode = 0;
121  }
122 
123  /* Enable fractional mode for all channels */
124  fracMode = 1;
125  aModeRefSel = 0;
126  loadSynthChannel = 0;
127 
128  reg32 = (bMode << 29);
130 
131  /* Enable Long shift Select for Synthesizer */
134 
135  /* Program Synth. setting */
136  reg32 = (channelSel << 2) | (fracMode << 30) |
137  (aModeRefSel << 28) | (loadSynthChannel << 31);
139 
140  /* Toggle Load Synth channel bit */
141  loadSynthChannel = 1;
142  reg32 = (channelSel << 2) | (fracMode << 30) |
143  (aModeRefSel << 28) | (loadSynthChannel << 31);
145 
146  ah->curchan = chan;
147  ah->curchan_rad_index = -1;
148 
149  return 0;
150 }
151 
152 /**
153  * ar9003_hw_spur_mitigate_mrc_cck - convert baseband spur frequency
154  * @ah: atheros hardware structure
155  * @chan:
156  *
157  * For single-chip solutions. Converts to baseband spur frequency given the
158  * input channel frequency and compute register settings below.
159  *
160  * Spur mitigation for MRC CCK
161  */
163  struct ath9k_channel *chan)
164 {
165  static const u32 spur_freq[4] = { 2420, 2440, 2464, 2480 };
166  int cur_bb_spur, negative = 0, cck_spur_freq;
167  int i;
168  int range, max_spur_cnts, synth_freq;
169  u8 *spur_fbin_ptr = NULL;
170 
171  /*
172  * Need to verify range +/- 10 MHz in control channel, otherwise spur
173  * is out-of-band and can be ignored.
174  */
175 
176  if (AR_SREV_9485(ah) || AR_SREV_9340(ah)) {
177  spur_fbin_ptr = ar9003_get_spur_chan_ptr(ah,
178  IS_CHAN_2GHZ(chan));
179  if (spur_fbin_ptr[0] == 0) /* No spur */
180  return;
181  max_spur_cnts = 5;
182  if (IS_CHAN_HT40(chan)) {
183  range = 19;
186  synth_freq = chan->channel + 10;
187  else
188  synth_freq = chan->channel - 10;
189  } else {
190  range = 10;
191  synth_freq = chan->channel;
192  }
193  } else {
194  range = 10;
195  max_spur_cnts = 4;
196  synth_freq = chan->channel;
197  }
198 
199  for (i = 0; i < max_spur_cnts; i++) {
200  negative = 0;
201  if (AR_SREV_9485(ah) || AR_SREV_9340(ah))
202  cur_bb_spur = FBIN2FREQ(spur_fbin_ptr[i],
203  IS_CHAN_2GHZ(chan)) - synth_freq;
204  else
205  cur_bb_spur = spur_freq[i] - synth_freq;
206 
207  if (cur_bb_spur < 0) {
208  negative = 1;
209  cur_bb_spur = -cur_bb_spur;
210  }
211  if (cur_bb_spur < range) {
212  cck_spur_freq = (int)((cur_bb_spur << 19) / 11);
213 
214  if (negative == 1)
215  cck_spur_freq = -cck_spur_freq;
216 
217  cck_spur_freq = cck_spur_freq & 0xfffff;
218 
225  0x2);
228  0x1);
231  cck_spur_freq);
232 
233  return;
234  }
235  }
236 
243 }
244 
245 /* Clean all spur register fields */
246 static void ar9003_hw_spur_ofdm_clear(struct ath_hw *ah)
247 {
266 
287 }
288 
289 static void ar9003_hw_spur_ofdm(struct ath_hw *ah,
290  int freq_offset,
291  int spur_freq_sd,
292  int spur_delta_phase,
293  int spur_subchannel_sd)
294 {
295  int mask_index = 0;
296 
297  /* OFDM Spur mitigation */
301  AR_PHY_TIMING11_SPUR_FREQ_SD, spur_freq_sd);
303  AR_PHY_TIMING11_SPUR_DELTA_PHASE, spur_delta_phase);
305  AR_PHY_SFCORR_EXT_SPUR_SUBCHANNEL_SD, spur_subchannel_sd);
316 
318  AR_PHY_MODE_DYNAMIC) == 0x1)
321 
322  mask_index = (freq_offset << 4) / 5;
323  if (mask_index < 0)
324  mask_index = mask_index - 1;
325 
326  mask_index = mask_index & 0x7f;
327 
348 }
349 
350 static void ar9003_hw_spur_ofdm_work(struct ath_hw *ah,
351  struct ath9k_channel *chan,
352  int freq_offset)
353 {
354  int spur_freq_sd = 0;
355  int spur_subchannel_sd = 0;
356  int spur_delta_phase = 0;
357 
358  if (IS_CHAN_HT40(chan)) {
359  if (freq_offset < 0) {
361  AR_PHY_GC_DYN2040_PRI_CH) == 0x0)
362  spur_subchannel_sd = 1;
363  else
364  spur_subchannel_sd = 0;
365 
366  spur_freq_sd = ((freq_offset + 10) << 9) / 11;
367 
368  } else {
370  AR_PHY_GC_DYN2040_PRI_CH) == 0x0)
371  spur_subchannel_sd = 0;
372  else
373  spur_subchannel_sd = 1;
374 
375  spur_freq_sd = ((freq_offset - 10) << 9) / 11;
376 
377  }
378 
379  spur_delta_phase = (freq_offset << 17) / 5;
380 
381  } else {
382  spur_subchannel_sd = 0;
383  spur_freq_sd = (freq_offset << 9) /11;
384  spur_delta_phase = (freq_offset << 18) / 5;
385  }
386 
387  spur_freq_sd = spur_freq_sd & 0x3ff;
388  spur_delta_phase = spur_delta_phase & 0xfffff;
389 
391  freq_offset,
392  spur_freq_sd,
393  spur_delta_phase,
394  spur_subchannel_sd);
395 }
396 
397 /* Spur mitigation for OFDM */
399  struct ath9k_channel *chan)
400 {
401  int synth_freq;
402  int range = 10;
403  int freq_offset = 0;
404  int mode;
405  u8* spurChansPtr;
406  unsigned int i;
407  struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
408 
409  if (IS_CHAN_5GHZ(chan)) {
410  spurChansPtr = &(eep->modalHeader5G.spurChans[0]);
411  mode = 0;
412  }
413  else {
414  spurChansPtr = &(eep->modalHeader2G.spurChans[0]);
415  mode = 1;
416  }
417 
418  if (spurChansPtr[0] == 0)
419  return; /* No spur in the mode */
420 
421  if (IS_CHAN_HT40(chan)) {
422  range = 19;
424  AR_PHY_GC_DYN2040_PRI_CH) == 0x0)
425  synth_freq = chan->channel - 10;
426  else
427  synth_freq = chan->channel + 10;
428  } else {
429  range = 10;
430  synth_freq = chan->channel;
431  }
432 
434 
435  for (i = 0; i < AR_EEPROM_MODAL_SPURS && spurChansPtr[i]; i++) {
436  freq_offset = FBIN2FREQ(spurChansPtr[i], mode) - synth_freq;
437  if (abs(freq_offset) < range) {
438  ar9003_hw_spur_ofdm_work(ah, chan, freq_offset);
439  break;
440  }
441  }
442 }
443 
444 static void ar9003_hw_spur_mitigate(struct ath_hw *ah,
445  struct ath9k_channel *chan)
446 {
449 }
450 
452  struct ath9k_channel *chan)
453 {
454  u32 pll;
455 
456  pll = SM(0x5, AR_RTC_9300_PLL_REFDIV);
457 
458  if (chan && IS_CHAN_HALF_RATE(chan))
459  pll |= SM(0x1, AR_RTC_9300_PLL_CLKSEL);
460  else if (chan && IS_CHAN_QUARTER_RATE(chan))
461  pll |= SM(0x2, AR_RTC_9300_PLL_CLKSEL);
462 
463  pll |= SM(0x2c, AR_RTC_9300_PLL_DIV);
464 
465  return pll;
466 }
467 
469  struct ath9k_channel *chan)
470 {
471  u32 phymode;
472  u32 enableDacFifo = 0;
473 
474  enableDacFifo =
476 
477  /* Enable 11n HT, 20 MHz */
479  AR_PHY_GC_SHORT_GI_40 | enableDacFifo;
480 
481  /* Configure baseband for dynamic 20/40 operation */
482  if (IS_CHAN_HT40(chan)) {
483  phymode |= AR_PHY_GC_DYN2040_EN;
484  /* Configure control (primary) channel at +-10MHz */
485  if ((chan->chanmode == CHANNEL_A_HT40PLUS) ||
486  (chan->chanmode == CHANNEL_G_HT40PLUS))
487  phymode |= AR_PHY_GC_DYN2040_PRI_CH;
488 
489  }
490 
491  /* make sure we preserve INI settings */
492  phymode |= REG_READ(ah, AR_PHY_GEN_CTRL);
493  /* turn off Green Field detection for STA for now */
494  phymode &= ~AR_PHY_GC_GF_DETECT_EN;
495 
496  REG_WRITE(ah, AR_PHY_GEN_CTRL, phymode);
497 
498  /* Configure MAC for 20/40 operation */
500 
501  /* global transmit timeout (25 TUs default)*/
503  /* carrier sense timeout */
505 }
506 
507 static void ar9003_hw_init_bb(struct ath_hw *ah,
508  struct ath9k_channel *chan)
509 {
510  u32 synthDelay;
511 
512  /*
513  * Wait for the frequency synth to settle (synth goes on
514  * via AR_PHY_ACTIVE_EN). Read the phy active delay register.
515  * Value is in 100ns increments.
516  */
518  if (IS_CHAN_B(chan))
519  synthDelay = (4 * synthDelay) / 22;
520  else
521  synthDelay /= 10;
522 
523  /* Activate the PHY (includes baseband activate + synthesizer on) */
525 
526  /*
527  * There is an issue if the AP starts the calibration before
528  * the base band timeout completes. This could result in the
529  * rx_clear false triggering. As a workaround we add delay an
530  * extra BASE_ACTIVATE_DELAY usecs to ensure this condition
531  * does not happen.
532  */
533  udelay(synthDelay + BASE_ACTIVATE_DELAY);
534 }
535 
537 {
538  switch (rx) {
539  case 0x5:
542  /* Fall through */
543  case 0x3:
544  case 0x1:
545  case 0x2:
546  case 0x7:
549  break;
550  default:
551  break;
552  }
553 
554  if ((ah->caps.hw_caps & ATH9K_HW_CAP_APM) && (tx == 0x7))
556  else
558 
559  if (tx == 0x5) {
562  }
563 }
564 
565 /*
566  * Override INI values with chip specific configuration.
567  */
568 static void ar9003_hw_override_ini(struct ath_hw *ah)
569 {
570  u32 val;
571 
572  /*
573  * Set the RX_ABORT and RX_DIS and clear it only after
574  * RXE is set for MAC. This prevents frames with
575  * corrupted descriptor status.
576  */
578 
579  /*
580  * For AR9280 and above, there is a new feature that allows
581  * Multicast search based on both MAC Address and Key ID. By default,
582  * this feature is enabled. But since the driver is not using this
583  * feature, we switch it off; otherwise multicast search based on
584  * MAC addr only will fail.
585  */
589 }
590 
591 static void ar9003_hw_prog_ini(struct ath_hw *ah,
592  struct ar5416IniArray *iniArr,
593  int column)
594 {
595  unsigned int i, regWrites = 0;
596 
597  /* New INI format: Array may be undefined (pre, core, post arrays) */
598  if (!iniArr->ia_array)
599  return;
600 
601  /*
602  * New INI format: Pre, core, and post arrays for a given subsystem
603  * may be modal (> 2 columns) or non-modal (2 columns). Determine if
604  * the array is non-modal and force the column to 1.
605  */
606  if ((unsigned int)column >= iniArr->ia_columns)
607  column = 1;
608 
609  for (i = 0; i < iniArr->ia_rows; i++) {
610  u32 reg = INI_RA(iniArr, i, 0);
611  u32 val = INI_RA(iniArr, i, column);
612 
613  REG_WRITE(ah, reg, val);
614 
615  DO_DELAY(regWrites);
616  }
617 }
618 
619 static int ar9003_hw_process_ini(struct ath_hw *ah,
620  struct ath9k_channel *chan)
621 {
622  struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
623  unsigned int regWrites = 0, i;
624  struct net80211_channel *channel = chan->chan;
625  u32 modesIndex;
626 
627  switch (chan->chanmode) {
628  case CHANNEL_A:
629  case CHANNEL_A_HT20:
630  modesIndex = 1;
631  break;
632  case CHANNEL_A_HT40PLUS:
633  case CHANNEL_A_HT40MINUS:
634  modesIndex = 2;
635  break;
636  case CHANNEL_G:
637  case CHANNEL_G_HT20:
638  case CHANNEL_B:
639  modesIndex = 4;
640  break;
641  case CHANNEL_G_HT40PLUS:
642  case CHANNEL_G_HT40MINUS:
643  modesIndex = 3;
644  break;
645 
646  default:
647  return -EINVAL;
648  }
649 
650  for (i = 0; i < ATH_INI_NUM_SPLIT; i++) {
651  ar9003_hw_prog_ini(ah, &ah->iniSOC[i], modesIndex);
652  ar9003_hw_prog_ini(ah, &ah->iniMac[i], modesIndex);
653  ar9003_hw_prog_ini(ah, &ah->iniBB[i], modesIndex);
654  ar9003_hw_prog_ini(ah, &ah->iniRadio[i], modesIndex);
655  }
656 
657  REG_WRITE_ARRAY(&ah->iniModesRxGain, 1, regWrites);
658  REG_WRITE_ARRAY(&ah->iniModesTxGain, modesIndex, regWrites);
659 
660  /*
661  * For 5GHz channels requiring Fast Clock, apply
662  * different modal values.
663  */
664  if (IS_CHAN_A_FAST_CLOCK(ah, chan))
665  REG_WRITE_ARRAY(&ah->iniModesAdditional,
666  modesIndex, regWrites);
667 
668  if (AR_SREV_9340(ah) && !ah->is_clk_25mhz)
669  REG_WRITE_ARRAY(&ah->iniModesAdditional_40M, 1, regWrites);
670 
673  ar9003_hw_set_chain_masks(ah, ah->rxchainmask, ah->txchainmask);
674 
675  /* Set TX power */
676  ah->eep_ops->set_txpower(ah, chan,
677  ath9k_regd_get_ctl(regulatory, chan),
678  0,
679  channel->maxpower * 2,
681  (u32) regulatory->power_limit), 0);
682 
683  return 0;
684 }
685 
686 static void ar9003_hw_set_rfmode(struct ath_hw *ah,
687  struct ath9k_channel *chan)
688 {
689  u32 rfMode = 0;
690 
691  if (chan == NULL)
692  return;
693 
694  rfMode |= (IS_CHAN_B(chan) || IS_CHAN_G(chan))
696 
697  if (IS_CHAN_A_FAST_CLOCK(ah, chan))
699 
700  REG_WRITE(ah, AR_PHY_MODE, rfMode);
701 }
702 
704 {
706 }
707 
708 static void ar9003_hw_set_delta_slope(struct ath_hw *ah,
709  struct ath9k_channel *chan)
710 {
711  u32 coef_scaled, ds_coef_exp, ds_coef_man;
712  u32 clockMhzScaled = 0x64000000;
713  struct chan_centers centers;
714 
715  /*
716  * half and quarter rate can divide the scaled clock by 2 or 4
717  * scale for selected channel bandwidth
718  */
719  if (IS_CHAN_HALF_RATE(chan))
720  clockMhzScaled = clockMhzScaled >> 1;
721  else if (IS_CHAN_QUARTER_RATE(chan))
722  clockMhzScaled = clockMhzScaled >> 2;
723 
724  /*
725  * ALGO -> coef = 1e8/fcarrier*fclock/40;
726  * scaled coef to provide precision for this floating calculation
727  */
728  ath9k_hw_get_channel_centers(ah, chan, &centers);
729  coef_scaled = clockMhzScaled / centers.synth_center;
730 
731  ath9k_hw_get_delta_slope_vals(ah, coef_scaled, &ds_coef_man,
732  &ds_coef_exp);
733 
735  AR_PHY_TIMING3_DSC_MAN, ds_coef_man);
737  AR_PHY_TIMING3_DSC_EXP, ds_coef_exp);
738 
739  /*
740  * For Short GI,
741  * scaled coeff is 9/10 that of normal coeff
742  */
743  coef_scaled = (9 * coef_scaled) / 10;
744 
745  ath9k_hw_get_delta_slope_vals(ah, coef_scaled, &ds_coef_man,
746  &ds_coef_exp);
747 
748  /* for short gi */
750  AR_PHY_SGI_DSC_MAN, ds_coef_man);
752  AR_PHY_SGI_DSC_EXP, ds_coef_exp);
753 }
754 
755 static int ar9003_hw_rfbus_req(struct ath_hw *ah)
756 {
760 }
761 
762 /*
763  * Wait for the frequency synth to settle (synth goes on via PHY_ACTIVE_EN).
764  * Read the phy active delay register. Value is in 100ns increments.
765  */
766 static void ar9003_hw_rfbus_done(struct ath_hw *ah)
767 {
769  if (IS_CHAN_B(ah->curchan))
770  synthDelay = (4 * synthDelay) / 22;
771  else
772  synthDelay /= 10;
773 
774  udelay(synthDelay + BASE_ACTIVATE_DELAY);
775 
777 }
778 
779 static void ar9003_hw_set_diversity(struct ath_hw *ah, int value)
780 {
782  if (value)
784  else
787 }
788 
789 static int ar9003_hw_ani_control(struct ath_hw *ah,
790  enum ath9k_ani_cmd cmd, int param)
791 {
792  struct ath9k_channel *chan = ah->curchan;
793  struct ar5416AniState *aniState = &chan->ani;
794  s32 value, value2;
795 
796  switch (cmd & ah->ani_function) {
798  /*
799  * on == 1 means ofdm weak signal detection is ON
800  * on == 1 is the default, for less noise immunity
801  *
802  * on == 0 means ofdm weak signal detection is OFF
803  * on == 0 means more noise imm
804  */
805  u32 on = param ? 1 : 0;
806  /*
807  * make register setting for default
808  * (weak sig detect ON) come from INI file
809  */
810  int m1ThreshLow = on ?
811  aniState->iniDef.m1ThreshLow : m1ThreshLow_off;
812  int m2ThreshLow = on ?
813  aniState->iniDef.m2ThreshLow : m2ThreshLow_off;
814  int m1Thresh = on ?
815  aniState->iniDef.m1Thresh : m1Thresh_off;
816  int m2Thresh = on ?
817  aniState->iniDef.m2Thresh : m2Thresh_off;
818  int m2CountThr = on ?
819  aniState->iniDef.m2CountThr : m2CountThr_off;
820  int m2CountThrLow = on ?
822  int m1ThreshLowExt = on ?
824  int m2ThreshLowExt = on ?
826  int m1ThreshExt = on ?
827  aniState->iniDef.m1ThreshExt : m1ThreshExt_off;
828  int m2ThreshExt = on ?
829  aniState->iniDef.m2ThreshExt : m2ThreshExt_off;
830 
833  m1ThreshLow);
836  m2ThreshLow);
838  AR_PHY_SFCORR_M1_THRESH, m1Thresh);
840  AR_PHY_SFCORR_M2_THRESH, m2Thresh);
842  AR_PHY_SFCORR_M2COUNT_THR, m2CountThr);
845  m2CountThrLow);
846 
848  AR_PHY_SFCORR_EXT_M1_THRESH_LOW, m1ThreshLowExt);
850  AR_PHY_SFCORR_EXT_M2_THRESH_LOW, m2ThreshLowExt);
852  AR_PHY_SFCORR_EXT_M1_THRESH, m1ThreshExt);
854  AR_PHY_SFCORR_EXT_M2_THRESH, m2ThreshExt);
855 
856  if (on)
859  else
862 
863  if (on != aniState->ofdmWeakSigDetect) {
864  DBG2("ath9k: "
865  "** ch %d: ofdm weak signal: %s=>%s\n",
866  chan->channel,
867  aniState->ofdmWeakSigDetect ?
868  "on" : "off",
869  on ? "on" : "off");
870  if (on)
871  ah->stats.ast_ani_ofdmon++;
872  else
873  ah->stats.ast_ani_ofdmoff++;
874  aniState->ofdmWeakSigDetect = on;
875  }
876  break;
877  }
879  u32 level = param;
880 
881  if (level >= ARRAY_SIZE(firstep_table)) {
882  DBG("ath9k: "
883  "ATH9K_ANI_FIRSTEP_LEVEL: level out of range (%d > %zd)\n",
884  level, ARRAY_SIZE(firstep_table));
885  return 0;
886  }
887 
888  /*
889  * make register setting relative to default
890  * from INI file & cap value
891  */
892  value = firstep_table[level] -
894  aniState->iniDef.firstep;
901  value);
902  /*
903  * we need to set first step low register too
904  * make register setting relative to default
905  * from INI file & cap value
906  */
907  value2 = firstep_table[level] -
909  aniState->iniDef.firstepLow;
910  if (value2 < ATH9K_SIG_FIRSTEP_SETTING_MIN)
912  if (value2 > ATH9K_SIG_FIRSTEP_SETTING_MAX)
914 
917 
918  if (level != aniState->firstepLevel) {
919  DBG2("ath9k: "
920  "** ch %d: level %d=>%d[def:%d] firstep[level]=%d ini=%d\n",
921  chan->channel,
922  aniState->firstepLevel,
923  level,
925  value,
926  aniState->iniDef.firstep);
927  DBG2("ath9k: "
928  "** ch %d: level %d=>%d[def:%d] firstep_low[level]=%d ini=%d\n",
929  chan->channel,
930  aniState->firstepLevel,
931  level,
933  value2,
934  aniState->iniDef.firstepLow);
935  if (level > aniState->firstepLevel)
936  ah->stats.ast_ani_stepup++;
937  else if (level < aniState->firstepLevel)
938  ah->stats.ast_ani_stepdown++;
939  aniState->firstepLevel = level;
940  }
941  break;
942  }
944  u32 level = param;
945 
946  if (level >= ARRAY_SIZE(cycpwrThr1_table)) {
947  DBG("ath9k: "
948  "ATH9K_ANI_SPUR_IMMUNITY_LEVEL: level out of range (%d > %zd)\n",
949  level, ARRAY_SIZE(cycpwrThr1_table));
950  return 0;
951  }
952  /*
953  * make register setting relative to default
954  * from INI file & cap value
955  */
956  value = cycpwrThr1_table[level] -
958  aniState->iniDef.cycpwrThr1;
965  value);
966 
967  /*
968  * set AR_PHY_EXT_CCA for extension channel
969  * make register setting relative to default
970  * from INI file & cap value
971  */
972  value2 = cycpwrThr1_table[level] -
974  aniState->iniDef.cycpwrThr1Ext;
975  if (value2 < ATH9K_SIG_SPUR_IMM_SETTING_MIN)
977  if (value2 > ATH9K_SIG_SPUR_IMM_SETTING_MAX)
980  AR_PHY_EXT_CYCPWR_THR1, value2);
981 
982  if (level != aniState->spurImmunityLevel) {
983  DBG2("ath9k: "
984  "** ch %d: level %d=>%d[def:%d] cycpwrThr1[level]=%d ini=%d\n",
985  chan->channel,
986  aniState->spurImmunityLevel,
987  level,
989  value,
990  aniState->iniDef.cycpwrThr1);
991  DBG2("ath9k: "
992  "** ch %d: level %d=>%d[def:%d] cycpwrThr1Ext[level]=%d ini=%d\n",
993  chan->channel,
994  aniState->spurImmunityLevel,
995  level,
997  value2,
998  aniState->iniDef.cycpwrThr1Ext);
999  if (level > aniState->spurImmunityLevel)
1000  ah->stats.ast_ani_spurup++;
1001  else if (level < aniState->spurImmunityLevel)
1002  ah->stats.ast_ani_spurdown++;
1003  aniState->spurImmunityLevel = level;
1004  }
1005  break;
1006  }
1007  case ATH9K_ANI_MRC_CCK:{
1008  /*
1009  * is_on == 1 means MRC CCK ON (default, less noise imm)
1010  * is_on == 0 means MRC CCK is OFF (more noise imm)
1011  */
1012  int is_on = param ? 1 : 0;
1014  AR_PHY_MRC_CCK_ENABLE, is_on);
1016  AR_PHY_MRC_CCK_MUX_REG, is_on);
1017  if (!(is_on != aniState->mrcCCKOff)) {
1018  DBG2("ath9k: "
1019  "** ch %d: MRC CCK: %s=>%s\n",
1020  chan->channel,
1021  !aniState->mrcCCKOff ? "on" : "off",
1022  is_on ? "on" : "off");
1023  if (is_on)
1024  ah->stats.ast_ani_ccklow++;
1025  else
1026  ah->stats.ast_ani_cckhigh++;
1027  aniState->mrcCCKOff = !is_on;
1028  }
1029  break;
1030  }
1031  case ATH9K_ANI_PRESENT:
1032  break;
1033  default:
1034  DBG2("ath9k: invalid cmd %d\n", cmd);
1035  return 0;
1036  }
1037 
1038  DBG2("ath9k: "
1039  "ANI parameters: SI=%d, ofdmWS=%s FS=%d MRCcck=%s listenTime=%d ofdmErrs=%d cckErrs=%d\n",
1040  aniState->spurImmunityLevel,
1041  aniState->ofdmWeakSigDetect ? "on" : "off",
1042  aniState->firstepLevel,
1043  !aniState->mrcCCKOff ? "on" : "off",
1044  aniState->listenTime,
1045  aniState->ofdmPhyErrCount,
1046  aniState->cckPhyErrCount);
1047  return 1;
1048 }
1049 
1050 static void ar9003_hw_do_getnf(struct ath_hw *ah,
1051  int16_t nfarray[NUM_NF_READINGS])
1052 {
1053 #define AR_PHY_CH_MINCCA_PWR 0x1FF00000
1054 #define AR_PHY_CH_MINCCA_PWR_S 20
1055 #define AR_PHY_CH_EXT_MINCCA_PWR 0x01FF0000
1056 #define AR_PHY_CH_EXT_MINCCA_PWR_S 16
1057 
1058  int16_t nf;
1059  int i;
1060 
1061  for (i = 0; i < AR9300_MAX_CHAINS; i++) {
1062  if (ah->rxchainmask & BIT(i)) {
1063  nf = MS(REG_READ(ah, ah->nf_regs[i]),
1065  nfarray[i] = sign_extend32(nf, 8);
1066 
1067  if (IS_CHAN_HT40(ah->curchan)) {
1068  u8 ext_idx = AR9300_MAX_CHAINS + i;
1069 
1070  nf = MS(REG_READ(ah, ah->nf_regs[ext_idx]),
1072  nfarray[ext_idx] = sign_extend32(nf, 8);
1073  }
1074  }
1075  }
1076 }
1077 
1078 static void ar9003_hw_set_nf_limits(struct ath_hw *ah)
1079 {
1082  ah->nf_2g.nominal = AR_PHY_CCA_NOM_VAL_9300_2GHZ;
1085  ah->nf_5g.nominal = AR_PHY_CCA_NOM_VAL_9300_5GHZ;
1086 }
1087 
1088 /*
1089  * Initialize the ANI register values with default (ini) values.
1090  * This routine is called during a (full) hardware reset after
1091  * all the registers are initialised from the INI.
1092  */
1094 {
1095  struct ar5416AniState *aniState;
1096  struct ath9k_channel *chan = ah->curchan;
1097  struct ath9k_ani_default *iniDef;
1098  u32 val;
1099 
1100  aniState = &ah->curchan->ani;
1101  iniDef = &aniState->iniDef;
1102 
1103  DBG2("ath9k: "
1104  "ver %d.%d chan %d Mhz/0x%x\n",
1105  ah->hw_version.macVersion,
1106  ah->hw_version.macRev,
1107  chan->channel,
1108  chan->channelFlags);
1109 
1111  iniDef->m1Thresh = MS(val, AR_PHY_SFCORR_M1_THRESH);
1112  iniDef->m2Thresh = MS(val, AR_PHY_SFCORR_M2_THRESH);
1114 
1119 
1125  iniDef->firstep = REG_READ_FIELD(ah,
1128  iniDef->firstepLow = REG_READ_FIELD(ah,
1131  iniDef->cycpwrThr1 = REG_READ_FIELD(ah,
1134  iniDef->cycpwrThr1Ext = REG_READ_FIELD(ah,
1137 
1138  /* these levels just got reset to defaults by the INI */
1142  aniState->mrcCCKOff = !ATH9K_ANI_ENABLE_MRC_CCK;
1143 }
1144 
1146  struct ath_hw_radar_conf *conf)
1147 {
1148  u32 radar_0 = 0, radar_1 = 0;
1149 
1150  if (!conf) {
1152  return;
1153  }
1154 
1156  radar_0 |= SM(conf->fir_power, AR_PHY_RADAR_0_FIRPWR);
1157  radar_0 |= SM(conf->radar_rssi, AR_PHY_RADAR_0_RRSSI);
1158  radar_0 |= SM(conf->pulse_height, AR_PHY_RADAR_0_HEIGHT);
1159  radar_0 |= SM(conf->pulse_rssi, AR_PHY_RADAR_0_PRSSI);
1160  radar_0 |= SM(conf->pulse_inband, AR_PHY_RADAR_0_INBAND);
1161 
1162  radar_1 |= AR_PHY_RADAR_1_MAX_RRSSI;
1163  radar_1 |= AR_PHY_RADAR_1_BLOCK_CHECK;
1164  radar_1 |= SM(conf->pulse_maxlen, AR_PHY_RADAR_1_MAXLEN);
1166  radar_1 |= SM(conf->radar_inband, AR_PHY_RADAR_1_RELPWR_THRESH);
1167 
1168  REG_WRITE(ah, AR_PHY_RADAR_0, radar_0);
1169  REG_WRITE(ah, AR_PHY_RADAR_1, radar_1);
1170  if (conf->ext_channel)
1172  else
1174 }
1175 
1176 static void ar9003_hw_set_radar_conf(struct ath_hw *ah)
1177 {
1178  struct ath_hw_radar_conf *conf = &ah->radar_conf;
1179 
1180  conf->fir_power = -28;
1181  conf->radar_rssi = 0;
1182  conf->pulse_height = 10;
1183  conf->pulse_rssi = 24;
1184  conf->pulse_inband = 8;
1185  conf->pulse_maxlen = 255;
1186  conf->pulse_inband_step = 12;
1187  conf->radar_inband = 8;
1188 }
1189 
1191  struct ath_hw_antcomb_conf *antconf)
1192 {
1193  u32 regval;
1194 
1195  regval = REG_READ(ah, AR_PHY_MC_GAIN_CTRL);
1196  antconf->main_lna_conf = (regval & AR_PHY_9485_ANT_DIV_MAIN_LNACONF) >>
1198  antconf->alt_lna_conf = (regval & AR_PHY_9485_ANT_DIV_ALT_LNACONF) >>
1200  antconf->fast_div_bias = (regval & AR_PHY_9485_ANT_FAST_DIV_BIAS) >>
1202  antconf->lna1_lna2_delta = -9;
1203  antconf->div_group = 2;
1204 }
1205 
1207  struct ath_hw_antcomb_conf *antconf)
1208 {
1209  u32 regval;
1210 
1211  regval = REG_READ(ah, AR_PHY_MC_GAIN_CTRL);
1212  regval &= ~(AR_PHY_9485_ANT_DIV_MAIN_LNACONF |
1217  regval |= ((antconf->main_lna_conf <<
1220  regval |= ((antconf->alt_lna_conf << AR_PHY_9485_ANT_DIV_ALT_LNACONF_S)
1222  regval |= ((antconf->fast_div_bias << AR_PHY_9485_ANT_FAST_DIV_BIAS_S)
1224  regval |= ((antconf->main_gaintb << AR_PHY_9485_ANT_DIV_MAIN_GAINTB_S)
1226  regval |= ((antconf->alt_gaintb << AR_PHY_9485_ANT_DIV_ALT_GAINTB_S)
1228 
1229  REG_WRITE(ah, AR_PHY_MC_GAIN_CTRL, regval);
1230 }
1231 
1233 {
1234  struct ath_hw_private_ops *priv_ops = ath9k_hw_private_ops(ah);
1235  struct ath_hw_ops *ops = ath9k_hw_ops(ah);
1236  static const u32 ar9300_cca_regs[6] = {
1237  AR_PHY_CCA_0,
1238  AR_PHY_CCA_1,
1239  AR_PHY_CCA_2,
1243  };
1244 
1245  priv_ops->rf_set_freq = ar9003_hw_set_channel;
1249  priv_ops->init_bb = ar9003_hw_init_bb;
1250  priv_ops->process_ini = ar9003_hw_process_ini;
1251  priv_ops->set_rfmode = ar9003_hw_set_rfmode;
1254  priv_ops->rfbus_req = ar9003_hw_rfbus_req;
1255  priv_ops->rfbus_done = ar9003_hw_rfbus_done;
1257  priv_ops->ani_control = ar9003_hw_ani_control;
1258  priv_ops->do_getnf = ar9003_hw_do_getnf;
1261 
1264 
1267  memcpy(ah->nf_regs, ar9300_cca_regs, sizeof(ah->nf_regs));
1268 }
1269 
1271 {
1272  u32 val;
1273 
1275  val &= ~AR_PHY_RESTART_ENA;
1276 
1278 }
#define BASE_ACTIVATE_DELAY
Definition: hw.h:133
#define AR_PHY_SFCORR_LOW
Definition: ar9002_phy.h:139
#define AR_PHY_SFCORR_LOW_M2_THRESH_LOW
Definition: ar9002_phy.h:145
#define AR9300_MAX_CHAINS
Definition: ar9003_eeprom.h:49
static const int m2CountThrLow_off
uint16_t u16
Definition: stdint.h:21
void(* set_delta_slope)(struct ath_hw *ah, struct ath9k_channel *chan)
Definition: hw.h:577
u8 spurChans[AR_EEPROM_MODAL_SPURS]
u8 fast_div_bias
Definition: hw.h:484
#define AR_PHY_GC_SHORT_GI_40
Definition: ar9003_phy.h:682
#define EINVAL
Invalid argument.
Definition: errno.h:428
static void ar9003_hw_prog_ini(struct ath_hw *ah, struct ar5416IniArray *iniArr, int column)
u16 channel
Definition: hw.h:349
iPXE I/O API
u32 chanmode
Definition: hw.h:351
#define AR_DIAG_RX_ABORT
Definition: reg.h:1524
#define AR_PHY_9485_ANT_DIV_MAIN_LNACONF
Definition: ar9003_phy.h:280
u32 listenTime
Definition: ani.h:130
Definition: hw.h:656
u16 synth_center
Definition: hw.h:422
static u32 ar9003_hw_compute_pll_control(struct ath_hw *ah __unused, struct ath9k_channel *chan)
#define AR_PHY_CCK_SPUR_MIT_SPUR_FILTER_TYPE
Definition: ar9003_phy.h:313
static void ar9003_hw_spur_mitigate_mrc_cck(struct ath_hw *ah, struct ath9k_channel *chan)
ar9003_hw_spur_mitigate_mrc_cck - convert baseband spur frequency @ah: atheros hardware structure @ch...
u16 m1ThreshLow
Definition: ani.h:103
#define AR_PHY_9485_ANT_DIV_MAIN_LNACONF_S
Definition: ar9003_phy.h:281
#define AR_PHY_MRC_CCK_CTRL
Definition: ar9003_phy.h:320
static const int firstep_table[]
#define AR_GTXTO_TIMEOUT_LIMIT_S
Definition: reg.h:155
#define AR_PHY_SFCORR_LOW_M1_THRESH_LOW
Definition: ar9002_phy.h:143
void(* init_bb)(struct ath_hw *ah, struct ath9k_channel *chan)
Definition: hw.h:571
#define AR_PHY_CCK_SPUR_MIT_USE_CCK_SPUR_MIT
Definition: ar9003_phy.h:315
#define AR_PHY_CCA_NOM_VAL_9300_5GHZ
Definition: ar9003_phy.h:329
#define AR_PHY_CCK_SPUR_MIT_SPUR_RSSI_THR
Definition: ar9003_phy.h:311
#define AR_PHY_GC_ENABLE_DAC_FIFO
Definition: ar9003_phy.h:686
u8 spurImmunityLevel
Definition: ani.h:126
static void ar9003_hw_set_radar_conf(struct ath_hw *ah)
#define IS_CHAN_B(_c)
Definition: ath5k.h:658
u8 mrcCCKOff
Definition: ani.h:125
static void ar9003_hw_override_ini(struct ath_hw *ah)
static void ar9003_hw_do_getnf(struct ath_hw *ah, int16_t nfarray[NUM_NF_READINGS])
int32_t s32
Definition: stdint.h:22
#define AR_PHY_RFBUS_REQ_EN
Definition: ar9002_phy.h:269
#define AR_PHY_TIMING4_ENABLE_CHAN_MASK
Definition: ar9003_phy.h:114
#define AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV
Definition: ar9002_phy.h:419
static void ar9003_hw_set_delta_slope(struct ath_hw *ah, struct ath9k_channel *chan)
u16 m2CountThrLow
Definition: ani.h:108
u16 m2CountThr
Definition: ani.h:107
#define AR_PHY_CCA_MAX_GOOD_VAL_9300_5GHZ
Definition: ar9003_phy.h:333
#define AR_RTC_9300_PLL_REFDIV
Definition: reg.h:1145
#define AR_PHY_GEN_CTRL
Definition: ar9003_phy.h:426
#define IS_CHAN_2GHZ(_c)
Definition: hw.h:361
#define AR_EEPROM_MODAL_SPURS
Definition: eeprom.h:25
#define DO_DELAY(x)
Definition: hw.h:112
#define MS(_v, _f)
Definition: hw.h:102
#define AR_PHY_SPUR_MASK_A_CF_PUNC_MASK_IDX_A
Definition: ar9003_phy.h:462
#define AR_PHY_RADAR_0_FFT_ENA
Definition: ar9002_phy.h:226
#define INI_RA(iniarray, row, column)
Definition: calib.h:45
#define AR_PHY_SPUR_MASK_A_CF_PUNC_MASK_A
Definition: ar9003_phy.h:464
#define REG_CLR_BIT(_a, _r, _f)
Definition: hw.h:109
#define AR_PHY_SGI_DELTA
Definition: ar9003_phy.h:221
#define ATH9K_SIG_FIRSTEP_SETTING_MAX
Definition: ani.h:72
#define AR_PHY_MRC_CCK_MUX_REG
Definition: ar9003_phy.h:323
#define AR_PHY_ACTIVE_EN
Definition: ar9002_phy.h:53
#define CHANSEL_5G(_freq)
Definition: phy.h:24
void(* spur_mitigate_freq)(struct ath_hw *ah, struct ath9k_channel *chan)
Definition: hw.h:563
#define AR_PHY_RESTART
Definition: ar9002_phy.h:264
static int32_t sign_extend32(uint32_t value, int index)
Definition: ath.h:69
#define AR_PHY_RADAR_EXT
Definition: ar9002_phy.h:221
#define AR_PHY_9485_ANT_FAST_DIV_BIAS
Definition: ar9003_phy.h:274
#define min(x, y)
Definition: ath.h:34
static void ar9003_hw_mark_phy_inactive(struct ath_hw *ah)
void ath9k_hw_get_delta_slope_vals(struct ath_hw *ah __unused, u32 coef_scaled, u32 *coef_mantissa, u32 *coef_exponent)
Definition: ath9k_hw.c:964
#define AR_PHY_FIND_SIG_LOW
Definition: ar9002_phy.h:119
#define AR_PHY_SFCORR_EXT_M1_THRESH_LOW
Definition: ar9002_phy.h:349
static void ar9003_hw_spur_ofdm_work(struct ath_hw *ah, struct ath9k_channel *chan, int freq_offset)
#define AR_PHY_RADAR_1_MAX_RRSSI
Definition: ar9002_phy.h:244
#define IS_CHAN_HALF_RATE(_c)
Definition: hw.h:362
#define AR_PHY_RESTART_ENA
Definition: ar9003_phy.h:409
#define CHANNEL_A_HT40MINUS
Definition: hw.h:322
#define AR_PHY_TIMING11_SPUR_FREQ_SD
Definition: ar9003_phy.h:36
#define AR_SREV_9485(_ah)
Definition: reg.h:867
void(* rfbus_done)(struct ath_hw *ah)
Definition: hw.h:579
void ar9003_hw_attach_phy_ops(struct ath_hw *ah)
u16 m1ThreshExt
Definition: ani.h:111
static const int m2ThreshLow_off
static void ar9003_hw_set_channel_regs(struct ath_hw *ah, struct ath9k_channel *chan)
#define AR_PHY_EXT_CCA_1
Definition: ar9003_phy.h:802
#define AR_PHY_SFCORR_EXT_M2_THRESH_LOW
Definition: ar9002_phy.h:351
u16 cycpwrThr1Ext
Definition: ani.h:116
#define AR_PHY_PILOT_SPUR_MASK_CF_PILOT_MASK_A
Definition: ar9003_phy.h:228
struct ath_hw_private_ops - callbacks used internally by hardware code
Definition: hw.h:550
#define AR_PHY_ACTIVE
Definition: ar9002_phy.h:52
#define CHANSEL_2G(_freq)
Definition: phy.h:23
#define AR_RTC_9300_PLL_CLKSEL
Definition: reg.h:1147
#define AR_PHY_SPUR_REG_ENABLE_MASK_PPM
Definition: ar9002_phy.h:522
struct net80211_channel * chan
Definition: hw.h:347
static void ar9003_hw_spur_ofdm(struct ath_hw *ah, int freq_offset, int spur_freq_sd, int spur_delta_phase, int spur_subchannel_sd)
u32 channelFlags
Definition: hw.h:350
#define CHANNEL_A
Definition: ath5k.h:638
#define AR_PHY_GC_DYN2040_EN
Definition: ar9003_phy.h:676
u16 m2Thresh
Definition: ani.h:106
static void ar9003_hw_set_nf_limits(struct ath_hw *ah)
#define AR_PHY_CCA_MIN_GOOD_VAL_9300_2GHZ
Definition: ar9003_phy.h:330
#define REG_RMW_FIELD(_a, _r, _f, _v)
Definition: hw.h:103
#define AR_PHY_ACTIVE_DIS
Definition: ar9002_phy.h:54
static const int m1ThreshLowExt_off
static void ar9003_hw_set_rfmode(struct ath_hw *ah, struct ath9k_channel *chan)
#define abs(x)
Definition: ath.h:44
void(* antdiv_comb_conf_set)(struct ath_hw *ah, struct ath_hw_antcomb_conf *antconf)
Definition: hw.h:641
void(* mark_phy_inactive)(struct ath_hw *ah)
Definition: hw.h:576
static void ar9003_hw_ani_cache_ini_regs(struct ath_hw *ah)
#define AR_PHY_SYNTH4_LONG_SHIFT_SELECT
Definition: ar9003_phy.h:603
#define AR_PHY_EXT_CCA
Definition: ar9002_phy.h:331
#define AR_PHY_RADAR_1
Definition: ar9002_phy.h:238
#define IS_CHAN_QUARTER_RATE(_c)
Definition: hw.h:363
unsigned int pulse_maxlen
Definition: hw.h:516
#define AR_SELFGEN_MASK
Definition: reg.h:1823
#define AR_PHY_TIMING4_ENABLE_SPUR_RSSI
Definition: ar9003_phy.h:119
int ext_channel
Definition: hw.h:522
#define AR_PHY_SFCORR_EXT_M2_THRESH
Definition: ar9002_phy.h:347
#define AR_PHY_TIMING5
Definition: ar9002_phy.h:202
void * memcpy(void *dest, const void *src, size_t len) __nonnull
u16 firstepLow
Definition: ani.h:114
#define AR_CST
Definition: reg.h:163
u32 ath9k_regd_get_ctl(struct ath_regulatory *reg, struct ath9k_channel *chan)
Definition: ath9k_hw.c:867
#define SM(_v, _f)
Definition: hw.h:101
int(* process_ini)(struct ath_hw *ah, struct ath9k_channel *chan)
Definition: hw.h:573
#define AR_PHY_GC_SINGLE_HT_LTF1
Definition: ar9003_phy.h:684
#define AR_PHY_RX_DELAY_DELAY
Definition: ar9002_phy.h:185
#define AR_PHY_ANALOG_SWAP
Definition: ar9002_phy.h:535
#define AR_PHY_RADAR_0_HEIGHT
Definition: ar9002_phy.h:231
#define AR_PHY_65NM_CH0_SYNTH7
Definition: ar9003_phy.h:605
#define AR_PHY_65NM_CH0_SYNTH4
Definition: ar9003_phy.h:602
#define CHANNEL_G
Definition: ath5k.h:640
#define AR_PHY_SFCORR_M1_THRESH
Definition: ar9002_phy.h:151
#define AR_PHY_TIMING11_USE_SPUR_FILTER_IN_SELFCOR
Definition: ar9003_phy.h:45
#define AR_PHY_SFCORR_EXT_SPUR_SUBCHANNEL_SD
Definition: ar9003_phy.h:145
u16 m1Thresh
Definition: ani.h:105
static void ar9003_hw_antdiv_comb_conf_get(struct ath_hw *ah, struct ath_hw_antcomb_conf *antconf)
u8 ofdmWeakSigDetect
Definition: ani.h:128
#define AR_PHY_CH_EXT_MINCCA_PWR
unsigned int pulse_inband_step
Definition: hw.h:513
unsigned int pulse_height
Definition: hw.h:514
static struct ath_regulatory * ath9k_hw_regulatory(struct ath_hw *ah)
Definition: hw.h:874
#define AR_PHY_SFCORR_LOW_M2COUNT_THR_LOW
Definition: ar9002_phy.h:141
#define AR_PHY_PILOT_SPUR_MASK
Definition: ar9003_phy.h:219
#define AR_PCU_MISC_MODE2
Definition: reg.h:1830
unsigned int radar_rssi
Definition: hw.h:518
void udelay(unsigned long usecs)
Delay for a fixed number of microseconds.
Definition: timer.c:60
#define AR_PHY_AGC_CONTROL
Definition: reg.h:1909
#define AR_PHY_RADAR_1_RELSTEP_THRESH
Definition: ar9002_phy.h:246
void(* ani_cache_ini_regs)(struct ath_hw *ah)
Definition: hw.h:591
#define AR_PHY_RADAR_0_RRSSI
Definition: ar9002_phy.h:233
static const int m2ThreshLowExt_off
u32 ia_rows
Definition: calib.h:35
int16_t power_limit
Definition: ath.h:143
#define AR_PHY_9485_ANT_DIV_ALT_GAINTB_S
Definition: ar9003_phy.h:283
uint32_t channel
RNDIS channel.
Definition: netvsc.h:14
u8 firstepLevel
Definition: ani.h:127
#define ATH9K_ANI_FIRSTEP_LVL_NEW
Definition: ani.h:55
#define AR_SREV_9340(_ah)
Definition: reg.h:878
int fir_power
Definition: hw.h:520
u8 * ar9003_get_spur_chan_ptr(struct ath_hw *ah, int is_2ghz)
#define AR_PHY_TIMING5_CYCPWR_THR1
Definition: ar9002_phy.h:203
static void ar9003_hw_init_bb(struct ath_hw *ah, struct ath9k_channel *chan)
#define AR_PHY_CHAN_SPUR_MASK_CF_CHAN_MASK_A
Definition: ar9003_phy.h:233
#define AR_PHY_9485_ANT_DIV_MAIN_GAINTB_S
Definition: ar9003_phy.h:285
uint32_t rx
Maximum number of receive queues.
Definition: intelvf.h:16
#define CHANNEL_A_HT20
Definition: hw.h:318
#define AR_PHY_CCA_MAX_GOOD_VAL_9300_2GHZ
Definition: ar9003_phy.h:332
u32 ia_columns
Definition: calib.h:36
#define AR_PHY_RFBUS_GRANT_EN
Definition: ar9002_phy.h:389
pseudo_bit_t value[0x00020]
Definition: arbel.h:13
u16 cycpwrThr1
Definition: ani.h:115
#define ATH9K_SIG_SPUR_IMM_SETTING_MIN
Definition: ani.h:73
#define AR_PHY_RADAR_0_INBAND
Definition: ar9002_phy.h:227
#define AR_PHY_CCA_NOM_VAL_9300_2GHZ
Definition: ar9003_phy.h:328
#define AR_PHY_SPUR_REG_SPUR_RSSI_THRESH
Definition: ar9002_phy.h:526
#define FBIN2FREQ(x, y)
Definition: ar9003_eeprom.h:48
#define AR_DIAG_RX_DIS
Definition: reg.h:1510
#define AR_PHY_9485_ANT_DIV_ALT_GAINTB
Definition: ar9003_phy.h:282
#define AR_PHY_FIND_SIG_LOW_FIRSTEP_LOW
Definition: ar9003_phy.h:191
#define AR_PHY_SGI_DSC_MAN
Definition: ar9003_phy.h:239
static void ar9003_hw_spur_mitigate(struct ath_hw *ah, struct ath9k_channel *chan)
#define AR_PHY_TIMING3_DSC_EXP
Definition: ar9002_phy.h:45
#define AR_PHY_RADAR_0_PRSSI
Definition: ar9002_phy.h:229
#define AR_PHY_SPUR_REG_MASK_RATE_CNTL
Definition: ar9002_phy.h:519
#define AR_PHY_CH_MINCCA_PWR
uint32_t tx
Maximum number of transmit queues.
Definition: intelvf.h:14
#define AR_PHY_TIMING11
Definition: ar9002_phy.h:295
static unsigned int unsigned int reg
Definition: intel.h:245
struct ath_hw_radar_conf - radar detection initialization parameters
Definition: hw.h:511
void ar9003_hw_disable_phy_restart(struct ath_hw *ah)
struct hv_monitor_parameter param[4][32]
Parameters.
Definition: hyperv.h:24
#define AR_PHY_RX_CHAINMASK
Definition: ar9002_phy.h:301
#define AR_PHY_RADAR_1_MAXLEN
Definition: ar9002_phy.h:248
#define AR_PHY_RX_DELAY
Definition: ar9002_phy.h:183
#define AR_PHY_SFCORR_LOW_USE_SELF_CORR_LOW
Definition: ar9002_phy.h:140
#define AR_PHY_TIMING11_SPUR_DELTA_PHASE
Definition: ar9002_phy.h:296
An 802.11 RF channel.
Definition: net80211.h:385
struct ath_hw_ops - callbacks used by hardware code and driver code
Definition: hw.h:603
uint32_t column[4]
Viewed as an array of four-byte columns.
Definition: aes.h:14
#define AR_PHY_CHAN_SPUR_MASK
Definition: ar9003_phy.h:220
#define AR_PHY_GC_WALSH
Definition: ar9003_phy.h:683
#define AR_PHY_9485_ANT_FAST_DIV_BIAS_S
Definition: ar9003_phy.h:275
#define AR_PHY_SPUR_REG
Definition: ar9002_phy.h:517
#define ARRAY_SIZE(x)
Definition: efx_common.h:43
#define AR_PHY_CAL_CHAINMASK
Definition: ar9002_phy.h:558
#define AR_PHY_TIMING4_ENABLE_PILOT_MASK
Definition: ar9003_phy.h:112
struct ar9300_modal_eep_header modalHeader2G
static void ar9003_hw_rfbus_done(struct ath_hw *ah)
struct ar9300_modal_eep_header modalHeader5G
#define AR_PHY_SWAP_ALT_CHAIN
Definition: ar9002_phy.h:536
#define AR_PHY_CCK_DETECT
Definition: ar9002_phy.h:413
#define AR_AGG_WEP_ENABLE
Definition: reg.h:1900
#define ATH9K_SIG_SPUR_IMM_SETTING_MAX
Definition: ani.h:74
static int ar9003_hw_process_ini(struct ath_hw *ah, struct ath9k_channel *chan)
static void ar9003_hw_set_diversity(struct ath_hw *ah, int value)
static const int m1Thresh_off
unsigned int radar_inband
Definition: hw.h:519
#define AR_PHY_SFCORR_M2COUNT_THR
Definition: ar9002_phy.h:149
#define AR_PHY_GC_DYN2040_PRI_CH
Definition: ar9003_phy.h:678
#define AR_PHY_CCA_1
Definition: ar9003_phy.h:823
static int ar9003_hw_rfbus_req(struct ath_hw *ah)
#define AR_PHY_TIMING4_ENABLE_SPUR_FILTER
Definition: ar9003_phy.h:117
#define ATH9K_ANI_SPUR_IMMUNE_LVL_NEW
Definition: ani.h:52
#define IS_CHAN_G(_c)
Definition: hw.h:355
#define AR_PHY_CCK_SPUR_MIT
Definition: ar9003_phy.h:310
unsigned int pulse_rssi
Definition: hw.h:515
static const int cycpwrThr1_table[]
static int ar9003_hw_ani_control(struct ath_hw *ah, enum ath9k_ani_cmd cmd, int param)
#define AR_PHY_GC_HT_EN
Definition: ar9003_phy.h:681
void(* set_rfmode)(struct ath_hw *ah, struct ath9k_channel *chan)
Definition: hw.h:575
#define REG_READ(_ah, _reg)
Definition: hw.h:80
#define AR_PHY_RADAR_0_ENA
Definition: ar9002_phy.h:225
#define AR_PHY_FIND_SIG_FIRSTEP
Definition: ar9002_phy.h:114
#define AR_PHY_TIMING3_DSC_MAN
Definition: ar9002_phy.h:43
#define IS_CHAN_5GHZ(_c)
Definition: hw.h:360
void __asmcall int val
Definition: setjmp.h:28
#define AR_CST_TIMEOUT_LIMIT_S
Definition: reg.h:166
#define AR_PHY_SGI_DSC_EXP
Definition: ar9003_phy.h:241
#define AR_PHY_RADAR_0_FIRPWR
Definition: ar9002_phy.h:235
void(* set_diversity)(struct ath_hw *ah, int value)
Definition: hw.h:581
#define AR_PHY_CHAN_SPUR_MASK_CF_CHAN_MASK_IDX_A
Definition: ar9003_phy.h:231
#define AR_PHY_SFCORR
Definition: ar9002_phy.h:148
#define REG_SET_BIT(_a, _r, _f)
Definition: hw.h:107
u16 m2ThreshLowExt
Definition: ani.h:110
#define __unused
Declare a variable or data structure as unused.
Definition: compiler.h:573
static struct ath_hw_ops * ath9k_hw_ops(struct ath_hw *ah)
Definition: hw.h:884
ath9k_ani_cmd
Definition: ani.h:80
#define AR_PHY_TIMING3
Definition: ar9002_phy.h:42
int(* rfbus_req)(struct ath_hw *ah)
Definition: hw.h:578
#define REG_WRITE_ARRAY(iniarray, column, regWr)
Definition: hw.h:119
#define BIT(nr)
Definition: ath.h:32
#define AR_PHY_SFCORR_M2_THRESH
Definition: ar9002_phy.h:153
#define AR_PHY_MODE_DYN_CCK_DISABLE
Definition: ar9002_phy.h:406
#define AR_GTXTO
Definition: reg.h:152
static const int m2Thresh_off
#define AR_PHY_CCA_MIN_GOOD_VAL_9300_5GHZ
Definition: ar9003_phy.h:331
#define AR_PHY_SFCORR_EXT
Definition: ar9002_phy.h:344
#define AR_PHY_EXT_CYCPWR_THR1
Definition: ar9003_phy.h:152
struct ar5416AniState ani
Definition: hw.h:348
#define AR_PHY_RADAR_1_BLOCK_CHECK
Definition: ar9002_phy.h:243
int ath9k_hw_wait(struct ath_hw *ah, u32 reg, u32 mask, u32 val, u32 timeout)
Definition: ath9k_hw.c:93
void ar9003_hw_set_chain_masks(struct ath_hw *ah, u8 rx, u8 tx)
int lna1_lna2_delta
Definition: hw.h:487
#define REG_WRITE(_ah, _reg, _val)
Definition: hw.h:77
#define AR_PHY_RFBUS_REQ
Definition: ar9002_phy.h:268
void ath9k_hw_set11nmac2040(struct ath_hw *ah)
Definition: ath9k_hw.c:1973
#define CHANNEL_A_HT40PLUS
Definition: hw.h:321
static const int m2CountThr_off
#define AR_RTC_9300_PLL_DIV
Definition: reg.h:1143
#define AR_PHY_SPUR_REG_EN_VIT_SPUR_RSSI
Definition: ar9003_phy.h:55
#define AR_PHY_AGC_CONTROL_YCOK_MAX
Definition: reg.h:1918
static void ar9003_hw_spur_mitigate_ofdm(struct ath_hw *ah, struct ath9k_channel *chan)
static void ar9003_hw_spur_ofdm_clear(struct ath_hw *ah)
#define AH_WAIT_TIMEOUT
Definition: hw.h:145
#define NUM_NF_READINGS
Definition: calib.h:30
u16 m1ThreshLowExt
Definition: ani.h:109
#define REG_READ_FIELD(_a, _r, _f)
Definition: hw.h:105
int(* ani_control)(struct ath_hw *ah, enum ath9k_ani_cmd cmd, int param)
Definition: hw.h:584
#define ATH9K_SIG_FIRSTEP_SETTING_MIN
Definition: ani.h:71
#define AR_PHY_SFCORR_EXT_M1_THRESH
Definition: ar9002_phy.h:345
#define AR_PHY_FIND_SIG
Definition: ar9002_phy.h:113
#define ATH9K_ANI_USE_OFDM_WEAK_SIG
Definition: ani.h:48
u32 ofdmPhyErrCount
Definition: ani.h:134
void(* antdiv_comb_conf_get)(struct ath_hw *ah, struct ath_hw_antcomb_conf *antconf)
Definition: hw.h:639
int(* rf_set_freq)(struct ath_hw *ah, struct ath9k_channel *chan)
Definition: hw.h:561
#define AR_PHY_CCK_SPUR_MIT_CCK_SPUR_FREQ
Definition: ar9003_phy.h:317
u16 m2ThreshLow
Definition: ani.h:104
void(* set_channel_regs)(struct ath_hw *ah, struct ath9k_channel *chan)
Definition: hw.h:570
void ath9k_hw_get_channel_centers(struct ath_hw *ah __unused, struct ath9k_channel *chan, struct chan_centers *centers)
Definition: ath9k_hw.c:189
#define AR_PHY_RADAR_0
Definition: ar9002_phy.h:224
unsigned int pulse_inband
Definition: hw.h:512
u8 main_lna_conf
Definition: hw.h:482
#define AR_PHY_MODE_OFDM
Definition: ar9002_phy.h:405
uint8_t ah
Definition: registers.h:85
static const int m2ThreshExt_off
#define AR_DIAG_SW
Definition: reg.h:1504
u32(* compute_pll_control)(struct ath_hw *ah, struct ath9k_channel *chan)
Definition: hw.h:582
void(* set_radar_params)(struct ath_hw *ah, struct ath_hw_radar_conf *conf)
Definition: hw.h:587
#define CHANNEL_G_HT20
Definition: hw.h:317
#define AR_PHY_MC_GAIN_CTRL
Definition: ar9003_phy.h:267
static const int m1ThreshLow_off
signed short int16_t
Definition: stdint.h:16
static struct ath_hw_private_ops * ath9k_hw_private_ops(struct ath_hw *ah)
Definition: hw.h:879
void(* do_getnf)(struct ath_hw *ah, int16_t nfarray[NUM_NF_READINGS])
Definition: hw.h:586
static void ar9003_hw_antdiv_comb_conf_set(struct ath_hw *ah, struct ath_hw_antcomb_conf *antconf)
#define ATH9K_ANI_ENABLE_MRC_CCK
Definition: ani.h:76
#define DBG(...)
Print a debugging message.
Definition: compiler.h:498
#define CHANNEL_B
Definition: ath5k.h:639
#define AR_PHY_SPUR_REG_ENABLE_NF_RSSI_SPUR_MIT
Definition: ar9003_phy.h:48
#define IS_CHAN_HT40(_c)
Definition: hw.h:372
#define AR_PHY_TIMING4
Definition: ar9003_phy.h:28
u32 cckPhyErrCount
Definition: ani.h:135
struct ath9k_ani_default iniDef
Definition: ani.h:139
u32 * ia_array
Definition: calib.h:34
#define CHANNEL_G_HT40PLUS
Definition: hw.h:319
u16 m2ThreshExt
Definition: ani.h:112
#define AR_PHY_MODE
Definition: ar9002_phy.h:396
static void ar9003_hw_set_radar_params(struct ath_hw *ah, struct ath_hw_radar_conf *conf)
#define IS_CHAN_A_FAST_CLOCK(_ah, _c)
Definition: hw.h:364
#define AR_PHY_9485_ANT_DIV_ALT_LNACONF
Definition: ar9003_phy.h:278
#define AR_PHY_RADAR_EXT_ENA
Definition: ar9002_phy.h:222
#define AR_PHY_RFBUS_GRANT
Definition: ar9002_phy.h:388
#define AR_PHY_TIMING11_USE_SPUR_FILTER_IN_AGC
Definition: ar9003_phy.h:42
#define NULL
NULL pointer (VOID *)
Definition: Base.h:362
struct golan_eqe_cmd cmd
Definition: CIB_PRM.h:29
#define AR_PHY_MRC_CCK_ENABLE
Definition: ar9003_phy.h:321
#define AR_PHY_9485_ANT_DIV_ALT_LNACONF_S
Definition: ar9003_phy.h:279
uint8_t u8
Definition: stdint.h:19
#define CHANNEL_G_HT40MINUS
Definition: hw.h:320
#define AR_PHY_EXT_CCA_2
Definition: ar9003_phy.h:858
static const int m1ThreshExt_off
#define MAX_RATE_POWER
Definition: hw.h:144
uint32_t u32
Definition: stdint.h:23
#define AR_PHY_PILOT_SPUR_MASK_CF_PILOT_MASK_IDX_A
Definition: ar9003_phy.h:226
#define AR_PHY_CCA_2
Definition: ar9003_phy.h:878
#define AR_AGG_WEP_ENABLE_FIX
Definition: reg.h:1893
#define DBG2(...)
Definition: compiler.h:515
#define AR_PHY_MODE_DYNAMIC
Definition: ar9002_phy.h:401
#define AR_PHY_RADAR_1_RELPWR_THRESH
Definition: ar9002_phy.h:241
#define AR_PHY_CCA_0
Definition: ar9003_phy.h:260
#define AR_PHY_SPUR_MASK_A
Definition: ar9003_phy.h:429
static int ar9003_hw_set_channel(struct ath_hw *ah, struct ath9k_channel *chan)
ar9003_hw_set_channel - set channel on single-chip device @ah: atheros hardware structure @chan:
#define AR_PHY_9485_ANT_DIV_MAIN_GAINTB
Definition: ar9003_phy.h:284
#define AR_ADHOC_MCAST_KEYID_ENABLE
Definition: reg.h:1894
#define AR_PHY_GC_GF_DETECT_EN
Definition: ar9003_phy.h:685
#define AR_PHY_SYNTH_CONTROL
Definition: ar9002_phy.h:158