iPXE
bnxt.h
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1 /*
2  * Copyright © 2018 Broadcom. All Rights Reserved.
3  * The term “Broadcom” refers to Broadcom Inc. and/or its subsidiaries.
4 
5  * This program is free software; you can redistribute it and/or modify it under
6  * the terms of version 2 of the GNU General Public License as published by the
7  * Free Software Foundation.
8 
9  * This program is distributed in the hope that it will be useful.
10  * ALL EXPRESS OR IMPLIED CONDITIONS, REPRESENTATIONS AND WARRANTIES, INCLUDING
11  * ANY IMPLIED WARRANTY OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR
12  * NON-INFRINGEMENT, ARE DISCLAIMED, EXCEPT TO THE EXTENT THAT SUCH DISCLAIMERS
13  * ARE HELD TO BE LEGALLY INVALID. See the GNU General Public License for more
14  * details, a copy of which can be found in the file COPYING included with this
15  * package.
16  */
17 
18 #undef ERRFILE
19 #define ERRFILE ERRFILE_tg3
20 
21 #define __le16 u16
22 #define __le32 u32
23 #define __le64 u64
24 #define __be16 u16
25 #define __be32 u32
26 #define __be64 u64
27 
28 #define dma_addr_t unsigned long
29 
30 union dma_addr64_t {
33 };
34 
35 #include "bnxt_hsi.h"
36 
37 #define DRV_MODULE_NAME "bnxt"
38 #define IPXE_VERSION_MAJOR 1
39 #define IPXE_VERSION_MINOR 0
40 #define IPXE_VERSION_UPDATE 0
41 
42 /*
43  * Broadcom ethernet driver defines.
44  */
45 #define FLAG_SET(f, b) ((f) |= (b))
46 #define FLAG_TEST(f, b) ((f) & (b))
47 #define FLAG_RESET(f, b) ((f) &= ~(b))
48 #define BNXT_FLAG_HWRM_SHORT_CMD_SUPP 0x0001
49 #define BNXT_FLAG_HWRM_SHORT_CMD_REQ 0x0002
50 #define BNXT_FLAG_RESOURCE_QCAPS_SUPPORT 0x0004
51 #define BNXT_FLAG_MULTI_HOST 0x0008
52 #define BNXT_FLAG_NPAR_MODE 0x0010
53 #define BNXT_FLAG_ATOMICS_ENABLE 0x0020
54 #define BNXT_FLAG_PCI_VF 0x0040
55 #define BNXT_FLAG_LINK_SPEEDS2 0x0080
56 #define BNXT_FLAG_IS_CHIP_P5 0x0100
57 #define BNXT_FLAG_IS_CHIP_P5_PLUS 0x0200
58 #define BNXT_FLAG_IS_CHIP_P7 0x0400
59 /*******************************************************************************
60  * Status codes.
61  ******************************************************************************/
62 #define STATUS_SUCCESS 0
63 #define STATUS_FAILURE 1
64 #define STATUS_NO_RESOURCE 2
65 #define STATUS_INVALID_PARAMETER 3
66 #define STATUS_LINK_ACTIVE 4
67 #define STATUS_LINK_DOWN 5
68 #define STATUS_LINK_SETTING_MISMATCH 6
69 #define STATUS_TOO_MANY_FRAGMENTS 7
70 #define STATUS_TRANSMIT_ABORTED 8
71 #define STATUS_TRANSMIT_ERROR 9
72 #define STATUS_RECEIVE_ABORTED 10
73 #define STATUS_RECEIVE_ERROR 11
74 #define STATUS_INVALID_PACKET_SIZE 12
75 #define STATUS_NO_MAP_REGISTER 13
76 #define STATUS_UNKNOWN_ADAPTER 14
77 #define STATUS_NO_COALESCE_BUFFER 15
78 #define STATUS_UNKNOWN_PHY 16
79 #define STATUS_PENDING 17
80 #define STATUS_NO_TX_DESC 18
81 #define STATUS_NO_TX_BD 19
82 #define STATUS_UNKNOWN_MEDIUM 20
83 #define STATUS_RESOURCE 21
84 #define STATUS_ABORT_REASON_DISCONNECT 22
85 #define STATUS_ABORT_REASON_UPLOAD 23
86 #define STATUS_TIMEOUT 0xffff
87 /*******************************************************************************
88  * Receive filter masks.
89  ******************************************************************************/
90 #define RX_MASK_ACCEPT_NONE 0x0000
91 #define RX_MASK_ACCEPT_UNICAST 0x0001
92 #define RX_MASK_ACCEPT_MULTICAST 0x0002
93 #define RX_MASK_ACCEPT_ALL_MULTICAST 0x0004
94 #define RX_MASK_ACCEPT_BROADCAST 0x0008
95 #define RX_MASK_ACCEPT_ERROR_PACKET 0x0010
96 #define RX_MASK_PROMISCUOUS_MODE 0x10000
97 /*******************************************************************************
98  * media speed.
99  ******************************************************************************/
100 #define MEDIUM_SPEED_AUTONEG 0x0000L
101 #define MEDIUM_SPEED_UNKNOWN 0x0000L
102 #define MEDIUM_SPEED_10MBPS 0x0100L
103 #define MEDIUM_SPEED_100MBPS 0x0200L
104 #define MEDIUM_SPEED_1000MBPS 0x0300L
105 #define MEDIUM_SPEED_2500MBPS 0x0400L
106 #define MEDIUM_SPEED_10GBPS 0x0600L
107 #define MEDIUM_SPEED_20GBPS 0x0700L
108 #define MEDIUM_SPEED_25GBPS 0x0800L
109 #define MEDIUM_SPEED_40GBPS 0x0900L
110 #define MEDIUM_SPEED_50GBPS 0x0a00L
111 #define MEDIUM_SPEED_100GBPS 0x0b00L
112 #define MEDIUM_SPEED_200GBPS 0x0c00L
113 #define MEDIUM_SPEED_50PAM4GBPS 0x0d00L
114 #define MEDIUM_SPEED_100PAM4GBPS 0x0e00L
115 #define MEDIUM_SPEED_100PAM4_112GBPS 0x0f00L
116 #define MEDIUM_SPEED_200PAM4_112GBPS 0x1000L
117 #define MEDIUM_SPEED_400PAM4GBPS 0x2000L
118 #define MEDIUM_SPEED_400PAM4_112GBPS 0x3000L
119 #define MEDIUM_SPEED_AUTONEG_1G_FALLBACK 0x8000L /* Serdes */
120 #define MEDIUM_SPEED_AUTONEG_2_5G_FALLBACK 0x8100L /* Serdes */
121 #define MEDIUM_SPEED_HARDWARE_DEFAULT 0xff00L /* Serdes nvram def.*/
122 #define MEDIUM_SPEED_MASK 0xff00L
123 #define GET_MEDIUM_SPEED(m) ((m) & MEDIUM_SPEED_MASK)
124 #define SET_MEDIUM_SPEED(bp, s) ((bp->medium & ~MEDIUM_SPEED_MASK) | s)
125 #define MEDIUM_UNKNOWN_DUPLEX 0x00000L
126 #define MEDIUM_FULL_DUPLEX 0x00000L
127 #define MEDIUM_HALF_DUPLEX 0x10000L
128 #define GET_MEDIUM_DUPLEX(m) ((m) & MEDIUM_HALF_DUPLEX)
129 #define SET_MEDIUM_DUPLEX(bp, d) ((bp->medium & ~MEDIUM_HALF_DUPLEX) | d)
130 #define MEDIUM_SELECTIVE_AUTONEG 0x01000000L
131 #define GET_MEDIUM_AUTONEG_MODE(m) ((m) & 0xff000000L)
132 #define PCICFG_ME_REGISTER 0x98
133 #define GRC_COM_CHAN_BASE 0
134 #define GRC_COM_CHAN_TRIG 0x100
135 #define GRC_IND_BAR_0_ADDR 0x78
136 #define GRC_IND_BAR_1_ADDR 0x7C
137 #define GRC_IND_BAR_0_DATA 0x80
138 #define GRC_IND_BAR_1_DATA 0x84
139 #define GRC_BASE_WIN_0 0x400
140 #define GRC_DATA_WIN_0 0x1000
141 #define HWRM_CMD_DEFAULT_TIMEOUT 500 /* in Miliseconds */
142 #define HWRM_CMD_POLL_WAIT_TIME 100 /* In MicroeSconds */
143 #define HWRM_CMD_DEFAULT_MULTIPLAYER(a) ((a) * 10)
144 #define HWRM_CMD_FLASH_MULTIPLAYER(a) ((a) * 100)
145 #define HWRM_CMD_FLASH_ERASE_MULTIPLAYER(a) ((a) * 1000)
146 #define HWRM_CMD_WAIT(b) ((bp->hwrm_cmd_timeout) * (b))
147 #define MAX_ETHERNET_PACKET_BUFFER_SIZE 1536
148 #define DEFAULT_NUMBER_OF_CMPL_RINGS 0x01
149 #define DEFAULT_NUMBER_OF_TX_RINGS 0x01
150 #define DEFAULT_NUMBER_OF_RX_RINGS 0x01
151 #define DEFAULT_NUMBER_OF_RING_GRPS 0x01
152 #define DEFAULT_NUMBER_OF_STAT_CTXS 0x01
153 #define NUM_RX_BUFFERS 8
154 #define MAX_RX_DESC_CNT 16
155 #define MAX_TX_DESC_CNT 16
156 #define MAX_CQ_DESC_CNT 64
157 #define TX_RING_BUFFER_SIZE (MAX_TX_DESC_CNT * sizeof(struct tx_bd_short))
158 #define RX_RING_BUFFER_SIZE \
159  (MAX_RX_DESC_CNT * sizeof(struct rx_prod_pkt_bd))
160 #define CQ_RING_BUFFER_SIZE (MAX_CQ_DESC_CNT * sizeof(struct cmpl_base))
161 #define BNXT_DMA_ALIGNMENT 256 //64
162 #define DMA_ALIGN_4K 4096 //thor tx & rx
163 #define REQ_BUFFER_SIZE 1024
164 #define RESP_BUFFER_SIZE 1024
165 #define DMA_BUFFER_SIZE 1024
166 #define LM_PAGE_BITS(a) (a)
167 #define BNXT_RX_STD_DMA_SZ (1536 + 64 + 2)
168 #define NEXT_IDX(N, S) (((N) + 1) & ((S) - 1))
169 #define BD_NOW(bd, entry, len) (&((u8 *)(bd))[(entry) * (len)])
170 #define BNXT_CQ_INTR_MODE(vf) (\
171  ((vf) ? RING_ALLOC_REQ_INT_MODE_MSIX : RING_ALLOC_REQ_INT_MODE_POLL))
172 /* Set default link timeout period to 1 second */
173 #define LINK_DEFAULT_TIMEOUT 1000
174 #define LINK_POLL_WAIT_TIME 100 /* In Miliseconds */
175 #define RX_MASK (\
176  RX_MASK_ACCEPT_BROADCAST | \
177  RX_MASK_ACCEPT_ALL_MULTICAST | \
178  RX_MASK_ACCEPT_MULTICAST)
179 #define MAX_NQ_DESC_CNT 64
180 #define NQ_RING_BUFFER_SIZE (MAX_NQ_DESC_CNT * sizeof(struct cmpl_base))
181 #define TX_RING_QID (FLAG_TEST(bp->flags, BNXT_FLAG_IS_CHIP_P5_PLUS) ? (u16)bp->queue_id : ((u16)bp->port_idx * 10))
182 #define RX_RING_QID (FLAG_TEST(bp->flags, BNXT_FLAG_IS_CHIP_P5_PLUS) ? bp->queue_id : 0)
183 #define STAT_CTX_ID ((bp->vf || FLAG_TEST(bp->flags, BNXT_FLAG_IS_CHIP_P5_PLUS)) ? bp->stat_ctx_id : 0)
184 #define TX_AVAIL(r) (r - 1)
185 #define TX_IN_USE(a, b, c) ((a - b) & (c - 1))
186 #define NO_MORE_NQ_BD_TO_SERVICE 1
187 #define SERVICE_NEXT_NQ_BD 0
188 #define NO_MORE_CQ_BD_TO_SERVICE 1
189 #define SERVICE_NEXT_CQ_BD 0
190 #define MAC_HDR_SIZE 12
191 #define VLAN_HDR_SIZE 4
192 #define ETHERTYPE_VLAN 0x8100
193 #define BYTE_SWAP_S(w) (\
194  (((w) & 0xff00) >> 8) | \
195  (((w) & 0x00ff) << 8))
196 #define DB_OFFSET_PF 0x10000
197 #define DB_OFFSET_VF 0x4000
198 #define DBC_MSG_IDX(idx) (\
199  ((idx) << DBC_DBC_INDEX_SFT) & DBC_DBC_INDEX_MASK)
200 #define DBC_MSG_XID(xid, flg) (\
201  (((xid) << DBC_DBC_XID_SFT) & DBC_DBC_XID_MASK) | \
202  DBC_DBC_PATH_L2 | (FLAG_TEST ( bp->flags, BNXT_FLAG_IS_CHIP_P7 ) ? DBC_DBC_VALID : 0) | (flg))
203 #define DBC_MSG_EPCH(idx) (\
204  ((idx) << DBC_DBC_EPOCH_SFT))
205 #define DBC_MSG_TOGGLE(idx) (\
206  ((idx) << DBC_DBC_TOGGLE_SFT) & DBC_DBC_TOGGLE_MASK)
207 #define PHY_STATUS 0x0001
208 #define PHY_SPEED 0x0002
209 #define DETECT_MEDIA 0x0004
210 #define SUPPORT_SPEEDS 0x0008
211 #define SUPPORT_SPEEDS2 0x0010
212 #define QCFG_PHY_ALL (\
213  SUPPORT_SPEEDS | SUPPORT_SPEEDS2 | \
214  DETECT_MEDIA | PHY_SPEED | PHY_STATUS)
215 #define str_mbps "Mbps"
216 #define str_gbps "Gbps"
217 /*
218  * Broadcom ethernet driver nvm defines.
219  */
220 /* nvm cfg 203 - u32 link_settings */
221 #define LINK_SPEED_DRV_NUM 203
222 #define LINK_SPEED_DRV_MASK 0x0000000F
223 #define LINK_SPEED_DRV_SHIFT 0
224 #define LINK_SPEED_DRV_AUTONEG 0x0
225 #define NS_LINK_SPEED_DRV_AUTONEG 0x0
226 #define LINK_SPEED_DRV_1G 0x1
227 #define NS_LINK_SPEED_DRV_1G 0x1
228 #define LINK_SPEED_DRV_10G 0x2
229 #define NS_LINK_SPEED_DRV_10G 0x2
230 #define LINK_SPEED_DRV_25G 0x3
231 #define NS_LINK_SPEED_DRV_25G 0x3
232 #define LINK_SPEED_DRV_40G 0x4
233 #define NS_LINK_SPEED_DRV_40G 0x4
234 #define LINK_SPEED_DRV_50G 0x5
235 #define NS_LINK_SPEED_DRV_50G 0x5
236 #define LINK_SPEED_DRV_100G 0x6
237 #define NS_LINK_SPEED_DRV_100G 0x6
238 #define LINK_SPEED_DRV_200G 0x7
239 #define NS_LINK_SPEED_DRV_200G 0x7
240 #define LINK_SPEED_DRV_2_5G 0xE
241 #define NS_LINK_SPEED_DRV_2_5G 0xE
242 #define LINK_SPEED_DRV_100M 0xF
243 #define NS_LINK_SPEED_DRV_100M 0xF
244 /* nvm cfg 201 - u32 speed_cap_mask */
245 #define SPEED_CAPABILITY_DRV_MASK 0x0000FFFF
246 #define SPEED_CAPABILITY_DRV_SHIFT 0
247 #define SPEED_CAPABILITY_DRV_1G 0x1
248 #define NS_SPEED_CAPABILITY_DRV_1G 0x1
249 #define SPEED_CAPABILITY_DRV_10G 0x2
250 #define NS_SPEED_CAPABILITY_DRV_10G 0x2
251 #define SPEED_CAPABILITY_DRV_25G 0x4
252 #define NS_SPEED_CAPABILITY_DRV_25G 0x4
253 #define SPEED_CAPABILITY_DRV_40G 0x8
254 #define NS_SPEED_CAPABILITY_DRV_40G 0x8
255 #define SPEED_CAPABILITY_DRV_50G 0x10
256 #define NS_SPEED_CAPABILITY_DRV_50G 0x10
257 #define SPEED_CAPABILITY_DRV_100G 0x20
258 #define NS_SPEED_CAPABILITY_DRV_100G 0x20
259 #define SPEED_CAPABILITY_DRV_200G 0x40
260 #define NS_SPEED_CAPABILITY_DRV_200G 0x40
261 #define SPEED_CAPABILITY_DRV_2_5G 0x4000
262 #define NS_SPEED_CAPABILITY_DRV_2_5G 0x4000
263 #define SPEED_CAPABILITY_DRV_100M 0x8000
264 #define NS_SPEED_CAPABILITY_DRV_100M 0x8000
265 /* nvm cfg 202 */
266 #define SPEED_CAPABILITY_FW_MASK 0xFFFF0000
267 #define SPEED_CAPABILITY_FW_SHIFT 16
268 #define SPEED_CAPABILITY_FW_1G (0x1L << 16)
269 #define NS_SPEED_CAPABILITY_FW_1G (0x1)
270 #define SPEED_CAPABILITY_FW_10G (0x2L << 16)
271 #define NS_SPEED_CAPABILITY_FW_10G (0x2)
272 #define SPEED_CAPABILITY_FW_25G (0x4L << 16)
273 #define NS_SPEED_CAPABILITY_FW_25G (0x4)
274 #define SPEED_CAPABILITY_FW_40G (0x8L << 16)
275 #define NS_SPEED_CAPABILITY_FW_40G (0x8)
276 #define SPEED_CAPABILITY_FW_50G (0x10L << 16)
277 #define NS_SPEED_CAPABILITY_FW_50G (0x10)
278 #define SPEED_CAPABILITY_FW_100G (0x20L << 16)
279 #define NS_SPEED_CAPABILITY_FW_100G (0x20)
280 #define SPEED_CAPABILITY_FW_200G (0x40L << 16)
281 #define NS_SPEED_CAPABILITY_FW_200G (0x40)
282 #define SPEED_CAPABILITY_FW_2_5G (0x4000L << 16)
283 #define NS_SPEED_CAPABILITY_FW_2_5G (0x4000)
284 #define SPEED_CAPABILITY_FW_100M (0x8000UL << 16)
285 #define NS_SPEED_CAPABILITY_FW_100M (0x8000)
286 /* nvm cfg 205 */
287 #define LINK_SPEED_FW_NUM 205
288 #define LINK_SPEED_FW_MASK 0x00000780
289 #define LINK_SPEED_FW_SHIFT 7
290 #define LINK_SPEED_FW_AUTONEG (0x0L << 7)
291 #define NS_LINK_SPEED_FW_AUTONEG (0x0)
292 #define LINK_SPEED_FW_1G (0x1L << 7)
293 #define NS_LINK_SPEED_FW_1G (0x1)
294 #define LINK_SPEED_FW_10G (0x2L << 7)
295 #define NS_LINK_SPEED_FW_10G (0x2)
296 #define LINK_SPEED_FW_25G (0x3L << 7)
297 #define NS_LINK_SPEED_FW_25G (0x3)
298 #define LINK_SPEED_FW_40G (0x4L << 7)
299 #define NS_LINK_SPEED_FW_40G (0x4)
300 #define LINK_SPEED_FW_50G (0x5L << 7)
301 #define NS_LINK_SPEED_FW_50G (0x5)
302 #define LINK_SPEED_FW_100G (0x6L << 7)
303 #define NS_LINK_SPEED_FW_100G (0x6)
304 #define LINK_SPEED_FW_200G (0x7L << 7)
305 #define NS_LINK_SPEED_FW_200G (0x7)
306 #define LINK_SPEED_FW_50G_PAM4 (0x8L << 7)
307 #define NS_LINK_SPEED_FW_50G_PAM4 (0x8)
308 #define LINK_SPEED_FW_100G_PAM4 (0x9L << 7)
309 #define NS_LINK_SPEED_FW_100G_PAM4 (0x9)
310 #define LINK_SPEED_FW_100G_PAM4_112 (0xAL << 7)
311 #define NS_LINK_SPEED_FW_100G_PAM4_112 (0xA)
312 #define LINK_SPEED_FW_200G_PAM4_112 (0xBL << 7)
313 #define NS_LINK_SPEED_FW_200G_PAM4_112 (0xB)
314 #define LINK_SPEED_FW_400G_PAM4 (0xCL << 7)
315 #define NS_LINK_SPEED_FW_400G_PAM4 (0xC)
316 #define LINK_SPEED_FW_400G_PAM4_112 (0xDL << 7)
317 #define NS_LINK_SPEED_FW_400G_PAM4_112 (0xD)
318 #define LINK_SPEED_FW_2_5G (0xEL << 7)
319 #define NS_LINK_SPEED_FW_2_5G (0xE)
320 #define LINK_SPEED_FW_100M (0xFL << 7)
321 #define NS_LINK_SPEED_FW_100M (0xF)
322 /* nvm cfg 210 */
323 #define D3_LINK_SPEED_FW_NUM 210
324 #define D3_LINK_SPEED_FW_MASK 0x000F0000
325 #define D3_LINK_SPEED_FW_SHIFT 16
326 #define D3_LINK_SPEED_FW_AUTONEG (0x0L << 16)
327 #define NS_D3_LINK_SPEED_FW_AUTONEG (0x0)
328 #define D3_LINK_SPEED_FW_1G (0x1L << 16)
329 #define NS_D3_LINK_SPEED_FW_1G (0x1)
330 #define D3_LINK_SPEED_FW_10G (0x2L << 16)
331 #define NS_D3_LINK_SPEED_FW_10G (0x2)
332 #define D3_LINK_SPEED_FW_25G (0x3L << 16)
333 #define NS_D3_LINK_SPEED_FW_25G (0x3)
334 #define D3_LINK_SPEED_FW_40G (0x4L << 16)
335 #define NS_D3_LINK_SPEED_FW_40G (0x4)
336 #define D3_LINK_SPEED_FW_50G (0x5L << 16)
337 #define NS_D3_LINK_SPEED_FW_50G (0x5)
338 #define D3_LINK_SPEED_FW_100G (0x6L << 16)
339 #define NS_D3_LINK_SPEED_FW_100G (0x6)
340 #define D3_LINK_SPEED_FW_200G (0x7L << 16)
341 #define NS_D3_LINK_SPEED_FW_200G (0x7)
342 #define D3_LINK_SPEED_FW_2_5G (0xEL << 16)
343 #define NS_D3_LINK_SPEED_FW_2_5G (0xE)
344 #define D3_LINK_SPEED_FW_100M (0xFL << 16)
345 #define NS_D3_LINK_SPEED_FW_100M (0xF)
346 /* nvm cfg 211 */
347 #define D3_FLOW_CONTROL_FW_NUM 211
348 #define D3_FLOW_CONTROL_FW_MASK 0x00700000
349 #define D3_FLOW_CONTROL_FW_SHIFT 20
350 #define D3_FLOW_CONTROL_FW_AUTO (0x0L << 20)
351 #define NS_D3_FLOW_CONTROL_FW_AUTO (0x0)
352 #define D3_FLOW_CONTROL_FW_TX (0x1L << 20)
353 #define NS_D3_FLOW_CONTROL_FW_TX (0x1)
354 #define D3_FLOW_CONTROL_FW_RX (0x2L << 20)
355 #define NS_D3_FLOW_CONTROL_FW_RX (0x2)
356 #define D3_FLOW_CONTROL_FW_BOTH (0x3L << 20)
357 #define NS_D3_FLOW_CONTROL_FW_BOTH (0x3)
358 #define D3_FLOW_CONTROL_FW_NONE (0x4L << 20)
359 #define NS_D3_FLOW_CONTROL_FW_NONE (0x4)
360 /* nvm cfg 213 */
361 #define PORT_CFG_LINK_SETTINGS_MEDIA_AUTO_DETECT_NUM 213
362 #define PORT_CFG_LINK_SETTINGS_MEDIA_AUTO_DETECT_MASK 0x02000000
363 #define PORT_CFG_LINK_SETTINGS_MEDIA_AUTO_DETECT_SHIFT 25
364 #define PORT_CFG_LINK_SETTINGS_MEDIA_AUTO_DETECT_DISABLED (0x0L << 25)
365 #define NS_PORT_CFG_LINK_SETTINGS_MEDIA_AUTO_DETECT_DISABLED (0x0)
366 #define PORT_CFG_LINK_SETTINGS_MEDIA_AUTO_DETECT_ENABLED (0x1L << 25)
367 #define NS_PORT_CFG_LINK_SETTINGS_MEDIA_AUTO_DETECT_ENABLED (0x1)
368 /* nvm cfg 357 - u32 mba_cfg2 */
369 #define FUNC_CFG_PRE_BOOT_MBA_VLAN_VALUE_NUM 357
370 #define FUNC_CFG_PRE_BOOT_MBA_VLAN_VALUE_MASK 0x0000FFFF
371 #define FUNC_CFG_PRE_BOOT_MBA_VLAN_VALUE_SHIFT 0
372 /* nvm cfg 358 - u32 mba_cfg2 */
373 #define FUNC_CFG_PRE_BOOT_MBA_VLAN_NUM 358
374 #define FUNC_CFG_PRE_BOOT_MBA_VLAN_MASK 0x00010000
375 #define FUNC_CFG_PRE_BOOT_MBA_VLAN_SHIFT 16
376 #define FUNC_CFG_PRE_BOOT_MBA_VLAN_DISABLED (0x0L << 16)
377 #define NS_FUNC_CFG_PRE_BOOT_MBA_VLAN_DISABLED (0x0)
378 #define FUNC_CFG_PRE_BOOT_MBA_VLAN_ENABLED (0x1L << 16)
379 #define NS_FUNC_CFG_PRE_BOOT_MBA_VLAN_ENABLED (0x1)
380 
381 struct tx_doorbell {
383 #define TX_DOORBELL_IDX_MASK 0xffffffUL
384 #define TX_DOORBELL_IDX_SFT 0
385 #define TX_DOORBELL_KEY_MASK 0xf0000000UL
386 #define TX_DOORBELL_KEY_SFT 28
387  #define TX_DOORBELL_KEY_TX (0x0UL << 28)
388  #define TX_DOORBELL_KEY_LAST TX_DOORBELL_KEY_TX
389 };
390 
391 struct rx_doorbell {
393 #define RX_DOORBELL_IDX_MASK 0xffffffUL
394 #define RX_DOORBELL_IDX_SFT 0
395 #define RX_DOORBELL_KEY_MASK 0xf0000000UL
396 #define RX_DOORBELL_KEY_SFT 28
397  #define RX_DOORBELL_KEY_RX (0x1UL << 28)
398  #define RX_DOORBELL_KEY_LAST RX_DOORBELL_KEY_RX
399 };
400 
403 #define CMPL_DOORBELL_IDX_MASK 0xffffffUL
404 #define CMPL_DOORBELL_IDX_SFT 0
405 #define CMPL_DOORBELL_IDX_VALID 0x4000000UL
406 #define CMPL_DOORBELL_MASK 0x8000000UL
407 #define CMPL_DOORBELL_KEY_MASK 0xf0000000UL
408 #define CMPL_DOORBELL_KEY_SFT 28
409  #define CMPL_DOORBELL_KEY_CMPL (0x2UL << 28)
410  #define CMPL_DOORBELL_KEY_LAST CMPL_DOORBELL_KEY_CMPL
411 };
412 
413 /* dbc_dbc (size:64b/8B) */
414 struct dbc_dbc {
416  #define DBC_DBC_INDEX_MASK 0xffffffUL
417  #define DBC_DBC_INDEX_SFT 0
418  #define DBC_DBC_EPOCH 0x1000000UL
419  #define DBC_DBC_EPOCH_SFT 24
420  #define DBC_DBC_TOGGLE_MASK 0x6000000UL
421  #define DBC_DBC_TOGGLE_SFT 25
423  #define DBC_DBC_XID_MASK 0xfffffUL
424  #define DBC_DBC_XID_SFT 0
425  #define DBC_DBC_PATH_MASK 0x3000000UL
426  #define DBC_DBC_PATH_SFT 24
427  #define DBC_DBC_PATH_ROCE (0x0UL << 24)
428  #define DBC_DBC_PATH_L2 (0x1UL << 24)
429  #define DBC_DBC_PATH_ENGINE (0x2UL << 24)
430  #define DBC_DBC_PATH_LAST DBC_DBC_PATH_ENGINE
431  #define DBC_DBC_VALID 0x4000000UL
432  #define DBC_DBC_DEBUG_TRACE 0x8000000UL
433  #define DBC_DBC_TYPE_MASK 0xf0000000UL
434  #define DBC_DBC_TYPE_SFT 28
435  #define DBC_DBC_TYPE_SQ (0x0UL << 28)
436  #define DBC_DBC_TYPE_RQ (0x1UL << 28)
437  #define DBC_DBC_TYPE_SRQ (0x2UL << 28)
438  #define DBC_DBC_TYPE_SRQ_ARM (0x3UL << 28)
439  #define DBC_DBC_TYPE_CQ (0x4UL << 28)
440  #define DBC_DBC_TYPE_CQ_ARMSE (0x5UL << 28)
441  #define DBC_DBC_TYPE_CQ_ARMALL (0x6UL << 28)
442  #define DBC_DBC_TYPE_CQ_ARMENA (0x7UL << 28)
443  #define DBC_DBC_TYPE_SRQ_ARMENA (0x8UL << 28)
444  #define DBC_DBC_TYPE_CQ_CUTOFF_ACK (0x9UL << 28)
445  #define DBC_DBC_TYPE_NQ (0xaUL << 28)
446  #define DBC_DBC_TYPE_NQ_ARM (0xbUL << 28)
447  #define DBC_DBC_TYPE_NULL (0xfUL << 28)
448  #define DBC_DBC_TYPE_LAST DBC_DBC_TYPE_NULL
449 };
450 
451 /*******************************************************************************
452  * Transmit info.
453  *****************************************************************************/
454 struct tx_bd_short {
456 #define TX_BD_SHORT_TYPE_MASK 0x3fUL
457 #define TX_BD_SHORT_TYPE_SFT 0
458 #define TX_BD_SHORT_TYPE_TX_BD_SHORT 0x0UL
459 #define TX_BD_SHORT_TYPE_LAST TX_BD_SHORT_TYPE_TX_BD_SHORT
460 #define TX_BD_SHORT_FLAGS_MASK 0xffc0UL
461 #define TX_BD_SHORT_FLAGS_SFT 6
462 #define TX_BD_SHORT_FLAGS_PACKET_END 0x40UL
463 #define TX_BD_SHORT_FLAGS_NO_CMPL 0x80UL
464 #define TX_BD_SHORT_FLAGS_BD_CNT_MASK 0x1f00UL
465 #define TX_BD_SHORT_FLAGS_BD_CNT_SFT 8
466 #define TX_BD_SHORT_FLAGS_LHINT_MASK 0x6000UL
467 #define TX_BD_SHORT_FLAGS_LHINT_SFT 13
468 #define TX_BD_SHORT_FLAGS_LHINT_LT512 (0x0UL << 13)
469 #define TX_BD_SHORT_FLAGS_LHINT_LT1K (0x1UL << 13)
470 #define TX_BD_SHORT_FLAGS_LHINT_LT2K (0x2UL << 13)
471 #define TX_BD_SHORT_FLAGS_LHINT_GTE2K (0x3UL << 13)
472 #define TX_BD_SHORT_FLAGS_LHINT_LAST TX_BD_SHORT_FLAGS_LHINT_GTE2K
473 #define TX_BD_SHORT_FLAGS_COAL_NOW 0x8000UL
477 };
478 
479 struct tx_cmpl {
481 #define TX_CMPL_TYPE_MASK 0x3fUL
482 #define TX_CMPL_TYPE_SFT 0
483 #define TX_CMPL_TYPE_TX_L2 0x0UL
484 #define TX_CMPL_TYPE_LAST TX_CMPL_TYPE_TX_L2
485 #define TX_CMPL_FLAGS_MASK 0xffc0UL
486 #define TX_CMPL_FLAGS_SFT 6
487 #define TX_CMPL_FLAGS_ERROR 0x40UL
488 #define TX_CMPL_FLAGS_PUSH 0x80UL
492 #define TX_CMPL_V 0x1UL
493 #define TX_CMPL_ERRORS_MASK 0xfffeUL
494 #define TX_CMPL_ERRORS_SFT 1
495 #define TX_CMPL_ERRORS_BUFFER_ERROR_MASK 0xeUL
496 #define TX_CMPL_ERRORS_BUFFER_ERROR_SFT 1
497 #define TX_CMPL_ERRORS_BUFFER_ERROR_NO_ERROR (0x0UL << 1)
498 #define TX_CMPL_ERRORS_BUFFER_ERROR_BAD_FMT (0x2UL << 1)
499 #define TX_CMPL_ERRORS_BUFFER_ERROR_LAST TX_CMPL_ERRORS_BUFFER_ERROR_BAD_FMT
500 #define TX_CMPL_ERRORS_ZERO_LENGTH_PKT 0x10UL
501 #define TX_CMPL_ERRORS_EXCESSIVE_BD_LENGTH 0x20UL
502 #define TX_CMPL_ERRORS_DMA_ERROR 0x40UL
503 #define TX_CMPL_ERRORS_HINT_TOO_SHORT 0x80UL
504 #define TX_CMPL_ERRORS_POISON_TLP_ERROR 0x100UL
507 };
508 
509 struct tx_info {
510  void *bd_virt;
512  u16 prod_id; /* Tx producer index. */
515  u32 cnt; /* Tx statistics. */
518  u8 res[3];
519 };
520 
521 struct cmpl_base {
523 #define CMPL_BASE_TYPE_MASK 0x3fUL
524 #define CMPL_BASE_TYPE_SFT 0
525 #define CMPL_BASE_TYPE_TX_L2 0x0UL
526 #define CMPL_BASE_TYPE_RX_L2 0x11UL
527 #define CMPL_BASE_TYPE_RX_AGG 0x12UL
528 #define CMPL_BASE_TYPE_RX_TPA_START 0x13UL
529 #define CMPL_BASE_TYPE_RX_TPA_END 0x15UL
530 #define CMPL_BASE_TYPE_RX_L2_V3 0x17UL
531 #define CMPL_BASE_TYPE_STAT_EJECT 0x1aUL
532 #define CMPL_BASE_TYPE_HWRM_DONE 0x20UL
533 #define CMPL_BASE_TYPE_HWRM_FWD_REQ 0x22UL
534 #define CMPL_BASE_TYPE_HWRM_FWD_RESP 0x24UL
535 #define CMPL_BASE_TYPE_HWRM_ASYNC_EVENT 0x2eUL
536 #define CMPL_BASE_TYPE_CQ_NOTIFICATION 0x30UL
537 #define CMPL_BASE_TYPE_SRQ_EVENT 0x32UL
538 #define CMPL_BASE_TYPE_DBQ_EVENT 0x34UL
539 #define CMPL_BASE_TYPE_QP_EVENT 0x38UL
540 #define CMPL_BASE_TYPE_FUNC_EVENT 0x3aUL
541 #define CMPL_BASE_TYPE_LAST CMPL_BASE_TYPE_FUNC_EVENT
545 #define CMPL_BASE_V 0x1UL
546 #define CMPL_BASE_INFO3_MASK 0xfffffffeUL
547 #define CMPL_BASE_INFO3_SFT 1
549 };
550 
551 struct cmp_info {
552  void *bd_virt;
557  u8 res[2];
558 };
559 
560 /* Completion Queue Notification */
561 /* nq_cn (size:128b/16B) */
562 struct nq_base {
564 /*
565  * This field indicates the exact type of the completion.
566  * By convention, the LSB identifies the length of the
567  * record in 16B units. Even values indicate 16B
568  * records. Odd values indicate 32B
569  * records.
570  */
571 #define NQ_CN_TYPE_MASK 0x3fUL
572 #define NQ_CN_TYPE_SFT 0
573 #define NQ_CN_TOGGLE_MASK 0xc0UL
574 #define NQ_CN_TOGGLE_SFT 6
575 /* CQ Notification */
576  #define NQ_CN_TYPE_CQ_NOTIFICATION 0x30UL
577  #define NQ_CN_TYPE_LAST NQ_CN_TYPE_CQ_NOTIFICATION
579 /*
580  * This is an application level ID used to identify the
581  * CQ. This field carries the lower 32b of the value.
582  */
585 /*
586  * This value is written by the NIC such that it will be different
587  * for each pass through the completion queue. The even passes
588  * will write 1. The odd passes will write 0.
589  */
590 #define NQ_CN_V 0x1UL
591 /*
592  * This is an application level ID used to identify the
593  * CQ. This field carries the upper 32b of the value.
594  */
596 };
597 
598 struct nq_info {
599  void *bd_virt;
605  u8 res[1];
606 };
607 
608 struct rx_pkt_cmpl {
610 #define RX_PKT_CMPL_TYPE_MASK 0x3fUL
611 #define RX_PKT_CMPL_TYPE_SFT 0
612 #define RX_PKT_CMPL_TYPE_RX_L2 0x11UL
613 #define RX_PKT_CMPL_TYPE_LAST RX_PKT_CMPL_TYPE_RX_L2
614 #define RX_PKT_CMPL_FLAGS_MASK 0xffc0UL
615 #define RX_PKT_CMPL_FLAGS_SFT 6
616 #define RX_PKT_CMPL_FLAGS_ERROR 0x40UL
617 #define RX_PKT_CMPL_FLAGS_PLACEMENT_MASK 0x380UL
618 #define RX_PKT_CMPL_FLAGS_PLACEMENT_SFT 7
619 #define RX_PKT_CMPL_FLAGS_PLACEMENT_NORMAL (0x0UL << 7)
620 #define RX_PKT_CMPL_FLAGS_PLACEMENT_JUMBO (0x1UL << 7)
621 #define RX_PKT_CMPL_FLAGS_PLACEMENT_HDS (0x2UL << 7)
622 #define RX_PKT_CMPL_FLAGS_PLACEMENT_LAST RX_PKT_CMPL_FLAGS_PLACEMENT_HDS
623 #define RX_PKT_CMPL_FLAGS_RSS_VALID 0x400UL
624 #define RX_PKT_CMPL_FLAGS_UNUSED 0x800UL
625 #define RX_PKT_CMPL_FLAGS_ITYPE_MASK 0xf000UL
626 #define RX_PKT_CMPL_FLAGS_ITYPE_SFT 12
627 #define RX_PKT_CMPL_FLAGS_ITYPE_NOT_KNOWN (0x0UL << 12)
628 #define RX_PKT_CMPL_FLAGS_ITYPE_IP (0x1UL << 12)
629 #define RX_PKT_CMPL_FLAGS_ITYPE_TCP (0x2UL << 12)
630 #define RX_PKT_CMPL_FLAGS_ITYPE_UDP (0x3UL << 12)
631 #define RX_PKT_CMPL_FLAGS_ITYPE_FCOE (0x4UL << 12)
632 #define RX_PKT_CMPL_FLAGS_ITYPE_ROCE (0x5UL << 12)
633 #define RX_PKT_CMPL_FLAGS_ITYPE_ICMP (0x7UL << 12)
634 #define RX_PKT_CMPL_FLAGS_ITYPE_PTP_WO_TIMESTAMP (0x8UL << 12)
635 #define RX_PKT_CMPL_FLAGS_ITYPE_PTP_W_TIMESTAMP (0x9UL << 12)
636 #define RX_PKT_CMPL_FLAGS_ITYPE_LAST RX_PKT_CMPL_FLAGS_ITYPE_PTP_W_TIMESTAMP
640 #define RX_PKT_CMPL_V1 0x1UL
641 #define RX_PKT_CMPL_AGG_BUFS_MASK 0x3eUL
642 #define RX_PKT_CMPL_AGG_BUFS_SFT 1
643 #define RX_PKT_CMPL_UNUSED1_MASK 0xc0UL
644 #define RX_PKT_CMPL_UNUSED1_SFT 6
649 };
650 
653 #define RX_PKT_CMPL_FLAGS2_IP_CS_CALC 0x1UL
654 #define RX_PKT_CMPL_FLAGS2_L4_CS_CALC 0x2UL
655 #define RX_PKT_CMPL_FLAGS2_T_IP_CS_CALC 0x4UL
656 #define RX_PKT_CMPL_FLAGS2_T_L4_CS_CALC 0x8UL
657 #define RX_PKT_CMPL_FLAGS2_META_FORMAT_MASK 0xf0UL
658 #define RX_PKT_CMPL_FLAGS2_META_FORMAT_SFT 4
659 #define RX_PKT_CMPL_FLAGS2_META_FORMAT_NONE (0x0UL << 4)
660 #define RX_PKT_CMPL_FLAGS2_META_FORMAT_VLAN (0x1UL << 4)
661 #define RX_PKT_CMPL_FLAGS2_META_FORMAT_LAST \
662  RX_PKT_CMPL_FLAGS2_META_FORMAT_VLAN
663 #define RX_PKT_CMPL_FLAGS2_IP_TYPE 0x100UL
665 #define RX_PKT_CMPL_METADATA_VID_MASK 0xfffUL
666 #define RX_PKT_CMPL_METADATA_VID_SFT 0
667 #define RX_PKT_CMPL_METADATA_DE 0x1000UL
668 #define RX_PKT_CMPL_METADATA_PRI_MASK 0xe000UL
669 #define RX_PKT_CMPL_METADATA_PRI_SFT 13
670 #define RX_PKT_CMPL_METADATA_TPID_MASK 0xffff0000UL
671 #define RX_PKT_CMPL_METADATA_TPID_SFT 16
673 #define RX_PKT_CMPL_V2 0x1UL
674 #define RX_PKT_CMPL_ERRORS_MASK 0xfffeUL
675 #define RX_PKT_CMPL_ERRORS_SFT 1
676 #define RX_PKT_CMPL_ERRORS_BUFFER_ERROR_MASK 0xeUL
677 #define RX_PKT_CMPL_ERRORS_BUFFER_ERROR_SFT 1
678 #define RX_PKT_CMPL_ERRORS_BUFFER_ERROR_NO_BUFFER (0x0UL << 1)
679 #define RX_PKT_CMPL_ERRORS_BUFFER_ERROR_DID_NOT_FIT (0x1UL << 1)
680 #define RX_PKT_CMPL_ERRORS_BUFFER_ERROR_NOT_ON_CHIP (0x2UL << 1)
681 #define RX_PKT_CMPL_ERRORS_BUFFER_ERROR_BAD_FORMAT (0x3UL << 1)
682 #define RX_PKT_CMPL_ERRORS_BUFFER_ERROR_LAST \
683  RX_PKT_CMPL_ERRORS_BUFFER_ERROR_BAD_FORMAT
684 #define RX_PKT_CMPL_ERRORS_IP_CS_ERROR 0x10UL
685 #define RX_PKT_CMPL_ERRORS_L4_CS_ERROR 0x20UL
686 #define RX_PKT_CMPL_ERRORS_T_IP_CS_ERROR 0x40UL
687 #define RX_PKT_CMPL_ERRORS_T_L4_CS_ERROR 0x80UL
688 #define RX_PKT_CMPL_ERRORS_CRC_ERROR 0x100UL
689 #define RX_PKT_CMPL_ERRORS_T_PKT_ERROR_MASK 0xe00UL
690 #define RX_PKT_CMPL_ERRORS_T_PKT_ERROR_SFT 9
691 #define RX_PKT_CMPL_ERRORS_T_PKT_ERROR_NO_ERROR (0x0UL << 9)
692 #define RX_PKT_CMPL_ERRORS_T_PKT_ERROR_T_L3_BAD_VERSION (0x1UL << 9)
693 #define RX_PKT_CMPL_ERRORS_T_PKT_ERROR_T_L3_BAD_HDR_LEN (0x2UL << 9)
694 #define RX_PKT_CMPL_ERRORS_T_PKT_ERROR_TUNNEL_TOTAL_ERROR (0x3UL << 9)
695 #define RX_PKT_CMPL_ERRORS_T_PKT_ERROR_T_IP_TOTAL_ERROR (0x4UL << 9)
696 #define RX_PKT_CMPL_ERRORS_T_PKT_ERROR_T_UDP_TOTAL_ERROR (0x5UL << 9)
697 #define RX_PKT_CMPL_ERRORS_T_PKT_ERROR_T_L3_BAD_TTL (0x6UL << 9)
698 #define RX_PKT_CMPL_ERRORS_T_PKT_ERROR_LAST \
699  RX_PKT_CMPL_ERRORS_T_PKT_ERROR_T_L3_BAD_TTL
700 #define RX_PKT_CMPL_ERRORS_PKT_ERROR_MASK 0xf000UL
701 #define RX_PKT_CMPL_ERRORS_PKT_ERROR_SFT 12
702 #define RX_PKT_CMPL_ERRORS_PKT_ERROR_NO_ERROR (0x0UL << 12)
703 #define RX_PKT_CMPL_ERRORS_PKT_ERROR_L3_BAD_VERSION (0x1UL << 12)
704 #define RX_PKT_CMPL_ERRORS_PKT_ERROR_L3_BAD_HDR_LEN (0x2UL << 12)
705 #define RX_PKT_CMPL_ERRORS_PKT_ERROR_L3_BAD_TTL (0x3UL << 12)
706 #define RX_PKT_CMPL_ERRORS_PKT_ERROR_IP_TOTAL_ERROR (0x4UL << 12)
707 #define RX_PKT_CMPL_ERRORS_PKT_ERROR_UDP_TOTAL_ERROR (0x5UL << 12)
708 #define RX_PKT_CMPL_ERRORS_PKT_ERROR_L4_BAD_HDR_LEN (0x6UL << 12)
709 #define RX_PKT_CMPL_ERRORS_PKT_ERROR_L4_BAD_HDR_LEN_TOO_SMALL (0x7UL << 12)
710 #define RX_PKT_CMPL_ERRORS_PKT_ERROR_L4_BAD_OPT_LEN (0x8UL << 12)
711 #define RX_PKT_CMPL_ERRORS_PKT_ERROR_LAST \
712  RX_PKT_CMPL_ERRORS_PKT_ERROR_L4_BAD_OPT_LEN
715 #define RX_PKT_CMPL_REORDER_MASK 0xffffffUL
716 #define RX_PKT_CMPL_REORDER_SFT 0
717 };
718 
721  #define RX_PKT_V3_CMPL_TYPE_MASK 0x3fUL
722  #define RX_PKT_V3_CMPL_TYPE_SFT 0
723  /*
724  * RX L2 V3 completion:
725  * Completion of and L2 RX packet. Length = 32B
726  * This is the new version of the RX_L2 completion used in Thor2
727  * and later chips.
728  */
729  #define RX_PKT_V3_CMPL_TYPE_RX_L2_V3 0x17UL
730  #define RX_PKT_V3_CMPL_TYPE_LAST RX_PKT_V3_CMPL_TYPE_RX_L2_V3
731  #define RX_PKT_V3_CMPL_FLAGS_MASK 0xffc0UL
732  #define RX_PKT_V3_CMPL_FLAGS_SFT 6
733  #define RX_PKT_V3_CMPL_FLAGS_ERROR 0x40UL
734  #define RX_PKT_V3_CMPL_FLAGS_PLACEMENT_MASK 0x380UL
735  #define RX_PKT_V3_CMPL_FLAGS_PLACEMENT_SFT 7
736  #define RX_PKT_V3_CMPL_FLAGS_PLACEMENT_NORMAL (0x0UL << 7)
737  #define RX_PKT_V3_CMPL_FLAGS_PLACEMENT_JUMBO (0x1UL << 7)
738  #define RX_PKT_V3_CMPL_FLAGS_PLACEMENT_HDS (0x2UL << 7)
739  #define RX_PKT_V3_CMPL_FLAGS_PLACEMENT_TRUNCATION (0x3UL << 7)
740  #define RX_PKT_V3_CMPL_FLAGS_PLACEMENT_LAST RX_PKT_V3_CMPL_FLAGS_PLACEMENT_TRUNCATION
741  #define RX_PKT_V3_CMPL_FLAGS_RSS_VALID 0x400UL
742  #define RX_PKT_V3_CMPL_FLAGS_PKT_METADATA_PRESENT 0x800UL
743  #define RX_PKT_V3_CMPL_FLAGS_ITYPE_MASK 0xf000UL
744  #define RX_PKT_V3_CMPL_FLAGS_ITYPE_SFT 12
745  #define RX_PKT_V3_CMPL_FLAGS_ITYPE_NOT_KNOWN (0x0UL << 12)
746  #define RX_PKT_V3_CMPL_FLAGS_ITYPE_IP (0x1UL << 12)
747  #define RX_PKT_V3_CMPL_FLAGS_ITYPE_TCP (0x2UL << 12)
748  #define RX_PKT_V3_CMPL_FLAGS_ITYPE_UDP (0x3UL << 12)
749  #define RX_PKT_V3_CMPL_FLAGS_ITYPE_FCOE (0x4UL << 12)
750  #define RX_PKT_V3_CMPL_FLAGS_ITYPE_ROCE (0x5UL << 12)
751  #define RX_PKT_V3_CMPL_FLAGS_ITYPE_ICMP (0x7UL << 12)
752  #define RX_PKT_V3_CMPL_FLAGS_ITYPE_PTP_WO_TIMESTAMP (0x8UL << 12)
753  #define RX_PKT_V3_CMPL_FLAGS_ITYPE_PTP_W_TIMESTAMP (0x9UL << 12)
754  #define RX_PKT_V3_CMPL_FLAGS_ITYPE_LAST RX_PKT_V3_CMPL_FLAGS_ITYPE_PTP_W_TIMESTAMP
758  #define RX_PKT_V3_CMPL_V1 0x1UL
759  #define RX_PKT_V3_CMPL_AGG_BUFS_MASK 0x3eUL
760  #define RX_PKT_V3_CMPL_AGG_BUFS_SFT 1
761  #define RX_PKT_V3_CMPL_UNUSED1 0x40UL
762  #define RX_PKT_V3_CMPL_RSS_HASH_TYPE_MASK 0xff80UL
763  #define RX_PKT_V3_CMPL_RSS_HASH_TYPE_SFT 7
764  #define RX_PKT_V3_CMPL_RSS_HASH_TYPE_ENUM_0 (0x0UL << 7)
765  #define RX_PKT_V3_CMPL_RSS_HASH_TYPE_ENUM_1 (0x1UL << 7)
766  #define RX_PKT_V3_CMPL_RSS_HASH_TYPE_ENUM_3 (0x3UL << 7)
767  #define RX_PKT_V3_CMPL_RSS_HASH_TYPE_ENUM_4 (0x4UL << 7)
768  #define RX_PKT_V3_CMPL_RSS_HASH_TYPE_ENUM_5 (0x5UL << 7)
769  #define RX_PKT_V3_CMPL_RSS_HASH_TYPE_ENUM_6 (0x6UL << 7)
770  #define RX_PKT_V3_CMPL_RSS_HASH_TYPE_ENUM_7 (0x7UL << 7)
771  #define RX_PKT_V3_CMPL_RSS_HASH_TYPE_ENUM_8 (0x8UL << 7)
772  #define RX_PKT_V3_CMPL_RSS_HASH_TYPE_ENUM_9 (0x9UL << 7)
773  #define RX_PKT_V3_CMPL_RSS_HASH_TYPE_ENUM_10 (0xaUL << 7)
774  #define RX_PKT_V3_CMPL_RSS_HASH_TYPE_ENUM_11 (0xbUL << 7)
775  #define RX_PKT_V3_CMPL_RSS_HASH_TYPE_ENUM_12 (0xcUL << 7)
776  #define RX_PKT_V3_CMPL_RSS_HASH_TYPE_ENUM_13 (0xdUL << 7)
777  #define RX_PKT_V3_CMPL_RSS_HASH_TYPE_ENUM_14 (0xeUL << 7)
778  #define RX_PKT_V3_CMPL_RSS_HASH_TYPE_LAST RX_PKT_V3_CMPL_RSS_HASH_TYPE_ENUM_14
780  #define RX_PKT_V3_CMPL_PAYLOAD_OFFSET_MASK 0x1ffUL
781  #define RX_PKT_V3_CMPL_PAYLOAD_OFFSET_SFT 0
782  #define RX_PKT_V3_CMPL_METADATA1_MASK 0xf000UL
783  #define RX_PKT_V3_CMPL_METADATA1_SFT 12
784  #define RX_PKT_V3_CMPL_METADATA1_TPID_SEL_MASK 0x7000UL
785  #define RX_PKT_V3_CMPL_METADATA1_TPID_SEL_SFT 12
786  #define RX_PKT_V3_CMPL_METADATA1_TPID_SEL_TPID88A8 (0x0UL << 12)
787  #define RX_PKT_V3_CMPL_METADATA1_TPID_SEL_TPID8100 (0x1UL << 12)
788  #define RX_PKT_V3_CMPL_METADATA1_TPID_SEL_TPID9100 (0x2UL << 12)
789  #define RX_PKT_V3_CMPL_METADATA1_TPID_SEL_TPID9200 (0x3UL << 12)
790  #define RX_PKT_V3_CMPL_METADATA1_TPID_SEL_TPID9300 (0x4UL << 12)
791  #define RX_PKT_V3_CMPL_METADATA1_TPID_SEL_TPIDCFG (0x5UL << 12)
792  #define RX_PKT_V3_CMPL_METADATA1_TPID_SEL_LAST RX_PKT_V3_CMPL_METADATA1_TPID_SEL_TPIDCFG
793  #define RX_PKT_V3_CMPL_METADATA1_VALID 0x8000UL
795 };
796 
799  #define RX_PKT_V3_CMPL_HI_FLAGS2_IP_CS_CALC 0x1UL
800  #define RX_PKT_V3_CMPL_HI_FLAGS2_L4_CS_CALC 0x2UL
801  #define RX_PKT_V3_CMPL_HI_FLAGS2_T_IP_CS_CALC 0x4UL
802  #define RX_PKT_V3_CMPL_HI_FLAGS2_T_L4_CS_CALC 0x8UL
803  #define RX_PKT_V3_CMPL_HI_FLAGS2_META_FORMAT_MASK 0xf0UL
804  #define RX_PKT_V3_CMPL_HI_FLAGS2_META_FORMAT_SFT 4
805  #define RX_PKT_V3_CMPL_HI_FLAGS2_META_FORMAT_NONE (0x0UL << 4)
806  #define RX_PKT_V3_CMPL_HI_FLAGS2_META_FORMAT_ACT_REC_PTR (0x1UL << 4)
807  #define RX_PKT_V3_CMPL_HI_FLAGS2_META_FORMAT_TUNNEL_ID (0x2UL << 4)
808  #define RX_PKT_V3_CMPL_HI_FLAGS2_META_FORMAT_CHDR_DATA (0x3UL << 4)
809  #define RX_PKT_V3_CMPL_HI_FLAGS2_META_FORMAT_HDR_OFFSET (0x4UL << 4)
810  #define RX_PKT_V3_CMPL_HI_FLAGS2_META_FORMAT_LAST RX_PKT_V3_CMPL_HI_FLAGS2_META_FORMAT_HDR_OFFSET
811  #define RX_PKT_V3_CMPL_HI_FLAGS2_IP_TYPE 0x100UL
812  #define RX_PKT_V3_CMPL_HI_FLAGS2_COMPLETE_CHECKSUM_CALC 0x200UL
813  #define RX_PKT_V3_CMPL_HI_FLAGS2_T_IP_TYPE 0x400UL
814  #define RX_PKT_V3_CMPL_HI_FLAGS2_T_IP_TYPE_IPV4 (0x0UL << 10)
815  #define RX_PKT_V3_CMPL_HI_FLAGS2_T_IP_TYPE_IPV6 (0x1UL << 10)
816  #define RX_PKT_V3_CMPL_HI_FLAGS2_T_IP_TYPE_LAST RX_PKT_V3_CMPL_HI_FLAGS2_T_IP_TYPE_IPV6
817  #define RX_PKT_V3_CMPL_HI_FLAGS2_COMPLETE_CHECKSUM_MASK 0xffff0000UL
818  #define RX_PKT_V3_CMPL_HI_FLAGS2_COMPLETE_CHECKSUM_SFT 16
821  #define RX_PKT_V3_CMPL_HI_V2 0x1UL
822  #define RX_PKT_V3_CMPL_HI_ERRORS_MASK 0xfffeUL
823  #define RX_PKT_V3_CMPL_HI_ERRORS_SFT 1
824  #define RX_PKT_V3_CMPL_HI_ERRORS_BUFFER_ERROR_MASK 0xeUL
825  #define RX_PKT_V3_CMPL_HI_ERRORS_BUFFER_ERROR_SFT 1
826  #define RX_PKT_V3_CMPL_HI_ERRORS_BUFFER_ERROR_NO_BUFFER (0x0UL << 1)
827  #define RX_PKT_V3_CMPL_HI_ERRORS_BUFFER_ERROR_DID_NOT_FIT (0x1UL << 1)
828  #define RX_PKT_V3_CMPL_HI_ERRORS_BUFFER_ERROR_NOT_ON_CHIP (0x2UL << 1)
829  #define RX_PKT_V3_CMPL_HI_ERRORS_BUFFER_ERROR_BAD_FORMAT (0x3UL << 1)
830  #define RX_PKT_V3_CMPL_HI_ERRORS_BUFFER_ERROR_FLUSH (0x5UL << 1)
831  #define RX_PKT_V3_CMPL_HI_ERRORS_BUFFER_ERROR_LAST RX_PKT_V3_CMPL_HI_ERRORS_BUFFER_ERROR_FLUSH
832  #define RX_PKT_V3_CMPL_HI_ERRORS_IP_CS_ERROR 0x10UL
833  #define RX_PKT_V3_CMPL_HI_ERRORS_L4_CS_ERROR 0x20UL
834  #define RX_PKT_V3_CMPL_HI_ERRORS_T_IP_CS_ERROR 0x40UL
835  #define RX_PKT_V3_CMPL_HI_ERRORS_T_L4_CS_ERROR 0x80UL
836  #define RX_PKT_V3_CMPL_HI_ERRORS_CRC_ERROR 0x100UL
837  #define RX_PKT_V3_CMPL_HI_ERRORS_T_PKT_ERROR_MASK 0xe00UL
838  #define RX_PKT_V3_CMPL_HI_ERRORS_T_PKT_ERROR_SFT 9
839  #define RX_PKT_V3_CMPL_HI_ERRORS_T_PKT_ERROR_NO_ERROR (0x0UL << 9)
840  #define RX_PKT_V3_CMPL_HI_ERRORS_T_PKT_ERROR_T_L3_BAD_VERSION (0x1UL << 9)
841  #define RX_PKT_V3_CMPL_HI_ERRORS_T_PKT_ERROR_T_L3_BAD_HDR_LEN (0x2UL << 9)
842  #define RX_PKT_V3_CMPL_HI_ERRORS_T_PKT_ERROR_T_IP_TOTAL_ERROR (0x3UL << 9)
843  #define RX_PKT_V3_CMPL_HI_ERRORS_T_PKT_ERROR_T_UDP_TOTAL_ERROR (0x4UL << 9)
844  #define RX_PKT_V3_CMPL_HI_ERRORS_T_PKT_ERROR_T_L3_BAD_TTL (0x5UL << 9)
845  #define RX_PKT_V3_CMPL_HI_ERRORS_T_PKT_ERROR_T_TOTAL_ERROR (0x6UL << 9)
846  #define RX_PKT_V3_CMPL_HI_ERRORS_T_PKT_ERROR_LAST RX_PKT_V3_CMPL_HI_ERRORS_T_PKT_ERROR_T_TOTAL_ERROR
847  #define RX_PKT_V3_CMPL_HI_ERRORS_PKT_ERROR_MASK 0xf000UL
848  #define RX_PKT_V3_CMPL_HI_ERRORS_PKT_ERROR_SFT 12
849  #define RX_PKT_V3_CMPL_HI_ERRORS_PKT_ERROR_NO_ERROR (0x0UL << 12)
850  #define RX_PKT_V3_CMPL_HI_ERRORS_PKT_ERROR_L3_BAD_VERSION (0x1UL << 12)
851  #define RX_PKT_V3_CMPL_HI_ERRORS_PKT_ERROR_L3_BAD_HDR_LEN (0x2UL << 12)
852  #define RX_PKT_V3_CMPL_HI_ERRORS_PKT_ERROR_L3_BAD_TTL (0x3UL << 12)
853  #define RX_PKT_V3_CMPL_HI_ERRORS_PKT_ERROR_IP_TOTAL_ERROR (0x4UL << 12)
854  #define RX_PKT_V3_CMPL_HI_ERRORS_PKT_ERROR_UDP_TOTAL_ERROR (0x5UL << 12)
855  #define RX_PKT_V3_CMPL_HI_ERRORS_PKT_ERROR_L4_BAD_HDR_LEN (0x6UL << 12)
856  #define RX_PKT_V3_CMPL_HI_ERRORS_PKT_ERROR_L4_BAD_HDR_LEN_TOO_SMALL (0x7UL << 12)
857  #define RX_PKT_V3_CMPL_HI_ERRORS_PKT_ERROR_L4_BAD_OPT_LEN (0x8UL << 12)
858  #define RX_PKT_V3_CMPL_HI_ERRORS_PKT_ERROR_LAST RX_PKT_V3_CMPL_HI_ERRORS_PKT_ERROR_L4_BAD_OPT_LEN
860  #define RX_PKT_V3_CMPL_HI_METADATA0_VID_MASK 0xfffUL
861  #define RX_PKT_V3_CMPL_HI_METADATA0_VID_SFT 0
862  #define RX_PKT_V3_CMPL_HI_METADATA0_DE 0x1000UL
863  /* When meta_format=1, this value is the VLAN PRI. */
864  #define RX_PKT_V3_CMPL_HI_METADATA0_PRI_MASK 0xe000UL
865  #define RX_PKT_V3_CMPL_HI_METADATA0_PRI_SFT 13
867 };
868 
871 #define RX_PROD_PKT_BD_TYPE_MASK 0x3fUL
872 #define RX_PROD_PKT_BD_TYPE_SFT 0
873 #define RX_PROD_PKT_BD_TYPE_RX_PROD_PKT 0x4UL
874 #define RX_PROD_PKT_BD_TYPE_LAST RX_PROD_PKT_BD_TYPE_RX_PROD_PKT
875 #define RX_PROD_PKT_BD_FLAGS_MASK 0xffc0UL
876 #define RX_PROD_PKT_BD_FLAGS_SFT 6
877 #define RX_PROD_PKT_BD_FLAGS_SOP_PAD 0x40UL
878 #define RX_PROD_PKT_BD_FLAGS_EOP_PAD 0x80UL
879 #define RX_PROD_PKT_BD_FLAGS_BUFFERS_MASK 0x300UL
880 #define RX_PROD_PKT_BD_FLAGS_BUFFERS_SFT 8
884 };
885 
886 struct rx_info {
887  void *bd_virt;
890  u16 buf_cnt; /* Total Rx buffer descriptors. */
892  u16 cons_id; /* Last processed consumer index. */
893 /* Receive statistics. */
900  u8 res[3];
901 };
902 
903 #define VALID_DRIVER_REG 0x0001
904 #define VALID_STAT_CTX 0x0002
905 #define VALID_RING_CQ 0x0004
906 #define VALID_RING_TX 0x0008
907 #define VALID_RING_RX 0x0010
908 #define VALID_RING_GRP 0x0020
909 #define VALID_VNIC_ID 0x0040
910 #define VALID_RX_IOB 0x0080
911 #define VALID_L2_FILTER 0x0100
912 #define VALID_RING_NQ 0x0200
913 
914 struct bnxt {
915 /* begin "general, frequently-used members" cacheline section */
916 /* If the IRQ handler (which runs lockless) needs to be
917  * quiesced, the following bitmask state is used. The
918  * SYNC flag is set by non-IRQ context code to initiate
919  * the quiescence.
920  *
921  * When the IRQ handler notices that SYNC is set, it
922  * disables interrupts and returns.
923  *
924  * When all outstanding IRQ handlers have returned after
925  * the SYNC flag has been set, the setter can be assured
926  * that interrupts will no longer get run.
927  *
928  * In this way all SMP driver locks are never acquired
929  * in hw IRQ context, only sw IRQ context or lower.
930  */
931  unsigned int irq_sync;
932  struct net_device *dev;
933  struct pci_device *pdev;
940  struct tx_info tx; /* Tx info. */
941  struct rx_info rx; /* Rx info. */
942  struct cmp_info cq; /* completion info. */
943  struct nq_info nq; /* completion info. */
950 /* PCI info. */
954  u8 pf_num; /* absolute PF number */
956  void *bar0;
957  void *bar1;
958  void *bar2;
959 /* Device info. */
961 /* chip num:16-31, rev:12-15, metal:4-11, bond_id:0-3 */
967  u8 mac_addr[ETH_ALEN]; /* HW MAC address */
1015 };
1016 
1017 /* defines required to rsolve checkpatch errors / warnings */
1018 #define test_if if
1019 #define write32 writel
1020 #define write64 writeq
1021 #define pci_read_byte pci_read_config_byte
1022 #define pci_read_word16 pci_read_config_word
1023 #define pci_write_word pci_write_config_word
1024 #define SHORT_CMD_SUPPORTED VER_GET_RESP_DEV_CAPS_CFG_SHORT_CMD_SUPPORTED
1025 #define SHORT_CMD_REQUIRED VER_GET_RESP_DEV_CAPS_CFG_SHORT_CMD_REQUIRED
1026 #define CQ_DOORBELL_KEY_MASK(a) (\
1027  CMPL_DOORBELL_KEY_CMPL | \
1028  CMPL_DOORBELL_IDX_VALID | \
1029  CMPL_DOORBELL_MASK | \
1030  (u32)(a))
1031 #define CQ_DOORBELL_KEY_IDX(a) (\
1032  CMPL_DOORBELL_KEY_CMPL | \
1033  CMPL_DOORBELL_IDX_VALID | \
1034  (u32)(a))
1035 #define TX_BD_FLAGS (\
1036  TX_BD_SHORT_TYPE_TX_BD_SHORT |\
1037  TX_BD_SHORT_FLAGS_COAL_NOW |\
1038  TX_BD_SHORT_FLAGS_PACKET_END |\
1039  (1 << TX_BD_SHORT_FLAGS_BD_CNT_SFT))
1040 #define PORT_PHY_FLAGS (\
1041  BNXT_FLAG_NPAR_MODE | \
1042  BNXT_FLAG_MULTI_HOST)
1043 #define RING_FREE(bp, rid, flag) bnxt_hwrm_ring_free(bp, rid, flag)
1044 #define SET_LINK(p, m, s) ((p & (m >> s)) << s)
1045 #define SET_MBA(p, m, s) ((p & (m >> s)) << s)
1046 #define SPEED_DRV_MASK LINK_SPEED_DRV_MASK
1047 #define SPEED_DRV_SHIFT LINK_SPEED_DRV_SHIFT
1048 #define SPEED_FW_MASK LINK_SPEED_FW_MASK
1049 #define SPEED_FW_SHIFT LINK_SPEED_FW_SHIFT
1050 #define D3_SPEED_FW_MASK D3_LINK_SPEED_FW_MASK
1051 #define D3_SPEED_FW_SHIFT D3_LINK_SPEED_FW_SHIFT
1052 #define MEDIA_AUTO_DETECT_MASK PORT_CFG_LINK_SETTINGS_MEDIA_AUTO_DETECT_MASK
1053 #define MEDIA_AUTO_DETECT_SHIFT PORT_CFG_LINK_SETTINGS_MEDIA_AUTO_DETECT_SHIFT
1054 #define VLAN_MASK FUNC_CFG_PRE_BOOT_MBA_VLAN_MASK
1055 #define VLAN_SHIFT FUNC_CFG_PRE_BOOT_MBA_VLAN_SHIFT
1056 #define VLAN_VALUE_MASK FUNC_CFG_PRE_BOOT_MBA_VLAN_VALUE_MASK
1057 #define VLAN_VALUE_SHIFT FUNC_CFG_PRE_BOOT_MBA_VLAN_VALUE_SHIFT
1058 #define VF_CFG_ENABLE_FLAGS (\
1059  FUNC_VF_CFG_REQ_ENABLES_MTU | \
1060  FUNC_VF_CFG_REQ_ENABLES_GUEST_VLAN | \
1061  FUNC_VF_CFG_REQ_ENABLES_ASYNC_EVENT_CR | \
1062  FUNC_VF_CFG_REQ_ENABLES_DFLT_MAC_ADDR)
1063 
1064 #define CHIP_NUM_57508 0x1750
1065 #define CHIP_NUM_57504 0x1751
1066 #define CHIP_NUM_57502 0x1752
1067 
1068 #define CHIP_NUM_57608 0x1760
u32 drop_vlan
Definition: bnxt.h:898
u16 subsystem_device
Definition: bnxt.h:952
uint16_t u16
Definition: stdint.h:21
u8 res[1]
Definition: bnxt.h:605
u16 stat_ctx_id
Definition: bnxt.h:981
uint32_t __le32
Definition: efx_common.h:30
void * hwrm_addr_req
Definition: bnxt.h:934
u8 epoch
Definition: bnxt.h:603
u32 opaque
Definition: bnxt.h:638
u16 errors_v
Definition: bnxt.h:491
u32 unused_2
Definition: bnxt.h:506
u32 drop_err
Definition: bnxt.h:896
u16 max_vnics
Definition: bnxt.h:994
dma_addr_t req_addr_mapping
Definition: bnxt.h:937
u8 res[2]
Definition: bnxt.h:557
u32 cnt
Definition: bnxt.h:515
u32 key_mask_valid_idx
Definition: bnxt.h:402
u16 max_rsscos_ctxs
Definition: bnxt.h:1005
u16 num_stat_ctxs
Definition: bnxt.h:1013
u8 epoch
Definition: bnxt.h:556
void * bd_virt
Definition: bnxt.h:599
u16 flags_type
Definition: bnxt.h:720
u32 cq_handle_high
Definition: bnxt.h:595
u16 ring_cnt
Definition: bnxt.h:601
u16 cons_id
Definition: bnxt.h:892
u16 min_cp_rings
Definition: bnxt.h:1002
u16 min_tx_rings
Definition: bnxt.h:998
u16 flags_type
Definition: bnxt.h:480
u32 chip_id
Definition: bnxt.h:962
u16 unused_1
Definition: bnxt.h:505
u8 port_idx
Definition: bnxt.h:969
void * hwrm_addr_dma
Definition: bnxt.h:936
unsigned long dma_addr_t
Definition: bnx2.h:20
u16 hwrm_spec_code
Definition: bnxt.h:964
u32 cnt_req
Definition: bnxt.h:516
u16 ring_cnt
Definition: bnxt.h:554
u8 completion_bit
Definition: bnxt.h:602
u16 cmd_reg
Definition: bnxt.h:953
u16 rx_ring_id
Definition: bnxt.h:975
u16 min_hw_ring_grps
Definition: bnxt.h:996
struct tx_info tx
Definition: bnxt.h:940
unsigned int irq_sync
Definition: bnxt.h:931
u16 min_l2_ctxs
Definition: bnxt.h:1006
u16 prod_id
Definition: bnxt.h:512
u32 flag_hwrm
Definition: bnxt.h:948
u32 reorder
Definition: bnxt.h:714
u16 rss_hash_type_agg_bufs_v1
Definition: bnxt.h:757
u32 v
Definition: bnxt.h:584
u16 len
Definition: bnxt.h:474
u16 min_rsscos_ctxs
Definition: bnxt.h:1004
void * bar1
Definition: bnxt.h:957
u16 tx_ring_id
Definition: bnxt.h:974
dma_addr_t addr
Definition: bnxt.h:31
struct cmp_info cq
Definition: bnxt.h:942
u16 cons_id
Definition: bnxt.h:513
u8 rsvd
Definition: bnxt.h:990
dma_addr_t dma_addr_mapping
Definition: bnxt.h:939
u16 max_hw_ring_grps
Definition: bnxt.h:997
u32 info4
Definition: bnxt.h:548
void * bd_virt
Definition: bnxt.h:510
void * bd_virt
Definition: bnxt.h:887
u16 max_cp_rings
Definition: bnxt.h:1003
u32 hwrm_cmd_timeout
Definition: bnxt.h:963
u32 drop_lb
Definition: bnxt.h:897
u16 type
Definition: bnxt.h:563
u16 max_msix
Definition: bnxt.h:995
u32 opaque
Definition: bnxt.h:475
u8 res[3]
Definition: bnxt.h:518
u16 reserved16
Definition: bnxt.h:578
u16 num_rx_rings
Definition: bnxt.h:1012
struct rx_info rx
Definition: bnxt.h:941
u32 cq_handle_low
Definition: bnxt.h:583
Definition: bnxt.h:414
u32 key_idx
Definition: bnxt.h:382
u16 ring_cnt
Definition: bnxt.h:891
u16 last_resp_code
Definition: bnxt.h:946
u32 info2
Definition: bnxt.h:543
u32 rss_hash
Definition: bnxt.h:794
u32 info3_v
Definition: bnxt.h:544
u8 vf
Definition: bnxt.h:955
uint64_t u64
Definition: stdint.h:25
u16 ring_grp_id
Definition: bnxt.h:972
u32 rss_hash
Definition: bnxt.h:648
u16 seq_id
Definition: bnxt.h:947
u8 pf_num
Definition: bnxt.h:954
u8 media_detect
Definition: bnxt.h:989
struct io_buffer * iob[MAX_TX_DESC_CNT]
Definition: bnxt.h:511
u8 epoch
Definition: bnxt.h:517
#define NUM_RX_BUFFERS
Definition: bnxt.h:153
u16 auto_link_speeds2_mask
Definition: bnxt.h:987
u32 flags2
Definition: bnxt.h:652
u16 subsystem_vendor
Definition: bnxt.h:951
void * bd_virt
Definition: bnxt.h:552
u16 max_tx_rings
Definition: bnxt.h:999
u16 min_stat_ctxs
Definition: bnxt.h:1008
u8 rss_hash_type
Definition: bnxt.h:645
u16 hwrm_max_req_len
Definition: bnxt.h:965
u16 vf_res_strategy
Definition: bnxt.h:992
u32 opaque
Definition: bnxt.h:756
u16 unused_0
Definition: bnxt.h:489
u16 min_rx_rings
Definition: bnxt.h:1000
u64 as_u64
Definition: bnxt.h:32
A PCI device.
Definition: pci.h:206
u8 agg_bufs_v1
Definition: bnxt.h:639
u16 min_vnics
Definition: bnxt.h:993
A network device.
Definition: netdevice.h:352
void * bar2
Definition: bnxt.h:958
u8 epoch
Definition: bnxt.h:899
struct pci_device * pdev
Definition: bnxt.h:933
u16 type
Definition: bnxt.h:522
u16 max_vfs
Definition: bnxt.h:991
Definition: bnxt.h:509
#define MAX_TX_DESC_CNT
Definition: bnxt.h:155
Definition: bnxt.h:598
u16 max_rx_rings
Definition: bnxt.h:1001
u32 opaque
Definition: bnxt.h:490
#define ETH_ALEN
Definition: if_ether.h:8
u16 cfa_code
Definition: bnxt.h:713
u8 unused1
Definition: bnxt.h:647
u16 current_link_speed
Definition: bnxt.h:976
u32 link_set
Definition: bnxt.h:988
void * hwrm_addr_resp
Definition: bnxt.h:935
u32 cnt
Definition: bnxt.h:894
u16 link_status
Definition: bnxt.h:977
u16 max_stat_ctxs
Definition: bnxt.h:1009
u16 flags_type
Definition: bnxt.h:455
u8 completion_bit
Definition: bnxt.h:555
u64 l2_filter_id
Definition: bnxt.h:979
u16 ring_cnt
Definition: bnxt.h:514
u8 queue_id
Definition: bnxt.h:945
struct net_device * dev
Definition: bnxt.h:932
u16 vlan_tx
Definition: bnxt.h:983
u32 flags
Definition: bnxt.h:949
u16 cons_id
Definition: bnxt.h:553
Definition: bnxt.h:479
u8 mac_addr[ETH_ALEN]
Definition: bnxt.h:967
u8 ordinal_value
Definition: bnxt.h:970
u32 opaque
Definition: bnxt.h:882
u32 mba_cfg2
Definition: bnxt.h:984
u16 info1
Definition: bnxt.h:542
u16 vlan_id
Definition: bnxt.h:982
u16 num_cmpl_rings
Definition: bnxt.h:1010
u16 nq_ring_id
Definition: bnxt.h:944
__le32 type_path_xid
Definition: bnxt.h:422
u16 num_hw_ring_grps
Definition: bnxt.h:1014
u16 metadata1_payload_offset
Definition: bnxt.h:779
u16 iob_cnt
Definition: bnxt.h:889
u16 buf_cnt
Definition: bnxt.h:890
u16 errors_v2
Definition: bnxt.h:672
__le32 index
Definition: bnxt.h:415
u16 hwrm_max_ext_req_len
Definition: bnxt.h:966
u16 wait_link_timeout
Definition: bnxt.h:978
struct io_buffer * iob[NUM_RX_BUFFERS]
Definition: bnxt.h:888
Definition: bnxt.h:551
u32 medium
Definition: bnxt.h:985
u16 support_speeds
Definition: bnxt.h:986
u16 chip_num
Definition: bnxt.h:960
void * bar0
Definition: bnxt.h:956
u8 payload_offset
Definition: bnxt.h:646
u32 metadata
Definition: bnxt.h:664
Definition: bnxt.h:562
u8 toggle
Definition: bnxt.h:604
u16 mtu
Definition: bnxt.h:971
u16 len
Definition: bnxt.h:637
u16 cq_ring_id
Definition: bnxt.h:973
u16 flags_type
Definition: bnxt.h:609
u16 cons_id
Definition: bnxt.h:600
u32 good
Definition: bnxt.h:895
Definition: bnxt.h:886
struct nq_info nq
Definition: bnxt.h:943
u8 res[3]
Definition: bnxt.h:900
u16 fid
Definition: bnxt.h:968
uint8_t u8
Definition: stdint.h:19
uint32_t u32
Definition: stdint.h:23
u16 num_tx_rings
Definition: bnxt.h:1011
union dma_addr64_t dma
Definition: bnxt.h:883
dma_addr_t resp_addr_mapping
Definition: bnxt.h:938
Definition: bnxt.h:914
u16 flags_type
Definition: bnxt.h:870
u32 key_idx
Definition: bnxt.h:392
union dma_addr64_t dma
Definition: bnxt.h:476
u16 max_l2_ctxs
Definition: bnxt.h:1007
A persistent I/O buffer.
Definition: iobuf.h:33
u16 vnic_id
Definition: bnxt.h:980