iPXE
pci.h
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1 #ifndef _IPXE_PCI_H
2 #define _IPXE_PCI_H
3 
4 /** @file
5  *
6  * PCI bus
7  *
8  */
9 
10 FILE_LICENCE ( GPL2_OR_LATER_OR_UBDL );
11 
12 #include <stdint.h>
13 #include <ipxe/device.h>
14 #include <ipxe/tables.h>
15 #include <ipxe/dma.h>
16 #include <ipxe/pci_io.h>
17 
18 /** PCI vendor ID */
19 #define PCI_VENDOR_ID 0x00
20 
21 /** PCI device ID */
22 #define PCI_DEVICE_ID 0x02
23 
24 /** PCI command */
25 #define PCI_COMMAND 0x04
26 #define PCI_COMMAND_IO 0x0001 /**< I/O space */
27 #define PCI_COMMAND_MEM 0x0002 /**< Memory space */
28 #define PCI_COMMAND_MASTER 0x0004 /**< Bus master */
29 #define PCI_COMMAND_INVALIDATE 0x0010 /**< Mem. write & invalidate */
30 #define PCI_COMMAND_PARITY 0x0040 /**< Parity error response */
31 #define PCI_COMMAND_SERR 0x0100 /**< SERR# enable */
32 #define PCI_COMMAND_INTX_DISABLE 0x0400 /**< Interrupt disable */
33 
34 /** PCI status */
35 #define PCI_STATUS 0x06
36 #define PCI_STATUS_CAP_LIST 0x0010 /**< Capabilities list */
37 #define PCI_STATUS_PARITY 0x0100 /**< Master data parity error */
38 #define PCI_STATUS_REC_TARGET_ABORT 0x1000 /**< Received target abort */
39 #define PCI_STATUS_REC_MASTER_ABORT 0x2000 /**< Received master abort */
40 #define PCI_STATUS_SIG_SYSTEM_ERROR 0x4000 /**< Signalled system error */
41 #define PCI_STATUS_DETECTED_PARITY 0x8000 /**< Detected parity error */
42 
43 /** PCI revision */
44 #define PCI_REVISION 0x08
45 
46 /** PCI cache line size */
47 #define PCI_CACHE_LINE_SIZE 0x0c
48 
49 /** PCI latency timer */
50 #define PCI_LATENCY_TIMER 0x0d
51 
52 /** PCI header type */
53 #define PCI_HEADER_TYPE 0x0e
54 #define PCI_HEADER_TYPE_NORMAL 0x00 /**< Normal header */
55 #define PCI_HEADER_TYPE_BRIDGE 0x01 /**< PCI-to-PCI bridge header */
56 #define PCI_HEADER_TYPE_CARDBUS 0x02 /**< CardBus header */
57 #define PCI_HEADER_TYPE_MASK 0x7f /**< Header type mask */
58 #define PCI_HEADER_TYPE_MULTI 0x80 /**< Multi-function device */
59 
60 /** PCI base address registers */
61 #define PCI_BASE_ADDRESS(n) ( 0x10 + ( 4 * (n) ) )
62 #define PCI_BASE_ADDRESS_0 PCI_BASE_ADDRESS ( 0 )
63 #define PCI_BASE_ADDRESS_1 PCI_BASE_ADDRESS ( 1 )
64 #define PCI_BASE_ADDRESS_2 PCI_BASE_ADDRESS ( 2 )
65 #define PCI_BASE_ADDRESS_3 PCI_BASE_ADDRESS ( 3 )
66 #define PCI_BASE_ADDRESS_4 PCI_BASE_ADDRESS ( 4 )
67 #define PCI_BASE_ADDRESS_5 PCI_BASE_ADDRESS ( 5 )
68 #define PCI_BASE_ADDRESS_SPACE_IO 0x00000001UL /**< I/O BAR */
69 #define PCI_BASE_ADDRESS_IO_MASK 0x00000003UL /**< I/O BAR mask */
70 #define PCI_BASE_ADDRESS_MEM_TYPE_64 0x00000004UL /**< 64-bit memory */
71 #define PCI_BASE_ADDRESS_MEM_TYPE_MASK 0x00000006UL /**< Memory type mask */
72 #define PCI_BASE_ADDRESS_MEM_MASK 0x0000000fUL /**< Memory BAR mask */
73 
74 /** PCI subsystem vendor ID */
75 #define PCI_SUBSYSTEM_VENDOR_ID 0x2c
76 
77 /** PCI subsystem ID */
78 #define PCI_SUBSYSTEM_ID 0x2e
79 
80 /** PCI expansion ROM base address */
81 #define PCI_ROM_ADDRESS 0x30
82 
83 /** PCI capabilities pointer */
84 #define PCI_CAPABILITY_LIST 0x34
85 
86 /** CardBus capabilities pointer */
87 #define PCI_CB_CAPABILITY_LIST 0x14
88 
89 /** PCI interrupt line */
90 #define PCI_INTERRUPT_LINE 0x3c
91 
92 /** Capability ID */
93 #define PCI_CAP_ID 0x00
94 #define PCI_CAP_ID_PM 0x01 /**< Power management */
95 #define PCI_CAP_ID_VPD 0x03 /**< Vital product data */
96 #define PCI_CAP_ID_VNDR 0x09 /**< Vendor-specific */
97 #define PCI_CAP_ID_EXP 0x10 /**< PCI Express */
98 #define PCI_CAP_ID_MSIX 0x11 /**< MSI-X */
99 #define PCI_CAP_ID_EA 0x14 /**< Enhanced Allocation */
100 
101 /** Next capability */
102 #define PCI_CAP_NEXT 0x01
103 
104 /** Power management control and status */
105 #define PCI_PM_CTRL 0x04
106 #define PCI_PM_CTRL_STATE_MASK 0x0003 /**< Current power state */
107 #define PCI_PM_CTRL_PME_ENABLE 0x0100 /**< PME pin enable */
108 #define PCI_PM_CTRL_PME_STATUS 0x8000 /**< PME pin status */
109 
110 /** PCI Express */
111 #define PCI_EXP_DEVCTL 0x08
112 #define PCI_EXP_DEVCTL_FLR 0x8000 /**< Function level reset */
113 
114 /** MSI-X interrupts */
115 #define PCI_MSIX_CTRL 0x02
116 #define PCI_MSIX_CTRL_ENABLE 0x8000 /**< Enable MSI-X */
117 #define PCI_MSIX_CTRL_MASK 0x4000 /**< Mask all interrupts */
118 #define PCI_MSIX_CTRL_SIZE(x) ( (x) & 0x07ff ) /**< Table size */
119 #define PCI_MSIX_DESC_TABLE 0x04
120 #define PCI_MSIX_DESC_PBA 0x08
121 #define PCI_MSIX_DESC_BIR(x) ( (x) & 0x00000007 ) /**< BAR index */
122 #define PCI_MSIX_DESC_OFFSET(x) ( (x) & 0xfffffff8 ) /**< BAR offset */
123 
124 /** Uncorrectable error status */
125 #define PCI_ERR_UNCOR_STATUS 0x04
126 
127 /** Network controller */
128 #define PCI_CLASS_NETWORK 0x02
129 
130 /** Bridge device */
131 #define PCI_CLASS_BRIDGE 0x06
132 #define PCI_CLASS_BRIDGE_PCI 0x04 /**< PCI-to-PCI bridge */
133 
134 /** Serial bus controller */
135 #define PCI_CLASS_SERIAL 0x0c
136 #define PCI_CLASS_SERIAL_USB 0x03 /**< USB controller */
137 #define PCI_CLASS_SERIAL_USB_UHCI 0x00 /**< UHCI USB controller */
138 #define PCI_CLASS_SERIAL_USB_OHCI 0x10 /**< OHCI USB controller */
139 #define PCI_CLASS_SERIAL_USB_EHCI 0x20 /**< ECHI USB controller */
140 #define PCI_CLASS_SERIAL_USB_XHCI 0x30 /**< xHCI USB controller */
141 
142 /** Primary bus number */
143 #define PCI_PRIMARY 0x18
144 
145 /** Secondary bus number */
146 #define PCI_SECONDARY 0x19
147 
148 /** Subordinate bus number */
149 #define PCI_SUBORDINATE 0x1a
150 
151 /** Memory base and limit */
152 #define PCI_MEM_BASE 0x20
153 #define PCI_MEM_LIMIT 0x22
154 #define PCI_MEM_MASK 0x000f
155 
156 /** Construct PCI class
157  *
158  * @v base Base class (or PCI_ANY_ID)
159  * @v sub Subclass (or PCI_ANY_ID)
160  * @v progif Programming interface (or PCI_ANY_ID)
161  */
162 #define PCI_CLASS( base, sub, progif ) \
163  ( ( ( (base) & 0xff ) << 16 ) | ( ( (sub) & 0xff ) << 8 ) | \
164  ( ( (progif) & 0xff) << 0 ) )
165 
166 /** PCI Express function level reset delay (in ms) */
167 #define PCI_EXP_FLR_DELAY_MS 100
168 
169 /** A PCI device ID list entry */
171  /** Name */
172  const char *name;
173  /** PCI vendor ID */
175  /** PCI device ID */
177  /** Arbitrary driver data */
178  unsigned long driver_data;
179 };
180 
181 /** Match-anything ID */
182 #define PCI_ANY_ID 0xffff
183 
184 /** A PCI class ID */
185 struct pci_class_id {
186  /** Class */
187  uint32_t class;
188  /** Class mask */
190 };
191 
192 /** Construct PCI class ID
193  *
194  * @v base Base class (or PCI_ANY_ID)
195  * @v sub Subclass (or PCI_ANY_ID)
196  * @v progif Programming interface (or PCI_ANY_ID)
197  */
198 #define PCI_CLASS_ID( base, sub, progif ) { \
199  .class = PCI_CLASS ( base, sub, progif ), \
200  .mask = ( ( ( ( (base) == PCI_ANY_ID ) ? 0x00 : 0xff ) << 16 ) | \
201  ( ( ( (sub) == PCI_ANY_ID ) ? 0x00 : 0xff ) << 8 ) | \
202  ( ( ( (progif) == PCI_ANY_ID ) ? 0x00 : 0xff ) << 0 ) ), \
203  }
204 
205 /** A PCI device */
206 struct pci_device {
207  /** Generic device */
208  struct device dev;
209  /** DMA device */
210  struct dma_device dma;
211  /** Memory base
212  *
213  * This is the physical address of the first valid memory BAR.
214  */
215  unsigned long membase;
216  /**
217  * I/O address
218  *
219  * This is the physical address of the first valid I/O BAR.
220  */
221  unsigned long ioaddr;
222  /** Vendor ID */
224  /** Device ID */
226  /** Device class */
227  uint32_t class;
228  /** Interrupt number */
230  /** Segment, bus, device, and function (bus:dev.fn) number */
232  /** Driver for this device */
234  /** Driver-private data
235  *
236  * Use pci_set_drvdata() and pci_get_drvdata() to access this
237  * field.
238  */
239  void *priv;
240  /** Driver device ID */
241  struct pci_device_id *id;
242 };
243 
244 /** A PCI driver */
245 struct pci_driver {
246  /** PCI ID table */
248  /** Number of entries in PCI ID table */
249  unsigned int id_count;
250  /** PCI class ID */
252  /**
253  * Probe device
254  *
255  * @v pci PCI device
256  * @ret rc Return status code
257  */
258  int ( * probe ) ( struct pci_device *pci );
259  /**
260  * Remove device
261  *
262  * @v pci PCI device
263  */
264  void ( * remove ) ( struct pci_device *pci );
265 };
266 
267 /** PCI driver table */
268 #define PCI_DRIVERS __table ( struct pci_driver, "pci_drivers" )
269 
270 /** Declare a PCI driver */
271 #define __pci_driver __table_entry ( PCI_DRIVERS, 01 )
272 
273 /** Declare a fallback PCI driver */
274 #define __pci_driver_fallback __table_entry ( PCI_DRIVERS, 02 )
275 
276 #define PCI_SEG( busdevfn ) ( ( (busdevfn) >> 16 ) & 0xffff )
277 #define PCI_BUS( busdevfn ) ( ( (busdevfn) >> 8 ) & 0xff )
278 #define PCI_SLOT( busdevfn ) ( ( (busdevfn) >> 3 ) & 0x1f )
279 #define PCI_FUNC( busdevfn ) ( ( (busdevfn) >> 0 ) & 0x07 )
280 #define PCI_FIRST_FUNC( busdevfn ) ( (busdevfn) & ~0x07 )
281 #define PCI_LAST_FUNC( busdevfn ) ( (busdevfn) | 0x07 )
282 
283 #define PCI_BASE_CLASS( class ) ( (class) >> 16 )
284 #define PCI_SUB_CLASS( class ) ( ( (class) >> 8 ) & 0xff )
285 #define PCI_PROG_INTF( class ) ( (class) & 0xff )
286 
287 /*
288  * PCI_ROM is used to build up entries in a struct pci_id array. It
289  * is also parsed by parserom.pl to generate Makefile rules and files
290  * for rom-o-matic.
291  *
292  * PCI_ID can be used to generate entries without creating a
293  * corresponding ROM in the build process.
294  */
295 #define PCI_ID( _vendor, _device, _name, _description, _data ) { \
296  .vendor = _vendor, \
297  .device = _device, \
298  .name = _name, \
299  .driver_data = _data \
300 }
301 #define PCI_ROM( _vendor, _device, _name, _description, _data ) \
302  PCI_ID( _vendor, _device, _name, _description, _data )
303 
304 /** PCI device debug message format */
305 #define PCI_FMT "%04x:%02x:%02x.%x"
306 
307 /** PCI device debug message arguments */
308 #define PCI_ARGS( pci ) \
309  PCI_SEG ( (pci)->busdevfn ), PCI_BUS ( (pci)->busdevfn ), \
310  PCI_SLOT ( (pci)->busdevfn ), PCI_FUNC ( (pci)->busdevfn )
311 
312 extern void adjust_pci_device ( struct pci_device *pci );
313 extern unsigned long pci_bar_start ( struct pci_device *pci,
314  unsigned int reg );
315 extern int pci_read_config ( struct pci_device *pci );
316 extern int pci_find_next ( struct pci_device *pci, uint32_t *busdevfn );
317 extern int pci_find_driver ( struct pci_device *pci );
318 extern int pci_probe ( struct pci_device *pci );
319 extern void pci_remove ( struct pci_device *pci );
320 extern int pci_find_capability ( struct pci_device *pci, int capability );
321 extern int pci_find_next_capability ( struct pci_device *pci,
322  int pos, int capability );
323 extern unsigned long pci_bar_size ( struct pci_device *pci, unsigned int reg );
324 extern void pci_reset ( struct pci_device *pci, unsigned int exp );
325 
326 /**
327  * Initialise PCI device
328  *
329  * @v pci PCI device
330  * @v busdevfn PCI bus:dev.fn address
331  */
332 static inline void pci_init ( struct pci_device *pci, unsigned int busdevfn ) {
333  pci->busdevfn = busdevfn;
334 }
335 
336 /**
337  * Set PCI driver
338  *
339  * @v pci PCI device
340  * @v driver PCI driver
341  * @v id PCI device ID
342  */
343 static inline void pci_set_driver ( struct pci_device *pci,
344  struct pci_driver *driver,
345  struct pci_device_id *id ) {
346  pci->driver = driver;
347  pci->id = id;
348  pci->dev.driver_name = id->name;
349 }
350 
351 /**
352  * Set PCI driver-private data
353  *
354  * @v pci PCI device
355  * @v priv Private data
356  */
357 static inline void pci_set_drvdata ( struct pci_device *pci, void *priv ) {
358  pci->priv = priv;
359 }
360 
361 /**
362  * Get PCI driver-private data
363  *
364  * @v pci PCI device
365  * @ret priv Private data
366  */
367 static inline void * pci_get_drvdata ( struct pci_device *pci ) {
368  return pci->priv;
369 }
370 
371 #endif /* _IPXE_PCI_H */
unsigned long membase
Memory base.
Definition: pci.h:215
uint8_t irq
Interrupt number.
Definition: pci.h:229
unsigned short uint16_t
Definition: stdint.h:11
DMA mappings.
struct pci_class_id class
PCI class ID.
Definition: pci.h:251
struct dma_device dma
DMA device.
Definition: pci.h:210
struct pci_driver * driver
Driver for this device.
Definition: pci.h:233
A PCI driver.
Definition: pci.h:245
static unsigned int unsigned int reg
Definition: myson.h:162
void(* remove)(struct pci_device *pci)
Remove device.
Definition: pci.h:264
int pci_probe(struct pci_device *pci)
Probe a PCI device.
Definition: pci.c:323
unsigned long ioaddr
I/O address.
Definition: pci.h:221
unsigned int id_count
Number of entries in PCI ID table.
Definition: pci.h:249
unsigned long driver_data
Arbitrary driver data.
Definition: pci.h:178
struct pci_device_id * ids
PCI ID table.
Definition: pci.h:247
static void pci_set_driver(struct pci_device *pci, struct pci_driver *driver, struct pci_device_id *id)
Set PCI driver.
Definition: pci.h:343
int pci_find_driver(struct pci_device *pci)
Find driver for PCI device.
Definition: pci.c:291
void pci_remove(struct pci_device *pci)
Remove a PCI device.
Definition: pci.c:345
uint32_t mask
Class mask.
Definition: pci.h:189
struct device dev
Generic device.
Definition: pci.h:208
int pci_find_next_capability(struct pci_device *pci, int pos, int capability)
Look for another PCI capability.
Definition: pciextra.c:75
static void pci_set_drvdata(struct pci_device *pci, void *priv)
Set PCI driver-private data.
Definition: pci.h:357
uint16_t busdevfn
PCI bus:dev.fn address.
Definition: ena.h:28
A hardware device.
Definition: device.h:73
void * priv
Driver-private data.
Definition: pci.h:239
uint16_t device
Device ID.
Definition: pci.h:225
u16 capability
Capability flags.
Definition: ieee80211.h:1036
const char * driver_name
Driver name.
Definition: device.h:77
uint8_t id
Request identifier.
Definition: ena.h:12
A PCI device.
Definition: pci.h:206
int pci_find_next(struct pci_device *pci, uint32_t *busdevfn)
Find next device on PCI bus.
Definition: pci.c:235
unsigned char uint8_t
Definition: stdint.h:10
A PCI class ID.
Definition: pci.h:185
A PCI device ID list entry.
Definition: pci.h:170
unsigned int uint32_t
Definition: stdint.h:12
const char * name
Name.
Definition: pci.h:172
uint16_t vendor
Vendor ID.
Definition: pci.h:223
void pci_reset(struct pci_device *pci, unsigned int exp)
Perform PCI Express function-level reset (FLR)
Definition: pciextra.c:124
static void * pci_get_drvdata(struct pci_device *pci)
Get PCI driver-private data.
Definition: pci.h:367
uint16_t vendor
PCI vendor ID.
Definition: pci.h:174
uint32_t busdevfn
Segment, bus, device, and function (bus:dev.fn) number.
Definition: pci.h:231
uint16_t device
PCI device ID.
Definition: pci.h:176
PCI I/O API.
static struct tlan_private * priv
Definition: tlan.c:224
int(* probe)(struct pci_device *pci)
Probe device.
Definition: pci.h:258
struct pci_device_id * id
Driver device ID.
Definition: pci.h:241
Linker tables.
Device model.
int pci_read_config(struct pci_device *pci)
Read PCI device configuration.
Definition: pci.c:182
static void pci_init(struct pci_device *pci, unsigned int busdevfn)
Initialise PCI device.
Definition: pci.h:332
FILE_LICENCE(GPL2_OR_LATER_OR_UBDL)
unsigned long pci_bar_start(struct pci_device *pci, unsigned int reg)
Find the start of a PCI BAR.
Definition: pci.c:96
int pci_find_capability(struct pci_device *pci, int capability)
Look for a PCI capability.
Definition: pciextra.c:38
unsigned long pci_bar_size(struct pci_device *pci, unsigned int reg)
Find the size of a PCI BAR.
Definition: pciextra.c:92
void adjust_pci_device(struct pci_device *pci)
Enable PCI device.
Definition: pci.c:154
A DMA-capable device.
Definition: dma.h:47