iPXE
pci.h
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1 #ifndef _IPXE_PCI_H
2 #define _IPXE_PCI_H
3 
4 /** @file
5  *
6  * PCI bus
7  *
8  */
9 
10 FILE_LICENCE ( GPL2_OR_LATER_OR_UBDL );
11 
12 #include <stdint.h>
13 #include <ipxe/device.h>
14 #include <ipxe/tables.h>
15 #include <ipxe/dma.h>
16 #include <ipxe/pci_io.h>
17 
18 /** PCI vendor ID */
19 #define PCI_VENDOR_ID 0x00
20 
21 /** PCI device ID */
22 #define PCI_DEVICE_ID 0x02
23 
24 /** PCI command */
25 #define PCI_COMMAND 0x04
26 #define PCI_COMMAND_IO 0x0001 /**< I/O space */
27 #define PCI_COMMAND_MEM 0x0002 /**< Memory space */
28 #define PCI_COMMAND_MASTER 0x0004 /**< Bus master */
29 #define PCI_COMMAND_INVALIDATE 0x0010 /**< Mem. write & invalidate */
30 #define PCI_COMMAND_PARITY 0x0040 /**< Parity error response */
31 #define PCI_COMMAND_SERR 0x0100 /**< SERR# enable */
32 #define PCI_COMMAND_INTX_DISABLE 0x0400 /**< Interrupt disable */
33 
34 /** PCI status */
35 #define PCI_STATUS 0x06
36 #define PCI_STATUS_CAP_LIST 0x0010 /**< Capabilities list */
37 #define PCI_STATUS_PARITY 0x0100 /**< Master data parity error */
38 #define PCI_STATUS_REC_TARGET_ABORT 0x1000 /**< Received target abort */
39 #define PCI_STATUS_REC_MASTER_ABORT 0x2000 /**< Received master abort */
40 #define PCI_STATUS_SIG_SYSTEM_ERROR 0x4000 /**< Signalled system error */
41 #define PCI_STATUS_DETECTED_PARITY 0x8000 /**< Detected parity error */
42 
43 /** PCI revision */
44 #define PCI_REVISION 0x08
45 
46 /** PCI cache line size */
47 #define PCI_CACHE_LINE_SIZE 0x0c
48 
49 /** PCI latency timer */
50 #define PCI_LATENCY_TIMER 0x0d
51 
52 /** PCI header type */
53 #define PCI_HEADER_TYPE 0x0e
54 #define PCI_HEADER_TYPE_NORMAL 0x00 /**< Normal header */
55 #define PCI_HEADER_TYPE_BRIDGE 0x01 /**< PCI-to-PCI bridge header */
56 #define PCI_HEADER_TYPE_CARDBUS 0x02 /**< CardBus header */
57 #define PCI_HEADER_TYPE_MASK 0x7f /**< Header type mask */
58 #define PCI_HEADER_TYPE_MULTI 0x80 /**< Multi-function device */
59 
60 /** PCI base address registers */
61 #define PCI_BASE_ADDRESS(n) ( 0x10 + ( 4 * (n) ) )
62 #define PCI_BASE_ADDRESS_0 PCI_BASE_ADDRESS ( 0 )
63 #define PCI_BASE_ADDRESS_1 PCI_BASE_ADDRESS ( 1 )
64 #define PCI_BASE_ADDRESS_2 PCI_BASE_ADDRESS ( 2 )
65 #define PCI_BASE_ADDRESS_3 PCI_BASE_ADDRESS ( 3 )
66 #define PCI_BASE_ADDRESS_4 PCI_BASE_ADDRESS ( 4 )
67 #define PCI_BASE_ADDRESS_5 PCI_BASE_ADDRESS ( 5 )
68 #define PCI_BASE_ADDRESS_SPACE_IO 0x00000001UL /**< I/O BAR */
69 #define PCI_BASE_ADDRESS_IO_MASK 0x00000003UL /**< I/O BAR mask */
70 #define PCI_BASE_ADDRESS_MEM_TYPE_64 0x00000004UL /**< 64-bit memory */
71 #define PCI_BASE_ADDRESS_MEM_TYPE_MASK 0x00000006UL /**< Memory type mask */
72 #define PCI_BASE_ADDRESS_MEM_MASK 0x0000000fUL /**< Memory BAR mask */
73 
74 /** PCI subsystem vendor ID */
75 #define PCI_SUBSYSTEM_VENDOR_ID 0x2c
76 
77 /** PCI subsystem ID */
78 #define PCI_SUBSYSTEM_ID 0x2e
79 
80 /** PCI expansion ROM base address */
81 #define PCI_ROM_ADDRESS 0x30
82 
83 /** PCI capabilities pointer */
84 #define PCI_CAPABILITY_LIST 0x34
85 
86 /** CardBus capabilities pointer */
87 #define PCI_CB_CAPABILITY_LIST 0x14
88 
89 /** PCI interrupt line */
90 #define PCI_INTERRUPT_LINE 0x3c
91 
92 /** Capability ID */
93 #define PCI_CAP_ID 0x00
94 #define PCI_CAP_ID_PM 0x01 /**< Power management */
95 #define PCI_CAP_ID_VPD 0x03 /**< Vital product data */
96 #define PCI_CAP_ID_VNDR 0x09 /**< Vendor-specific */
97 #define PCI_CAP_ID_EXP 0x10 /**< PCI Express */
98 #define PCI_CAP_ID_MSIX 0x11 /**< MSI-X */
99 #define PCI_CAP_ID_EA 0x14 /**< Enhanced Allocation */
100 
101 /** Next capability */
102 #define PCI_CAP_NEXT 0x01
103 
104 /** Power management control and status */
105 #define PCI_PM_CTRL 0x04
106 #define PCI_PM_CTRL_STATE_MASK 0x0003 /**< Current power state */
107 #define PCI_PM_CTRL_PME_ENABLE 0x0100 /**< PME pin enable */
108 #define PCI_PM_CTRL_PME_STATUS 0x8000 /**< PME pin status */
109 
110 /** PCI Express */
111 #define PCI_EXP_DEVCTL 0x08
112 #define PCI_EXP_DEVCTL_FLR 0x8000 /**< Function level reset */
113 
114 /** MSI-X interrupts */
115 #define PCI_MSIX_CTRL 0x02
116 #define PCI_MSIX_CTRL_ENABLE 0x8000 /**< Enable MSI-X */
117 #define PCI_MSIX_CTRL_MASK 0x4000 /**< Mask all interrupts */
118 #define PCI_MSIX_CTRL_SIZE(x) ( (x) & 0x07ff ) /**< Table size */
119 #define PCI_MSIX_DESC_TABLE 0x04
120 #define PCI_MSIX_DESC_PBA 0x08
121 #define PCI_MSIX_DESC_BIR(x) ( (x) & 0x00000007 ) /**< BAR index */
122 #define PCI_MSIX_DESC_OFFSET(x) ( (x) & 0xfffffff8 ) /**< BAR offset */
123 
124 /** Uncorrectable error status */
125 #define PCI_ERR_UNCOR_STATUS 0x04
126 
127 /** Network controller */
128 #define PCI_CLASS_NETWORK 0x02
129 
130 /** Serial bus controller */
131 #define PCI_CLASS_SERIAL 0x0c
132 #define PCI_CLASS_SERIAL_USB 0x03 /**< USB controller */
133 #define PCI_CLASS_SERIAL_USB_UHCI 0x00 /**< UHCI USB controller */
134 #define PCI_CLASS_SERIAL_USB_OHCI 0x10 /**< OHCI USB controller */
135 #define PCI_CLASS_SERIAL_USB_EHCI 0x20 /**< ECHI USB controller */
136 #define PCI_CLASS_SERIAL_USB_XHCI 0x30 /**< xHCI USB controller */
137 
138 /** Subordinate bus number */
139 #define PCI_SUBORDINATE 0x1a
140 
141 /** Construct PCI class
142  *
143  * @v base Base class (or PCI_ANY_ID)
144  * @v sub Subclass (or PCI_ANY_ID)
145  * @v progif Programming interface (or PCI_ANY_ID)
146  */
147 #define PCI_CLASS( base, sub, progif ) \
148  ( ( ( (base) & 0xff ) << 16 ) | ( ( (sub) & 0xff ) << 8 ) | \
149  ( ( (progif) & 0xff) << 0 ) )
150 
151 /** PCI Express function level reset delay (in ms) */
152 #define PCI_EXP_FLR_DELAY_MS 100
153 
154 /** A PCI device ID list entry */
156  /** Name */
157  const char *name;
158  /** PCI vendor ID */
160  /** PCI device ID */
162  /** Arbitrary driver data */
163  unsigned long driver_data;
164 };
165 
166 /** Match-anything ID */
167 #define PCI_ANY_ID 0xffff
168 
169 /** A PCI class ID */
170 struct pci_class_id {
171  /** Class */
172  uint32_t class;
173  /** Class mask */
175 };
176 
177 /** Construct PCI class ID
178  *
179  * @v base Base class (or PCI_ANY_ID)
180  * @v sub Subclass (or PCI_ANY_ID)
181  * @v progif Programming interface (or PCI_ANY_ID)
182  */
183 #define PCI_CLASS_ID( base, sub, progif ) { \
184  .class = PCI_CLASS ( base, sub, progif ), \
185  .mask = ( ( ( ( (base) == PCI_ANY_ID ) ? 0x00 : 0xff ) << 16 ) | \
186  ( ( ( (sub) == PCI_ANY_ID ) ? 0x00 : 0xff ) << 8 ) | \
187  ( ( ( (progif) == PCI_ANY_ID ) ? 0x00 : 0xff ) << 0 ) ), \
188  }
189 
190 /** A PCI device */
191 struct pci_device {
192  /** Generic device */
193  struct device dev;
194  /** DMA device */
195  struct dma_device dma;
196  /** Memory base
197  *
198  * This is the physical address of the first valid memory BAR.
199  */
200  unsigned long membase;
201  /**
202  * I/O address
203  *
204  * This is the physical address of the first valid I/O BAR.
205  */
206  unsigned long ioaddr;
207  /** Vendor ID */
209  /** Device ID */
211  /** Device class */
212  uint32_t class;
213  /** Interrupt number */
215  /** Segment, bus, device, and function (bus:dev.fn) number */
217  /** Driver for this device */
219  /** Driver-private data
220  *
221  * Use pci_set_drvdata() and pci_get_drvdata() to access this
222  * field.
223  */
224  void *priv;
225  /** Driver device ID */
226  struct pci_device_id *id;
227 };
228 
229 /** A PCI driver */
230 struct pci_driver {
231  /** PCI ID table */
233  /** Number of entries in PCI ID table */
234  unsigned int id_count;
235  /** PCI class ID */
237  /**
238  * Probe device
239  *
240  * @v pci PCI device
241  * @ret rc Return status code
242  */
243  int ( * probe ) ( struct pci_device *pci );
244  /**
245  * Remove device
246  *
247  * @v pci PCI device
248  */
249  void ( * remove ) ( struct pci_device *pci );
250 };
251 
252 /** PCI driver table */
253 #define PCI_DRIVERS __table ( struct pci_driver, "pci_drivers" )
254 
255 /** Declare a PCI driver */
256 #define __pci_driver __table_entry ( PCI_DRIVERS, 01 )
257 
258 /** Declare a fallback PCI driver */
259 #define __pci_driver_fallback __table_entry ( PCI_DRIVERS, 02 )
260 
261 #define PCI_SEG( busdevfn ) ( ( (busdevfn) >> 16 ) & 0xffff )
262 #define PCI_BUS( busdevfn ) ( ( (busdevfn) >> 8 ) & 0xff )
263 #define PCI_SLOT( busdevfn ) ( ( (busdevfn) >> 3 ) & 0x1f )
264 #define PCI_FUNC( busdevfn ) ( ( (busdevfn) >> 0 ) & 0x07 )
265 #define PCI_BUSDEVFN( segment, bus, slot, func ) \
266  ( ( (segment) << 16 ) | ( (bus) << 8 ) | \
267  ( (slot) << 3 ) | ( (func) << 0 ) )
268 #define PCI_FIRST_FUNC( busdevfn ) ( (busdevfn) & ~0x07 )
269 #define PCI_LAST_FUNC( busdevfn ) ( (busdevfn) | 0x07 )
270 
271 #define PCI_BASE_CLASS( class ) ( (class) >> 16 )
272 #define PCI_SUB_CLASS( class ) ( ( (class) >> 8 ) & 0xff )
273 #define PCI_PROG_INTF( class ) ( (class) & 0xff )
274 
275 /*
276  * PCI_ROM is used to build up entries in a struct pci_id array. It
277  * is also parsed by parserom.pl to generate Makefile rules and files
278  * for rom-o-matic.
279  *
280  * PCI_ID can be used to generate entries without creating a
281  * corresponding ROM in the build process.
282  */
283 #define PCI_ID( _vendor, _device, _name, _description, _data ) { \
284  .vendor = _vendor, \
285  .device = _device, \
286  .name = _name, \
287  .driver_data = _data \
288 }
289 #define PCI_ROM( _vendor, _device, _name, _description, _data ) \
290  PCI_ID( _vendor, _device, _name, _description, _data )
291 
292 /** PCI device debug message format */
293 #define PCI_FMT "%04x:%02x:%02x.%x"
294 
295 /** PCI device debug message arguments */
296 #define PCI_ARGS( pci ) \
297  PCI_SEG ( (pci)->busdevfn ), PCI_BUS ( (pci)->busdevfn ), \
298  PCI_SLOT ( (pci)->busdevfn ), PCI_FUNC ( (pci)->busdevfn )
299 
300 extern void adjust_pci_device ( struct pci_device *pci );
301 extern unsigned long pci_bar_start ( struct pci_device *pci,
302  unsigned int reg );
303 extern int pci_read_config ( struct pci_device *pci );
304 extern int pci_find_next ( struct pci_device *pci, unsigned int busdevfn );
305 extern int pci_find_driver ( struct pci_device *pci );
306 extern int pci_probe ( struct pci_device *pci );
307 extern void pci_remove ( struct pci_device *pci );
308 extern int pci_find_capability ( struct pci_device *pci, int capability );
309 extern int pci_find_next_capability ( struct pci_device *pci,
310  int pos, int capability );
311 extern unsigned long pci_bar_size ( struct pci_device *pci, unsigned int reg );
312 
313 /**
314  * Initialise PCI device
315  *
316  * @v pci PCI device
317  * @v busdevfn PCI bus:dev.fn address
318  */
319 static inline void pci_init ( struct pci_device *pci, unsigned int busdevfn ) {
320  pci->busdevfn = busdevfn;
321 }
322 
323 /**
324  * Set PCI driver
325  *
326  * @v pci PCI device
327  * @v driver PCI driver
328  * @v id PCI device ID
329  */
330 static inline void pci_set_driver ( struct pci_device *pci,
331  struct pci_driver *driver,
332  struct pci_device_id *id ) {
333  pci->driver = driver;
334  pci->id = id;
335  pci->dev.driver_name = id->name;
336 }
337 
338 /**
339  * Set PCI driver-private data
340  *
341  * @v pci PCI device
342  * @v priv Private data
343  */
344 static inline void pci_set_drvdata ( struct pci_device *pci, void *priv ) {
345  pci->priv = priv;
346 }
347 
348 /**
349  * Get PCI driver-private data
350  *
351  * @v pci PCI device
352  * @ret priv Private data
353  */
354 static inline void * pci_get_drvdata ( struct pci_device *pci ) {
355  return pci->priv;
356 }
357 
358 #endif /* _IPXE_PCI_H */
unsigned long membase
Memory base.
Definition: pci.h:200
uint8_t irq
Interrupt number.
Definition: pci.h:214
unsigned short uint16_t
Definition: stdint.h:11
DMA mappings.
struct pci_class_id class
PCI class ID.
Definition: pci.h:236
struct dma_device dma
DMA device.
Definition: pci.h:195
struct pci_driver * driver
Driver for this device.
Definition: pci.h:218
A PCI driver.
Definition: pci.h:230
static unsigned int unsigned int reg
Definition: myson.h:162
void(* remove)(struct pci_device *pci)
Remove device.
Definition: pci.h:249
int pci_probe(struct pci_device *pci)
Probe a PCI device.
Definition: pci.c:309
unsigned long ioaddr
I/O address.
Definition: pci.h:206
unsigned int id_count
Number of entries in PCI ID table.
Definition: pci.h:234
unsigned long driver_data
Arbitrary driver data.
Definition: pci.h:163
struct pci_device_id * ids
PCI ID table.
Definition: pci.h:232
static void pci_set_driver(struct pci_device *pci, struct pci_driver *driver, struct pci_device_id *id)
Set PCI driver.
Definition: pci.h:330
int pci_find_driver(struct pci_device *pci)
Find driver for PCI device.
Definition: pci.c:277
void pci_remove(struct pci_device *pci)
Remove a PCI device.
Definition: pci.c:331
uint32_t mask
Class mask.
Definition: pci.h:174
struct device dev
Generic device.
Definition: pci.h:193
int pci_find_next_capability(struct pci_device *pci, int pos, int capability)
Look for another PCI capability.
Definition: pciextra.c:73
static void pci_set_drvdata(struct pci_device *pci, void *priv)
Set PCI driver-private data.
Definition: pci.h:344
A hardware device.
Definition: device.h:73
void * priv
Driver-private data.
Definition: pci.h:224
uint16_t device
Device ID.
Definition: pci.h:210
u16 capability
Capability flags.
Definition: ieee80211.h:1036
const char * driver_name
Driver name.
Definition: device.h:77
uint8_t id
Request identifier.
Definition: ena.h:12
A PCI device.
Definition: pci.h:191
unsigned char uint8_t
Definition: stdint.h:10
A PCI class ID.
Definition: pci.h:170
A PCI device ID list entry.
Definition: pci.h:155
unsigned int uint32_t
Definition: stdint.h:12
const char * name
Name.
Definition: pci.h:157
uint16_t vendor
Vendor ID.
Definition: pci.h:208
static void * pci_get_drvdata(struct pci_device *pci)
Get PCI driver-private data.
Definition: pci.h:354
uint16_t vendor
PCI vendor ID.
Definition: pci.h:159
uint32_t busdevfn
Segment, bus, device, and function (bus:dev.fn) number.
Definition: pci.h:216
uint16_t device
PCI device ID.
Definition: pci.h:161
int pci_find_next(struct pci_device *pci, unsigned int busdevfn)
Find next device on PCI bus.
Definition: pci.c:229
PCI I/O API.
static struct tlan_private * priv
Definition: tlan.c:224
int(* probe)(struct pci_device *pci)
Probe device.
Definition: pci.h:243
struct pci_device_id * id
Driver device ID.
Definition: pci.h:226
Linker tables.
Device model.
int pci_read_config(struct pci_device *pci)
Read PCI device configuration.
Definition: pci.c:177
static void pci_init(struct pci_device *pci, unsigned int busdevfn)
Initialise PCI device.
Definition: pci.h:319
FILE_LICENCE(GPL2_OR_LATER_OR_UBDL)
unsigned long pci_bar_start(struct pci_device *pci, unsigned int reg)
Find the start of a PCI BAR.
Definition: pci.c:96
int pci_find_capability(struct pci_device *pci, int capability)
Look for a PCI capability.
Definition: pciextra.c:36
unsigned long pci_bar_size(struct pci_device *pci, unsigned int reg)
Find the size of a PCI BAR.
Definition: pciextra.c:90
void adjust_pci_device(struct pci_device *pci)
Enable PCI device.
Definition: pci.c:149
A DMA-capable device.
Definition: dma.h:47