iPXE
|
IC+ network driver. More...
Go to the source code of this file.
Data Structures | |
union | icplus_fragment |
Data fragment. More... | |
struct | icplus_descriptor |
Transmit or receive descriptor. More... | |
struct | icplus_ring |
Descriptor ring. More... | |
struct | icplus_nic |
An IC+ network card. More... | |
Macros | |
#define | ICP_BAR_SIZE 0x200 |
BAR size. More... | |
#define | ICP_ALIGN 0x8 |
Alignment requirement. More... | |
#define | ICP_BASE_LO 0x0 |
Base address low register offset. More... | |
#define | ICP_BASE_HI 0x4 |
Base address high register offset. More... | |
#define | ICP_ASICCTRL 0x30 |
ASIC control register (double word) More... | |
#define | ICP_ASICCTRL_PHYSPEED1000 0x00000040UL |
PHY speed 1000. More... | |
#define | ICP_ASICCTRL_GLOBALRESET 0x00010000UL |
Global reset. More... | |
#define | ICP_ASICCTRL_DMA 0x00080000UL |
DMA. More... | |
#define | ICP_ASICCTRL_FIFO 0x00100000UL |
FIFO. More... | |
#define | ICP_ASICCTRL_NETWORK 0x00200000UL |
Network. More... | |
#define | ICP_ASICCTRL_HOST 0x00400000UL |
Host. More... | |
#define | ICP_ASICCTRL_AUTOINIT 0x00800000UL |
Auto init. More... | |
#define | ICP_ASICCTRL_RESETBUSY 0x04000000UL |
Reset busy. More... | |
#define | ICP_RESET_MAX_WAIT_MS 1000 |
Maximum time to wait for reset. More... | |
#define | ICP_DMACTRL 0x00 |
DMA control register (word/double word) More... | |
#define | ICP_DMACTRL_RXPOLLNOW 0x0010 |
Receive poll now. More... | |
#define | ICP_DMACTRL_TXPOLLNOW 0x1000 |
Transmit poll now. More... | |
#define | ICP_EEPROMCTRL 0x4a |
EEPROM control register (word) More... | |
#define | ICP_EEPROMCTRL_ADDRESS(x) ( (x) << 0 ) |
Address. More... | |
#define | ICP_EEPROMCTRL_OPCODE(x) ( (x) << 8 ) |
Opcode. More... | |
#define | ICP_EEPROMCTRL_OPCODE_READ ICP_EEPROMCTRL_OPCODE ( 2 ) |
Read register. More... | |
#define | ICP_EEPROMCTRL_BUSY 0x8000 |
EEPROM busy. More... | |
#define | ICP_EEPROM_MAX_WAIT_MS 1000 |
Maximum time to wait for reading EEPROM. More... | |
#define | ICP_EEPROM_WORD_LEN_LOG2 1 |
EEPROM word length. More... | |
#define | ICP_EEPROM_MIN_SIZE_WORDS 0x20 |
Minimum EEPROM size, in words. More... | |
#define | ICP_EEPROM_MAC 0x10 |
Address of MAC address within EEPROM. More... | |
#define | ICP_EEPROMDATA 0x48 |
EEPROM data register (word) More... | |
#define | ICP_INTSTATUS 0x5e |
Interupt status register (word) More... | |
#define | ICP_INTSTATUS_TXCOMPLETE 0x0004 |
TX complete. More... | |
#define | ICP_INTSTATUS_LINKEVENT 0x0100 |
Link event. More... | |
#define | ICP_INTSTATUS_RXDMACOMPLETE 0x0400 |
RX DMA complete. More... | |
#define | ICP_MACCTRL 0x6c |
MAC control register (double word) More... | |
#define | ICP_MACCTRL_DUPLEX 0x00000020UL |
Duplex select. More... | |
#define | ICP_MACCTRL_TXENABLE 0x01000000UL |
TX enable. More... | |
#define | ICP_MACCTRL_TXDISABLE 0x02000000UL |
TX disable. More... | |
#define | ICP_MACCTRL_RXENABLE 0x08000000UL |
RX enable. More... | |
#define | ICP_MACCTRL_RXDISABLE 0x10000000UL |
RX disable. More... | |
#define | ICP_PHYCTRL 0x76 |
PHY control register (byte) More... | |
#define | ICP_PHYCTRL_MGMTCLK 0x01 |
Management clock. More... | |
#define | ICP_PHYCTRL_MGMTDATA 0x02 |
Management data. More... | |
#define | ICP_PHYCTRL_MGMTDIR 0x04 |
Management direction. More... | |
#define | ICP_PHYCTRL_LINKSPEED 0xc0 |
Link speed. More... | |
#define | ICP_RXMODE 0x88 |
Receive mode register (word) More... | |
#define | ICP_RXMODE_UNICAST 0x0001 |
Receive unicast. More... | |
#define | ICP_RXMODE_MULTICAST 0x0002 |
Receice multicast. More... | |
#define | ICP_RXMODE_BROADCAST 0x0004 |
Receive broadcast. More... | |
#define | ICP_RXMODE_ALLFRAMES 0x0008 |
Receive all frames. More... | |
#define | ICP_RFDLISTPTR 0x1c |
List pointer receive register. More... | |
#define | ICP_TFDLISTPTR 0x10 |
List pointer transmit register. More... | |
#define | ICP_TXSTATUS 0x60 |
Transmit status register. More... | |
#define | ICP_TXSTATUS_ERROR 0x00000001UL |
TX error. More... | |
#define | ICP_DONE 0x80 |
Descriptor complete. More... | |
#define | ICP_TX_UNALIGN 0x01 |
Transmit alignment disabled. More... | |
#define | ICP_TX_INDICATE 0x40 |
Request transmit completion. More... | |
#define | ICP_TX_SOLE_FRAG 0x01 |
Sole transmit fragment. More... | |
#define | ICP_RX_ERR_OVERRUN 0x01 |
Recieve frame overrun error. More... | |
#define | ICP_RX_ERR_RUNT 0x02 |
Receive runt frame error. More... | |
#define | ICP_RX_ERR_ALIGN 0x04 |
Receive alignment error. More... | |
#define | ICP_RX_ERR_FCS 0x08 |
Receive FCS error. More... | |
#define | ICP_RX_ERR_OVERSIZED 0x10 |
Receive oversized frame error. More... | |
#define | ICP_RX_ERR_LEN 0x20 |
Recieve length error. More... | |
#define | ICP_NUM_DESC 4 |
Number of descriptors. More... | |
#define | ICP_RX_MAX_LEN ETH_FRAME_LEN |
Maximum receive packet length. More... | |
Functions | |
FILE_LICENCE (GPL2_OR_LATER_OR_UBDL) | |
IC+ network driver.
Definition in file icplus.h.
#define ICP_ASICCTRL 0x30 |
#define ICP_ASICCTRL_PHYSPEED1000 0x00000040UL |
#define ICP_RESET_MAX_WAIT_MS 1000 |
#define ICP_DMACTRL 0x00 |
#define ICP_EEPROMCTRL_OPCODE_READ ICP_EEPROMCTRL_OPCODE ( 2 ) |
#define ICP_EEPROM_MAX_WAIT_MS 1000 |
#define ICP_EEPROM_MIN_SIZE_WORDS 0x20 |
#define ICP_EEPROM_MAC 0x10 |
#define ICP_TFDLISTPTR 0x10 |
#define ICP_RX_ERR_OVERRUN 0x01 |
#define ICP_RX_ERR_OVERSIZED 0x10 |
#define ICP_RX_MAX_LEN ETH_FRAME_LEN |
FILE_LICENCE | ( | GPL2_OR_LATER_OR_UBDL | ) |