iPXE
icplus.h
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1 #ifndef _ICPLUS_H
2 #define _ICPLUS_H
3 
4 /** @file
5  *
6  * IC+ network driver
7  *
8  */
9 
10 #include <ipxe/nvs.h>
11 #include <ipxe/mii_bit.h>
12 
13 FILE_LICENCE ( GPL2_OR_LATER_OR_UBDL );
14 
15 /** BAR size */
16 #define ICP_BAR_SIZE 0x200
17 
18 /** Alignment requirement */
19 #define ICP_ALIGN 0x8
20 
21 /** Base address low register offset */
22 #define ICP_BASE_LO 0x0
23 
24 /** Base address high register offset */
25 #define ICP_BASE_HI 0x4
26 
27 /** ASIC control register (double word) */
28 #define ICP_ASICCTRL 0x30
29 #define ICP_ASICCTRL_PHYSPEED1000 0x00000040UL /**< PHY speed 1000 */
30 #define ICP_ASICCTRL_GLOBALRESET 0x00010000UL /**< Global reset */
31 #define ICP_ASICCTRL_DMA 0x00080000UL /**< DMA */
32 #define ICP_ASICCTRL_FIFO 0x00100000UL /**< FIFO */
33 #define ICP_ASICCTRL_NETWORK 0x00200000UL /**< Network */
34 #define ICP_ASICCTRL_HOST 0x00400000UL /**< Host */
35 #define ICP_ASICCTRL_AUTOINIT 0x00800000UL /**< Auto init */
36 #define ICP_ASICCTRL_RESETBUSY 0x04000000UL /**< Reset busy */
37 
38 /** Maximum time to wait for reset */
39 #define ICP_RESET_MAX_WAIT_MS 1000
40 
41 /** DMA control register (word/double word) */
42 #define ICP_DMACTRL 0x00
43 #define ICP_DMACTRL_RXPOLLNOW 0x0010 /**< Receive poll now */
44 #define ICP_DMACTRL_TXPOLLNOW 0x1000 /**< Transmit poll now */
45 
46 /** EEPROM control register (word) */
47 #define ICP_EEPROMCTRL 0x4a
48 #define ICP_EEPROMCTRL_ADDRESS( x ) ( (x) << 0 ) /**< Address */
49 #define ICP_EEPROMCTRL_OPCODE( x ) ( (x) << 8 ) /**< Opcode */
50 #define ICP_EEPROMCTRL_OPCODE_READ \
51  ICP_EEPROMCTRL_OPCODE ( 2 ) /**< Read register */
52 #define ICP_EEPROMCTRL_BUSY 0x8000 /**< EEPROM busy */
53 
54 /** Maximum time to wait for reading EEPROM */
55 #define ICP_EEPROM_MAX_WAIT_MS 1000
56 
57 /** EEPROM word length */
58 #define ICP_EEPROM_WORD_LEN_LOG2 1
59 
60 /** Minimum EEPROM size, in words */
61 #define ICP_EEPROM_MIN_SIZE_WORDS 0x20
62 
63 /** Address of MAC address within EEPROM */
64 #define ICP_EEPROM_MAC 0x10
65 
66 /** EEPROM data register (word) */
67 #define ICP_EEPROMDATA 0x48
68 
69 /** Interupt status register (word) */
70 #define ICP_INTSTATUS 0x5e
71 #define ICP_INTSTATUS_TXCOMPLETE 0x0004 /**< TX complete */
72 #define ICP_INTSTATUS_LINKEVENT 0x0100 /**< Link event */
73 #define ICP_INTSTATUS_RXDMACOMPLETE 0x0400 /**< RX DMA complete */
74 
75 /** MAC control register (double word) */
76 #define ICP_MACCTRL 0x6c
77 #define ICP_MACCTRL_DUPLEX 0x00000020UL /**< Duplex select */
78 #define ICP_MACCTRL_TXENABLE 0x01000000UL /**< TX enable */
79 #define ICP_MACCTRL_TXDISABLE 0x02000000UL /**< TX disable */
80 #define ICP_MACCTRL_RXENABLE 0x08000000UL /**< RX enable */
81 #define ICP_MACCTRL_RXDISABLE 0x10000000UL /**< RX disable */
82 
83 /** PHY control register (byte) */
84 #define ICP_PHYCTRL 0x76
85 #define ICP_PHYCTRL_MGMTCLK 0x01 /**< Management clock */
86 #define ICP_PHYCTRL_MGMTDATA 0x02 /**< Management data */
87 #define ICP_PHYCTRL_MGMTDIR 0x04 /**< Management direction */
88 #define ICP_PHYCTRL_LINKSPEED 0xc0 /**< Link speed */
89 
90 /** Receive mode register (word) */
91 #define ICP_RXMODE 0x88
92 #define ICP_RXMODE_UNICAST 0x0001 /**< Receive unicast */
93 #define ICP_RXMODE_MULTICAST 0x0002 /**< Receice multicast */
94 #define ICP_RXMODE_BROADCAST 0x0004 /**< Receive broadcast */
95 #define ICP_RXMODE_ALLFRAMES 0x0008 /**< Receive all frames */
96 
97 /** List pointer receive register */
98 #define ICP_RFDLISTPTR 0x1c
99 
100 /** List pointer transmit register */
101 #define ICP_TFDLISTPTR 0x10
102 
103 /** Transmit status register */
104 #define ICP_TXSTATUS 0x60
105 #define ICP_TXSTATUS_ERROR 0x00000001UL /**< TX error */
106 
107 /** Data fragment */
109  /** Address of data */
111  /** Length */
112  struct {
113  /** Reserved */
115  /** Length of data */
117  };
118 };
119 
120 /** Transmit or receive descriptor */
122  /** Address of next descriptor */
124  /** Actual length */
126  /** Flags */
128  /** Control */
130  /** VLAN */
132  /** Reserved */
134  /** Data buffer */
136  /** Reserved */
138 };
139 
140 /** Descriptor complete */
141 #define ICP_DONE 0x80
142 
143 /** Transmit alignment disabled */
144 #define ICP_TX_UNALIGN 0x01
145 
146 /** Request transmit completion */
147 #define ICP_TX_INDICATE 0x40
148 
149 /** Sole transmit fragment */
150 #define ICP_TX_SOLE_FRAG 0x01
151 
152 /** Recieve frame overrun error */
153 #define ICP_RX_ERR_OVERRUN 0x01
154 
155 /** Receive runt frame error */
156 #define ICP_RX_ERR_RUNT 0x02
157 
158 /** Receive alignment error */
159 #define ICP_RX_ERR_ALIGN 0x04
160 
161 /** Receive FCS error */
162 #define ICP_RX_ERR_FCS 0x08
163 
164 /** Receive oversized frame error */
165 #define ICP_RX_ERR_OVERSIZED 0x10
166 
167 /** Recieve length error */
168 #define ICP_RX_ERR_LEN 0x20
169 
170 /** Descriptor ring */
171 struct icplus_ring {
172  /** Producer counter */
173  unsigned int prod;
174  /** Consumer counter */
175  unsigned int cons;
176  /** Ring entries */
178  /* List pointer register */
179  unsigned int listptr;
180 };
181 
182 /** Number of descriptors */
183 #define ICP_NUM_DESC 4
184 
185 /** Maximum receive packet length */
186 #define ICP_RX_MAX_LEN ETH_FRAME_LEN
187 
188 /** An IC+ network card */
189 struct icplus_nic {
190  /** Registers */
191  void *regs;
192  /** EEPROM */
194  /** MII bit bashing interface */
196  /** MII device */
197  struct mii_device mii;
198  /** Transmit descriptor ring */
199  struct icplus_ring tx;
200  /** Receive descriptor ring */
201  struct icplus_ring rx;
202  /** Receive I/O buffers */
204 };
205 
206 #endif /* _ICPLUS_H */
unsigned short uint16_t
Definition: stdint.h:11
uint8_t flags
Flags.
Definition: icplus.h:127
struct icplus_ring tx
Transmit descriptor ring.
Definition: icplus.h:199
unsigned int prod
Producer counter.
Definition: icplus.h:173
A non-volatile storage device.
Definition: nvs.h:15
Descriptor ring.
Definition: icplus.h:171
Data fragment.
Definition: icplus.h:108
unsigned long long uint64_t
Definition: stdint.h:13
Non-volatile storage.
struct icplus_descriptor * entry
Ring entries.
Definition: icplus.h:177
uint16_t len
Actual length.
Definition: icplus.h:125
uint8_t control
Control.
Definition: icplus.h:129
uint64_t address
Address of data.
Definition: icplus.h:110
eeprom
Definition: 3c90x.h:232
uint8_t reserved[6]
Reserved.
Definition: icplus.h:114
An MII device.
Definition: mii.h:49
MII bit-bashing interface.
unsigned int cons
Consumer counter.
Definition: icplus.h:175
Transmit or receive descriptor.
Definition: icplus.h:121
uint8_t reserved_b[8]
Reserved.
Definition: icplus.h:137
uint16_t len
Length of data.
Definition: icplus.h:116
unsigned char uint8_t
Definition: stdint.h:10
An IC+ network card.
Definition: icplus.h:189
unsigned int listptr
Definition: icplus.h:179
struct mii_bit_basher miibit
MII bit bashing interface.
Definition: icplus.h:195
#define ICP_NUM_DESC
Number of descriptors.
Definition: icplus.h:183
struct mii_device mii
MII device.
Definition: icplus.h:197
FILE_LICENCE(GPL2_OR_LATER_OR_UBDL)
struct io_buffer * rx_iobuf[ICP_NUM_DESC]
Receive I/O buffers.
Definition: icplus.h:203
uint64_t next
Address of next descriptor.
Definition: icplus.h:123
uint16_t reserved_a
Reserved.
Definition: icplus.h:133
struct icplus_ring rx
Receive descriptor ring.
Definition: icplus.h:201
union icplus_fragment data
Data buffer.
Definition: icplus.h:135
A bit-bashing MII interface.
Definition: mii_bit.h:33
uint16_t vlan
VLAN.
Definition: icplus.h:131
A persistent I/O buffer.
Definition: iobuf.h:32
void * regs
Registers.
Definition: icplus.h:191