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| #define | XEN_FLEX_ARRAY_DIM 1 /* variable size */ |
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| #define | __xen_mk_uint(x) x ## U |
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| #define | __xen_mk_ulong(x) x ## UL |
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| #define | __xen_mk_ullong(x) x ## ULL |
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| #define | xen_mk_uint(x) __xen_mk_uint(x) |
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| #define | xen_mk_ulong(x) __xen_mk_ulong(x) |
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| #define | xen_mk_ullong(x) __xen_mk_ullong(x) |
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| #define | __HYPERVISOR_set_trap_table 0 |
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| #define | __HYPERVISOR_mmu_update 1 |
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| #define | __HYPERVISOR_set_gdt 2 |
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| #define | __HYPERVISOR_stack_switch 3 |
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| #define | __HYPERVISOR_set_callbacks 4 |
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| #define | __HYPERVISOR_fpu_taskswitch 5 |
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| #define | __HYPERVISOR_sched_op_compat 6 /* compat since 0x00030101 */ |
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| #define | __HYPERVISOR_platform_op 7 |
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| #define | __HYPERVISOR_set_debugreg 8 |
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| #define | __HYPERVISOR_get_debugreg 9 |
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| #define | __HYPERVISOR_update_descriptor 10 |
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| #define | __HYPERVISOR_memory_op 12 |
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| #define | __HYPERVISOR_multicall 13 |
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| #define | __HYPERVISOR_update_va_mapping 14 |
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| #define | __HYPERVISOR_set_timer_op 15 |
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| #define | __HYPERVISOR_event_channel_op_compat 16 /* compat since 0x00030202 */ |
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| #define | __HYPERVISOR_xen_version 17 |
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| #define | __HYPERVISOR_console_io 18 |
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| #define | __HYPERVISOR_physdev_op_compat 19 /* compat since 0x00030202 */ |
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| #define | __HYPERVISOR_grant_table_op 20 |
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| #define | __HYPERVISOR_vm_assist 21 |
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| #define | __HYPERVISOR_update_va_mapping_otherdomain 22 |
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| #define | __HYPERVISOR_iret 23 /* x86 only */ |
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| #define | __HYPERVISOR_vcpu_op 24 |
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| #define | __HYPERVISOR_set_segment_base 25 /* x86/64 only */ |
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| #define | __HYPERVISOR_mmuext_op 26 |
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| #define | __HYPERVISOR_xsm_op 27 |
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| #define | __HYPERVISOR_nmi_op 28 |
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| #define | __HYPERVISOR_sched_op 29 |
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| #define | __HYPERVISOR_callback_op 30 |
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| #define | __HYPERVISOR_xenoprof_op 31 |
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| #define | __HYPERVISOR_event_channel_op 32 |
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| #define | __HYPERVISOR_physdev_op 33 |
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| #define | __HYPERVISOR_hvm_op 34 |
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| #define | __HYPERVISOR_sysctl 35 |
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| #define | __HYPERVISOR_domctl 36 |
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| #define | __HYPERVISOR_kexec_op 37 |
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| #define | __HYPERVISOR_tmem_op 38 |
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| #define | __HYPERVISOR_argo_op 39 |
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| #define | __HYPERVISOR_xenpmu_op 40 |
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| #define | __HYPERVISOR_dm_op 41 |
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| #define | __HYPERVISOR_hypfs_op 42 |
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| #define | __HYPERVISOR_arch_0 48 |
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| #define | __HYPERVISOR_arch_1 49 |
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| #define | __HYPERVISOR_arch_2 50 |
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| #define | __HYPERVISOR_arch_3 51 |
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| #define | __HYPERVISOR_arch_4 52 |
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| #define | __HYPERVISOR_arch_5 53 |
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| #define | __HYPERVISOR_arch_6 54 |
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| #define | __HYPERVISOR_arch_7 55 |
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| #define | __HYPERVISOR_sched_op __HYPERVISOR_sched_op_compat |
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| #define | __HYPERVISOR_event_channel_op __HYPERVISOR_event_channel_op_compat |
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| #define | __HYPERVISOR_physdev_op __HYPERVISOR_physdev_op_compat |
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| #define | __HYPERVISOR_dom0_op __HYPERVISOR_platform_op |
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| #define | VIRQ_TIMER 0 /* V. Timebase update, and/or requested timeout. */ |
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| #define | VIRQ_DEBUG 1 /* V. Request guest to dump debug info. */ |
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| #define | VIRQ_CONSOLE 2 /* G. (DOM0) Bytes received on emergency console. */ |
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| #define | VIRQ_DOM_EXC 3 /* G. (DOM0) Exceptional event for some domain. */ |
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| #define | VIRQ_TBUF 4 /* G. (DOM0) Trace buffer has records available. */ |
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| #define | VIRQ_DEBUGGER 6 /* G. (DOM0) A domain has paused for debugging. */ |
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| #define | VIRQ_XENOPROF 7 /* V. XenOprofile interrupt: new sample available */ |
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| #define | VIRQ_CON_RING 8 /* G. (DOM0) Bytes received on console */ |
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| #define | VIRQ_PCPU_STATE 9 /* G. (DOM0) PCPU state changed */ |
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| #define | VIRQ_MEM_EVENT 10 /* G. (DOM0) A memory event has occurred */ |
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| #define | VIRQ_ARGO 11 /* G. Argo interdomain message notification */ |
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| #define | VIRQ_ENOMEM 12 /* G. (DOM0) Low on heap memory */ |
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| #define | VIRQ_XENPMU 13 /* V. PMC interrupt */ |
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| #define | VIRQ_ARCH_0 16 |
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| #define | VIRQ_ARCH_1 17 |
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| #define | VIRQ_ARCH_2 18 |
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| #define | VIRQ_ARCH_3 19 |
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| #define | VIRQ_ARCH_4 20 |
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| #define | VIRQ_ARCH_5 21 |
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| #define | VIRQ_ARCH_6 22 |
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| #define | VIRQ_ARCH_7 23 |
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| #define | NR_VIRQS 24 |
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| #define | MMU_NORMAL_PT_UPDATE 0 /* checked '*ptr = val'. ptr is MA. */ |
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| #define | MMU_MACHPHYS_UPDATE 1 /* ptr = MA of frame to modify entry for */ |
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| #define | MMU_PT_UPDATE_PRESERVE_AD 2 /* atomically: *ptr = val | (*ptr&(A|D)) */ |
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| #define | MMU_PT_UPDATE_NO_TRANSLATE 3 /* checked '*ptr = val'. ptr is MA. */ |
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| #define | MMUEXT_PIN_L1_TABLE 0 |
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| #define | MMUEXT_PIN_L2_TABLE 1 |
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| #define | MMUEXT_PIN_L3_TABLE 2 |
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| #define | MMUEXT_PIN_L4_TABLE 3 |
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| #define | MMUEXT_UNPIN_TABLE 4 |
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| #define | MMUEXT_NEW_BASEPTR 5 |
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| #define | MMUEXT_TLB_FLUSH_LOCAL 6 |
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| #define | MMUEXT_INVLPG_LOCAL 7 |
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| #define | MMUEXT_TLB_FLUSH_MULTI 8 |
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| #define | MMUEXT_INVLPG_MULTI 9 |
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| #define | MMUEXT_TLB_FLUSH_ALL 10 |
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| #define | MMUEXT_INVLPG_ALL 11 |
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| #define | MMUEXT_FLUSH_CACHE 12 |
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| #define | MMUEXT_SET_LDT 13 |
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| #define | MMUEXT_NEW_USER_BASEPTR 15 |
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| #define | MMUEXT_CLEAR_PAGE 16 |
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| #define | MMUEXT_COPY_PAGE 17 |
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| #define | MMUEXT_FLUSH_CACHE_GLOBAL 18 |
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| #define | MMUEXT_MARK_SUPER 19 |
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| #define | MMUEXT_UNMARK_SUPER 20 |
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| #define | UVMF_NONE (xen_mk_ulong(0)<<0) /* No flushing at all. */ |
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| #define | UVMF_TLB_FLUSH (xen_mk_ulong(1)<<0) /* Flush entire TLB(s). */ |
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| #define | UVMF_INVLPG (xen_mk_ulong(2)<<0) /* Flush only one entry. */ |
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| #define | UVMF_FLUSHTYPE_MASK (xen_mk_ulong(3)<<0) |
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| #define | UVMF_MULTI (xen_mk_ulong(0)<<2) /* Flush subset of TLBs. */ |
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| #define | UVMF_LOCAL (xen_mk_ulong(0)<<2) /* Flush local TLB. */ |
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| #define | UVMF_ALL (xen_mk_ulong(1)<<2) /* Flush all TLBs. */ |
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| #define | CONSOLEIO_write 0 |
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| #define | CONSOLEIO_read 1 |
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| #define | VMASST_CMD_enable 0 |
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| #define | VMASST_CMD_disable 1 |
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| #define | VMASST_TYPE_4gb_segments 0 |
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| #define | VMASST_TYPE_4gb_segments_notify 1 |
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| #define | VMASST_TYPE_writable_pagetables 2 |
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| #define | VMASST_TYPE_pae_extended_cr3 3 |
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| #define | VMASST_TYPE_architectural_iopl 4 |
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| #define | VMASST_TYPE_runstate_update_flag 5 |
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| #define | VMASST_TYPE_m2p_strict 32 |
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| #define | MAX_VMASST_TYPE 3 |
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| #define | DOMID_FIRST_RESERVED xen_mk_uint(0x7FF0) |
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| #define | DOMID_SELF xen_mk_uint(0x7FF0) |
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| #define | DOMID_IO xen_mk_uint(0x7FF1) |
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| #define | DOMID_XEN xen_mk_uint(0x7FF2) |
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| #define | DOMID_COW xen_mk_uint(0x7FF3) |
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| #define | DOMID_INVALID xen_mk_uint(0x7FF4) |
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| #define | DOMID_IDLE xen_mk_uint(0x7FFF) |
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| #define | DOMID_MASK xen_mk_uint(0x7FFF) |
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| #define | NR_EVENT_CHANNELS EVTCHN_2L_NR_CHANNELS |
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| #define | XEN_PVCLOCK_TSC_STABLE_BIT (1 << 0) |
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| #define | XEN_PVCLOCK_GUEST_STOPPED (1 << 1) |
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| #define | xen_wc_sec_hi wc_sec_hi |
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| #define | SIF_PRIVILEGED (1<<0) /* Is the domain privileged? */ |
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| #define | SIF_INITDOMAIN (1<<1) /* Is this the initial control domain? */ |
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| #define | SIF_MULTIBOOT_MOD (1<<2) /* Is mod_start a multiboot module? */ |
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| #define | SIF_MOD_START_PFN (1<<3) /* Is mod_start a PFN? */ |
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| #define | SIF_VIRT_P2M_4TOOLS (1<<4) /* Do Xen tools understand a virt. mapped */ |
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| #define | SIF_PM_MASK (0xFF<<8) /* reserve 1 byte for xen-pm options */ |
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| #define | XEN_VGATYPE_TEXT_MODE_3 0x03 |
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| #define | XEN_VGATYPE_VESA_LFB 0x23 |
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| #define | XEN_VGATYPE_EFI_LFB 0x70 |
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| #define | xen_vga_console_info dom0_vga_console_info |
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| #define | xen_vga_console_info_t dom0_vga_console_info_t |
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| #define | XEN_DEFINE_UUID_(a, b, c, d, e1, e2, e3, e4, e5, e6) |
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| #define | XEN_DEFINE_UUID(a, b, c, d, e1, e2, e3, e4, e5, e6) XEN_DEFINE_UUID_(a, b, c, d, e1, e2, e3, e4, e5, e6) |
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