Definition at line 12 of file setjmp.h.
Referenced by __ew32(), __gm_phy_read(), __mdio_write(), __tg3_set_coalesce(), __vxge_hw_pio_mem_write32_lower(), __vxge_hw_pio_mem_write32_upper(), __vxge_hw_vpath_pci_read(), __xm_phy_read(), _tw32_flush(), a3c90x_internal_IssueCommand(), amd8111e_read_phy(), ar5008_hw_ani_cache_ini_regs(), ar5008_hw_override_ini(), ar5008_hw_process_ini(), ar9002_hw_adc_dccal_calibrate(), ar9002_hw_adc_gaincal_calibrate(), ar9002_hw_configpcipowersave(), ar9002_hw_get_radiorev(), ar9002_hw_load_ani_reg(), ar9002_hw_rf_claim(), ar9002_hw_set_clrdmask(), ar9003_hw_ani_cache_ini_regs(), ar9003_hw_ant_ctrl_chain_get(), ar9003_hw_ant_ctrl_common_2_get(), ar9003_hw_ant_ctrl_common_get(), ar9003_hw_disable_phy_restart(), ar9003_hw_init_cal(), ar9003_hw_override_ini(), ar9003_hw_prog_ini(), ar9003_hw_set_clrdmask(), ar9300_eeprom_read_byte(), ar9300_eeprom_read_word(), ath5k_eeprom_bin2freq(), ath5k_eeprom_init_11a_pcal_freq(), ath5k_eeprom_init_header(), ath5k_eeprom_read_ants(), ath5k_eeprom_read_ctl_info(), ath5k_eeprom_read_freq_list(), ath5k_eeprom_read_modes(), ath5k_eeprom_read_pcal_info_2413(), ath5k_eeprom_read_pcal_info_5111(), ath5k_eeprom_read_pcal_info_5112(), ath5k_eeprom_read_target_rate_pwr_info(), ath5k_eeprom_read_turbo_modes(), ath5k_hw_bitswap(), ath5k_hw_nic_reset(), ath5k_hw_reg_write(), ath5k_hw_rfb_op(), ath5k_hw_set_ack_bitrate_high(), ath5k_hw_set_gpio(), ath9k_hw_analog_shift_regwrite(), ath9k_hw_analog_shift_rmw(), ath9k_hw_gpio_get(), ath9k_hw_loadnf(), ath9k_hw_read_revisions(), ath9k_hw_reverse_bits(), ath9k_hw_set_ack_timeout(), ath9k_hw_set_clrdmask(), ath9k_hw_set_cts_timeout(), ath9k_hw_set_gpio(), ath9k_hw_set_power_awake(), ath9k_hw_set_reset(), ath9k_hw_setslottime(), ath9k_hw_wait(), ath9k_ioread32(), ath9k_iowrite32(), ath9k_reg_rmw(), ath_pci_probe(), atl1e_mdio_write(), atl1e_phy_commit(), atl1e_read_phy_reg(), atl1e_up(), atl1e_write_phy_reg(), atl2_hw_fw_init_(), atl2_hw_get_link(), atl2_hw_start(), atl2_hw_stop(), atl_hw_reset_flb_(), atl_hw_reset_rbl_(), atl_ring_next_dx(), b44_cam_write(), b44_chip_reset(), b44_init_hw(), b44_phy_read(), b44_phy_reset(), b44_phy_write(), b44_set_mac_addr(), b44_set_rx_mode(), b44_wait_bit(), bcom_phy_init(), bnx2_5708s_linkup(), bnx2_alloc_bad_rbuf(), bnx2_ctx_wr(), bnx2_disable_nvram_access(), bnx2_enable_nvram_access(), bnx2_fw_sync(), bnx2_init_5706s_phy(), bnx2_init_5708s_phy(), bnx2_init_chip(), bnx2_init_copper_phy(), bnx2_init_nvram(), bnx2_init_phy(), bnx2_init_rx_ring(), bnx2_init_tx_ring(), bnx2_read_phy(), bnx2_reg_wr_ind(), bnx2_reset_chip(), bnx2_resolve_flow_ctrl(), bnx2_set_link(), bnx2_set_mac_addr(), bnx2_set_mac_link(), bnx2_set_power_state_0(), bnx2_write_phy(), bw32(), dev_p5_db(), dev_p7_db(), falcon_txc_logic_reset(), flexboot_nodnic_arm_cq(), gdbstub_get_packet_args(), gm_phy_write(), golan_eq_update_ci(), hfa384x_drvr_setconfig16(), hfa384x_setreg(), hfa384x_setreg_noswap(), ifec_mdio_read(), ifec_mdio_write(), ifec_spi_write_bit(), jme_disable_rx_engine(), jme_disable_tx_engine(), jme_load_macaddr(), jme_mdio_read(), jme_mdio_write(), jme_reload_eeprom(), jme_reset_phy_processor(), jme_set_custom_macaddr(), jwrite32(), jwrite32f(), load_cpu_fw(), load_rv2p_fw(), mdio_write(), myri10ge_net_irq(), oncrpc_iob_add_int(), oncrpc_iob_add_int64(), pcnet32_dwio_write_bcr(), pcnet32_dwio_write_csr(), pcnet32_dwio_write_rap(), pcnet32_irq_enable(), pcnet32_mdio_write(), pcnet32_open(), pcnet32_setup_if_duplex(), pcnet32_setup_mac_addr(), pcnet32_wio_write_bcr(), pcnet32_wio_write_csr(), pcnet32_wio_write_rap(), rtl818x_iowrite16(), rtl818x_iowrite32(), rtl818x_iowrite8(), sis190_phy_task(), sis190_set_speed_auto(), skge_write16(), skge_write32(), skge_write8(), sky2_pci_write16(), sky2_pci_write32(), sky2_write16(), sky2_write32(), sky2_write8(), ssb_core_reset(), ssb_pci_setup(), tg3_aux_stat_to_speed_duplex(), tg3_chip_reset(), tg3_do_test_dma(), tg3_generate_fw_event(), tg3_get_eeprom_hw_cfg(), tg3_get_invariants(), tg3_issue_otp_command(), tg3_nvram_read(), tg3_nvram_read_be32(), tg3_nvram_read_using_eeprom(), tg3_phy_autoneg_cfg(), tg3_phy_auxctl_read(), tg3_phy_reset(), tg3_phy_set_wirespeed(), tg3_phydsp_write(), tg3_poll_fw(), tg3_read_indirect_mbox(), tg3_read_indirect_reg32(), tg3_read_mem(), tg3_readphy(), tg3_reset_hw(), tg3_restore_pci_state(), tg3_setup_copper_phy(), tg3_setup_fiber_hw_autoneg(), tg3_setup_phy(), tg3_setup_rxbd_thresholds(), tg3_stop_block(), tg3_test_dma(), tg3_ump_link_report(), tg3_write32_mbox_5906(), tg3_write_indirect_mbox(), tg3_write_indirect_reg32(), tg3_write_mem(), tg3_writephy(), TLan_MiiReadReg(), TLan_MiiWriteReg(), tw32_mailbox_flush(), and xm_phy_write().