Intel 10 Gigabit Ethernet network card driver. More...

#include <stdint.h>
#include <ipxe/if_ether.h>
#include "intel.h"

Macros
#define	INTELX_CTRL 0x00000UL
	Device Control Register. More...

#define	INTELX_CTRL_LRST 0x00000008UL
	Link reset. More...

#define	INTELX_CTRL_RST 0x04000000UL
	Device reset. More...

#define	INTELX_RESET_DELAY_MS 20
	Time to delay for device reset, in milliseconds. More...

#define	INTELX_EICR 0x00800UL
	Extended Interrupt Cause Read Register. More...

#define	INTELX_EIRQ_RX0 0x00000001UL
	RX0 (via IVAR) More...

#define	INTELX_EIRQ_TX0 0x00000002UL
	RX0 (via IVAR) More...

#define	INTELX_EIRQ_RXO 0x00020000UL
	Receive overrun. More...

#define	INTELX_EIRQ_LSC 0x00100000UL
	Link status change. More...

#define	INTELX_EIMS 0x00880UL
	Interrupt Mask Set/Read Register. More...

#define	INTELX_EIMC 0x00888UL
	Interrupt Mask Clear Register. More...

#define	INTELX_IVAR 0x00900UL
	Interrupt Vector Allocation Register. More...

#define	INTELX_IVAR_RX0(bit) ( (bit) << 0 )
	RX queue 0 allocation. More...

#define	INTELX_IVAR_RX0_DEFAULT INTELX_IVAR_RX0 ( 0x00 )

#define	INTELX_IVAR_RX0_MASK INTELX_IVAR_RX0 ( 0x3f )

#define	INTELX_IVAR_RX0_VALID 0x00000080UL
	RX queue 0 valid. More...

#define	INTELX_IVAR_TX0(bit) ( (bit) << 8 )
	TX queue 0 allocation. More...

#define	INTELX_IVAR_TX0_DEFAULT INTELX_IVAR_TX0 ( 0x01 )

#define	INTELX_IVAR_TX0_MASK INTELX_IVAR_TX0 ( 0x3f )

#define	INTELX_IVAR_TX0_VALID 0x00008000UL
	TX queue 0 valid. More...

#define	INTELX_FCTRL 0x05080UL
	Receive Filter Control Register. More...

#define	INTELX_FCTRL_MPE 0x00000100UL
	Multicast promiscuous. More...

#define	INTELX_FCTRL_UPE 0x00000200UL
	Unicast promiscuous mode. More...

#define	INTELX_FCTRL_BAM 0x00000400UL
	Broadcast accept mode. More...

#define	INTELX_RAL0 0x05400UL
	Receive Address Low. More...

#define	INTELX_RAL0_ALT 0x0a200UL

#define	INTELX_RAH0 0x05404UL
	Receive Address High. More...

#define	INTELX_RAH0_ALT 0x0a204UL

#define	INTELX_RAH0_AV 0x80000000UL
	Address valid. More...

#define	INTELX_RD 0x01000UL
	Receive Descriptor register block. More...

#define	INTELX_RXDCTL_VME 0x40000000UL
	Receive Descriptor Control Register. More...

#define	INTELX_SRRCTL 0x02100UL
	Split Receive Control Register. More...

#define	INTELX_SRRCTL_BSIZE(kb) ( (kb) << 0 )
	Receive buffer size. More...

#define	INTELX_SRRCTL_BSIZE_DEFAULT INTELX_SRRCTL_BSIZE ( 0x02 )

#define	INTELX_SRRCTL_BSIZE_MASK INTELX_SRRCTL_BSIZE ( 0x1f )

#define	INTELX_RDRXCTL 0x02f00UL
	Receive DMA Control Register. More...

#define	INTELX_RDRXCTL_SECRC 0x00000001UL
	Strip CRC. More...

#define	INTELX_RXCTRL 0x03000UL
	Receive Control Register. More...

#define	INTELX_RXCTRL_RXEN 0x00000001UL
	Receive enable. More...

#define	INTELX_DMATXCTL 0x04a80UL
	Transmit DMA Control Register. More...

#define	INTELX_DMATXCTL_TE 0x00000001UL
	Transmit enable. More...

#define	INTELX_TD 0x06000UL
	Transmit Descriptor register block. More...

#define	INTELX_DCA_RXCTRL 0x02200UL
	RX DCA Control Register. More...

#define	INTELX_DCA_RXCTRL_MUST_BE_ZERO 0x00001000UL
	Must be zero. More...

#define	INTELX_HLREG0 0x04240UL
	MAC Core Control 0 Register. More...

#define	INTELX_HLREG0_JUMBOEN 0x00000004UL
	Jumbo frame enable. More...

#define	INTELX_MAXFRS 0x04268UL
	Maximum Frame Size Register. More...

#define	INTELX_MAXFRS_MFS(len) ( (len) << 16 )
	Maximum frame size. More...

#define	INTELX_MAXFRS_MFS_DEFAULT INTELX_MAXFRS_MFS ( ETH_FRAME_LEN + 4 /* VLAN / + 4 / CRC */ )

#define	INTELX_MAXFRS_MFS_MASK INTELX_MAXFRS_MFS ( 0xffff )

#define	INTELX_LINKS 0x042a4UL
	Link Status Register. More...

#define	INTELX_LINKS_UP 0x40000000UL
	Link up. More...

Functions
	FILE_LICENCE (GPL2_OR_LATER_OR_UBDL)

Detailed Description

Intel 10 Gigabit Ethernet network card driver.

Definition in file intelx.h.

Macro Definition Documentation

◆ INTELX_CTRL

#define INTELX_CTRL 0x00000UL

Device Control Register.

Definition at line 17 of file intelx.h.

◆ INTELX_CTRL_LRST

#define INTELX_CTRL_LRST 0x00000008UL

Link reset.

Definition at line 18 of file intelx.h.

◆ INTELX_CTRL_RST

#define INTELX_CTRL_RST 0x04000000UL

Device reset.

Definition at line 19 of file intelx.h.

◆ INTELX_RESET_DELAY_MS

#define INTELX_RESET_DELAY_MS 20

Time to delay for device reset, in milliseconds.

Definition at line 22 of file intelx.h.

◆ INTELX_EICR

#define INTELX_EICR 0x00800UL

Extended Interrupt Cause Read Register.

Definition at line 25 of file intelx.h.

◆ INTELX_EIRQ_RX0

#define INTELX_EIRQ_RX0 0x00000001UL

RX0 (via IVAR)

Definition at line 26 of file intelx.h.

◆ INTELX_EIRQ_TX0

#define INTELX_EIRQ_TX0 0x00000002UL

RX0 (via IVAR)

Definition at line 27 of file intelx.h.

◆ INTELX_EIRQ_RXO

#define INTELX_EIRQ_RXO 0x00020000UL

Receive overrun.

Definition at line 28 of file intelx.h.

◆ INTELX_EIRQ_LSC

#define INTELX_EIRQ_LSC 0x00100000UL

Link status change.

Definition at line 29 of file intelx.h.

◆ INTELX_EIMS

#define INTELX_EIMS 0x00880UL

Interrupt Mask Set/Read Register.

Definition at line 32 of file intelx.h.

◆ INTELX_EIMC

#define INTELX_EIMC 0x00888UL

Interrupt Mask Clear Register.

Definition at line 35 of file intelx.h.

◆ INTELX_IVAR

#define INTELX_IVAR 0x00900UL

Interrupt Vector Allocation Register.

Definition at line 38 of file intelx.h.

◆ INTELX_IVAR_RX0

#define INTELX_IVAR_RX0 ( bit ) ( (bit) << 0 )

RX queue 0 allocation.

Definition at line 39 of file intelx.h.

◆ INTELX_IVAR_RX0_DEFAULT

#define INTELX_IVAR_RX0_DEFAULT INTELX_IVAR_RX0 ( 0x00 )

Definition at line 40 of file intelx.h.

◆ INTELX_IVAR_RX0_MASK

#define INTELX_IVAR_RX0_MASK INTELX_IVAR_RX0 ( 0x3f )

Definition at line 41 of file intelx.h.

◆ INTELX_IVAR_RX0_VALID

#define INTELX_IVAR_RX0_VALID 0x00000080UL

RX queue 0 valid.

Definition at line 42 of file intelx.h.

◆ INTELX_IVAR_TX0

#define INTELX_IVAR_TX0 ( bit ) ( (bit) << 8 )

TX queue 0 allocation.

Definition at line 43 of file intelx.h.

◆ INTELX_IVAR_TX0_DEFAULT

#define INTELX_IVAR_TX0_DEFAULT INTELX_IVAR_TX0 ( 0x01 )

Definition at line 44 of file intelx.h.

◆ INTELX_IVAR_TX0_MASK

#define INTELX_IVAR_TX0_MASK INTELX_IVAR_TX0 ( 0x3f )

Definition at line 45 of file intelx.h.

◆ INTELX_IVAR_TX0_VALID

#define INTELX_IVAR_TX0_VALID 0x00008000UL

TX queue 0 valid.

Definition at line 46 of file intelx.h.

◆ INTELX_FCTRL

#define INTELX_FCTRL 0x05080UL

Receive Filter Control Register.

Definition at line 49 of file intelx.h.

◆ INTELX_FCTRL_MPE

#define INTELX_FCTRL_MPE 0x00000100UL

Multicast promiscuous.

Definition at line 50 of file intelx.h.

◆ INTELX_FCTRL_UPE

#define INTELX_FCTRL_UPE 0x00000200UL

Unicast promiscuous mode.

Definition at line 51 of file intelx.h.

◆ INTELX_FCTRL_BAM

#define INTELX_FCTRL_BAM 0x00000400UL

Broadcast accept mode.

Definition at line 52 of file intelx.h.

◆ INTELX_RAL0

#define INTELX_RAL0 0x05400UL

Receive Address Low.

The MAC address registers RAL0/RAH0 exist at address 0x05400 for the 82598 and 0x0a200 for the 82599, according to the datasheet. In practice, the 82599 seems to also provide a copy of these registers at 0x05400. To aim for maximum compatibility, we try both addresses when reading the initial MAC address, and set both addresses when setting the MAC address.

Definition at line 63 of file intelx.h.

◆ INTELX_RAL0_ALT

#define INTELX_RAL0_ALT 0x0a200UL

Definition at line 64 of file intelx.h.

◆ INTELX_RAH0

#define INTELX_RAH0 0x05404UL

Receive Address High.

Definition at line 67 of file intelx.h.

◆ INTELX_RAH0_ALT

#define INTELX_RAH0_ALT 0x0a204UL

Definition at line 68 of file intelx.h.

◆ INTELX_RAH0_AV

#define INTELX_RAH0_AV 0x80000000UL

Address valid.

Definition at line 69 of file intelx.h.

◆ INTELX_RD

#define INTELX_RD 0x01000UL

Receive Descriptor register block.

Definition at line 72 of file intelx.h.

◆ INTELX_RXDCTL_VME

#define INTELX_RXDCTL_VME 0x40000000UL

Receive Descriptor Control Register.

Strip VLAN tag

Definition at line 75 of file intelx.h.

◆ INTELX_SRRCTL

#define INTELX_SRRCTL 0x02100UL

Split Receive Control Register.

Definition at line 78 of file intelx.h.

◆ INTELX_SRRCTL_BSIZE

#define INTELX_SRRCTL_BSIZE ( kb ) ( (kb) << 0 )

Receive buffer size.

Definition at line 79 of file intelx.h.

◆ INTELX_SRRCTL_BSIZE_DEFAULT

#define INTELX_SRRCTL_BSIZE_DEFAULT INTELX_SRRCTL_BSIZE ( 0x02 )

Definition at line 80 of file intelx.h.

◆ INTELX_SRRCTL_BSIZE_MASK

#define INTELX_SRRCTL_BSIZE_MASK INTELX_SRRCTL_BSIZE ( 0x1f )

Definition at line 81 of file intelx.h.

◆ INTELX_RDRXCTL

#define INTELX_RDRXCTL 0x02f00UL

Receive DMA Control Register.

Definition at line 84 of file intelx.h.

◆ INTELX_RDRXCTL_SECRC

#define INTELX_RDRXCTL_SECRC 0x00000001UL

Strip CRC.

Definition at line 85 of file intelx.h.

◆ INTELX_RXCTRL

#define INTELX_RXCTRL 0x03000UL

Receive Control Register.

Definition at line 88 of file intelx.h.

◆ INTELX_RXCTRL_RXEN

#define INTELX_RXCTRL_RXEN 0x00000001UL

Receive enable.

Definition at line 89 of file intelx.h.

◆ INTELX_DMATXCTL

#define INTELX_DMATXCTL 0x04a80UL

Transmit DMA Control Register.

Definition at line 92 of file intelx.h.

◆ INTELX_DMATXCTL_TE

#define INTELX_DMATXCTL_TE 0x00000001UL

Transmit enable.

Definition at line 93 of file intelx.h.

◆ INTELX_TD

#define INTELX_TD 0x06000UL

Transmit Descriptor register block.

Definition at line 96 of file intelx.h.

◆ INTELX_DCA_RXCTRL

#define INTELX_DCA_RXCTRL 0x02200UL

RX DCA Control Register.

Definition at line 99 of file intelx.h.

◆ INTELX_DCA_RXCTRL_MUST_BE_ZERO

#define INTELX_DCA_RXCTRL_MUST_BE_ZERO 0x00001000UL

Must be zero.

Definition at line 100 of file intelx.h.

◆ INTELX_HLREG0

#define INTELX_HLREG0 0x04240UL

MAC Core Control 0 Register.

Definition at line 103 of file intelx.h.

◆ INTELX_HLREG0_JUMBOEN

#define INTELX_HLREG0_JUMBOEN 0x00000004UL

Jumbo frame enable.

Definition at line 104 of file intelx.h.

◆ INTELX_MAXFRS

#define INTELX_MAXFRS 0x04268UL

Maximum Frame Size Register.

Definition at line 107 of file intelx.h.

◆ INTELX_MAXFRS_MFS

#define INTELX_MAXFRS_MFS ( len ) ( (len) << 16 )

Maximum frame size.

Definition at line 108 of file intelx.h.

◆ INTELX_MAXFRS_MFS_DEFAULT

#define INTELX_MAXFRS_MFS_DEFAULT INTELX_MAXFRS_MFS ( ETH_FRAME_LEN + 4 /* VLAN */ + 4 /* CRC */ )

Definition at line 109 of file intelx.h.

◆ INTELX_MAXFRS_MFS_MASK

#define INTELX_MAXFRS_MFS_MASK INTELX_MAXFRS_MFS ( 0xffff )

Definition at line 111 of file intelx.h.

◆ INTELX_LINKS

#define INTELX_LINKS 0x042a4UL

Link Status Register.

Definition at line 114 of file intelx.h.

◆ INTELX_LINKS_UP

#define INTELX_LINKS_UP 0x40000000UL

Link up.

Definition at line 115 of file intelx.h.

Function Documentation

◆ FILE_LICENCE()

FILE_LICENCE ( GPL2_OR_LATER_OR_UBDL )

Macros

Functions