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intel.h
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1 #ifndef _INTEL_H
2 #define _INTEL_H
3 
4 /** @file
5  *
6  * Intel 10/100/1000 network card driver
7  *
8  */
9 
10 FILE_LICENCE ( GPL2_OR_LATER_OR_UBDL );
11 
12 #include <stdint.h>
13 #include <ipxe/if_ether.h>
14 #include <ipxe/nvs.h>
15 #include <ipxe/dma.h>
16 
17 /** Intel BAR size */
18 #define INTEL_BAR_SIZE ( 128 * 1024 )
19 
20 /** A packet descriptor */
22  /** Buffer address */
24  /** Length */
26  /** Flags */
28  /** Command */
30  /** Status */
32 } __attribute__ (( packed ));
33 
34 /** Descriptor type */
35 #define INTEL_DESC_FL_DTYP( dtyp ) ( (dtyp) << 4 )
36 #define INTEL_DESC_FL_DTYP_DATA INTEL_DESC_FL_DTYP ( 0x03 )
37 
38 /** Descriptor extension */
39 #define INTEL_DESC_CMD_DEXT 0x20
40 
41 /** Report status */
42 #define INTEL_DESC_CMD_RS 0x08
43 
44 /** Insert frame checksum (CRC) */
45 #define INTEL_DESC_CMD_IFCS 0x02
46 
47 /** End of packet */
48 #define INTEL_DESC_CMD_EOP 0x01
49 
50 /** Descriptor done */
51 #define INTEL_DESC_STATUS_DD 0x00000001UL
52 
53 /** Receive error */
54 #define INTEL_DESC_STATUS_RXE 0x00000100UL
55 
56 /** Payload length */
57 #define INTEL_DESC_STATUS_PAYLEN( len ) ( (len) << 14 )
58 
59 /** Device Control Register */
60 #define INTEL_CTRL 0x00000UL
61 #define INTEL_CTRL_LRST 0x00000008UL /**< Link reset */
62 #define INTEL_CTRL_ASDE 0x00000020UL /**< Auto-speed detection */
63 #define INTEL_CTRL_SLU 0x00000040UL /**< Set link up */
64 #define INTEL_CTRL_FRCSPD 0x00000800UL /**< Force speed */
65 #define INTEL_CTRL_FRCDPLX 0x00001000UL /**< Force duplex */
66 #define INTEL_CTRL_RST 0x04000000UL /**< Device reset */
67 #define INTEL_CTRL_PHY_RST 0x80000000UL /**< PHY reset */
68 
69 /** Time to delay for device reset, in milliseconds */
70 #define INTEL_RESET_DELAY_MS 20
71 
72 /** Device Status Register */
73 #define INTEL_STATUS 0x00008UL
74 #define INTEL_STATUS_LU 0x00000002UL /**< Link up */
75 
76 /** EEPROM Read Register */
77 #define INTEL_EERD 0x00014UL
78 #define INTEL_EERD_START 0x00000001UL /**< Start read */
79 #define INTEL_EERD_DONE_SMALL 0x00000010UL /**< Read done (small EERD) */
80 #define INTEL_EERD_DONE_LARGE 0x00000002UL /**< Read done (large EERD) */
81 #define INTEL_EERD_ADDR_SHIFT_SMALL 8 /**< Address shift (small) */
82 #define INTEL_EERD_ADDR_SHIFT_LARGE 2 /**< Address shift (large) */
83 #define INTEL_EERD_DATA(value) ( (value) >> 16 ) /**< Read data */
84 
85 /** Maximum time to wait for EEPROM read, in milliseconds */
86 #define INTEL_EEPROM_MAX_WAIT_MS 100
87 
88 /** EEPROM word length */
89 #define INTEL_EEPROM_WORD_LEN_LOG2 1
90 
91 /** Minimum EEPROM size, in words */
92 #define INTEL_EEPROM_MIN_SIZE_WORDS 64
93 
94 /** Offset of MAC address within EEPROM */
95 #define INTEL_EEPROM_MAC 0x00
96 
97 /** Interrupt Cause Read Register */
98 #define INTEL_ICR 0x000c0UL
99 #define INTEL_IRQ_TXDW 0x00000001UL /**< Transmit descriptor done */
100 #define INTEL_IRQ_TXQE 0x00000002UL /**< Transmit queue empty */
101 #define INTEL_IRQ_LSC 0x00000004UL /**< Link status change */
102 #define INTEL_IRQ_RXDMT0 0x00000010UL /**< Receive queue low */
103 #define INTEL_IRQ_RXO 0x00000040UL /**< Receive overrun */
104 #define INTEL_IRQ_RXT0 0x00000080UL /**< Receive timer */
105 
106 /** Interrupt Mask Set/Read Register */
107 #define INTEL_IMS 0x000d0UL
108 
109 /** Interrupt Mask Clear Register */
110 #define INTEL_IMC 0x000d8UL
111 
112 /** Receive Control Register */
113 #define INTEL_RCTL 0x00100UL
114 #define INTEL_RCTL_EN 0x00000002UL /**< Receive enable */
115 #define INTEL_RCTL_UPE 0x00000008UL /**< Unicast promiscuous mode */
116 #define INTEL_RCTL_MPE 0x00000010UL /**< Multicast promiscuous */
117 #define INTEL_RCTL_BAM 0x00008000UL /**< Broadcast accept mode */
118 #define INTEL_RCTL_BSIZE_BSEX(bsex,bsize) \
119  ( ( (bsize) << 16 ) | ( (bsex) << 25 ) ) /**< Buffer size */
120 #define INTEL_RCTL_BSIZE_2048 INTEL_RCTL_BSIZE_BSEX ( 0, 0 )
121 #define INTEL_RCTL_BSIZE_BSEX_MASK INTEL_RCTL_BSIZE_BSEX ( 1, 3 )
122 #define INTEL_RCTL_SECRC 0x04000000UL /**< Strip CRC */
124 /** Transmit Control Register */
125 #define INTEL_TCTL 0x00400UL
126 #define INTEL_TCTL_EN 0x00000002UL /**< Transmit enable */
127 #define INTEL_TCTL_PSP 0x00000008UL /**< Pad short packets */
128 #define INTEL_TCTL_CT(x) ( (x) << 4 ) /**< Collision threshold */
129 #define INTEL_TCTL_CT_DEFAULT INTEL_TCTL_CT ( 0x0f )
130 #define INTEL_TCTL_CT_MASK INTEL_TCTL_CT ( 0xff )
131 #define INTEL_TCTL_COLD(x) ( (x) << 12 ) /**< Collision distance */
132 #define INTEL_TCTL_COLD_DEFAULT INTEL_TCTL_COLD ( 0x040 )
133 #define INTEL_TCTL_COLD_MASK INTEL_TCTL_COLD ( 0x3ff )
135 /** Packet Buffer Allocation */
136 #define INTEL_PBA 0x01000UL
138 /** Packet Buffer Size */
139 #define INTEL_PBS 0x01008UL
141 /** Receive Descriptor register block */
142 #define INTEL_RD 0x02800UL
144 /** Number of receive descriptors
145  *
146  * Minimum value is 8, since the descriptor ring length must be a
147  * multiple of 128.
148  */
149 #define INTEL_NUM_RX_DESC 16
151 /** Receive descriptor ring fill level */
152 #define INTEL_RX_FILL 8
154 /** Receive buffer length */
155 #define INTEL_RX_MAX_LEN 2048
157 /** Transmit Descriptor register block */
158 #define INTEL_TD 0x03800UL
160 /** Number of transmit descriptors
161  *
162  * Descriptor ring length must be a multiple of 16. ICH8/9/10
163  * requires a minimum of 16 TX descriptors.
164  */
165 #define INTEL_NUM_TX_DESC 16
167 /** Transmit descriptor ring maximum fill level */
168 #define INTEL_TX_FILL ( INTEL_NUM_TX_DESC - 1 )
170 /** Receive/Transmit Descriptor Base Address Low (offset) */
171 #define INTEL_xDBAL 0x00
173 /** Receive/Transmit Descriptor Base Address High (offset) */
174 #define INTEL_xDBAH 0x04
176 /** Receive/Transmit Descriptor Length (offset) */
177 #define INTEL_xDLEN 0x08
179 /** Receive/Transmit Descriptor Head (offset) */
180 #define INTEL_xDH 0x10
182 /** Receive/Transmit Descriptor Tail (offset) */
183 #define INTEL_xDT 0x18
185 /** Receive/Transmit Descriptor Control (offset) */
186 #define INTEL_xDCTL 0x28
187 #define INTEL_xDCTL_ENABLE 0x02000000UL /**< Queue enable */
189 /** Maximum time to wait for queue disable, in milliseconds */
190 #define INTEL_DISABLE_MAX_WAIT_MS 100
192 /** Receive Address Low */
193 #define INTEL_RAL0 0x05400UL
195 /** Receive Address High */
196 #define INTEL_RAH0 0x05404UL
197 #define INTEL_RAH0_AV 0x80000000UL /**< Address valid */
199 /** Future Extended NVM register 11 */
200 #define INTEL_FEXTNVM11 0x05bbcUL
201 #define INTEL_FEXTNVM11_WTF 0x00002000UL /**< Don't ask */
203 /** Receive address */
204 union intel_receive_address {
205  struct {
206  uint32_t low;
208  } __attribute__ (( packed )) reg;
210 };
211 
212 /** An Intel descriptor ring */
213 struct intel_ring {
214  /** Descriptors */
215  struct intel_descriptor *desc;
216  /** Descriptor ring DMA mapping */
217  struct dma_mapping map;
218  /** Producer index */
219  unsigned int prod;
220  /** Consumer index */
221  unsigned int cons;
223  /** Register block */
224  unsigned int reg;
225  /** Length (in bytes) */
226  size_t len;
228  /** Populate descriptor
229  *
230  * @v desc Descriptor
231  * @v addr Data buffer address
232  * @v len Length of data
233  */
234  void ( * describe ) ( struct intel_descriptor *desc, physaddr_t addr,
235  size_t len );
236 };
237 
238 /**
239  * Initialise descriptor ring
240  *
241  * @v ring Descriptor ring
242  * @v count Number of descriptors
243  * @v reg Descriptor register block
244  * @v describe Method to populate descriptor
245  */
246 static inline __attribute__ (( always_inline)) void
247 intel_init_ring ( struct intel_ring *ring, unsigned int count, unsigned int reg,
248  void ( * describe ) ( struct intel_descriptor *desc,
249  physaddr_t addr, size_t len ) ) {
250 
251  ring->len = ( count * sizeof ( ring->desc[0] ) );
252  ring->reg = reg;
253  ring->describe = describe;
254 }
255 
256 /** An Intel virtual function mailbox */
257 struct intel_mailbox {
258  /** Mailbox control register */
259  unsigned int ctrl;
260  /** Mailbox memory base */
261  unsigned int mem;
262 };
263 
264 /**
265  * Initialise mailbox
266  *
267  * @v mbox Mailbox
268  * @v ctrl Mailbox control register
269  * @v mem Mailbox memory register base
270  */
271 static inline __attribute__ (( always_inline )) void
272 intel_init_mbox ( struct intel_mailbox *mbox, unsigned int ctrl,
273  unsigned int mem ) {
274 
275  mbox->ctrl = ctrl;
276  mbox->mem = mem;
277 }
278 
279 /** An Intel network card */
280 struct intel_nic {
281  /** Registers */
282  void *regs;
283  /** DMA device */
284  struct dma_device *dma;
285  /** Port number (for multi-port devices) */
286  unsigned int port;
287  /** Flags */
288  unsigned int flags;
289  /** Forced interrupts */
290  unsigned int force_icr;
292  /** EEPROM */
293  struct nvs_device eeprom;
294  /** EEPROM done flag */
296  /** EEPROM address shift */
297  unsigned int eerd_addr_shift;
299  /** Mailbox */
300  struct intel_mailbox mbox;
302  /** Transmit descriptor ring */
303  struct intel_ring tx;
304  /** Receive descriptor ring */
305  struct intel_ring rx;
306  /** Receive I/O buffers */
308 };
309 
310 /** Driver flags */
311 enum intel_flags {
312  /** PBS/PBA errata workaround required */
313  INTEL_PBS_ERRATA = 0x0001,
314  /** VMware missing interrupt workaround required */
315  INTEL_VMWARE = 0x0002,
316  /** PHY reset is broken */
317  INTEL_NO_PHY_RST = 0x0004,
318  /** ASDE is broken */
319  INTEL_NO_ASDE = 0x0008,
320  /** Reset may cause a complete device hang */
321  INTEL_RST_HANG = 0x0010,
322 };
323 
324 /** The i219 has a seriously broken reset mechanism */
325 #define INTEL_I219 ( INTEL_NO_PHY_RST | INTEL_RST_HANG )
327 /**
328  * Dump diagnostic information
329  *
330  * @v intel Intel device
331  */
332 static inline void intel_diag ( struct intel_nic *intel ) {
334  DBGC ( intel, "INTEL %p TX %04x(%02x)/%04x(%02x) "
335  "RX %04x(%02x)/%04x(%02x)\n", intel,
336  ( intel->tx.cons & 0xffff ),
337  readl ( intel->regs + intel->tx.reg + INTEL_xDH ),
338  ( intel->tx.prod & 0xffff ),
339  readl ( intel->regs + intel->tx.reg + INTEL_xDT ),
340  ( intel->rx.cons & 0xffff ),
341  readl ( intel->regs + intel->rx.reg + INTEL_xDH ),
342  ( intel->rx.prod & 0xffff ),
343  readl ( intel->regs + intel->rx.reg + INTEL_xDT ) );
344 }
345 
346 extern void intel_describe_tx ( struct intel_descriptor *tx,
347  physaddr_t addr, size_t len );
348 extern void intel_describe_tx_adv ( struct intel_descriptor *tx,
349  physaddr_t addr, size_t len );
350 extern void intel_describe_rx ( struct intel_descriptor *rx,
351  physaddr_t addr, size_t len );
352 extern void intel_reset_ring ( struct intel_nic *intel, unsigned int reg );
353 extern int intel_create_ring ( struct intel_nic *intel,
354  struct intel_ring *ring );
355 extern void intel_destroy_ring ( struct intel_nic *intel,
356  struct intel_ring *ring );
357 extern void intel_refill_rx ( struct intel_nic *intel );
358 extern void intel_empty_rx ( struct intel_nic *intel );
359 extern int intel_transmit ( struct net_device *netdev,
360  struct io_buffer *iobuf );
361 extern void intel_poll_tx ( struct net_device *netdev );
362 extern void intel_poll_rx ( struct net_device *netdev );
363 
364 #endif /* _INTEL_H */
unsigned int force_icr
Forced interrupts.
Definition: intel.h:291
void * regs
Registers.
Definition: intel.h:283
PHY reset is broken.
Definition: intel.h:318
#define __attribute__(x)
Definition: compiler.h:10
void intel_describe_tx_adv(struct intel_descriptor *tx, physaddr_t addr, size_t len)
Populate advanced transmit descriptor.
Definition: intel.c:402
unsigned short uint16_t
Definition: stdint.h:11
DMA mappings.
#define INTEL_NUM_RX_DESC
Number of receive descriptors.
Definition: intel.h:150
static unsigned int unsigned int reg
Definition: myson.h:162
ASDE is broken.
Definition: intel.h:320
void intel_poll_tx(struct net_device *netdev)
Poll for completed packets.
Definition: intel.c:779
VMware missing interrupt workaround required.
Definition: intel.h:316
struct dma_mapping map
Descriptor ring DMA mapping.
Definition: intel.h:218
A non-volatile storage device.
Definition: nvs.h:15
void intel_describe_rx(struct intel_descriptor *rx, physaddr_t addr, size_t len)
Populate receive descriptor.
Definition: intel.c:421
uint32_t readl(volatile uint32_t *io_addr)
Read 32-bit dword from memory-mapped device.
uint32_t status
Status.
Definition: intel.h:31
struct intel_ring rx
Receive descriptor ring.
Definition: intel.h:306
#define DBGC(...)
Definition: compiler.h:505
#define INTEL_xDT
Receive/Transmit Descriptor Tail (offset)
Definition: intel.h:184
size_t len
Length (in bytes)
Definition: intel.h:227
unsigned long long uint64_t
Definition: stdint.h:13
Non-volatile storage.
PBS/PBA errata workaround required.
Definition: intel.h:314
An Intel descriptor ring.
Definition: intel.h:214
static void intel_init_ring(struct intel_ring *ring, unsigned int count, unsigned int reg, void(*describe)(struct intel_descriptor *desc, physaddr_t addr, size_t len))
Initialise descriptor ring.
Definition: intel.h:248
uint8_t raw[ETH_ALEN]
Definition: intel.h:210
unsigned int cons
Consumer index.
Definition: intel.h:222
unsigned int reg
Register block.
Definition: intel.h:225
eeprom
Definition: 3c90x.h:232
struct intel_receive_address::@64 reg
unsigned int port
Port number (for multi-port devices)
Definition: intel.h:287
#define INTEL_xDH
Receive/Transmit Descriptor Head (offset)
Definition: intel.h:181
static void intel_init_mbox(struct intel_mailbox *mbox, unsigned int ctrl, unsigned int mem)
Initialise mailbox.
Definition: intel.h:273
int intel_create_ring(struct intel_nic *intel, struct intel_ring *ring)
Create descriptor ring.
Definition: intel.c:499
uint32_t eerd_done
EEPROM done flag.
Definition: intel.h:296
static struct net_device * netdev
Definition: gdbudp.c:52
struct io_buffer * rx_iobuf[INTEL_NUM_RX_DESC]
Receive I/O buffers.
Definition: intel.h:308
Definition: golan.c:120
uint64_t address
Buffer address.
Definition: intel.h:23
static void intel_diag(struct intel_nic *intel)
Dump diagnostic information.
Definition: intel.h:333
int intel_transmit(struct net_device *netdev, struct io_buffer *iobuf)
Transmit packet.
Definition: intel.c:740
void intel_refill_rx(struct intel_nic *intel)
Refill receive descriptor ring.
Definition: intel.c:568
FILE_LICENCE(GPL2_OR_LATER_OR_UBDL)
void intel_destroy_ring(struct intel_nic *intel, struct intel_ring *ring)
Destroy descriptor ring.
Definition: intel.c:551
An Intel virtual function mailbox.
Definition: intel.h:258
A network device.
Definition: netdevice.h:352
u32 addr
Definition: sky2.h:8
unsigned char uint8_t
Definition: stdint.h:10
#define ETH_ALEN
Definition: if_ether.h:8
unsigned int uint32_t
Definition: stdint.h:12
uint16_t length
Length.
Definition: intel.h:25
void intel_poll_rx(struct net_device *netdev)
Poll for received packets.
Definition: intel.c:808
void intel_reset_ring(struct intel_nic *intel, unsigned int reg)
Reset descriptor ring.
Definition: intel.c:475
void(* describe)(struct intel_descriptor *desc, physaddr_t addr, size_t len)
Populate descriptor.
Definition: intel.h:235
unsigned int mem
Mailbox memory base.
Definition: intel.h:262
unsigned long physaddr_t
Definition: stdint.h:20
struct dma_device * dma
DMA device.
Definition: intel.h:285
unsigned int ctrl
Mailbox control register.
Definition: intel.h:260
A packet descriptor.
Definition: intel.h:21
uint32_t len
Length.
Definition: ena.h:14
unsigned int prod
Producer index.
Definition: intel.h:220
uint16_t count
Number of entries.
Definition: ena.h:22
void intel_empty_rx(struct intel_nic *intel)
Discard unused receive I/O buffers.
Definition: intel.c:618
u8 rx[WPA_TKIP_MIC_KEY_LEN]
MIC key for packets from the AP.
Definition: wpa.h:234
u8 ctrl
Definition: sky2.h:10
An Intel network card.
Definition: intel.h:281
struct intel_descriptor * desc
Descriptors.
Definition: intel.h:216
struct intel_ring tx
Transmit descriptor ring.
Definition: intel.h:304
Receive address.
Definition: intel.h:205
Reset may cause a complete device hang.
Definition: intel.h:322
uint8_t command
Command.
Definition: intel.h:29
unsigned int eerd_addr_shift
EEPROM address shift.
Definition: intel.h:298
intel_flags
Driver flags.
Definition: intel.h:312
unsigned int flags
Flags.
Definition: intel.h:289
A DMA mapping.
Definition: dma.h:32
uint8_t flags
Flags.
Definition: intel.h:27
u8 tx[WPA_TKIP_MIC_KEY_LEN]
MIC key for packets to the AP.
Definition: wpa.h:237
A DMA-capable device.
Definition: dma.h:47
void intel_describe_tx(struct intel_descriptor *tx, physaddr_t addr, size_t len)
Populate transmit descriptor.
Definition: intel.c:383
A persistent I/O buffer.
Definition: iobuf.h:33