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intel.h
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1 #ifndef _INTEL_H
2 #define _INTEL_H
3 
4 /** @file
5  *
6  * Intel 10/100/1000 network card driver
7  *
8  */
9 
10 FILE_LICENCE ( GPL2_OR_LATER_OR_UBDL );
11 
12 #include <stdint.h>
13 #include <ipxe/if_ether.h>
14 #include <ipxe/nvs.h>
15 
16 /** Intel BAR size */
17 #define INTEL_BAR_SIZE ( 128 * 1024 )
18 
19 /** A packet descriptor */
21  /** Buffer address */
23  /** Length */
25  /** Flags */
27  /** Command */
29  /** Status */
31 } __attribute__ (( packed ));
32 
33 /** Descriptor type */
34 #define INTEL_DESC_FL_DTYP( dtyp ) ( (dtyp) << 4 )
35 #define INTEL_DESC_FL_DTYP_DATA INTEL_DESC_FL_DTYP ( 0x03 )
36 
37 /** Descriptor extension */
38 #define INTEL_DESC_CMD_DEXT 0x20
39 
40 /** Report status */
41 #define INTEL_DESC_CMD_RS 0x08
42 
43 /** Insert frame checksum (CRC) */
44 #define INTEL_DESC_CMD_IFCS 0x02
45 
46 /** End of packet */
47 #define INTEL_DESC_CMD_EOP 0x01
48 
49 /** Descriptor done */
50 #define INTEL_DESC_STATUS_DD 0x00000001UL
51 
52 /** Receive error */
53 #define INTEL_DESC_STATUS_RXE 0x00000100UL
54 
55 /** Payload length */
56 #define INTEL_DESC_STATUS_PAYLEN( len ) ( (len) << 14 )
57 
58 /** Device Control Register */
59 #define INTEL_CTRL 0x00000UL
60 #define INTEL_CTRL_LRST 0x00000008UL /**< Link reset */
61 #define INTEL_CTRL_ASDE 0x00000020UL /**< Auto-speed detection */
62 #define INTEL_CTRL_SLU 0x00000040UL /**< Set link up */
63 #define INTEL_CTRL_FRCSPD 0x00000800UL /**< Force speed */
64 #define INTEL_CTRL_FRCDPLX 0x00001000UL /**< Force duplex */
65 #define INTEL_CTRL_RST 0x04000000UL /**< Device reset */
66 #define INTEL_CTRL_PHY_RST 0x80000000UL /**< PHY reset */
67 
68 /** Time to delay for device reset, in milliseconds */
69 #define INTEL_RESET_DELAY_MS 20
70 
71 /** Device Status Register */
72 #define INTEL_STATUS 0x00008UL
73 #define INTEL_STATUS_LU 0x00000002UL /**< Link up */
74 
75 /** EEPROM Read Register */
76 #define INTEL_EERD 0x00014UL
77 #define INTEL_EERD_START 0x00000001UL /**< Start read */
78 #define INTEL_EERD_DONE_SMALL 0x00000010UL /**< Read done (small EERD) */
79 #define INTEL_EERD_DONE_LARGE 0x00000002UL /**< Read done (large EERD) */
80 #define INTEL_EERD_ADDR_SHIFT_SMALL 8 /**< Address shift (small) */
81 #define INTEL_EERD_ADDR_SHIFT_LARGE 2 /**< Address shift (large) */
82 #define INTEL_EERD_DATA(value) ( (value) >> 16 ) /**< Read data */
83 
84 /** Maximum time to wait for EEPROM read, in milliseconds */
85 #define INTEL_EEPROM_MAX_WAIT_MS 100
86 
87 /** EEPROM word length */
88 #define INTEL_EEPROM_WORD_LEN_LOG2 1
89 
90 /** Minimum EEPROM size, in words */
91 #define INTEL_EEPROM_MIN_SIZE_WORDS 64
92 
93 /** Offset of MAC address within EEPROM */
94 #define INTEL_EEPROM_MAC 0x00
95 
96 /** Interrupt Cause Read Register */
97 #define INTEL_ICR 0x000c0UL
98 #define INTEL_IRQ_TXDW 0x00000001UL /**< Transmit descriptor done */
99 #define INTEL_IRQ_TXQE 0x00000002UL /**< Transmit queue empty */
100 #define INTEL_IRQ_LSC 0x00000004UL /**< Link status change */
101 #define INTEL_IRQ_RXDMT0 0x00000010UL /**< Receive queue low */
102 #define INTEL_IRQ_RXO 0x00000040UL /**< Receive overrun */
103 #define INTEL_IRQ_RXT0 0x00000080UL /**< Receive timer */
104 
105 /** Interrupt Mask Set/Read Register */
106 #define INTEL_IMS 0x000d0UL
107 
108 /** Interrupt Mask Clear Register */
109 #define INTEL_IMC 0x000d8UL
110 
111 /** Receive Control Register */
112 #define INTEL_RCTL 0x00100UL
113 #define INTEL_RCTL_EN 0x00000002UL /**< Receive enable */
114 #define INTEL_RCTL_UPE 0x00000008UL /**< Unicast promiscuous mode */
115 #define INTEL_RCTL_MPE 0x00000010UL /**< Multicast promiscuous */
116 #define INTEL_RCTL_BAM 0x00008000UL /**< Broadcast accept mode */
117 #define INTEL_RCTL_BSIZE_BSEX(bsex,bsize) \
118  ( ( (bsize) << 16 ) | ( (bsex) << 25 ) ) /**< Buffer size */
119 #define INTEL_RCTL_BSIZE_2048 INTEL_RCTL_BSIZE_BSEX ( 0, 0 )
120 #define INTEL_RCTL_BSIZE_BSEX_MASK INTEL_RCTL_BSIZE_BSEX ( 1, 3 )
121 #define INTEL_RCTL_SECRC 0x04000000UL /**< Strip CRC */
123 /** Transmit Control Register */
124 #define INTEL_TCTL 0x00400UL
125 #define INTEL_TCTL_EN 0x00000002UL /**< Transmit enable */
126 #define INTEL_TCTL_PSP 0x00000008UL /**< Pad short packets */
127 #define INTEL_TCTL_CT(x) ( (x) << 4 ) /**< Collision threshold */
128 #define INTEL_TCTL_CT_DEFAULT INTEL_TCTL_CT ( 0x0f )
129 #define INTEL_TCTL_CT_MASK INTEL_TCTL_CT ( 0xff )
130 #define INTEL_TCTL_COLD(x) ( (x) << 12 ) /**< Collision distance */
131 #define INTEL_TCTL_COLD_DEFAULT INTEL_TCTL_COLD ( 0x040 )
132 #define INTEL_TCTL_COLD_MASK INTEL_TCTL_COLD ( 0x3ff )
134 /** Packet Buffer Allocation */
135 #define INTEL_PBA 0x01000UL
137 /** Packet Buffer Size */
138 #define INTEL_PBS 0x01008UL
140 /** Receive Descriptor register block */
141 #define INTEL_RD 0x02800UL
143 /** Number of receive descriptors
144  *
145  * Minimum value is 8, since the descriptor ring length must be a
146  * multiple of 128.
147  */
148 #define INTEL_NUM_RX_DESC 16
150 /** Receive descriptor ring fill level */
151 #define INTEL_RX_FILL 8
153 /** Receive buffer length */
154 #define INTEL_RX_MAX_LEN 2048
156 /** Transmit Descriptor register block */
157 #define INTEL_TD 0x03800UL
159 /** Number of transmit descriptors
160  *
161  * Descriptor ring length must be a multiple of 16. ICH8/9/10
162  * requires a minimum of 16 TX descriptors.
163  */
164 #define INTEL_NUM_TX_DESC 16
166 /** Transmit descriptor ring maximum fill level */
167 #define INTEL_TX_FILL ( INTEL_NUM_TX_DESC - 1 )
169 /** Receive/Transmit Descriptor Base Address Low (offset) */
170 #define INTEL_xDBAL 0x00
172 /** Receive/Transmit Descriptor Base Address High (offset) */
173 #define INTEL_xDBAH 0x04
175 /** Receive/Transmit Descriptor Length (offset) */
176 #define INTEL_xDLEN 0x08
178 /** Receive/Transmit Descriptor Head (offset) */
179 #define INTEL_xDH 0x10
181 /** Receive/Transmit Descriptor Tail (offset) */
182 #define INTEL_xDT 0x18
184 /** Receive/Transmit Descriptor Control (offset) */
185 #define INTEL_xDCTL 0x28
186 #define INTEL_xDCTL_ENABLE 0x02000000UL /**< Queue enable */
188 /** Maximum time to wait for queue disable, in milliseconds */
189 #define INTEL_DISABLE_MAX_WAIT_MS 100
191 /** Receive Address Low */
192 #define INTEL_RAL0 0x05400UL
194 /** Receive Address High */
195 #define INTEL_RAH0 0x05404UL
196 #define INTEL_RAH0_AV 0x80000000UL /**< Address valid */
198 /** Future Extended NVM register 11 */
199 #define INTEL_FEXTNVM11 0x05bbcUL
200 #define INTEL_FEXTNVM11_WTF 0x00002000UL /**< Don't ask */
202 /** Receive address */
203 union intel_receive_address {
204  struct {
205  uint32_t low;
207  } __attribute__ (( packed )) reg;
209 };
210 
211 /** An Intel descriptor ring */
212 struct intel_ring {
213  /** Descriptors */
214  struct intel_descriptor *desc;
215  /** Producer index */
216  unsigned int prod;
217  /** Consumer index */
218  unsigned int cons;
220  /** Register block */
221  unsigned int reg;
222  /** Length (in bytes) */
223  size_t len;
225  /** Populate descriptor
226  *
227  * @v desc Descriptor
228  * @v addr Data buffer address
229  * @v len Length of data
230  */
231  void ( * describe ) ( struct intel_descriptor *desc, physaddr_t addr,
232  size_t len );
233 };
234 
235 /**
236  * Initialise descriptor ring
237  *
238  * @v ring Descriptor ring
239  * @v count Number of descriptors
240  * @v reg Descriptor register block
241  * @v describe Method to populate descriptor
242  */
243 static inline __attribute__ (( always_inline)) void
244 intel_init_ring ( struct intel_ring *ring, unsigned int count, unsigned int reg,
245  void ( * describe ) ( struct intel_descriptor *desc,
246  physaddr_t addr, size_t len ) ) {
247 
248  ring->len = ( count * sizeof ( ring->desc[0] ) );
249  ring->reg = reg;
250  ring->describe = describe;
251 }
252 
253 /** An Intel virtual function mailbox */
254 struct intel_mailbox {
255  /** Mailbox control register */
256  unsigned int ctrl;
257  /** Mailbox memory base */
258  unsigned int mem;
259 };
260 
261 /**
262  * Initialise mailbox
263  *
264  * @v mbox Mailbox
265  * @v ctrl Mailbox control register
266  * @v mem Mailbox memory register base
267  */
268 static inline __attribute__ (( always_inline )) void
269 intel_init_mbox ( struct intel_mailbox *mbox, unsigned int ctrl,
270  unsigned int mem ) {
272  mbox->ctrl = ctrl;
273  mbox->mem = mem;
274 }
275 
276 /** An Intel network card */
277 struct intel_nic {
278  /** Registers */
279  void *regs;
280  /** Port number (for multi-port devices) */
281  unsigned int port;
282  /** Flags */
283  unsigned int flags;
284  /** Forced interrupts */
285  unsigned int force_icr;
287  /** EEPROM */
288  struct nvs_device eeprom;
289  /** EEPROM done flag */
291  /** EEPROM address shift */
292  unsigned int eerd_addr_shift;
294  /** Mailbox */
295  struct intel_mailbox mbox;
297  /** Transmit descriptor ring */
298  struct intel_ring tx;
299  /** Receive descriptor ring */
300  struct intel_ring rx;
301  /** Receive I/O buffers */
303 };
304 
305 /** Driver flags */
306 enum intel_flags {
307  /** PBS/PBA errata workaround required */
308  INTEL_PBS_ERRATA = 0x0001,
309  /** VMware missing interrupt workaround required */
310  INTEL_VMWARE = 0x0002,
311  /** PHY reset is broken */
312  INTEL_NO_PHY_RST = 0x0004,
313  /** ASDE is broken */
314  INTEL_NO_ASDE = 0x0008,
315  /** Reset may cause a complete device hang */
316  INTEL_RST_HANG = 0x0010,
317 };
318 
319 /** The i219 has a seriously broken reset mechanism */
320 #define INTEL_I219 ( INTEL_NO_PHY_RST | INTEL_RST_HANG )
322 /**
323  * Dump diagnostic information
324  *
325  * @v intel Intel device
326  */
327 static inline void intel_diag ( struct intel_nic *intel ) {
329  DBGC ( intel, "INTEL %p TX %04x(%02x)/%04x(%02x) "
330  "RX %04x(%02x)/%04x(%02x)\n", intel,
331  ( intel->tx.cons & 0xffff ),
332  readl ( intel->regs + intel->tx.reg + INTEL_xDH ),
333  ( intel->tx.prod & 0xffff ),
334  readl ( intel->regs + intel->tx.reg + INTEL_xDT ),
335  ( intel->rx.cons & 0xffff ),
336  readl ( intel->regs + intel->rx.reg + INTEL_xDH ),
337  ( intel->rx.prod & 0xffff ),
338  readl ( intel->regs + intel->rx.reg + INTEL_xDT ) );
339 }
340 
341 extern void intel_describe_tx ( struct intel_descriptor *tx,
342  physaddr_t addr, size_t len );
343 extern void intel_describe_tx_adv ( struct intel_descriptor *tx,
344  physaddr_t addr, size_t len );
345 extern void intel_describe_rx ( struct intel_descriptor *rx,
346  physaddr_t addr, size_t len );
347 extern void intel_reset_ring ( struct intel_nic *intel, unsigned int reg );
348 extern int intel_create_ring ( struct intel_nic *intel,
349  struct intel_ring *ring );
350 extern void intel_destroy_ring ( struct intel_nic *intel,
351  struct intel_ring *ring );
352 extern void intel_refill_rx ( struct intel_nic *intel );
353 extern void intel_empty_rx ( struct intel_nic *intel );
354 extern int intel_transmit ( struct net_device *netdev,
355  struct io_buffer *iobuf );
356 extern void intel_poll_tx ( struct net_device *netdev );
357 extern void intel_poll_rx ( struct net_device *netdev );
358 
359 #endif /* _INTEL_H */
unsigned int force_icr
Forced interrupts.
Definition: intel.h:286
void * regs
Registers.
Definition: intel.h:280
PHY reset is broken.
Definition: intel.h:313
void intel_describe_tx_adv(struct intel_descriptor *tx, physaddr_t addr, size_t len)
Populate advanced transmit descriptor.
Definition: intel.c:402
static unsigned int unsigned int void(* describe)(struct intel_descriptor *desc, physaddr_t addr, size_t len))
Definition: intel.h:246
unsigned short uint16_t
Definition: stdint.h:11
static unsigned int count
Definition: intel.h:245
#define INTEL_NUM_RX_DESC
Number of receive descriptors.
Definition: intel.h:149
ASDE is broken.
Definition: intel.h:315
void intel_poll_tx(struct net_device *netdev)
Poll for completed packets.
Definition: intel.c:781
VMware missing interrupt workaround required.
Definition: intel.h:311
A non-volatile storage device.
Definition: nvs.h:15
void intel_describe_rx(struct intel_descriptor *rx, physaddr_t addr, size_t len)
Populate receive descriptor.
Definition: intel.c:421
uint32_t readl(volatile uint32_t *io_addr)
Read 32-bit dword from memory-mapped device.
uint32_t status
Status.
Definition: intel.h:30
struct intel_ring rx
Receive descriptor ring.
Definition: intel.h:301
#define DBGC(...)
Definition: compiler.h:505
#define INTEL_xDT
Receive/Transmit Descriptor Tail (offset)
Definition: intel.h:183
size_t len
Length (in bytes)
Definition: intel.h:224
unsigned long long uint64_t
Definition: stdint.h:13
union intel_receive_address __attribute__
Non-volatile storage.
PBS/PBA errata workaround required.
Definition: intel.h:309
An Intel descriptor ring.
Definition: intel.h:213
uint8_t raw[ETH_ALEN]
Definition: intel.h:209
unsigned int cons
Consumer index.
Definition: intel.h:219
unsigned int reg
Register block.
Definition: intel.h:222
eeprom
Definition: 3c90x.h:232
unsigned int port
Port number (for multi-port devices)
Definition: intel.h:282
#define INTEL_xDH
Receive/Transmit Descriptor Head (offset)
Definition: intel.h:180
int intel_create_ring(struct intel_nic *intel, struct intel_ring *ring)
Create descriptor ring.
Definition: intel.c:499
uint32_t eerd_done
EEPROM done flag.
Definition: intel.h:291
static struct net_device * netdev
Definition: gdbudp.c:52
struct io_buffer * rx_iobuf[INTEL_NUM_RX_DESC]
Receive I/O buffers.
Definition: intel.h:303
Definition: golan.c:120
uint64_t address
Buffer address.
Definition: intel.h:22
uint32_t rx
Maximum number of receive queues.
Definition: intelvf.h:16
static void intel_diag(struct intel_nic *intel)
Dump diagnostic information.
Definition: intel.h:328
int intel_transmit(struct net_device *netdev, struct io_buffer *iobuf)
Transmit packet.
Definition: intel.c:740
void intel_refill_rx(struct intel_nic *intel)
Refill receive descriptor ring.
Definition: intel.c:567
FILE_LICENCE(GPL2_OR_LATER_OR_UBDL)
void intel_destroy_ring(struct intel_nic *intel, struct intel_ring *ring)
Destroy descriptor ring.
Definition: intel.c:550
uint32_t tx
Maximum number of transmit queues.
Definition: intelvf.h:14
static unsigned int unsigned int reg
Definition: intel.h:245
An Intel virtual function mailbox.
Definition: intel.h:255
A network device.
Definition: netdevice.h:348
u32 addr
Definition: sky2.h:8
unsigned char uint8_t
Definition: stdint.h:10
#define ETH_ALEN
Definition: if_ether.h:8
unsigned int uint32_t
Definition: stdint.h:12
uint16_t length
Length.
Definition: intel.h:24
void intel_poll_rx(struct net_device *netdev)
Poll for received packets.
Definition: intel.c:810
void intel_reset_ring(struct intel_nic *intel, unsigned int reg)
Reset descriptor ring.
Definition: intel.c:475
void(* describe)(struct intel_descriptor *desc, physaddr_t addr, size_t len)
Populate descriptor.
Definition: intel.h:232
unsigned int mem
Mailbox memory base.
Definition: intel.h:259
unsigned long physaddr_t
Definition: stdint.h:20
unsigned int ctrl
Mailbox control register.
Definition: intel.h:257
A packet descriptor.
Definition: intel.h:20
uint32_t len
Length.
Definition: ena.h:14
static unsigned int ctrl
Definition: intel.h:270
struct intel_receive_address::@58 __attribute__((packed)) reg
unsigned int prod
Producer index.
Definition: intel.h:217
void intel_empty_rx(struct intel_nic *intel)
Discard unused receive I/O buffers.
Definition: intel.c:619
An Intel network card.
Definition: intel.h:278
struct intel_descriptor * desc
Descriptors.
Definition: intel.h:215
struct intel_ring tx
Transmit descriptor ring.
Definition: intel.h:299
Receive address.
Definition: intel.h:204
Reset may cause a complete device hang.
Definition: intel.h:317
uint8_t command
Command.
Definition: intel.h:28
unsigned int eerd_addr_shift
EEPROM address shift.
Definition: intel.h:293
intel_flags
Driver flags.
Definition: intel.h:307
unsigned int flags
Flags.
Definition: intel.h:284
uint8_t flags
Flags.
Definition: intel.h:26
void intel_describe_tx(struct intel_descriptor *tx, physaddr_t addr, size_t len)
Populate transmit descriptor.
Definition: intel.c:383
static unsigned int unsigned int mem
Definition: intel.h:271
A persistent I/O buffer.
Definition: iobuf.h:32