iPXE
Data Structures | Macros | Enumerations | Functions | Variables
jme.h File Reference

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Data Structures

struct  txdesc
 
struct  rxdesc
 
struct  jme_ring
 
struct  jme_adapter
 

Macros

#define __JME_H_INCLUDED__
 
#define PCI_VENDOR_ID_JMICRON   0x197b
 
#define PCI_DEVICE_ID_JMICRON_JMC250   0x0250
 
#define PCI_DEVICE_ID_JMICRON_JMC260   0x0260
 
#define PCI_DCSR_MRRS   0x59
 
#define PCI_DCSR_MRRS_MASK   0x70
 
#define RING_DESC_ALIGN   16 /* Descriptor alignment */
 
#define TX_DESC_SIZE   16
 
#define TXDESC_MSS_SHIFT   2
 
#define RX_DESC_SIZE   16
 
#define RX_BUF_DMA_ALIGN   8
 
#define RX_PREPAD_SIZE   10
 
#define ETH_CRC_LEN   2
 
#define RX_VLANHDR_LEN   2
 
#define RX_EXTRA_LEN
 
#define FIXED_MTU   1500
 
#define RX_ALLOC_LEN   (FIXED_MTU + RX_EXTRA_LEN)
 
#define JME_TX_DISABLE_TIMEOUT   10 /* 10 msec */
 
#define JME_RX_DISABLE_TIMEOUT   10 /* 10 msec */
 
#define WAKEUP_FRAME_NR   8
 
#define WAKEUP_FRAME_MASK_DWNR   4
 
#define JME_PHY_TIMEOUT   100 /* 100 msec */
 
#define JME_PHY_REG_NR   32
 
#define JME_SPDRSV_TIMEOUT   500 /* 500 us */
 
#define JME_EEPROM_RELOAD_TIMEOUT   2000 /* 2000 msec */
 
#define JME_SMB_BUSY_TIMEOUT   20 /* 20 msec */
 
#define JME_SMB_LEN   256
 
#define JME_EEPROM_MAGIC   0x250
 

Enumerations

enum  pci_dcsr_mrrs_vals {
  MRRS_128B = 0x00, MRRS_256B = 0x10, MRRS_512B = 0x20, MRRS_1024B = 0x30,
  MRRS_2048B = 0x40, MRRS_4096B = 0x50
}
 
enum  jme_txdesc_flags_bits {
  TXFLAG_OWN = 0x80, TXFLAG_INT = 0x40, TXFLAG_64BIT = 0x20, TXFLAG_TCPCS = 0x10,
  TXFLAG_UDPCS = 0x08, TXFLAG_IPCS = 0x04, TXFLAG_LSEN = 0x02, TXFLAG_TAGON = 0x01
}
 
enum  jme_txwbdesc_flags_bits {
  TXWBFLAG_OWN = 0x80, TXWBFLAG_INT = 0x40, TXWBFLAG_TMOUT = 0x20, TXWBFLAG_TRYOUT = 0x10,
  TXWBFLAG_COL = 0x08, TXWBFLAG_ALLERR
}
 
enum  jme_rxdesc_flags_bits { RXFLAG_OWN = 0x80, RXFLAG_INT = 0x40, RXFLAG_64BIT = 0x20 }
 
enum  jme_rxwbdesc_flags_bits {
  RXWBFLAG_OWN = 0x8000, RXWBFLAG_INT = 0x4000, RXWBFLAG_MF = 0x2000, RXWBFLAG_64BIT = 0x2000,
  RXWBFLAG_TCPON = 0x1000, RXWBFLAG_UDPON = 0x0800, RXWBFLAG_IPCS = 0x0400, RXWBFLAG_TCPCS = 0x0200,
  RXWBFLAG_UDPCS = 0x0100, RXWBFLAG_TAGON = 0x0080, RXWBFLAG_IPV4 = 0x0040, RXWBFLAG_IPV6 = 0x0020,
  RXWBFLAG_PAUSE = 0x0010, RXWBFLAG_MAGIC = 0x0008, RXWBFLAG_WAKEUP = 0x0004, RXWBFLAG_DEST = 0x0003,
  RXWBFLAG_DEST_UNI = 0x0001, RXWBFLAG_DEST_MUL = 0x0002, RXWBFLAG_DEST_BRO = 0x0003
}
 
enum  jme_rxwbdesc_desccnt_mask { RXWBDCNT_WBCPL = 0x80, RXWBDCNT_DCNT = 0x7F }
 
enum  jme_rxwbdesc_errstat_bits {
  RXWBERR_LIMIT = 0x80, RXWBERR_MIIER = 0x40, RXWBERR_NIBON = 0x20, RXWBERR_COLON = 0x10,
  RXWBERR_ABORT = 0x08, RXWBERR_SHORT = 0x04, RXWBERR_OVERUN = 0x02, RXWBERR_CRCERR = 0x01,
  RXWBERR_ALLERR = 0xFF
}
 
enum  jme_iomap_regs_value { JME_REGS_SIZE = 0x1000 }
 
enum  jme_iomap_offsets { JME_MAC = 0x0000, JME_PHY = 0x0400, JME_MISC = 0x0800, JME_RSS = 0x0C00 }
 
enum  jme_iomap_lens { JME_MAC_LEN = 0x80, JME_PHY_LEN = 0x58, JME_MISC_LEN = 0x98, JME_RSS_LEN = 0xFF }
 
enum  jme_iomap_regs {
  JME_TXCS = JME_MAC | 0x00, JME_TXDBA_LO = JME_MAC | 0x04, JME_TXDBA_HI = JME_MAC | 0x08, JME_TXQDC = JME_MAC | 0x0C,
  JME_TXNDA = JME_MAC | 0x10, JME_TXMCS = JME_MAC | 0x14, JME_TXPFC = JME_MAC | 0x18, JME_TXTRHD = JME_MAC | 0x1C,
  JME_RXCS = JME_MAC | 0x20, JME_RXDBA_LO = JME_MAC | 0x24, JME_RXDBA_HI = JME_MAC | 0x28, JME_RXQDC = JME_MAC | 0x2C,
  JME_RXNDA = JME_MAC | 0x30, JME_RXMCS = JME_MAC | 0x34, JME_RXUMA_LO = JME_MAC | 0x38, JME_RXUMA_HI = JME_MAC | 0x3C,
  JME_RXMCHT_LO = JME_MAC | 0x40, JME_RXMCHT_HI = JME_MAC | 0x44, JME_WFODP = JME_MAC | 0x48, JME_WFOI = JME_MAC | 0x4C,
  JME_SMI = JME_MAC | 0x50, JME_GHC = JME_MAC | 0x54, JME_PMCS = JME_MAC | 0x60, JME_PHY_CS = JME_PHY | 0x28,
  JME_PHY_LINK = JME_PHY | 0x30, JME_SMBCSR = JME_PHY | 0x40, JME_SMBINTF = JME_PHY | 0x44, JME_TMCSR = JME_MISC | 0x00,
  JME_GPREG0 = JME_MISC | 0x08, JME_GPREG1 = JME_MISC | 0x0C, JME_IEVE = JME_MISC | 0x20, JME_IREQ = JME_MISC | 0x24,
  JME_IENS = JME_MISC | 0x28, JME_IENC = JME_MISC | 0x2C, JME_PCCRX0 = JME_MISC | 0x30, JME_PCCTX = JME_MISC | 0x40,
  JME_CHIPMODE = JME_MISC | 0x44, JME_SHBA_HI = JME_MISC | 0x48, JME_SHBA_LO = JME_MISC | 0x4C, JME_TIMER1 = JME_MISC | 0x70,
  JME_TIMER2 = JME_MISC | 0x74, JME_APMC = JME_MISC | 0x7C, JME_PCCSRX0 = JME_MISC | 0x80
}
 
enum  jme_txcs_bits {
  TXCS_QUEUE7S = 0x00008000, TXCS_QUEUE6S = 0x00004000, TXCS_QUEUE5S = 0x00002000, TXCS_QUEUE4S = 0x00001000,
  TXCS_QUEUE3S = 0x00000800, TXCS_QUEUE2S = 0x00000400, TXCS_QUEUE1S = 0x00000200, TXCS_QUEUE0S = 0x00000100,
  TXCS_FIFOTH = 0x000000C0, TXCS_DMASIZE = 0x00000030, TXCS_BURST = 0x00000004, TXCS_ENABLE = 0x00000001
}
 
enum  jme_txcs_value {
  TXCS_FIFOTH_16QW = 0x000000C0, TXCS_FIFOTH_12QW = 0x00000080, TXCS_FIFOTH_8QW = 0x00000040, TXCS_FIFOTH_4QW = 0x00000000,
  TXCS_DMASIZE_64B = 0x00000000, TXCS_DMASIZE_128B = 0x00000010, TXCS_DMASIZE_256B = 0x00000020, TXCS_DMASIZE_512B = 0x00000030,
  TXCS_SELECT_QUEUE0 = 0x00000000, TXCS_SELECT_QUEUE1 = 0x00010000, TXCS_SELECT_QUEUE2 = 0x00020000, TXCS_SELECT_QUEUE3 = 0x00030000,
  TXCS_SELECT_QUEUE4 = 0x00040000, TXCS_SELECT_QUEUE5 = 0x00050000, TXCS_SELECT_QUEUE6 = 0x00060000, TXCS_SELECT_QUEUE7 = 0x00070000,
  TXCS_DEFAULT
}
 
enum  jme_txmcs_bit_masks {
  TXMCS_IFG2 = 0xC0000000, TXMCS_IFG1 = 0x30000000, TXMCS_TTHOLD = 0x00000300, TXMCS_FBURST = 0x00000080,
  TXMCS_CARRIEREXT = 0x00000040, TXMCS_DEFER = 0x00000020, TXMCS_BACKOFF = 0x00000010, TXMCS_CARRIERSENSE = 0x00000008,
  TXMCS_COLLISION = 0x00000004, TXMCS_CRC = 0x00000002, TXMCS_PADDING = 0x00000001
}
 
enum  jme_txmcs_values {
  TXMCS_IFG2_6_4 = 0x00000000, TXMCS_IFG2_8_5 = 0x40000000, TXMCS_IFG2_10_6 = 0x80000000, TXMCS_IFG2_12_7 = 0xC0000000,
  TXMCS_IFG1_8_4 = 0x00000000, TXMCS_IFG1_12_6 = 0x10000000, TXMCS_IFG1_16_8 = 0x20000000, TXMCS_IFG1_20_10 = 0x30000000,
  TXMCS_TTHOLD_1_8 = 0x00000000, TXMCS_TTHOLD_1_4 = 0x00000100, TXMCS_TTHOLD_1_2 = 0x00000200, TXMCS_TTHOLD_FULL = 0x00000300,
  TXMCS_DEFAULT
}
 
enum  jme_txpfc_bits_masks { TXPFC_VLAN_TAG = 0xFFFF0000, TXPFC_VLAN_EN = 0x00008000, TXPFC_PF_EN = 0x00000001 }
 
enum  jme_txtrhd_bits_masks { TXTRHD_TXPEN = 0x80000000, TXTRHD_TXP = 0x7FFFFF00, TXTRHD_TXREN = 0x00000080, TXTRHD_TXRL = 0x0000007F }
 
enum  jme_txtrhd_shifts { TXTRHD_TXP_SHIFT = 8, TXTRHD_TXRL_SHIFT = 0 }
 
enum  jme_rxcs_bit_masks {
  RXCS_FIFOTHTP = 0x30000000, RXCS_FIFOTHNP = 0x0C000000, RXCS_DMAREQSZ = 0x03000000, RXCS_QUEUESEL = 0x00030000,
  RXCS_RETRYGAP = 0x0000F000, RXCS_RETRYCNT = 0x00000F00, RXCS_WAKEUP = 0x00000040, RXCS_MAGIC = 0x00000020,
  RXCS_SHORT = 0x00000010, RXCS_ABORT = 0x00000008, RXCS_QST = 0x00000004, RXCS_SUSPEND = 0x00000002,
  RXCS_ENABLE = 0x00000001
}
 
enum  jme_rxcs_values {
  RXCS_FIFOTHTP_16T = 0x00000000, RXCS_FIFOTHTP_32T = 0x10000000, RXCS_FIFOTHTP_64T = 0x20000000, RXCS_FIFOTHTP_128T = 0x30000000,
  RXCS_FIFOTHNP_16QW = 0x00000000, RXCS_FIFOTHNP_32QW = 0x04000000, RXCS_FIFOTHNP_64QW = 0x08000000, RXCS_FIFOTHNP_128QW = 0x0C000000,
  RXCS_DMAREQSZ_16B = 0x00000000, RXCS_DMAREQSZ_32B = 0x01000000, RXCS_DMAREQSZ_64B = 0x02000000, RXCS_DMAREQSZ_128B = 0x03000000,
  RXCS_QUEUESEL_Q0 = 0x00000000, RXCS_QUEUESEL_Q1 = 0x00010000, RXCS_QUEUESEL_Q2 = 0x00020000, RXCS_QUEUESEL_Q3 = 0x00030000,
  RXCS_RETRYGAP_256ns = 0x00000000, RXCS_RETRYGAP_512ns = 0x00001000, RXCS_RETRYGAP_1024ns = 0x00002000, RXCS_RETRYGAP_2048ns = 0x00003000,
  RXCS_RETRYGAP_4096ns = 0x00004000, RXCS_RETRYGAP_8192ns = 0x00005000, RXCS_RETRYGAP_16384ns = 0x00006000, RXCS_RETRYGAP_32768ns = 0x00007000,
  RXCS_RETRYCNT_0 = 0x00000000, RXCS_RETRYCNT_4 = 0x00000100, RXCS_RETRYCNT_8 = 0x00000200, RXCS_RETRYCNT_12 = 0x00000300,
  RXCS_RETRYCNT_16 = 0x00000400, RXCS_RETRYCNT_20 = 0x00000500, RXCS_RETRYCNT_24 = 0x00000600, RXCS_RETRYCNT_28 = 0x00000700,
  RXCS_RETRYCNT_32 = 0x00000800, RXCS_RETRYCNT_36 = 0x00000900, RXCS_RETRYCNT_40 = 0x00000A00, RXCS_RETRYCNT_44 = 0x00000B00,
  RXCS_RETRYCNT_48 = 0x00000C00, RXCS_RETRYCNT_52 = 0x00000D00, RXCS_RETRYCNT_56 = 0x00000E00, RXCS_RETRYCNT_60 = 0x00000F00,
  RXCS_DEFAULT
}
 
enum  jme_rxmcs_bits {
  RXMCS_ALLFRAME = 0x00000800, RXMCS_BRDFRAME = 0x00000400, RXMCS_MULFRAME = 0x00000200, RXMCS_UNIFRAME = 0x00000100,
  RXMCS_ALLMULFRAME = 0x00000080, RXMCS_MULFILTERED = 0x00000040, RXMCS_RXCOLLDEC = 0x00000020, RXMCS_FLOWCTRL = 0x00000008,
  RXMCS_VTAGRM = 0x00000004, RXMCS_PREPAD = 0x00000002, RXMCS_CHECKSUM = 0x00000001, RXMCS_DEFAULT
}
 
enum  jme_wfoi_bit_masks { WFOI_MASK_SEL = 0x00000070, WFOI_CRC_SEL = 0x00000008, WFOI_FRAME_SEL = 0x00000007 }
 
enum  jme_wfoi_shifts { WFOI_MASK_SHIFT = 4 }
 
enum  jme_smi_bit_mask {
  SMI_DATA_MASK = 0xFFFF0000, SMI_REG_ADDR_MASK = 0x0000F800, SMI_PHY_ADDR_MASK = 0x000007C0, SMI_OP_WRITE = 0x00000020,
  SMI_OP_REQ = 0x00000010, SMI_OP_MDIO = 0x00000008, SMI_OP_MDOE = 0x00000004, SMI_OP_MDC = 0x00000002,
  SMI_OP_MDEN = 0x00000001
}
 
enum  jme_smi_bit_shift { SMI_DATA_SHIFT = 16, SMI_REG_ADDR_SHIFT = 11, SMI_PHY_ADDR_SHIFT = 6 }
 
enum  jme_ghc_bit_mask { GHC_SWRST = 0x40000000, GHC_DPX = 0x00000040, GHC_SPEED = 0x00000030, GHC_LINK_POLL = 0x00000001 }
 
enum  jme_ghc_speed_val { GHC_SPEED_10M = 0x00000010, GHC_SPEED_100M = 0x00000020, GHC_SPEED_1000M = 0x00000030 }
 
enum  jme_ghc_to_clk { GHC_TO_CLK_OFF = 0x00000000, GHC_TO_CLK_GPHY = 0x00400000, GHC_TO_CLK_PCIE = 0x00800000, GHC_TO_CLK_INVALID = 0x00C00000 }
 
enum  jme_ghc_txmac_clk { GHC_TXMAC_CLK_OFF = 0x00000000, GHC_TXMAC_CLK_GPHY = 0x00100000, GHC_TXMAC_CLK_PCIE = 0x00200000, GHC_TXMAC_CLK_INVALID = 0x00300000 }
 
enum  jme_pmcs_bit_masks {
  PMCS_WF7DET = 0x80000000, PMCS_WF6DET = 0x40000000, PMCS_WF5DET = 0x20000000, PMCS_WF4DET = 0x10000000,
  PMCS_WF3DET = 0x08000000, PMCS_WF2DET = 0x04000000, PMCS_WF1DET = 0x02000000, PMCS_WF0DET = 0x01000000,
  PMCS_LFDET = 0x00040000, PMCS_LRDET = 0x00020000, PMCS_MFDET = 0x00010000, PMCS_WF7EN = 0x00008000,
  PMCS_WF6EN = 0x00004000, PMCS_WF5EN = 0x00002000, PMCS_WF4EN = 0x00001000, PMCS_WF3EN = 0x00000800,
  PMCS_WF2EN = 0x00000400, PMCS_WF1EN = 0x00000200, PMCS_WF0EN = 0x00000100, PMCS_LFEN = 0x00000004,
  PMCS_LREN = 0x00000002, PMCS_MFEN = 0x00000001
}
 
enum  jme_phy_link_bit_mask {
  PHY_LINK_SPEED_MASK = 0x0000C000, PHY_LINK_DUPLEX = 0x00002000, PHY_LINK_SPEEDDPU_RESOLVED = 0x00000800, PHY_LINK_UP = 0x00000400,
  PHY_LINK_AUTONEG_COMPLETE = 0x00000200, PHY_LINK_MDI_STAT = 0x00000040
}
 
enum  jme_phy_link_speed_val { PHY_LINK_SPEED_10M = 0x00000000, PHY_LINK_SPEED_100M = 0x00004000, PHY_LINK_SPEED_1000M = 0x00008000 }
 
enum  jme_smbcsr_bit_mask {
  SMBCSR_CNACK = 0x00020000, SMBCSR_RELOAD = 0x00010000, SMBCSR_EEPROMD = 0x00000020, SMBCSR_INITDONE = 0x00000010,
  SMBCSR_BUSY = 0x0000000F
}
 
enum  jme_smbintf_bit_mask {
  SMBINTF_HWDATR = 0xFF000000, SMBINTF_HWDATW = 0x00FF0000, SMBINTF_HWADDR = 0x0000FF00, SMBINTF_HWRWN = 0x00000020,
  SMBINTF_HWCMD = 0x00000010, SMBINTF_FASTM = 0x00000008, SMBINTF_GPIOSCL = 0x00000004, SMBINTF_GPIOSDA = 0x00000002,
  SMBINTF_GPIOEN = 0x00000001
}
 
enum  jme_smbintf_vals { SMBINTF_HWRWN_READ = 0x00000020, SMBINTF_HWRWN_WRITE = 0x00000000 }
 
enum  jme_smbintf_shifts { SMBINTF_HWDATR_SHIFT = 24, SMBINTF_HWDATW_SHIFT = 16, SMBINTF_HWADDR_SHIFT = 8 }
 
enum  jme_tmcsr_bit_masks { TMCSR_SWIT = 0x80000000, TMCSR_EN = 0x01000000, TMCSR_CNT = 0x00FFFFFF }
 
enum  jme_gpreg0_masks {
  GPREG0_DISSH = 0xFF000000, GPREG0_PCIRLMT = 0x00300000, GPREG0_PCCNOMUTCLR = 0x00040000, GPREG0_LNKINTPOLL = 0x00001000,
  GPREG0_PCCTMR = 0x00000300, GPREG0_PHYADDR = 0x0000001F
}
 
enum  jme_gpreg0_vals {
  GPREG0_DISSH_DW7 = 0x80000000, GPREG0_DISSH_DW6 = 0x40000000, GPREG0_DISSH_DW5 = 0x20000000, GPREG0_DISSH_DW4 = 0x10000000,
  GPREG0_DISSH_DW3 = 0x08000000, GPREG0_DISSH_DW2 = 0x04000000, GPREG0_DISSH_DW1 = 0x02000000, GPREG0_DISSH_DW0 = 0x01000000,
  GPREG0_DISSH_ALL = 0xFF000000, GPREG0_PCIRLMT_8 = 0x00000000, GPREG0_PCIRLMT_6 = 0x00100000, GPREG0_PCIRLMT_5 = 0x00200000,
  GPREG0_PCIRLMT_4 = 0x00300000, GPREG0_PCCTMR_16ns = 0x00000000, GPREG0_PCCTMR_256ns = 0x00000100, GPREG0_PCCTMR_1us = 0x00000200,
  GPREG0_PCCTMR_1ms = 0x00000300, GPREG0_PHYADDR_1 = 0x00000001, GPREG0_DEFAULT
}
 
enum  jme_gpreg1_masks { GPREG1_INTRDELAYUNIT = 0x00000018, GPREG1_INTRDELAYENABLE = 0x00000007 }
 
enum  jme_gpreg1_vals {
  GPREG1_RSSPATCH = 0x00000040, GPREG1_HALFMODEPATCH = 0x00000020, GPREG1_INTDLYUNIT_16NS = 0x00000000, GPREG1_INTDLYUNIT_256NS = 0x00000008,
  GPREG1_INTDLYUNIT_1US = 0x00000010, GPREG1_INTDLYUNIT_16US = 0x00000018, GPREG1_INTDLYEN_1U = 0x00000001, GPREG1_INTDLYEN_2U = 0x00000002,
  GPREG1_INTDLYEN_3U = 0x00000003, GPREG1_INTDLYEN_4U = 0x00000004, GPREG1_INTDLYEN_5U = 0x00000005, GPREG1_INTDLYEN_6U = 0x00000006,
  GPREG1_INTDLYEN_7U = 0x00000007, GPREG1_DEFAULT = 0x00000000
}
 
enum  jme_interrupt_bits {
  INTR_SWINTR = 0x80000000, INTR_TMINTR = 0x40000000, INTR_LINKCH = 0x20000000, INTR_PAUSERCV = 0x10000000,
  INTR_MAGICRCV = 0x08000000, INTR_WAKERCV = 0x04000000, INTR_PCCRX0TO = 0x02000000, INTR_PCCRX1TO = 0x01000000,
  INTR_PCCRX2TO = 0x00800000, INTR_PCCRX3TO = 0x00400000, INTR_PCCTXTO = 0x00200000, INTR_PCCRX0 = 0x00100000,
  INTR_PCCRX1 = 0x00080000, INTR_PCCRX2 = 0x00040000, INTR_PCCRX3 = 0x00020000, INTR_PCCTX = 0x00010000,
  INTR_RX3EMP = 0x00008000, INTR_RX2EMP = 0x00004000, INTR_RX1EMP = 0x00002000, INTR_RX0EMP = 0x00001000,
  INTR_RX3 = 0x00000800, INTR_RX2 = 0x00000400, INTR_RX1 = 0x00000200, INTR_RX0 = 0x00000100,
  INTR_TX7 = 0x00000080, INTR_TX6 = 0x00000040, INTR_TX5 = 0x00000020, INTR_TX4 = 0x00000010,
  INTR_TX3 = 0x00000008, INTR_TX2 = 0x00000004, INTR_TX1 = 0x00000002, INTR_TX0 = 0x00000001
}
 
enum  jme_pccrx_masks { PCCRXTO_MASK = 0xFFFF0000, PCCRX_MASK = 0x0000FF00 }
 
enum  jme_pcctx_masks { PCCTXTO_MASK = 0xFFFF0000, PCCTX_MASK = 0x0000FF00, PCCTX_QS_MASK = 0x000000FF }
 
enum  jme_pccrx_shifts { PCCRXTO_SHIFT = 16, PCCRX_SHIFT = 8 }
 
enum  jme_pcctx_shifts { PCCTXTO_SHIFT = 16, PCCTX_SHIFT = 8 }
 
enum  jme_pcctx_bits {
  PCCTXQ0_EN = 0x00000001, PCCTXQ1_EN = 0x00000002, PCCTXQ2_EN = 0x00000004, PCCTXQ3_EN = 0x00000008,
  PCCTXQ4_EN = 0x00000010, PCCTXQ5_EN = 0x00000020, PCCTXQ6_EN = 0x00000040, PCCTXQ7_EN = 0x00000080
}
 
enum  jme_chipmode_bit_masks { CM_FPGAVER_MASK = 0xFFFF0000, CM_CHIPREV_MASK = 0x0000FF00, CM_CHIPMODE_MASK = 0x0000000F }
 
enum  jme_chipmode_shifts { CM_FPGAVER_SHIFT = 16, CM_CHIPREV_SHIFT = 8 }
 

Functions

 FILE_LICENCE (GPL2_OR_LATER)
 
static uint32_t smi_reg_addr (int x)
 
static uint32_t smi_phy_addr (int x)
 
static int is_buggy250 (unsigned short device, unsigned int chiprev)
 
static uint32_t jread32 (struct jme_adapter *jme, uint32_t reg)
 
static void jwrite32 (struct jme_adapter *jme, uint32_t reg, uint32_t val)
 
static void jwrite32f (struct jme_adapter *jme, uint32_t reg, uint32_t val)
 

Variables

static const uint32_t INTR_ENABLE
 

Macro Definition Documentation

◆ __JME_H_INCLUDED__

#define __JME_H_INCLUDED__

Definition at line 24 of file jme.h.

◆ PCI_VENDOR_ID_JMICRON

#define PCI_VENDOR_ID_JMICRON   0x197b

Definition at line 26 of file jme.h.

◆ PCI_DEVICE_ID_JMICRON_JMC250

#define PCI_DEVICE_ID_JMICRON_JMC250   0x0250

Definition at line 27 of file jme.h.

◆ PCI_DEVICE_ID_JMICRON_JMC260

#define PCI_DEVICE_ID_JMICRON_JMC260   0x0260

Definition at line 28 of file jme.h.

◆ PCI_DCSR_MRRS

#define PCI_DCSR_MRRS   0x59

Definition at line 33 of file jme.h.

◆ PCI_DCSR_MRRS_MASK

#define PCI_DCSR_MRRS_MASK   0x70

Definition at line 34 of file jme.h.

◆ RING_DESC_ALIGN

#define RING_DESC_ALIGN   16 /* Descriptor alignment */

Definition at line 50 of file jme.h.

◆ TX_DESC_SIZE

#define TX_DESC_SIZE   16

Definition at line 51 of file jme.h.

◆ TXDESC_MSS_SHIFT

#define TXDESC_MSS_SHIFT   2

Definition at line 122 of file jme.h.

◆ RX_DESC_SIZE

#define RX_DESC_SIZE   16

Definition at line 135 of file jme.h.

◆ RX_BUF_DMA_ALIGN

#define RX_BUF_DMA_ALIGN   8

Definition at line 136 of file jme.h.

◆ RX_PREPAD_SIZE

#define RX_PREPAD_SIZE   10

Definition at line 137 of file jme.h.

◆ ETH_CRC_LEN

#define ETH_CRC_LEN   2

Definition at line 138 of file jme.h.

◆ RX_VLANHDR_LEN

#define RX_VLANHDR_LEN   2

Definition at line 139 of file jme.h.

◆ RX_EXTRA_LEN

#define RX_EXTRA_LEN
Value:
ETH_CRC_LEN + \
RX_VLANHDR_LEN + \
RX_BUF_DMA_ALIGN)
#define ETH_HLEN
Definition: if_ether.h:9

Definition at line 140 of file jme.h.

◆ FIXED_MTU

#define FIXED_MTU   1500

Definition at line 144 of file jme.h.

◆ RX_ALLOC_LEN

#define RX_ALLOC_LEN   (FIXED_MTU + RX_EXTRA_LEN)

Definition at line 145 of file jme.h.

◆ JME_TX_DISABLE_TIMEOUT

#define JME_TX_DISABLE_TIMEOUT   10 /* 10 msec */

Definition at line 386 of file jme.h.

◆ JME_RX_DISABLE_TIMEOUT

#define JME_RX_DISABLE_TIMEOUT   10 /* 10 msec */

Definition at line 522 of file jme.h.

◆ WAKEUP_FRAME_NR

#define WAKEUP_FRAME_NR   8

Definition at line 548 of file jme.h.

◆ WAKEUP_FRAME_MASK_DWNR

#define WAKEUP_FRAME_MASK_DWNR   4

Definition at line 549 of file jme.h.

◆ JME_PHY_TIMEOUT

#define JME_PHY_TIMEOUT   100 /* 100 msec */

Definition at line 593 of file jme.h.

◆ JME_PHY_REG_NR

#define JME_PHY_REG_NR   32

Definition at line 594 of file jme.h.

◆ JME_SPDRSV_TIMEOUT

#define JME_SPDRSV_TIMEOUT   500 /* 500 us */

Definition at line 672 of file jme.h.

◆ JME_EEPROM_RELOAD_TIMEOUT

#define JME_EEPROM_RELOAD_TIMEOUT   2000 /* 2000 msec */

Definition at line 708 of file jme.h.

◆ JME_SMB_BUSY_TIMEOUT

#define JME_SMB_BUSY_TIMEOUT   20 /* 20 msec */

Definition at line 709 of file jme.h.

◆ JME_SMB_LEN

#define JME_SMB_LEN   256

Definition at line 710 of file jme.h.

◆ JME_EEPROM_MAGIC

#define JME_EEPROM_MAGIC   0x250

Definition at line 711 of file jme.h.

Enumeration Type Documentation

◆ pci_dcsr_mrrs_vals

Enumerator
MRRS_128B 
MRRS_256B 
MRRS_512B 
MRRS_1024B 
MRRS_2048B 
MRRS_4096B 

Definition at line 36 of file jme.h.

36  {
37  MRRS_128B = 0x00,
38  MRRS_256B = 0x10,
39  MRRS_512B = 0x20,
40  MRRS_1024B = 0x30,
41  MRRS_2048B = 0x40,
42  MRRS_4096B = 0x50,
43 };
Definition: jme.h:42
Definition: jme.h:38
Definition: jme.h:41
Definition: jme.h:39
Definition: jme.h:40
Definition: jme.h:37

◆ jme_txdesc_flags_bits

Enumerator
TXFLAG_OWN 
TXFLAG_INT 
TXFLAG_64BIT 
TXFLAG_TCPCS 
TXFLAG_UDPCS 
TXFLAG_IPCS 
TXFLAG_LSEN 
TXFLAG_TAGON 

Definition at line 111 of file jme.h.

111  {
112  TXFLAG_OWN = 0x80,
113  TXFLAG_INT = 0x40,
114  TXFLAG_64BIT = 0x20,
115  TXFLAG_TCPCS = 0x10,
116  TXFLAG_UDPCS = 0x08,
117  TXFLAG_IPCS = 0x04,
118  TXFLAG_LSEN = 0x02,
119  TXFLAG_TAGON = 0x01,
120 };

◆ jme_txwbdesc_flags_bits

Enumerator
TXWBFLAG_OWN 
TXWBFLAG_INT 
TXWBFLAG_TMOUT 
TXWBFLAG_TRYOUT 
TXWBFLAG_COL 
TXWBFLAG_ALLERR 

Definition at line 123 of file jme.h.

123  {
124  TXWBFLAG_OWN = 0x80,
125  TXWBFLAG_INT = 0x40,
126  TXWBFLAG_TMOUT = 0x20,
127  TXWBFLAG_TRYOUT = 0x10,
128  TXWBFLAG_COL = 0x08,
129 
132  TXWBFLAG_COL,
133 };

◆ jme_rxdesc_flags_bits

Enumerator
RXFLAG_OWN 
RXFLAG_INT 
RXFLAG_64BIT 

Definition at line 188 of file jme.h.

188  {
189  RXFLAG_OWN = 0x80,
190  RXFLAG_INT = 0x40,
191  RXFLAG_64BIT = 0x20,
192 };

◆ jme_rxwbdesc_flags_bits

Enumerator
RXWBFLAG_OWN 
RXWBFLAG_INT 
RXWBFLAG_MF 
RXWBFLAG_64BIT 
RXWBFLAG_TCPON 
RXWBFLAG_UDPON 
RXWBFLAG_IPCS 
RXWBFLAG_TCPCS 
RXWBFLAG_UDPCS 
RXWBFLAG_TAGON 
RXWBFLAG_IPV4 
RXWBFLAG_IPV6 
RXWBFLAG_PAUSE 
RXWBFLAG_MAGIC 
RXWBFLAG_WAKEUP 
RXWBFLAG_DEST 
RXWBFLAG_DEST_UNI 
RXWBFLAG_DEST_MUL 
RXWBFLAG_DEST_BRO 

Definition at line 194 of file jme.h.

194  {
195  RXWBFLAG_OWN = 0x8000,
196  RXWBFLAG_INT = 0x4000,
197  RXWBFLAG_MF = 0x2000,
198  RXWBFLAG_64BIT = 0x2000,
199  RXWBFLAG_TCPON = 0x1000,
200  RXWBFLAG_UDPON = 0x0800,
201  RXWBFLAG_IPCS = 0x0400,
202  RXWBFLAG_TCPCS = 0x0200,
203  RXWBFLAG_UDPCS = 0x0100,
204  RXWBFLAG_TAGON = 0x0080,
205  RXWBFLAG_IPV4 = 0x0040,
206  RXWBFLAG_IPV6 = 0x0020,
207  RXWBFLAG_PAUSE = 0x0010,
208  RXWBFLAG_MAGIC = 0x0008,
209  RXWBFLAG_WAKEUP = 0x0004,
210  RXWBFLAG_DEST = 0x0003,
211  RXWBFLAG_DEST_UNI = 0x0001,
212  RXWBFLAG_DEST_MUL = 0x0002,
213  RXWBFLAG_DEST_BRO = 0x0003,
214 };

◆ jme_rxwbdesc_desccnt_mask

Enumerator
RXWBDCNT_WBCPL 
RXWBDCNT_DCNT 

Definition at line 216 of file jme.h.

216  {
217  RXWBDCNT_WBCPL = 0x80,
218  RXWBDCNT_DCNT = 0x7F,
219 };

◆ jme_rxwbdesc_errstat_bits

Enumerator
RXWBERR_LIMIT 
RXWBERR_MIIER 
RXWBERR_NIBON 
RXWBERR_COLON 
RXWBERR_ABORT 
RXWBERR_SHORT 
RXWBERR_OVERUN 
RXWBERR_CRCERR 
RXWBERR_ALLERR 

Definition at line 221 of file jme.h.

221  {
222  RXWBERR_LIMIT = 0x80,
223  RXWBERR_MIIER = 0x40,
224  RXWBERR_NIBON = 0x20,
225  RXWBERR_COLON = 0x10,
226  RXWBERR_ABORT = 0x08,
227  RXWBERR_SHORT = 0x04,
228  RXWBERR_OVERUN = 0x02,
229  RXWBERR_CRCERR = 0x01,
230  RXWBERR_ALLERR = 0xFF,
231 };

◆ jme_iomap_regs_value

Enumerator
JME_REGS_SIZE 

Definition at line 274 of file jme.h.

274  {
275  JME_REGS_SIZE = 0x1000,
276 };

◆ jme_iomap_offsets

Enumerator
JME_MAC 
JME_PHY 
JME_MISC 
JME_RSS 

Definition at line 278 of file jme.h.

278  {
279  JME_MAC = 0x0000,
280  JME_PHY = 0x0400,
281  JME_MISC = 0x0800,
282  JME_RSS = 0x0C00,
283 };
Definition: jme.h:280
Definition: jme.h:281
Definition: jme.h:282
Definition: jme.h:279

◆ jme_iomap_lens

Enumerator
JME_MAC_LEN 
JME_PHY_LEN 
JME_MISC_LEN 
JME_RSS_LEN 

Definition at line 285 of file jme.h.

285  {
286  JME_MAC_LEN = 0x80,
287  JME_PHY_LEN = 0x58,
288  JME_MISC_LEN = 0x98,
289  JME_RSS_LEN = 0xFF,
290 };

◆ jme_iomap_regs

Enumerator
JME_TXCS 
JME_TXDBA_LO 
JME_TXDBA_HI 
JME_TXQDC 
JME_TXNDA 
JME_TXMCS 
JME_TXPFC 
JME_TXTRHD 
JME_RXCS 
JME_RXDBA_LO 
JME_RXDBA_HI 
JME_RXQDC 
JME_RXNDA 
JME_RXMCS 
JME_RXUMA_LO 
JME_RXUMA_HI 
JME_RXMCHT_LO 
JME_RXMCHT_HI 
JME_WFODP 
JME_WFOI 
JME_SMI 
JME_GHC 
JME_PMCS 
JME_PHY_CS 
JME_PHY_LINK 
JME_SMBCSR 
JME_SMBINTF 
JME_TMCSR 
JME_GPREG0 
JME_GPREG1 
JME_IEVE 
JME_IREQ 
JME_IENS 
JME_IENC 
JME_PCCRX0 
JME_PCCTX 
JME_CHIPMODE 
JME_SHBA_HI 
JME_SHBA_LO 
JME_TIMER1 
JME_TIMER2 
JME_APMC 
JME_PCCSRX0 

Definition at line 292 of file jme.h.

292  {
293  JME_TXCS = JME_MAC | 0x00, /* Transmit Control and Status */
294  JME_TXDBA_LO = JME_MAC | 0x04, /* Transmit Queue Desc Base Addr */
295  JME_TXDBA_HI = JME_MAC | 0x08, /* Transmit Queue Desc Base Addr */
296  JME_TXQDC = JME_MAC | 0x0C, /* Transmit Queue Desc Count */
297  JME_TXNDA = JME_MAC | 0x10, /* Transmit Queue Next Desc Addr */
298  JME_TXMCS = JME_MAC | 0x14, /* Transmit MAC Control Status */
299  JME_TXPFC = JME_MAC | 0x18, /* Transmit Pause Frame Control */
300  JME_TXTRHD = JME_MAC | 0x1C, /* Transmit Timer/Retry@Half-Dup */
301 
302  JME_RXCS = JME_MAC | 0x20, /* Receive Control and Status */
303  JME_RXDBA_LO = JME_MAC | 0x24, /* Receive Queue Desc Base Addr */
304  JME_RXDBA_HI = JME_MAC | 0x28, /* Receive Queue Desc Base Addr */
305  JME_RXQDC = JME_MAC | 0x2C, /* Receive Queue Desc Count */
306  JME_RXNDA = JME_MAC | 0x30, /* Receive Queue Next Desc Addr */
307  JME_RXMCS = JME_MAC | 0x34, /* Receive MAC Control Status */
308  JME_RXUMA_LO = JME_MAC | 0x38, /* Receive Unicast MAC Address */
309  JME_RXUMA_HI = JME_MAC | 0x3C, /* Receive Unicast MAC Address */
310  JME_RXMCHT_LO = JME_MAC | 0x40, /* Recv Multicast Addr HashTable */
311  JME_RXMCHT_HI = JME_MAC | 0x44, /* Recv Multicast Addr HashTable */
312  JME_WFODP = JME_MAC | 0x48, /* Wakeup Frame Output Data Port */
313  JME_WFOI = JME_MAC | 0x4C, /* Wakeup Frame Output Interface */
314 
315  JME_SMI = JME_MAC | 0x50, /* Station Management Interface */
316  JME_GHC = JME_MAC | 0x54, /* Global Host Control */
317  JME_PMCS = JME_MAC | 0x60, /* Power Management Control/Stat */
318 
319 
320  JME_PHY_CS = JME_PHY | 0x28, /* PHY Ctrl and Status Register */
321  JME_PHY_LINK = JME_PHY | 0x30, /* PHY Link Status Register */
322  JME_SMBCSR = JME_PHY | 0x40, /* SMB Control and Status */
323  JME_SMBINTF = JME_PHY | 0x44, /* SMB Interface */
324 
325 
326  JME_TMCSR = JME_MISC | 0x00, /* Timer Control/Status Register */
327  JME_GPREG0 = JME_MISC | 0x08, /* General purpose REG-0 */
328  JME_GPREG1 = JME_MISC | 0x0C, /* General purpose REG-1 */
329  JME_IEVE = JME_MISC | 0x20, /* Interrupt Event Status */
330  JME_IREQ = JME_MISC | 0x24, /* Intr Req Status(For Debug) */
331  JME_IENS = JME_MISC | 0x28, /* Intr Enable - Setting Port */
332  JME_IENC = JME_MISC | 0x2C, /* Interrupt Enable - Clear Port */
333  JME_PCCRX0 = JME_MISC | 0x30, /* PCC Control for RX Queue 0 */
334  JME_PCCTX = JME_MISC | 0x40, /* PCC Control for TX Queues */
335  JME_CHIPMODE = JME_MISC | 0x44, /* Identify FPGA Version */
336  JME_SHBA_HI = JME_MISC | 0x48, /* Shadow Register Base HI */
337  JME_SHBA_LO = JME_MISC | 0x4C, /* Shadow Register Base LO */
338  JME_TIMER1 = JME_MISC | 0x70, /* Timer1 */
339  JME_TIMER2 = JME_MISC | 0x74, /* Timer2 */
340  JME_APMC = JME_MISC | 0x7C, /* Aggressive Power Mode Control */
341  JME_PCCSRX0 = JME_MISC | 0x80, /* PCC Status of RX0 */
342 };
Definition: jme.h:280
Definition: jme.h:330
Definition: jme.h:296
Definition: jme.h:281
Definition: jme.h:302
Definition: jme.h:332
Definition: jme.h:293
Definition: jme.h:297
Definition: jme.h:279
Definition: jme.h:315
Definition: jme.h:316
Definition: jme.h:340
Definition: jme.h:298
Definition: jme.h:331
Definition: jme.h:306
Definition: jme.h:326
Definition: jme.h:307
Definition: jme.h:334
Definition: jme.h:312
Definition: jme.h:329
Definition: jme.h:317
Definition: jme.h:299
Definition: jme.h:305
Definition: jme.h:313

◆ jme_txcs_bits

Enumerator
TXCS_QUEUE7S 
TXCS_QUEUE6S 
TXCS_QUEUE5S 
TXCS_QUEUE4S 
TXCS_QUEUE3S 
TXCS_QUEUE2S 
TXCS_QUEUE1S 
TXCS_QUEUE0S 
TXCS_FIFOTH 
TXCS_DMASIZE 
TXCS_BURST 
TXCS_ENABLE 

Definition at line 347 of file jme.h.

347  {
348  TXCS_QUEUE7S = 0x00008000,
349  TXCS_QUEUE6S = 0x00004000,
350  TXCS_QUEUE5S = 0x00002000,
351  TXCS_QUEUE4S = 0x00001000,
352  TXCS_QUEUE3S = 0x00000800,
353  TXCS_QUEUE2S = 0x00000400,
354  TXCS_QUEUE1S = 0x00000200,
355  TXCS_QUEUE0S = 0x00000100,
356  TXCS_FIFOTH = 0x000000C0,
357  TXCS_DMASIZE = 0x00000030,
358  TXCS_BURST = 0x00000004,
359  TXCS_ENABLE = 0x00000001,
360 };

◆ jme_txcs_value

Enumerator
TXCS_FIFOTH_16QW 
TXCS_FIFOTH_12QW 
TXCS_FIFOTH_8QW 
TXCS_FIFOTH_4QW 
TXCS_DMASIZE_64B 
TXCS_DMASIZE_128B 
TXCS_DMASIZE_256B 
TXCS_DMASIZE_512B 
TXCS_SELECT_QUEUE0 
TXCS_SELECT_QUEUE1 
TXCS_SELECT_QUEUE2 
TXCS_SELECT_QUEUE3 
TXCS_SELECT_QUEUE4 
TXCS_SELECT_QUEUE5 
TXCS_SELECT_QUEUE6 
TXCS_SELECT_QUEUE7 
TXCS_DEFAULT 

Definition at line 362 of file jme.h.

362  {
363  TXCS_FIFOTH_16QW = 0x000000C0,
364  TXCS_FIFOTH_12QW = 0x00000080,
365  TXCS_FIFOTH_8QW = 0x00000040,
366  TXCS_FIFOTH_4QW = 0x00000000,
367 
368  TXCS_DMASIZE_64B = 0x00000000,
369  TXCS_DMASIZE_128B = 0x00000010,
370  TXCS_DMASIZE_256B = 0x00000020,
371  TXCS_DMASIZE_512B = 0x00000030,
372 
373  TXCS_SELECT_QUEUE0 = 0x00000000,
374  TXCS_SELECT_QUEUE1 = 0x00010000,
375  TXCS_SELECT_QUEUE2 = 0x00020000,
376  TXCS_SELECT_QUEUE3 = 0x00030000,
377  TXCS_SELECT_QUEUE4 = 0x00040000,
378  TXCS_SELECT_QUEUE5 = 0x00050000,
379  TXCS_SELECT_QUEUE6 = 0x00060000,
380  TXCS_SELECT_QUEUE7 = 0x00070000,
381 
383  TXCS_BURST,
384 };

◆ jme_txmcs_bit_masks

Enumerator
TXMCS_IFG2 
TXMCS_IFG1 
TXMCS_TTHOLD 
TXMCS_FBURST 
TXMCS_CARRIEREXT 
TXMCS_DEFER 
TXMCS_BACKOFF 
TXMCS_CARRIERSENSE 
TXMCS_COLLISION 
TXMCS_CRC 
TXMCS_PADDING 

Definition at line 391 of file jme.h.

391  {
392  TXMCS_IFG2 = 0xC0000000,
393  TXMCS_IFG1 = 0x30000000,
394  TXMCS_TTHOLD = 0x00000300,
395  TXMCS_FBURST = 0x00000080,
396  TXMCS_CARRIEREXT = 0x00000040,
397  TXMCS_DEFER = 0x00000020,
398  TXMCS_BACKOFF = 0x00000010,
399  TXMCS_CARRIERSENSE = 0x00000008,
400  TXMCS_COLLISION = 0x00000004,
401  TXMCS_CRC = 0x00000002,
402  TXMCS_PADDING = 0x00000001,
403 };
Definition: jme.h:401

◆ jme_txmcs_values

Enumerator
TXMCS_IFG2_6_4 
TXMCS_IFG2_8_5 
TXMCS_IFG2_10_6 
TXMCS_IFG2_12_7 
TXMCS_IFG1_8_4 
TXMCS_IFG1_12_6 
TXMCS_IFG1_16_8 
TXMCS_IFG1_20_10 
TXMCS_TTHOLD_1_8 
TXMCS_TTHOLD_1_4 
TXMCS_TTHOLD_1_2 
TXMCS_TTHOLD_FULL 
TXMCS_DEFAULT 

Definition at line 405 of file jme.h.

405  {
406  TXMCS_IFG2_6_4 = 0x00000000,
407  TXMCS_IFG2_8_5 = 0x40000000,
408  TXMCS_IFG2_10_6 = 0x80000000,
409  TXMCS_IFG2_12_7 = 0xC0000000,
410 
411  TXMCS_IFG1_8_4 = 0x00000000,
412  TXMCS_IFG1_12_6 = 0x10000000,
413  TXMCS_IFG1_16_8 = 0x20000000,
414  TXMCS_IFG1_20_10 = 0x30000000,
415 
416  TXMCS_TTHOLD_1_8 = 0x00000000,
417  TXMCS_TTHOLD_1_4 = 0x00000100,
418  TXMCS_TTHOLD_1_2 = 0x00000200,
419  TXMCS_TTHOLD_FULL = 0x00000300,
420 
424  TXMCS_DEFER |
425  TXMCS_CRC |
427 };
Definition: jme.h:401

◆ jme_txpfc_bits_masks

Enumerator
TXPFC_VLAN_TAG 
TXPFC_VLAN_EN 
TXPFC_PF_EN 

Definition at line 429 of file jme.h.

429  {
430  TXPFC_VLAN_TAG = 0xFFFF0000,
431  TXPFC_VLAN_EN = 0x00008000,
432  TXPFC_PF_EN = 0x00000001,
433 };

◆ jme_txtrhd_bits_masks

Enumerator
TXTRHD_TXPEN 
TXTRHD_TXP 
TXTRHD_TXREN 
TXTRHD_TXRL 

Definition at line 435 of file jme.h.

435  {
436  TXTRHD_TXPEN = 0x80000000,
437  TXTRHD_TXP = 0x7FFFFF00,
438  TXTRHD_TXREN = 0x00000080,
439  TXTRHD_TXRL = 0x0000007F,
440 };

◆ jme_txtrhd_shifts

Enumerator
TXTRHD_TXP_SHIFT 
TXTRHD_TXRL_SHIFT 

Definition at line 442 of file jme.h.

442  {
443  TXTRHD_TXP_SHIFT = 8,
444  TXTRHD_TXRL_SHIFT = 0,
445 };

◆ jme_rxcs_bit_masks

Enumerator
RXCS_FIFOTHTP 
RXCS_FIFOTHNP 
RXCS_DMAREQSZ 
RXCS_QUEUESEL 
RXCS_RETRYGAP 
RXCS_RETRYCNT 
RXCS_WAKEUP 
RXCS_MAGIC 
RXCS_SHORT 
RXCS_ABORT 
RXCS_QST 
RXCS_SUSPEND 
RXCS_ENABLE 

Definition at line 450 of file jme.h.

450  {
451  /* FIFO full threshold for transmitting Tx Pause Packet */
452  RXCS_FIFOTHTP = 0x30000000,
453  /* FIFO threshold for processing next packet */
454  RXCS_FIFOTHNP = 0x0C000000,
455  RXCS_DMAREQSZ = 0x03000000, /* DMA Request Size */
456  RXCS_QUEUESEL = 0x00030000, /* Queue selection */
457  RXCS_RETRYGAP = 0x0000F000, /* RX Desc full retry gap */
458  RXCS_RETRYCNT = 0x00000F00, /* RX Desc full retry counter */
459  RXCS_WAKEUP = 0x00000040, /* Enable receive wakeup packet */
460  RXCS_MAGIC = 0x00000020, /* Enable receive magic packet */
461  RXCS_SHORT = 0x00000010, /* Enable receive short packet */
462  RXCS_ABORT = 0x00000008, /* Enable receive errorr packet */
463  RXCS_QST = 0x00000004, /* Receive queue start */
464  RXCS_SUSPEND = 0x00000002,
465  RXCS_ENABLE = 0x00000001,
466 };
Definition: jme.h:463

◆ jme_rxcs_values

Enumerator
RXCS_FIFOTHTP_16T 
RXCS_FIFOTHTP_32T 
RXCS_FIFOTHTP_64T 
RXCS_FIFOTHTP_128T 
RXCS_FIFOTHNP_16QW 
RXCS_FIFOTHNP_32QW 
RXCS_FIFOTHNP_64QW 
RXCS_FIFOTHNP_128QW 
RXCS_DMAREQSZ_16B 
RXCS_DMAREQSZ_32B 
RXCS_DMAREQSZ_64B 
RXCS_DMAREQSZ_128B 
RXCS_QUEUESEL_Q0 
RXCS_QUEUESEL_Q1 
RXCS_QUEUESEL_Q2 
RXCS_QUEUESEL_Q3 
RXCS_RETRYGAP_256ns 
RXCS_RETRYGAP_512ns 
RXCS_RETRYGAP_1024ns 
RXCS_RETRYGAP_2048ns 
RXCS_RETRYGAP_4096ns 
RXCS_RETRYGAP_8192ns 
RXCS_RETRYGAP_16384ns 
RXCS_RETRYGAP_32768ns 
RXCS_RETRYCNT_0 
RXCS_RETRYCNT_4 
RXCS_RETRYCNT_8 
RXCS_RETRYCNT_12 
RXCS_RETRYCNT_16 
RXCS_RETRYCNT_20 
RXCS_RETRYCNT_24 
RXCS_RETRYCNT_28 
RXCS_RETRYCNT_32 
RXCS_RETRYCNT_36 
RXCS_RETRYCNT_40 
RXCS_RETRYCNT_44 
RXCS_RETRYCNT_48 
RXCS_RETRYCNT_52 
RXCS_RETRYCNT_56 
RXCS_RETRYCNT_60 
RXCS_DEFAULT 

Definition at line 468 of file jme.h.

468  {
469  RXCS_FIFOTHTP_16T = 0x00000000,
470  RXCS_FIFOTHTP_32T = 0x10000000,
471  RXCS_FIFOTHTP_64T = 0x20000000,
472  RXCS_FIFOTHTP_128T = 0x30000000,
473 
474  RXCS_FIFOTHNP_16QW = 0x00000000,
475  RXCS_FIFOTHNP_32QW = 0x04000000,
476  RXCS_FIFOTHNP_64QW = 0x08000000,
477  RXCS_FIFOTHNP_128QW = 0x0C000000,
478 
479  RXCS_DMAREQSZ_16B = 0x00000000,
480  RXCS_DMAREQSZ_32B = 0x01000000,
481  RXCS_DMAREQSZ_64B = 0x02000000,
482  RXCS_DMAREQSZ_128B = 0x03000000,
483 
484  RXCS_QUEUESEL_Q0 = 0x00000000,
485  RXCS_QUEUESEL_Q1 = 0x00010000,
486  RXCS_QUEUESEL_Q2 = 0x00020000,
487  RXCS_QUEUESEL_Q3 = 0x00030000,
488 
489  RXCS_RETRYGAP_256ns = 0x00000000,
490  RXCS_RETRYGAP_512ns = 0x00001000,
491  RXCS_RETRYGAP_1024ns = 0x00002000,
492  RXCS_RETRYGAP_2048ns = 0x00003000,
493  RXCS_RETRYGAP_4096ns = 0x00004000,
494  RXCS_RETRYGAP_8192ns = 0x00005000,
495  RXCS_RETRYGAP_16384ns = 0x00006000,
496  RXCS_RETRYGAP_32768ns = 0x00007000,
497 
498  RXCS_RETRYCNT_0 = 0x00000000,
499  RXCS_RETRYCNT_4 = 0x00000100,
500  RXCS_RETRYCNT_8 = 0x00000200,
501  RXCS_RETRYCNT_12 = 0x00000300,
502  RXCS_RETRYCNT_16 = 0x00000400,
503  RXCS_RETRYCNT_20 = 0x00000500,
504  RXCS_RETRYCNT_24 = 0x00000600,
505  RXCS_RETRYCNT_28 = 0x00000700,
506  RXCS_RETRYCNT_32 = 0x00000800,
507  RXCS_RETRYCNT_36 = 0x00000900,
508  RXCS_RETRYCNT_40 = 0x00000A00,
509  RXCS_RETRYCNT_44 = 0x00000B00,
510  RXCS_RETRYCNT_48 = 0x00000C00,
511  RXCS_RETRYCNT_52 = 0x00000D00,
512  RXCS_RETRYCNT_56 = 0x00000E00,
513  RXCS_RETRYCNT_60 = 0x00000F00,
514 
520 };

◆ jme_rxmcs_bits

Enumerator
RXMCS_ALLFRAME 
RXMCS_BRDFRAME 
RXMCS_MULFRAME 
RXMCS_UNIFRAME 
RXMCS_ALLMULFRAME 
RXMCS_MULFILTERED 
RXMCS_RXCOLLDEC 
RXMCS_FLOWCTRL 
RXMCS_VTAGRM 
RXMCS_PREPAD 
RXMCS_CHECKSUM 
RXMCS_DEFAULT 

Definition at line 527 of file jme.h.

527  {
528  RXMCS_ALLFRAME = 0x00000800,
529  RXMCS_BRDFRAME = 0x00000400,
530  RXMCS_MULFRAME = 0x00000200,
531  RXMCS_UNIFRAME = 0x00000100,
532  RXMCS_ALLMULFRAME = 0x00000080,
533  RXMCS_MULFILTERED = 0x00000040,
534  RXMCS_RXCOLLDEC = 0x00000020,
535  RXMCS_FLOWCTRL = 0x00000008,
536  RXMCS_VTAGRM = 0x00000004,
537  RXMCS_PREPAD = 0x00000002,
538  RXMCS_CHECKSUM = 0x00000001,
539 
543 };

◆ jme_wfoi_bit_masks

Enumerator
WFOI_MASK_SEL 
WFOI_CRC_SEL 
WFOI_FRAME_SEL 

Definition at line 551 of file jme.h.

551  {
552  WFOI_MASK_SEL = 0x00000070,
553  WFOI_CRC_SEL = 0x00000008,
554  WFOI_FRAME_SEL = 0x00000007,
555 };

◆ jme_wfoi_shifts

Enumerator
WFOI_MASK_SHIFT 

Definition at line 557 of file jme.h.

557  {
558  WFOI_MASK_SHIFT = 4,
559 };

◆ jme_smi_bit_mask

Enumerator
SMI_DATA_MASK 
SMI_REG_ADDR_MASK 
SMI_PHY_ADDR_MASK 
SMI_OP_WRITE 
SMI_OP_REQ 
SMI_OP_MDIO 
SMI_OP_MDOE 
SMI_OP_MDC 
SMI_OP_MDEN 

Definition at line 564 of file jme.h.

564  {
565  SMI_DATA_MASK = 0xFFFF0000,
566  SMI_REG_ADDR_MASK = 0x0000F800,
567  SMI_PHY_ADDR_MASK = 0x000007C0,
568  SMI_OP_WRITE = 0x00000020,
569  /* Set to 1, after req done it'll be cleared to 0 */
570  SMI_OP_REQ = 0x00000010,
571  SMI_OP_MDIO = 0x00000008, /* Software assess In/Out */
572  SMI_OP_MDOE = 0x00000004, /* Software Output Enable */
573  SMI_OP_MDC = 0x00000002, /* Software CLK Control */
574  SMI_OP_MDEN = 0x00000001, /* Software access Enable */
575 };

◆ jme_smi_bit_shift

Enumerator
SMI_DATA_SHIFT 
SMI_REG_ADDR_SHIFT 
SMI_PHY_ADDR_SHIFT 

Definition at line 577 of file jme.h.

577  {
578  SMI_DATA_SHIFT = 16,
579  SMI_REG_ADDR_SHIFT = 11,
580  SMI_PHY_ADDR_SHIFT = 6,
581 };

◆ jme_ghc_bit_mask

Enumerator
GHC_SWRST 
GHC_DPX 
GHC_SPEED 
GHC_LINK_POLL 

Definition at line 599 of file jme.h.

599  {
600  GHC_SWRST = 0x40000000,
601  GHC_DPX = 0x00000040,
602  GHC_SPEED = 0x00000030,
603  GHC_LINK_POLL = 0x00000001,
604 };
Definition: jme.h:600
Definition: jme.h:601
Definition: jme.h:602

◆ jme_ghc_speed_val

Enumerator
GHC_SPEED_10M 
GHC_SPEED_100M 
GHC_SPEED_1000M 

Definition at line 606 of file jme.h.

606  {
607  GHC_SPEED_10M = 0x00000010,
608  GHC_SPEED_100M = 0x00000020,
609  GHC_SPEED_1000M = 0x00000030,
610 };

◆ jme_ghc_to_clk

Enumerator
GHC_TO_CLK_OFF 
GHC_TO_CLK_GPHY 
GHC_TO_CLK_PCIE 
GHC_TO_CLK_INVALID 

Definition at line 612 of file jme.h.

612  {
613  GHC_TO_CLK_OFF = 0x00000000,
614  GHC_TO_CLK_GPHY = 0x00400000,
615  GHC_TO_CLK_PCIE = 0x00800000,
616  GHC_TO_CLK_INVALID = 0x00C00000,
617 };

◆ jme_ghc_txmac_clk

Enumerator
GHC_TXMAC_CLK_OFF 
GHC_TXMAC_CLK_GPHY 
GHC_TXMAC_CLK_PCIE 
GHC_TXMAC_CLK_INVALID 

Definition at line 619 of file jme.h.

619  {
620  GHC_TXMAC_CLK_OFF = 0x00000000,
621  GHC_TXMAC_CLK_GPHY = 0x00100000,
622  GHC_TXMAC_CLK_PCIE = 0x00200000,
623  GHC_TXMAC_CLK_INVALID = 0x00300000,
624 };

◆ jme_pmcs_bit_masks

Enumerator
PMCS_WF7DET 
PMCS_WF6DET 
PMCS_WF5DET 
PMCS_WF4DET 
PMCS_WF3DET 
PMCS_WF2DET 
PMCS_WF1DET 
PMCS_WF0DET 
PMCS_LFDET 
PMCS_LRDET 
PMCS_MFDET 
PMCS_WF7EN 
PMCS_WF6EN 
PMCS_WF5EN 
PMCS_WF4EN 
PMCS_WF3EN 
PMCS_WF2EN 
PMCS_WF1EN 
PMCS_WF0EN 
PMCS_LFEN 
PMCS_LREN 
PMCS_MFEN 

Definition at line 629 of file jme.h.

629  {
630  PMCS_WF7DET = 0x80000000,
631  PMCS_WF6DET = 0x40000000,
632  PMCS_WF5DET = 0x20000000,
633  PMCS_WF4DET = 0x10000000,
634  PMCS_WF3DET = 0x08000000,
635  PMCS_WF2DET = 0x04000000,
636  PMCS_WF1DET = 0x02000000,
637  PMCS_WF0DET = 0x01000000,
638  PMCS_LFDET = 0x00040000,
639  PMCS_LRDET = 0x00020000,
640  PMCS_MFDET = 0x00010000,
641  PMCS_WF7EN = 0x00008000,
642  PMCS_WF6EN = 0x00004000,
643  PMCS_WF5EN = 0x00002000,
644  PMCS_WF4EN = 0x00001000,
645  PMCS_WF3EN = 0x00000800,
646  PMCS_WF2EN = 0x00000400,
647  PMCS_WF1EN = 0x00000200,
648  PMCS_WF0EN = 0x00000100,
649  PMCS_LFEN = 0x00000004,
650  PMCS_LREN = 0x00000002,
651  PMCS_MFEN = 0x00000001,
652 };
Definition: jme.h:650
Definition: jme.h:649
Definition: jme.h:651

◆ jme_phy_link_bit_mask

Enumerator
PHY_LINK_SPEED_MASK 
PHY_LINK_DUPLEX 
PHY_LINK_SPEEDDPU_RESOLVED 
PHY_LINK_UP 
PHY_LINK_AUTONEG_COMPLETE 
PHY_LINK_MDI_STAT 

Definition at line 657 of file jme.h.

657  {
658  PHY_LINK_SPEED_MASK = 0x0000C000,
659  PHY_LINK_DUPLEX = 0x00002000,
660  PHY_LINK_SPEEDDPU_RESOLVED = 0x00000800,
661  PHY_LINK_UP = 0x00000400,
662  PHY_LINK_AUTONEG_COMPLETE = 0x00000200,
663  PHY_LINK_MDI_STAT = 0x00000040,
664 };

◆ jme_phy_link_speed_val

Enumerator
PHY_LINK_SPEED_10M 
PHY_LINK_SPEED_100M 
PHY_LINK_SPEED_1000M 

Definition at line 666 of file jme.h.

666  {
667  PHY_LINK_SPEED_10M = 0x00000000,
668  PHY_LINK_SPEED_100M = 0x00004000,
669  PHY_LINK_SPEED_1000M = 0x00008000,
670 };

◆ jme_smbcsr_bit_mask

Enumerator
SMBCSR_CNACK 
SMBCSR_RELOAD 
SMBCSR_EEPROMD 
SMBCSR_INITDONE 
SMBCSR_BUSY 

Definition at line 677 of file jme.h.

677  {
678  SMBCSR_CNACK = 0x00020000,
679  SMBCSR_RELOAD = 0x00010000,
680  SMBCSR_EEPROMD = 0x00000020,
681  SMBCSR_INITDONE = 0x00000010,
682  SMBCSR_BUSY = 0x0000000F,
683 };

◆ jme_smbintf_bit_mask

Enumerator
SMBINTF_HWDATR 
SMBINTF_HWDATW 
SMBINTF_HWADDR 
SMBINTF_HWRWN 
SMBINTF_HWCMD 
SMBINTF_FASTM 
SMBINTF_GPIOSCL 
SMBINTF_GPIOSDA 
SMBINTF_GPIOEN 

Definition at line 685 of file jme.h.

685  {
686  SMBINTF_HWDATR = 0xFF000000,
687  SMBINTF_HWDATW = 0x00FF0000,
688  SMBINTF_HWADDR = 0x0000FF00,
689  SMBINTF_HWRWN = 0x00000020,
690  SMBINTF_HWCMD = 0x00000010,
691  SMBINTF_FASTM = 0x00000008,
692  SMBINTF_GPIOSCL = 0x00000004,
693  SMBINTF_GPIOSDA = 0x00000002,
694  SMBINTF_GPIOEN = 0x00000001,
695 };

◆ jme_smbintf_vals

Enumerator
SMBINTF_HWRWN_READ 
SMBINTF_HWRWN_WRITE 

Definition at line 697 of file jme.h.

697  {
698  SMBINTF_HWRWN_READ = 0x00000020,
699  SMBINTF_HWRWN_WRITE = 0x00000000,
700 };

◆ jme_smbintf_shifts

Enumerator
SMBINTF_HWDATR_SHIFT 
SMBINTF_HWDATW_SHIFT 
SMBINTF_HWADDR_SHIFT 

Definition at line 702 of file jme.h.

◆ jme_tmcsr_bit_masks

Enumerator
TMCSR_SWIT 
TMCSR_EN 
TMCSR_CNT 

Definition at line 716 of file jme.h.

716  {
717  TMCSR_SWIT = 0x80000000,
718  TMCSR_EN = 0x01000000,
719  TMCSR_CNT = 0x00FFFFFF,
720 };
Definition: jme.h:718
Definition: jme.h:719

◆ jme_gpreg0_masks

Enumerator
GPREG0_DISSH 
GPREG0_PCIRLMT 
GPREG0_PCCNOMUTCLR 
GPREG0_LNKINTPOLL 
GPREG0_PCCTMR 
GPREG0_PHYADDR 

Definition at line 725 of file jme.h.

725  {
726  GPREG0_DISSH = 0xFF000000,
727  GPREG0_PCIRLMT = 0x00300000,
728  GPREG0_PCCNOMUTCLR = 0x00040000,
729  GPREG0_LNKINTPOLL = 0x00001000,
730  GPREG0_PCCTMR = 0x00000300,
731  GPREG0_PHYADDR = 0x0000001F,
732 };

◆ jme_gpreg0_vals

Enumerator
GPREG0_DISSH_DW7 
GPREG0_DISSH_DW6 
GPREG0_DISSH_DW5 
GPREG0_DISSH_DW4 
GPREG0_DISSH_DW3 
GPREG0_DISSH_DW2 
GPREG0_DISSH_DW1 
GPREG0_DISSH_DW0 
GPREG0_DISSH_ALL 
GPREG0_PCIRLMT_8 
GPREG0_PCIRLMT_6 
GPREG0_PCIRLMT_5 
GPREG0_PCIRLMT_4 
GPREG0_PCCTMR_16ns 
GPREG0_PCCTMR_256ns 
GPREG0_PCCTMR_1us 
GPREG0_PCCTMR_1ms 
GPREG0_PHYADDR_1 
GPREG0_DEFAULT 

Definition at line 734 of file jme.h.

734  {
735  GPREG0_DISSH_DW7 = 0x80000000,
736  GPREG0_DISSH_DW6 = 0x40000000,
737  GPREG0_DISSH_DW5 = 0x20000000,
738  GPREG0_DISSH_DW4 = 0x10000000,
739  GPREG0_DISSH_DW3 = 0x08000000,
740  GPREG0_DISSH_DW2 = 0x04000000,
741  GPREG0_DISSH_DW1 = 0x02000000,
742  GPREG0_DISSH_DW0 = 0x01000000,
743  GPREG0_DISSH_ALL = 0xFF000000,
744 
745  GPREG0_PCIRLMT_8 = 0x00000000,
746  GPREG0_PCIRLMT_6 = 0x00100000,
747  GPREG0_PCIRLMT_5 = 0x00200000,
748  GPREG0_PCIRLMT_4 = 0x00300000,
749 
750  GPREG0_PCCTMR_16ns = 0x00000000,
751  GPREG0_PCCTMR_256ns = 0x00000100,
752  GPREG0_PCCTMR_1us = 0x00000200,
753  GPREG0_PCCTMR_1ms = 0x00000300,
754 
755  GPREG0_PHYADDR_1 = 0x00000001,
756 
761 };

◆ jme_gpreg1_masks

Enumerator
GPREG1_INTRDELAYUNIT 
GPREG1_INTRDELAYENABLE 

Definition at line 768 of file jme.h.

768  {
769  GPREG1_INTRDELAYUNIT = 0x00000018,
770  GPREG1_INTRDELAYENABLE = 0x00000007,
771 };

◆ jme_gpreg1_vals

Enumerator
GPREG1_RSSPATCH 
GPREG1_HALFMODEPATCH 
GPREG1_INTDLYUNIT_16NS 
GPREG1_INTDLYUNIT_256NS 
GPREG1_INTDLYUNIT_1US 
GPREG1_INTDLYUNIT_16US 
GPREG1_INTDLYEN_1U 
GPREG1_INTDLYEN_2U 
GPREG1_INTDLYEN_3U 
GPREG1_INTDLYEN_4U 
GPREG1_INTDLYEN_5U 
GPREG1_INTDLYEN_6U 
GPREG1_INTDLYEN_7U 
GPREG1_DEFAULT 

Definition at line 773 of file jme.h.

773  {
774  GPREG1_RSSPATCH = 0x00000040,
775  GPREG1_HALFMODEPATCH = 0x00000020,
776 
777  GPREG1_INTDLYUNIT_16NS = 0x00000000,
778  GPREG1_INTDLYUNIT_256NS = 0x00000008,
779  GPREG1_INTDLYUNIT_1US = 0x00000010,
780  GPREG1_INTDLYUNIT_16US = 0x00000018,
781 
782  GPREG1_INTDLYEN_1U = 0x00000001,
783  GPREG1_INTDLYEN_2U = 0x00000002,
784  GPREG1_INTDLYEN_3U = 0x00000003,
785  GPREG1_INTDLYEN_4U = 0x00000004,
786  GPREG1_INTDLYEN_5U = 0x00000005,
787  GPREG1_INTDLYEN_6U = 0x00000006,
788  GPREG1_INTDLYEN_7U = 0x00000007,
789 
790  GPREG1_DEFAULT = 0x00000000,
791 };

◆ jme_interrupt_bits

Enumerator
INTR_SWINTR 
INTR_TMINTR 
INTR_LINKCH 
INTR_PAUSERCV 
INTR_MAGICRCV 
INTR_WAKERCV 
INTR_PCCRX0TO 
INTR_PCCRX1TO 
INTR_PCCRX2TO 
INTR_PCCRX3TO 
INTR_PCCTXTO 
INTR_PCCRX0 
INTR_PCCRX1 
INTR_PCCRX2 
INTR_PCCRX3 
INTR_PCCTX 
INTR_RX3EMP 
INTR_RX2EMP 
INTR_RX1EMP 
INTR_RX0EMP 
INTR_RX3 
INTR_RX2 
INTR_RX1 
INTR_RX0 
INTR_TX7 
INTR_TX6 
INTR_TX5 
INTR_TX4 
INTR_TX3 
INTR_TX2 
INTR_TX1 
INTR_TX0 

Definition at line 796 of file jme.h.

796  {
797  INTR_SWINTR = 0x80000000,
798  INTR_TMINTR = 0x40000000,
799  INTR_LINKCH = 0x20000000,
800  INTR_PAUSERCV = 0x10000000,
801  INTR_MAGICRCV = 0x08000000,
802  INTR_WAKERCV = 0x04000000,
803  INTR_PCCRX0TO = 0x02000000,
804  INTR_PCCRX1TO = 0x01000000,
805  INTR_PCCRX2TO = 0x00800000,
806  INTR_PCCRX3TO = 0x00400000,
807  INTR_PCCTXTO = 0x00200000,
808  INTR_PCCRX0 = 0x00100000,
809  INTR_PCCRX1 = 0x00080000,
810  INTR_PCCRX2 = 0x00040000,
811  INTR_PCCRX3 = 0x00020000,
812  INTR_PCCTX = 0x00010000,
813  INTR_RX3EMP = 0x00008000,
814  INTR_RX2EMP = 0x00004000,
815  INTR_RX1EMP = 0x00002000,
816  INTR_RX0EMP = 0x00001000,
817  INTR_RX3 = 0x00000800,
818  INTR_RX2 = 0x00000400,
819  INTR_RX1 = 0x00000200,
820  INTR_RX0 = 0x00000100,
821  INTR_TX7 = 0x00000080,
822  INTR_TX6 = 0x00000040,
823  INTR_TX5 = 0x00000020,
824  INTR_TX4 = 0x00000010,
825  INTR_TX3 = 0x00000008,
826  INTR_TX2 = 0x00000004,
827  INTR_TX1 = 0x00000002,
828  INTR_TX0 = 0x00000001,
829 };
Definition: jme.h:825
Definition: jme.h:821
Definition: jme.h:828
Definition: jme.h:823
Definition: jme.h:822
Definition: jme.h:817
Definition: jme.h:827
Definition: jme.h:820
Definition: jme.h:826
Definition: jme.h:818
Definition: jme.h:819
Definition: jme.h:824

◆ jme_pccrx_masks

Enumerator
PCCRXTO_MASK 
PCCRX_MASK 

Definition at line 839 of file jme.h.

839  {
840  PCCRXTO_MASK = 0xFFFF0000,
841  PCCRX_MASK = 0x0000FF00,
842 };

◆ jme_pcctx_masks

Enumerator
PCCTXTO_MASK 
PCCTX_MASK 
PCCTX_QS_MASK 

Definition at line 844 of file jme.h.

844  {
845  PCCTXTO_MASK = 0xFFFF0000,
846  PCCTX_MASK = 0x0000FF00,
847  PCCTX_QS_MASK = 0x000000FF,
848 };

◆ jme_pccrx_shifts

Enumerator
PCCRXTO_SHIFT 
PCCRX_SHIFT 

Definition at line 850 of file jme.h.

850  {
851  PCCRXTO_SHIFT = 16,
852  PCCRX_SHIFT = 8,
853 };

◆ jme_pcctx_shifts

Enumerator
PCCTXTO_SHIFT 
PCCTX_SHIFT 

Definition at line 855 of file jme.h.

855  {
856  PCCTXTO_SHIFT = 16,
857  PCCTX_SHIFT = 8,
858 };

◆ jme_pcctx_bits

Enumerator
PCCTXQ0_EN 
PCCTXQ1_EN 
PCCTXQ2_EN 
PCCTXQ3_EN 
PCCTXQ4_EN 
PCCTXQ5_EN 
PCCTXQ6_EN 
PCCTXQ7_EN 

Definition at line 860 of file jme.h.

860  {
861  PCCTXQ0_EN = 0x00000001,
862  PCCTXQ1_EN = 0x00000002,
863  PCCTXQ2_EN = 0x00000004,
864  PCCTXQ3_EN = 0x00000008,
865  PCCTXQ4_EN = 0x00000010,
866  PCCTXQ5_EN = 0x00000020,
867  PCCTXQ6_EN = 0x00000040,
868  PCCTXQ7_EN = 0x00000080,
869 };

◆ jme_chipmode_bit_masks

Enumerator
CM_FPGAVER_MASK 
CM_CHIPREV_MASK 
CM_CHIPMODE_MASK 

Definition at line 874 of file jme.h.

874  {
875  CM_FPGAVER_MASK = 0xFFFF0000,
876  CM_CHIPREV_MASK = 0x0000FF00,
877  CM_CHIPMODE_MASK = 0x0000000F,
878 };

◆ jme_chipmode_shifts

Enumerator
CM_FPGAVER_SHIFT 
CM_CHIPREV_SHIFT 

Definition at line 880 of file jme.h.

880  {
881  CM_FPGAVER_SHIFT = 16,
882  CM_CHIPREV_SHIFT = 8,
883 };

Function Documentation

◆ FILE_LICENCE()

FILE_LICENCE ( GPL2_OR_LATER  )

◆ smi_reg_addr()

static uint32_t smi_reg_addr ( int  x)
inlinestatic

Definition at line 583 of file jme.h.

584 {
585  return (x << SMI_REG_ADDR_SHIFT) & SMI_REG_ADDR_MASK;
586 }

References SMI_REG_ADDR_MASK, and SMI_REG_ADDR_SHIFT.

Referenced by jme_mdio_read(), and jme_mdio_write().

◆ smi_phy_addr()

static uint32_t smi_phy_addr ( int  x)
inlinestatic

Definition at line 588 of file jme.h.

589 {
590  return (x << SMI_PHY_ADDR_SHIFT) & SMI_PHY_ADDR_MASK;
591 }

References SMI_PHY_ADDR_MASK, and SMI_PHY_ADDR_SHIFT.

Referenced by jme_mdio_read(), and jme_mdio_write().

◆ is_buggy250()

static int is_buggy250 ( unsigned short  device,
unsigned int  chiprev 
)
inlinestatic

Definition at line 888 of file jme.h.

889 {
890  return device == PCI_DEVICE_ID_JMICRON_JMC250 && chiprev == 0x11;
891 }
#define PCI_DEVICE_ID_JMICRON_JMC250
Definition: jme.h:27
A hardware device.
Definition: device.h:73
unsigned int chiprev
Definition: jme.h:257

References PCI_DEVICE_ID_JMICRON_JMC250.

Referenced by jme_check_link().

◆ jread32()

static uint32_t jread32 ( struct jme_adapter jme,
uint32_t  reg 
)
inlinestatic

Definition at line 896 of file jme.h.

897 {
898  return readl(jme->regs + reg);
899 }
uint32_t readl(volatile uint32_t *io_addr)
Read 32-bit dword from memory-mapped device.
void * regs
Definition: jme.h:253
static unsigned int unsigned int reg
Definition: intel.h:245

References readl(), reg, and jme_adapter::regs.

Referenced by jme_check_hw_ver(), jme_check_link(), jme_disable_rx_engine(), jme_disable_tx_engine(), jme_load_macaddr(), jme_mdio_read(), jme_mdio_write(), jme_poll(), and jme_reload_eeprom().

◆ jwrite32()

static void jwrite32 ( struct jme_adapter jme,
uint32_t  reg,
uint32_t  val 
)
inlinestatic

Definition at line 901 of file jme.h.

902 {
903  writel(val, jme->regs + reg);
904 }
void * regs
Definition: jme.h:253
void writel(uint32_t data, volatile uint32_t *io_addr)
Write 32-bit dword to memory-mapped device.
static unsigned int unsigned int reg
Definition: intel.h:245
void __asmcall int val
Definition: setjmp.h:28

References reg, jme_adapter::regs, val, and writel().

Referenced by jme_check_link(), jme_disable_rx_engine(), jme_disable_tx_engine(), jme_enable_rx_engine(), jme_enable_tx_engine(), jme_mdio_read(), jme_mdio_write(), jme_poll(), jme_reload_eeprom(), jme_reset_ghc_speed(), jme_reset_mac_processor(), jme_restart_rx_engine(), jme_set_custom_macaddr(), jme_set_multi(), jme_setup_wakeup_frame(), jme_start_irq(), and jme_transmit().

◆ jwrite32f()

static void jwrite32f ( struct jme_adapter jme,
uint32_t  reg,
uint32_t  val 
)
static

Definition at line 906 of file jme.h.

907 {
908  /*
909  * Read after write should cause flush
910  */
911  writel(val, jme->regs + reg);
912  readl(jme->regs + reg);
913 }
uint32_t readl(volatile uint32_t *io_addr)
Read 32-bit dword from memory-mapped device.
void * regs
Definition: jme.h:253
void writel(uint32_t data, volatile uint32_t *io_addr)
Write 32-bit dword to memory-mapped device.
static unsigned int unsigned int reg
Definition: intel.h:245
void __asmcall int val
Definition: setjmp.h:28

References readl(), reg, jme_adapter::regs, val, and writel().

Referenced by jme_stop_irq().

Variable Documentation

◆ INTR_ENABLE

const uint32_t INTR_ENABLE
static
Initial value:

Definition at line 831 of file jme.h.

Referenced by jme_poll(), jme_start_irq(), and jme_stop_irq().