iPXE
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Myson Technology network card driver. More...
Go to the source code of this file.
Data Structures | |
struct | myson_descriptor |
A packet descriptor. More... | |
union | myson_physical_address |
Physical address. More... | |
struct | myson_ring |
A Myson descriptor ring. More... | |
struct | myson_nic |
A myson network card. More... | |
Macros | |
#define | MYSON_BAR_SIZE 256 |
BAR size. More... | |
#define | MYSON_TX_STAT_OWN 0x80000000UL |
Owner. More... | |
#define | MYSON_TX_STAT_ABORT 0x00002000UL |
Abort. More... | |
#define | MYSON_TX_STAT_CSL 0x00001000UL |
Carrier sense lost. More... | |
#define | MYSON_TX_CTRL_IC 0x80000000UL |
Interrupt control. More... | |
#define | MYSON_TX_CTRL_LD 0x20000000UL |
Last descriptor. More... | |
#define | MYSON_TX_CTRL_FD 0x10000000UL |
First descriptor. More... | |
#define | MYSON_TX_CTRL_CRC 0x08000000UL |
CRC append. More... | |
#define | MYSON_TX_CTRL_PAD 0x04000000UL |
Pad control. More... | |
#define | MYSON_TX_CTRL_RTLC 0x02000000UL |
Retry late collision. More... | |
#define | MYSON_TX_CTRL_PKTS(x) ( (x) << 11 ) |
Packet size. More... | |
#define | MYSON_TX_CTRL_TBS(x) ( (x) << 0 ) |
Transmit buffer size. More... | |
#define | MYSON_RX_STAT_OWN 0x80000000UL |
Owner. More... | |
#define | MYSON_RX_STAT_FLNG(status) ( ( (status) >> 16 ) & 0xfff ) |
#define | MYSON_RX_STAT_ES 0x00000080UL |
Error summary. More... | |
#define | MYSON_RX_CTRL_RBS(x) ( (x) << 0 ) |
Receive buffer size. More... | |
#define | MYSON_RING_ALIGN 4 |
Descriptor ring alignment. More... | |
#define | MYSON_PAR0 0x00 |
Physical Address Register 0. More... | |
#define | MYSON_PAR4 0x04 |
Physical Address Register 4. More... | |
#define | MYSON_TCR_RCR 0x18 |
Transmit and Receive Configuration Register. More... | |
#define | MYSON_TCR_TXS 0x80000000UL |
Transmit status. More... | |
#define | MYSON_TCR_TE 0x00040000UL |
Transmit enable. More... | |
#define | MYSON_RCR_RXS 0x00008000UL |
Receive status. More... | |
#define | MYSON_RCR_PROM 0x00000080UL |
Promiscuous mode. More... | |
#define | MYSON_RCR_AB 0x00000040UL |
Accept broadcast. More... | |
#define | MYSON_RCR_AM 0x00000020UL |
Accept multicast. More... | |
#define | MYSON_RCR_ARP 0x00000008UL |
Accept runt packet. More... | |
#define | MYSON_RCR_ALP 0x00000004UL |
Accept long packet. More... | |
#define | MYSON_RCR_RE 0x00000001UL |
Receive enable. More... | |
#define | MYSON_IDLE_MAX_WAIT_MS 100 |
Maximum time to wait for transmit and receive to be idle, in milliseconds. More... | |
#define | MYSON_BCR 0x1c |
Bus Command Register. More... | |
#define | MYSON_BCR_RLE 0x00000100UL |
Read line enable. More... | |
#define | MYSON_BCR_RME 0x00000080UL |
Read multiple enable. More... | |
#define | MYSON_BCR_WIE 0x00000040UL |
Write and invalidate. More... | |
#define | MYSON_BCR_PBL(x) ( (x) << 3 ) |
Burst length. More... | |
#define | MYSON_BCR_PBL_MASK MYSON_BCR_PBL ( 0x7 ) |
#define | MYSON_BCR_PBL_DEFAULT MYSON_BCR_PBL ( 0x6 ) |
#define | MYSON_BCR_SWR 0x00000001UL |
Software reset. More... | |
#define | MYSON_RESET_MAX_WAIT_MS 100 |
Maximum time to wait for a reset, in milliseconds. More... | |
#define | MYSON_TXPDR 0x20 |
Transmit Poll Demand Register. More... | |
#define | MYSON_RXPDR 0x24 |
Receive Poll Demand Register. More... | |
#define | MYSON_TXLBA 0x2c |
Transmit List Base Address. More... | |
#define | MYSON_NUM_TX_DESC 4 |
Number of transmit descriptors. More... | |
#define | MYSON_RXLBA 0x30 |
Receive List Base Address. More... | |
#define | MYSON_NUM_RX_DESC 4 |
Number of receive descriptors. More... | |
#define | MYSON_RX_MAX_LEN ( ETH_FRAME_LEN + 4 /* VLAN */ + 4 /* CRC */ ) |
Receive buffer length. More... | |
#define | MYSON_ISR 0x34 |
Interrupt Status Register. More... | |
#define | MYSON_IRQ_TI 0x00000008UL |
Transmit interrupt. More... | |
#define | MYSON_IRQ_RI 0x00000004UL |
Receive interrupt. More... | |
#define | MYSON_ISR_IODELAY_COUNT 4 |
Number of I/O delays between ISR reads. More... | |
#define | MYSON_IMR 0x38 |
Interrupt Mask Register. More... | |
#define | MYSON_ROM_MII 0x40 |
Boot ROM / EEPROM / MII Management Register. More... | |
#define | MYSON_ROM_AUTOLD 0x00100000UL |
Auto load. More... | |
#define | MYSON_AUTOLD_MAX_WAIT_MS 100 |
Maximum time to wait for a configuration reload, in milliseconds. More... | |
Functions | |
FILE_LICENCE (GPL2_OR_LATER_OR_UBDL) | |
struct myson_descriptor | __attribute__ ((packed)) |
static | __attribute__ ((always_inline)) void myson_init_ring(struct myson_ring *ring |
Initialise descriptor ring. More... | |
Variables | |
uint32_t | status |
Status. More... | |
uint32_t | control |
Control. More... | |
uint32_t | address |
Buffer start address. More... | |
uint32_t | next |
Next descriptor address. More... | |
uint32_t | low |
Low 16 bits of address. More... | |
uint32_t | high |
High 32 bits of address. More... | |
union myson_physical_address | __attribute__ |
static unsigned int | count |
static unsigned int unsigned int | reg |
Myson Technology network card driver.
Definition in file myson.h.
#define MYSON_TX_CTRL_RTLC 0x02000000UL |
#define MYSON_TX_CTRL_TBS | ( | x | ) | ( (x) << 0 ) |
#define MYSON_RX_CTRL_RBS | ( | x | ) | ( (x) << 0 ) |
#define MYSON_TCR_RCR 0x18 |
#define MYSON_IDLE_MAX_WAIT_MS 100 |
#define MYSON_BCR_PBL_MASK MYSON_BCR_PBL ( 0x7 ) |
#define MYSON_BCR_PBL_DEFAULT MYSON_BCR_PBL ( 0x6 ) |
#define MYSON_RESET_MAX_WAIT_MS 100 |
#define MYSON_RX_MAX_LEN ( ETH_FRAME_LEN + 4 /* VLAN */ + 4 /* CRC */ ) |
#define MYSON_ISR_IODELAY_COUNT 4 |
#define MYSON_ROM_MII 0x40 |
#define MYSON_AUTOLD_MAX_WAIT_MS 100 |
FILE_LICENCE | ( | GPL2_OR_LATER_OR_UBDL | ) |
struct myson_descriptor __attribute__ | ( | (packed) | ) |
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inlinestatic |
uint8_t control |
Control.
Control byte.
Definition at line 14 of file myson.h.
Referenced by alloc_form(), ata_command(), block_read(), block_read_capacity(), block_write(), draw_errors(), draw_form(), form_loop(), ibft_install(), layout_form(), linda_close(), linda_ib_epb_ram_xfer(), linda_init_ib_serdes(), linda_open(), load_values(), parse_names(), pci_reset(), qib7322_reset(), save_values(), scsi_command(), skge_rx_done(), skge_rx_refill(), skge_tx_done(), skge_xmit_frame(), TLan_PhyDetect(), TLan_PhyStartLink(), ucode_status(), ucode_update_all(), uhci_describe(), and uhci_endpoint_poll().
uint32_t address |
struct arbelprm_wqe_segment_next next |
Next descriptor address.
Definition at line 18 of file myson.h.
Referenced by aes_setkey(), asn1_okx(), ath5k_handle_rx(), cert_exec(), cms_message(), efi_local_open_path(), efi_path_fetch(), efi_path_guid(), efi_path_mac(), efi_path_uri(), efi_path_vlan(), ehci_ring_alloc(), http_parse_headers(), ice_admin_switch(), icplus_create_ring(), image_argument(), image_asn1(), image_x509(), inline_list_add(), inline_list_add_tail(), inline_list_del(), intelxl_admin_switch(), ipair_rx_pubkey(), ipv6_route_okx(), meme820(), myson_create_ring(), ne_poll(), ns8390_poll(), pem_image_asn1(), rdc_create_ring(), rhine_create_ring(), sis190_free_phy(), tftp_rx_oack(), tls_new_alert(), tls_new_finished(), tls_new_server_hello(), tls_new_server_hello_done(), and xhci_extended_capability().
uint16_t low |
Low 16 bits of address.
Definition at line 19 of file myson.h.
Referenced by arbel_map_vpm(), bigint_mod_exp_raw(), bigint_montgomery_raw(), bigint_montgomery_relaxed_raw(), efi_entropy_tick(), forcedeth_open(), hermon_map_vpm(), initrd_swap(), initrd_swap_any(), pci_bar(), pciea_bar_value(), pit8254_speaker_delay(), tg3_phy_write_and_check_testpat(), usb_bcd(), vmxnet3_get_hw_addr(), vmxnet3_set_ll_addr(), and x25519_reverse().
uint32_t high |
High 32 bits of address.
Definition at line 20 of file myson.h.
Referenced by ar5008_hw_ani_control_old(), arbel_map_vpm(), ath5k_hw_set_ack_bitrate_high(), bigint_montgomery_raw(), bigint_montgomery_relaxed_raw(), hermon_map_vpm(), initrd_swap(), initrd_swap_any(), lldp_fetch(), pci_bar(), pciea_bar_value(), pit8254_speaker_delay(), tg3_phy_write_and_check_testpat(), usb_bcd(), vmxnet3_get_hw_addr(), vmxnet3_set_ll_addr(), and x25519_reverse().
ring reg |
Definition at line 162 of file myson.h.
Referenced by __er32(), __ew32(), __gm_phy_read(), __mdio_read(), __mdio_write(), __vxge_hw_device_register_poll(), __xm_phy_read(), _efx_readl(), _efx_writel(), amd8111e_read_phy(), ar5008_hw_process_ini(), ar9002_hw_load_ani_reg(), ar9003_hw_drive_strength_apply(), ar9003_hw_prog_ini(), ath5k_hw_reg_read(), ath5k_hw_reg_write(), ath5k_hw_write_rate_duration(), ath5k_setup_pwr_to_pdadc_table(), ath9k_hw_analog_shift_regwrite(), ath9k_hw_analog_shift_rmw(), ath9k_hw_check_alive(), ath9k_hw_setrxabort(), ath9k_hw_wait(), ath9k_init_band_txpower(), ath9k_regd_get_ctl(), ath_regd_get_band_ctl(), b44_phy_read(), b44_phy_write(), b44_wait_bit(), bcom_phy_init(), bflush(), bnx2_init_board(), bnx2_read_phy(), bnx2_reset_phy(), bnx2_write_phy(), bnxt_pci_base(), br32(), bw32(), des_setkey(), efx_hunt_clear_interrupts(), efx_hunt_evq_read_ack(), efx_hunt_notify_rx_desc(), efx_hunt_notify_tx_desc(), efx_probe(), efx_readl(), efx_writel(), exanic_clear_base(), exanic_write_base(), falcon_clear_interrupts(), falcon_eventq_read_ack(), falcon_i2c_bit_read(), falcon_i2c_bit_write(), falcon_init_resources(), falcon_init_sram(), falcon_mask_status_intr(), falcon_mdio_read(), falcon_mdio_write(), falcon_notify_rx_desc(), falcon_notify_tx_desc(), falcon_pm8358_phy_init(), falcon_read(), falcon_read_sram(), falcon_readl(), falcon_reconfigure_mac_wrapper(), falcon_reconfigure_xmac(), falcon_reset_xaui(), falcon_reset_xmac(), falcon_setup_nic(), falcon_spi_rw(), falcon_spi_wait(), falcon_tenxpress_phy_init(), falcon_write(), falcon_write_sram(), falcon_writel(), falcon_xaui_link_ok(), falcon_xgmii_status(), forcedeth_map_regs(), genesis_reset(), genesis_stop(), gm_phy_read(), gm_phy_write(), gma_read16(), gma_read32(), gma_set_addr(), hfa384x_copy_from_bap(), hfa384x_docmd_wait(), hfa384x_getreg(), hfa384x_getreg_noswap(), hfa384x_prepare_bap(), hfa384x_setreg(), hfa384x_setreg_noswap(), hfa384x_wait_for_event(), icplus_mii_read_bit(), icplus_mii_write_bit(), intel_disable_ring(), intel_init_ring(), intel_reset_ring(), is_yukon_lite_a0(), jme_mdio_read(), jme_mdio_write(), jread32(), jwrite32(), jwrite32f(), linda_ib_epb_mod_reg(), linda_set_serdes_param(), mdio_clause45_check_mmds(), mdio_read(), mdio_read_latched(), mdio_write(), mentormac_init(), mentormac_reset(), mii_bit_read(), mii_bit_rw(), mii_bit_write(), mii_read(), mii_rw(), mii_write(), natsemi_spi_read_bit(), natsemi_spi_write_bit(), pci_bar(), pci_bar_size(), pci_bar_start(), pci_read_bases(), pcnet32_mdio_read(), pcnet32_mdio_write(), phantom_crb_access_128m(), phantom_crb_access_2m(), phantom_crb_access_32m(), phantom_readl(), phantom_writel(), phy_init(), prism2_poll(), qib7322_ahb_mod_reg_all(), rdc_init_ring(), rdc_mii_read(), rdc_mii_write(), realtek_init_ring(), realtek_mii_read(), realtek_mii_write(), realtek_spi_read_bit(), realtek_spi_write_bit(), rhine_mii_read(), rhine_mii_write(), rtl818x_init_hw(), rtl818x_poll(), rtl818x_probe(), rtl818x_set_anaparam(), rtl818x_spi_read_bit(), rtl818x_spi_write_bit(), rtl818x_start(), rtl818x_stop(), rtl8225_read(), rtl8225_rf_set_tx_power(), rtl8225_rf_stop(), rtl8225_write(), sfe4001_init(), sis190_get_mac_addr(), sis190_get_mac_addr_from_apc(), sis190_mii_probe_88e1111_fixup(), sis190_read_eeprom(), sis190_set_rgmii(), sis630e_get_mac_addr(), skge_read16(), skge_read32(), skge_read8(), skge_reset(), skge_write16(), skge_write32(), skge_write8(), sky2_gmac_reset(), sky2_link_down(), sky2_link_up(), sky2_mac_init(), sky2_pci_read16(), sky2_pci_read32(), sky2_pci_write16(), sky2_pci_write32(), sky2_phy_init(), sky2_power_on(), sky2_read16(), sky2_read32(), sky2_read8(), sky2_set_multicast(), sky2_write16(), sky2_write32(), sky2_write8(), smscusb_mii_read(), smscusb_mii_write(), tg3_phy_auxctl_read(), tg3_phy_auxctl_write(), tg3_phy_toggle_automdix(), tg3_phydsp_write(), tg3_readphy(), tg3_ump_link_report(), tg3_writephy(), TLan_MiiReadReg(), TLan_MiiWriteReg(), velocity_mii_read(), velocity_mii_write(), xhci_writeq(), xm_outaddr(), xm_outhash(), xm_phy_read(), xm_phy_write(), xm_read16(), xm_read32(), yukon_link_up(), and yukon_mac_init().