48 #define TLAN_MIN_FRAME_SIZE 64 49 #define TLAN_MAX_FRAME_SIZE 1600 51 #define TLAN_NUM_RX_LISTS 4 52 #define TLAN_NUM_TX_LISTS 2 59 #define TLAN_DEBUG_GNRL 0x0001 60 #define TLAN_DEBUG_TX 0x0002 61 #define TLAN_DEBUG_RX 0x0004 62 #define TLAN_DEBUG_LIST 0x0008 63 #define TLAN_DEBUG_PROBE 0x0010 65 #define TX_TIMEOUT (10*HZ) 66 #define MAX_TLAN_BOARDS 8 74 #define PCI_DEVICE_ID_NETELLIGENT_10_T2 0xB012 75 #define PCI_DEVICE_ID_NETELLIGENT_10_100_WS_5100 0xB030 76 #ifndef PCI_DEVICE_ID_OLICOM_OC2183 77 #define PCI_DEVICE_ID_OLICOM_OC2183 0x0013 79 #ifndef PCI_DEVICE_ID_OLICOM_OC2325 80 #define PCI_DEVICE_ID_OLICOM_OC2325 0x0012 82 #ifndef PCI_DEVICE_ID_OLICOM_OC2326 83 #define PCI_DEVICE_ID_OLICOM_OC2326 0x0014 94 #define TLAN_ADAPTER_NONE 0x00000000 95 #define TLAN_ADAPTER_UNMANAGED_PHY 0x00000001 96 #define TLAN_ADAPTER_BIT_RATE_PHY 0x00000002 97 #define TLAN_ADAPTER_USE_INTERN_10 0x00000004 98 #define TLAN_ADAPTER_ACTIVITY_LED 0x00000008 100 #define TLAN_SPEED_DEFAULT 0 101 #define TLAN_SPEED_10 10 102 #define TLAN_SPEED_100 100 104 #define TLAN_DUPLEX_DEFAULT 0 105 #define TLAN_DUPLEX_HALF 1 106 #define TLAN_DUPLEX_FULL 2 115 #define EISA_ID 0xc80 116 #define EISA_ID0 0xc80 117 #define EISA_ID1 0xc81 118 #define EISA_ID2 0xc82 119 #define EISA_ID3 0xc83 120 #define EISA_CR 0xc84 121 #define EISA_REG0 0xc88 122 #define EISA_REG1 0xc89 123 #define EISA_REG2 0xc8a 124 #define EISA_REG3 0xc8f 125 #define EISA_APROM 0xc90 134 #define TLAN_BUFFERS_PER_LIST 10 135 #define TLAN_LAST_BUFFER 0x80000000 136 #define TLAN_CSTAT_UNUSED 0x8000 137 #define TLAN_CSTAT_FRM_CMP 0x4000 138 #define TLAN_CSTAT_READY 0x3000 139 #define TLAN_CSTAT_EOC 0x0800 140 #define TLAN_CSTAT_RX_ERROR 0x0400 141 #define TLAN_CSTAT_PASS_CRC 0x0200 142 #define TLAN_CSTAT_DP_PR 0x0100 154 #define TLAN_PHY_MAX_ADDR 0x1F 155 #define TLAN_PHY_NONE 0x20 164 #define TLAN_TIMER_LINK_BEAT 1 165 #define TLAN_TIMER_ACTIVITY 2 166 #define TLAN_TIMER_PHY_PDOWN 3 167 #define TLAN_TIMER_PHY_PUP 4 168 #define TLAN_TIMER_PHY_RESET 5 169 #define TLAN_TIMER_PHY_START_LINK 6 170 #define TLAN_TIMER_PHY_FINISH_AN 7 171 #define TLAN_TIMER_FINISH_RESET 8 173 #define TLAN_TIMER_ACT_DELAY (HZ/10) 183 #define TLAN_EEPROM_ACK 0 184 #define TLAN_EEPROM_STOP 1 194 #define TLAN_HOST_CMD 0x00 195 #define TLAN_HC_GO 0x80000000 196 #define TLAN_HC_STOP 0x40000000 197 #define TLAN_HC_ACK 0x20000000 198 #define TLAN_HC_CS_MASK 0x1FE00000 199 #define TLAN_HC_EOC 0x00100000 200 #define TLAN_HC_RT 0x00080000 201 #define TLAN_HC_NES 0x00040000 202 #define TLAN_HC_AD_RST 0x00008000 203 #define TLAN_HC_LD_TMR 0x00004000 204 #define TLAN_HC_LD_THR 0x00002000 205 #define TLAN_HC_REQ_INT 0x00001000 206 #define TLAN_HC_INT_OFF 0x00000800 207 #define TLAN_HC_INT_ON 0x00000400 208 #define TLAN_HC_AC_MASK 0x000000FF 209 #define TLAN_CH_PARM 0x04 210 #define TLAN_DIO_ADR 0x08 211 #define TLAN_DA_ADR_INC 0x8000 212 #define TLAN_DA_RAM_ADR 0x4000 213 #define TLAN_HOST_INT 0x0A 214 #define TLAN_HI_IV_MASK 0x1FE0 215 #define TLAN_HI_IT_MASK 0x001C 216 #define TLAN_DIO_DATA 0x0C 221 #define TLAN_NET_CMD 0x00 222 #define TLAN_NET_CMD_NRESET 0x80 223 #define TLAN_NET_CMD_NWRAP 0x40 224 #define TLAN_NET_CMD_CSF 0x20 225 #define TLAN_NET_CMD_CAF 0x10 226 #define TLAN_NET_CMD_NOBRX 0x08 227 #define TLAN_NET_CMD_DUPLEX 0x04 228 #define TLAN_NET_CMD_TRFRAM 0x02 229 #define TLAN_NET_CMD_TXPACE 0x01 230 #define TLAN_NET_SIO 0x01 231 #define TLAN_NET_SIO_MINTEN 0x80 232 #define TLAN_NET_SIO_ECLOK 0x40 233 #define TLAN_NET_SIO_ETXEN 0x20 234 #define TLAN_NET_SIO_EDATA 0x10 235 #define TLAN_NET_SIO_NMRST 0x08 236 #define TLAN_NET_SIO_MCLK 0x04 237 #define TLAN_NET_SIO_MTXEN 0x02 238 #define TLAN_NET_SIO_MDATA 0x01 239 #define TLAN_NET_STS 0x02 240 #define TLAN_NET_STS_MIRQ 0x80 241 #define TLAN_NET_STS_HBEAT 0x40 242 #define TLAN_NET_STS_TXSTOP 0x20 243 #define TLAN_NET_STS_RXSTOP 0x10 244 #define TLAN_NET_STS_RSRVD 0x0F 245 #define TLAN_NET_MASK 0x03 246 #define TLAN_NET_MASK_MASK7 0x80 247 #define TLAN_NET_MASK_MASK6 0x40 248 #define TLAN_NET_MASK_MASK5 0x20 249 #define TLAN_NET_MASK_MASK4 0x10 250 #define TLAN_NET_MASK_RSRVD 0x0F 251 #define TLAN_NET_CONFIG 0x04 252 #define TLAN_NET_CFG_RCLK 0x8000 253 #define TLAN_NET_CFG_TCLK 0x4000 254 #define TLAN_NET_CFG_BIT 0x2000 255 #define TLAN_NET_CFG_RXCRC 0x1000 256 #define TLAN_NET_CFG_PEF 0x0800 257 #define TLAN_NET_CFG_1FRAG 0x0400 258 #define TLAN_NET_CFG_1CHAN 0x0200 259 #define TLAN_NET_CFG_MTEST 0x0100 260 #define TLAN_NET_CFG_PHY_EN 0x0080 261 #define TLAN_NET_CFG_MSMASK 0x007F 262 #define TLAN_MAN_TEST 0x06 263 #define TLAN_DEF_VENDOR_ID 0x08 264 #define TLAN_DEF_DEVICE_ID 0x0A 265 #define TLAN_DEF_REVISION 0x0C 266 #define TLAN_DEF_SUBCLASS 0x0D 267 #define TLAN_DEF_MIN_LAT 0x0E 268 #define TLAN_DEF_MAX_LAT 0x0F 269 #define TLAN_AREG_0 0x10 270 #define TLAN_AREG_1 0x16 271 #define TLAN_AREG_2 0x1C 272 #define TLAN_AREG_3 0x22 273 #define TLAN_HASH_1 0x28 274 #define TLAN_HASH_2 0x2C 275 #define TLAN_GOOD_TX_FRMS 0x30 276 #define TLAN_TX_UNDERUNS 0x33 277 #define TLAN_GOOD_RX_FRMS 0x34 278 #define TLAN_RX_OVERRUNS 0x37 279 #define TLAN_DEFERRED_TX 0x38 280 #define TLAN_CRC_ERRORS 0x3A 281 #define TLAN_CODE_ERRORS 0x3B 282 #define TLAN_MULTICOL_FRMS 0x3C 283 #define TLAN_SINGLECOL_FRMS 0x3E 284 #define TLAN_EXCESSCOL_FRMS 0x40 285 #define TLAN_LATE_COLS 0x41 286 #define TLAN_CARRIER_LOSS 0x42 287 #define TLAN_ACOMMIT 0x43 288 #define TLAN_LED_REG 0x44 289 #define TLAN_LED_ACT 0x10 290 #define TLAN_LED_LINK 0x01 291 #define TLAN_BSIZE_REG 0x45 292 #define TLAN_MAX_RX 0x46 293 #define TLAN_INT_DIS 0x48 294 #define TLAN_ID_TX_EOC 0x04 295 #define TLAN_ID_RX_EOF 0x02 296 #define TLAN_ID_RX_EOC 0x01 302 #define TLAN_INT_NUMBER_OF_INTS 8 304 #define TLAN_INT_NONE 0x0000 305 #define TLAN_INT_TX_EOF 0x0001 306 #define TLAN_INT_STAT_OVERFLOW 0x0002 307 #define TLAN_INT_RX_EOF 0x0003 308 #define TLAN_INT_DUMMY 0x0004 309 #define TLAN_INT_TX_EOC 0x0005 310 #define TLAN_INT_STATUS_CHECK 0x0006 311 #define TLAN_INT_RX_EOC 0x0007 319 #define TLAN_TLPHY_ID 0x10 320 #define TLAN_TLPHY_CTL 0x11 321 #define TLAN_TC_IGLINK 0x8000 322 #define TLAN_TC_SWAPOL 0x4000 323 #define TLAN_TC_AUISEL 0x2000 324 #define TLAN_TC_SQEEN 0x1000 325 #define TLAN_TC_MTEST 0x0800 326 #define TLAN_TC_RESERVED 0x07F8 327 #define TLAN_TC_NFEW 0x0004 328 #define TLAN_TC_INTEN 0x0002 329 #define TLAN_TC_TINT 0x0001 330 #define TLAN_TLPHY_STS 0x12 331 #define TLAN_TS_MINT 0x8000 332 #define TLAN_TS_PHOK 0x4000 333 #define TLAN_TS_POLOK 0x2000 334 #define TLAN_TS_TPENERGY 0x1000 335 #define TLAN_TS_RESERVED 0x0FFF 336 #define TLAN_TLPHY_PAR 0x19 337 #define TLAN_PHY_CIM_STAT 0x0020 338 #define TLAN_PHY_SPEED_100 0x0040 339 #define TLAN_PHY_DUPLEX_FULL 0x0080 340 #define TLAN_PHY_AN_EN_STAT 0x0400 343 #define NAT_SEM_ID1 0x2000 344 #define NAT_SEM_ID2 0x5C01 345 #define LEVEL1_ID1 0x7810 346 #define LEVEL1_ID2 0x0000 348 #define CIRC_INC( a, b ) if ( ++a >= b ) a = 0 434 #define TLan_ClearBit( bit, port ) outb_p(inb_p(port) & ~bit, port) 435 #define TLan_GetBit( bit, port ) ((int) (inb_p(port) & bit)) 436 #define TLan_SetBit( bit, port ) outb_p(inb_p(port) | bit, port) 438 #ifdef I_LIKE_A_FAST_HASH_FUNCTION 445 hash = (a[0] ^ a[3]);
446 hash ^= ((a[0] ^ a[3]) >> 6);
447 hash ^= ((a[1] ^ a[4]) << 2);
448 hash ^= ((a[1] ^ a[4]) >> 4);
449 hash ^= ((a[2] ^ a[5]) << 4);
450 hash ^= ((a[2] ^ a[5]) >> 2);
459 return ((a && !b) || (!a && b));
462 #define XOR8( a, b, c, d, e, f, g, h ) xor( a, xor( b, xor( c, xor( d, xor( e, xor( f, xor( g, h ) ) ) ) ) ) ) 463 #define DA( a, bit ) ( ( (u8) a[bit/8] ) & ( (u8) ( 1 << bit%8 ) ) ) 470 XOR8(
DA(a, 0),
DA(a, 6),
DA(a, 12),
DA(a, 18),
DA(a, 24),
471 DA(a, 30),
DA(a, 36),
DA(a, 42));
473 XOR8(
DA(a, 1),
DA(a, 7),
DA(a, 13),
DA(a, 19),
DA(a, 25),
474 DA(a, 31),
DA(a, 37),
DA(a, 43)) << 1;
476 XOR8(
DA(a, 2),
DA(a, 8),
DA(a, 14),
DA(a, 20),
DA(a, 26),
477 DA(a, 32),
DA(a, 38),
DA(a, 44)) << 2;
479 XOR8(
DA(a, 3),
DA(a, 9),
DA(a, 15),
DA(a, 21),
DA(a, 27),
480 DA(a, 33),
DA(a, 39),
DA(a, 45)) << 3;
482 XOR8(
DA(a, 4),
DA(a, 10),
DA(a, 16),
DA(a, 22),
DA(a, 28),
483 DA(a, 34),
DA(a, 40),
DA(a, 46)) << 4;
485 XOR8(
DA(a, 5),
DA(a, 11),
DA(a, 17),
DA(a, 23),
DA(a, 29),
486 DA(a, 35),
DA(a, 41),
DA(a, 47)) << 5;
pseudo_bit_t hash[0x00010]
static u32 TLan_DioRead32(u16 base_addr, u16 internal_addr)
#define outb_p(data, io_addr)
Write byte to I/O-mapped device, slowly.
static u16 TLan_DioRead16(u16 base_addr, u16 internal_addr)
uint16_t inw(volatile uint16_t *io_addr)
Read 16-bit word from I/O-mapped device.
#define TLan_ClearBit(bit, port)
#define outw(data, io_addr)
static u8 TLan_DioRead8(u16 base_addr, u16 internal_addr)
struct tlan_adapter_entry TLanAdapterEntry
static unsigned int unsigned int bit
static void TLan_DioWrite16(u16 base_addr, u16 internal_addr, u16 data)
#define TLan_SetBit(bit, port)
static u32 xor(u32 a, u32 b)
#define inb_p(io_addr)
Read byte from I/O-mapped device.
FILE_LICENCE(GPL2_OR_LATER)
#define outl(data, io_addr)
#define XOR8(a, b, c, d, e, f, g, h)
#define TLan_GetBit(bit, port)
static u32 TLan_HashFunc(u8 *a)
uint8_t inb(volatile uint8_t *io_addr)
Read byte from I/O-mapped device.
#define outb(data, io_addr)
uint32_t inl(volatile uint32_t *io_addr)
Read 32-bit dword from I/O-mapped device.
uint8_t data[48]
Additional event data.
static void TLan_DioWrite8(u16 base_addr, u16 internal_addr, u8 data)
static void TLan_DioWrite32(u16 base_addr, u16 internal_addr, u32 data)