iPXE
tlan.h
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1 /**************************************************************************
2 *
3 * tlan.c -- Etherboot device driver for the Texas Instruments ThunderLAN
4 * Written 2003-2003 by Timothy Legge <tlegge@rogers.com>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
19 * 02110-1301, USA.
20 *
21 * Portions of this code (almost all) based on:
22 * tlan.c: Linux ThunderLan Driver:
23 *
24 * by James Banks
25 *
26 * (C) 1997-1998 Caldera, Inc.
27 * (C) 1998 James Banks
28 * (C) 1999-2001 Torben Mathiasen
29 * (C) 2002 Samuel Chessman
30 *
31 * REVISION HISTORY:
32 * ================
33 * v1.0 07-08-2003 timlegge Initial not quite working version
34 *
35 * Indent Style: indent -kr -i8
36 ***************************************************************************/
37 
38 FILE_LICENCE ( GPL2_OR_LATER );
39 
40 /*****************************************************************
41 * TLan Definitions
42 *
43 ****************************************************************/
44 
45 #define FALSE 0
46 #define TRUE 1
47 
48 #define TLAN_MIN_FRAME_SIZE 64
49 #define TLAN_MAX_FRAME_SIZE 1600
50 
51 #define TLAN_NUM_RX_LISTS 4
52 #define TLAN_NUM_TX_LISTS 2
53 
54 #define TLAN_IGNORE 0
55 #define TLAN_RECORD 1
56 /*
57 #define TLAN_DBG(lvl, format, args...) if (debug&lvl) printf("TLAN: " format, ##args );
58 */
59 #define TLAN_DEBUG_GNRL 0x0001
60 #define TLAN_DEBUG_TX 0x0002
61 #define TLAN_DEBUG_RX 0x0004
62 #define TLAN_DEBUG_LIST 0x0008
63 #define TLAN_DEBUG_PROBE 0x0010
64 
65 #define TX_TIMEOUT (10*HZ) /* We need time for auto-neg */
66 #define MAX_TLAN_BOARDS 8 /* Max number of boards installed at a time */
67 
68 
69  /*****************************************************************
70  * Device Identification Definitions
71  *
72  ****************************************************************/
73 
74 #define PCI_DEVICE_ID_NETELLIGENT_10_T2 0xB012
75 #define PCI_DEVICE_ID_NETELLIGENT_10_100_WS_5100 0xB030
76 #ifndef PCI_DEVICE_ID_OLICOM_OC2183
77 #define PCI_DEVICE_ID_OLICOM_OC2183 0x0013
78 #endif
79 #ifndef PCI_DEVICE_ID_OLICOM_OC2325
80 #define PCI_DEVICE_ID_OLICOM_OC2325 0x0012
81 #endif
82 #ifndef PCI_DEVICE_ID_OLICOM_OC2326
83 #define PCI_DEVICE_ID_OLICOM_OC2326 0x0014
84 #endif
85 
86 typedef struct tlan_adapter_entry {
89  char *deviceLabel;
93 
94 #define TLAN_ADAPTER_NONE 0x00000000
95 #define TLAN_ADAPTER_UNMANAGED_PHY 0x00000001
96 #define TLAN_ADAPTER_BIT_RATE_PHY 0x00000002
97 #define TLAN_ADAPTER_USE_INTERN_10 0x00000004
98 #define TLAN_ADAPTER_ACTIVITY_LED 0x00000008
99 
100 #define TLAN_SPEED_DEFAULT 0
101 #define TLAN_SPEED_10 10
102 #define TLAN_SPEED_100 100
103 
104 #define TLAN_DUPLEX_DEFAULT 0
105 #define TLAN_DUPLEX_HALF 1
106 #define TLAN_DUPLEX_FULL 2
107 
108 
109 
110  /*****************************************************************
111  * EISA Definitions
112  *
113  ****************************************************************/
114 
115 #define EISA_ID 0xc80 /* EISA ID Registers */
116 #define EISA_ID0 0xc80 /* EISA ID Register 0 */
117 #define EISA_ID1 0xc81 /* EISA ID Register 1 */
118 #define EISA_ID2 0xc82 /* EISA ID Register 2 */
119 #define EISA_ID3 0xc83 /* EISA ID Register 3 */
120 #define EISA_CR 0xc84 /* EISA Control Register */
121 #define EISA_REG0 0xc88 /* EISA Configuration Register 0 */
122 #define EISA_REG1 0xc89 /* EISA Configuration Register 1 */
123 #define EISA_REG2 0xc8a /* EISA Configuration Register 2 */
124 #define EISA_REG3 0xc8f /* EISA Configuration Register 3 */
125 #define EISA_APROM 0xc90 /* Ethernet Address PROM */
126 
127 
128 
129  /*****************************************************************
130  * Rx/Tx List Definitions
131  *
132  ****************************************************************/
133 
134 #define TLAN_BUFFERS_PER_LIST 10
135 #define TLAN_LAST_BUFFER 0x80000000
136 #define TLAN_CSTAT_UNUSED 0x8000
137 #define TLAN_CSTAT_FRM_CMP 0x4000
138 #define TLAN_CSTAT_READY 0x3000
139 #define TLAN_CSTAT_EOC 0x0800
140 #define TLAN_CSTAT_RX_ERROR 0x0400
141 #define TLAN_CSTAT_PASS_CRC 0x0200
142 #define TLAN_CSTAT_DP_PR 0x0100
143 
144 
145 
146 
147 
148 
149  /*****************************************************************
150  * PHY definitions
151  *
152  ****************************************************************/
153 
154 #define TLAN_PHY_MAX_ADDR 0x1F
155 #define TLAN_PHY_NONE 0x20
156 
157 
158 
159  /*****************************************************************
160  * TLan Driver Timer Definitions
161  *
162  ****************************************************************/
163 
164 #define TLAN_TIMER_LINK_BEAT 1
165 #define TLAN_TIMER_ACTIVITY 2
166 #define TLAN_TIMER_PHY_PDOWN 3
167 #define TLAN_TIMER_PHY_PUP 4
168 #define TLAN_TIMER_PHY_RESET 5
169 #define TLAN_TIMER_PHY_START_LINK 6
170 #define TLAN_TIMER_PHY_FINISH_AN 7
171 #define TLAN_TIMER_FINISH_RESET 8
172 
173 #define TLAN_TIMER_ACT_DELAY (HZ/10)
174 
175 
176 
177 
178  /*****************************************************************
179  * TLan Driver Eeprom Definitions
180  *
181  ****************************************************************/
182 
183 #define TLAN_EEPROM_ACK 0
184 #define TLAN_EEPROM_STOP 1
185 
186 
187 
188 
189  /*****************************************************************
190  * Host Register Offsets and Contents
191  *
192  ****************************************************************/
193 
194 #define TLAN_HOST_CMD 0x00
195 #define TLAN_HC_GO 0x80000000
196 #define TLAN_HC_STOP 0x40000000
197 #define TLAN_HC_ACK 0x20000000
198 #define TLAN_HC_CS_MASK 0x1FE00000
199 #define TLAN_HC_EOC 0x00100000
200 #define TLAN_HC_RT 0x00080000
201 #define TLAN_HC_NES 0x00040000
202 #define TLAN_HC_AD_RST 0x00008000
203 #define TLAN_HC_LD_TMR 0x00004000
204 #define TLAN_HC_LD_THR 0x00002000
205 #define TLAN_HC_REQ_INT 0x00001000
206 #define TLAN_HC_INT_OFF 0x00000800
207 #define TLAN_HC_INT_ON 0x00000400
208 #define TLAN_HC_AC_MASK 0x000000FF
209 #define TLAN_CH_PARM 0x04
210 #define TLAN_DIO_ADR 0x08
211 #define TLAN_DA_ADR_INC 0x8000
212 #define TLAN_DA_RAM_ADR 0x4000
213 #define TLAN_HOST_INT 0x0A
214 #define TLAN_HI_IV_MASK 0x1FE0
215 #define TLAN_HI_IT_MASK 0x001C
216 #define TLAN_DIO_DATA 0x0C
217 
218 
219 /* ThunderLAN Internal Register DIO Offsets */
220 
221 #define TLAN_NET_CMD 0x00
222 #define TLAN_NET_CMD_NRESET 0x80
223 #define TLAN_NET_CMD_NWRAP 0x40
224 #define TLAN_NET_CMD_CSF 0x20
225 #define TLAN_NET_CMD_CAF 0x10
226 #define TLAN_NET_CMD_NOBRX 0x08
227 #define TLAN_NET_CMD_DUPLEX 0x04
228 #define TLAN_NET_CMD_TRFRAM 0x02
229 #define TLAN_NET_CMD_TXPACE 0x01
230 #define TLAN_NET_SIO 0x01
231 #define TLAN_NET_SIO_MINTEN 0x80
232 #define TLAN_NET_SIO_ECLOK 0x40
233 #define TLAN_NET_SIO_ETXEN 0x20
234 #define TLAN_NET_SIO_EDATA 0x10
235 #define TLAN_NET_SIO_NMRST 0x08
236 #define TLAN_NET_SIO_MCLK 0x04
237 #define TLAN_NET_SIO_MTXEN 0x02
238 #define TLAN_NET_SIO_MDATA 0x01
239 #define TLAN_NET_STS 0x02
240 #define TLAN_NET_STS_MIRQ 0x80
241 #define TLAN_NET_STS_HBEAT 0x40
242 #define TLAN_NET_STS_TXSTOP 0x20
243 #define TLAN_NET_STS_RXSTOP 0x10
244 #define TLAN_NET_STS_RSRVD 0x0F
245 #define TLAN_NET_MASK 0x03
246 #define TLAN_NET_MASK_MASK7 0x80
247 #define TLAN_NET_MASK_MASK6 0x40
248 #define TLAN_NET_MASK_MASK5 0x20
249 #define TLAN_NET_MASK_MASK4 0x10
250 #define TLAN_NET_MASK_RSRVD 0x0F
251 #define TLAN_NET_CONFIG 0x04
252 #define TLAN_NET_CFG_RCLK 0x8000
253 #define TLAN_NET_CFG_TCLK 0x4000
254 #define TLAN_NET_CFG_BIT 0x2000
255 #define TLAN_NET_CFG_RXCRC 0x1000
256 #define TLAN_NET_CFG_PEF 0x0800
257 #define TLAN_NET_CFG_1FRAG 0x0400
258 #define TLAN_NET_CFG_1CHAN 0x0200
259 #define TLAN_NET_CFG_MTEST 0x0100
260 #define TLAN_NET_CFG_PHY_EN 0x0080
261 #define TLAN_NET_CFG_MSMASK 0x007F
262 #define TLAN_MAN_TEST 0x06
263 #define TLAN_DEF_VENDOR_ID 0x08
264 #define TLAN_DEF_DEVICE_ID 0x0A
265 #define TLAN_DEF_REVISION 0x0C
266 #define TLAN_DEF_SUBCLASS 0x0D
267 #define TLAN_DEF_MIN_LAT 0x0E
268 #define TLAN_DEF_MAX_LAT 0x0F
269 #define TLAN_AREG_0 0x10
270 #define TLAN_AREG_1 0x16
271 #define TLAN_AREG_2 0x1C
272 #define TLAN_AREG_3 0x22
273 #define TLAN_HASH_1 0x28
274 #define TLAN_HASH_2 0x2C
275 #define TLAN_GOOD_TX_FRMS 0x30
276 #define TLAN_TX_UNDERUNS 0x33
277 #define TLAN_GOOD_RX_FRMS 0x34
278 #define TLAN_RX_OVERRUNS 0x37
279 #define TLAN_DEFERRED_TX 0x38
280 #define TLAN_CRC_ERRORS 0x3A
281 #define TLAN_CODE_ERRORS 0x3B
282 #define TLAN_MULTICOL_FRMS 0x3C
283 #define TLAN_SINGLECOL_FRMS 0x3E
284 #define TLAN_EXCESSCOL_FRMS 0x40
285 #define TLAN_LATE_COLS 0x41
286 #define TLAN_CARRIER_LOSS 0x42
287 #define TLAN_ACOMMIT 0x43
288 #define TLAN_LED_REG 0x44
289 #define TLAN_LED_ACT 0x10
290 #define TLAN_LED_LINK 0x01
291 #define TLAN_BSIZE_REG 0x45
292 #define TLAN_MAX_RX 0x46
293 #define TLAN_INT_DIS 0x48
294 #define TLAN_ID_TX_EOC 0x04
295 #define TLAN_ID_RX_EOF 0x02
296 #define TLAN_ID_RX_EOC 0x01
297 
298 
299 
300 /* ThunderLAN Interrupt Codes */
301 
302 #define TLAN_INT_NUMBER_OF_INTS 8
303 
304 #define TLAN_INT_NONE 0x0000
305 #define TLAN_INT_TX_EOF 0x0001
306 #define TLAN_INT_STAT_OVERFLOW 0x0002
307 #define TLAN_INT_RX_EOF 0x0003
308 #define TLAN_INT_DUMMY 0x0004
309 #define TLAN_INT_TX_EOC 0x0005
310 #define TLAN_INT_STATUS_CHECK 0x0006
311 #define TLAN_INT_RX_EOC 0x0007
312 
313 
314 
315 /* ThunderLAN MII Registers */
316 
317 /* ThunderLAN Specific MII/PHY Registers */
318 
319 #define TLAN_TLPHY_ID 0x10
320 #define TLAN_TLPHY_CTL 0x11
321 #define TLAN_TC_IGLINK 0x8000
322 #define TLAN_TC_SWAPOL 0x4000
323 #define TLAN_TC_AUISEL 0x2000
324 #define TLAN_TC_SQEEN 0x1000
325 #define TLAN_TC_MTEST 0x0800
326 #define TLAN_TC_RESERVED 0x07F8
327 #define TLAN_TC_NFEW 0x0004
328 #define TLAN_TC_INTEN 0x0002
329 #define TLAN_TC_TINT 0x0001
330 #define TLAN_TLPHY_STS 0x12
331 #define TLAN_TS_MINT 0x8000
332 #define TLAN_TS_PHOK 0x4000
333 #define TLAN_TS_POLOK 0x2000
334 #define TLAN_TS_TPENERGY 0x1000
335 #define TLAN_TS_RESERVED 0x0FFF
336 #define TLAN_TLPHY_PAR 0x19
337 #define TLAN_PHY_CIM_STAT 0x0020
338 #define TLAN_PHY_SPEED_100 0x0040
339 #define TLAN_PHY_DUPLEX_FULL 0x0080
340 #define TLAN_PHY_AN_EN_STAT 0x0400
341 
342 /* National Sem. & Level1 PHY id's */
343 #define NAT_SEM_ID1 0x2000
344 #define NAT_SEM_ID2 0x5C01
345 #define LEVEL1_ID1 0x7810
346 #define LEVEL1_ID2 0x0000
347 
348 #define CIRC_INC( a, b ) if ( ++a >= b ) a = 0
349 
350 /* Routines to access internal registers. */
351 
352 static inline u8 TLan_DioRead8(u16 base_addr, u16 internal_addr)
353 {
354  outw(internal_addr, base_addr + TLAN_DIO_ADR);
355  return (inb((base_addr + TLAN_DIO_DATA) + (internal_addr & 0x3)));
356 
357 } /* TLan_DioRead8 */
358 
359 
360 
361 
362 static inline u16 TLan_DioRead16(u16 base_addr, u16 internal_addr)
363 {
364  outw(internal_addr, base_addr + TLAN_DIO_ADR);
365  return (inw((base_addr + TLAN_DIO_DATA) + (internal_addr & 0x2)));
366 
367 } /* TLan_DioRead16 */
368 
369 
370 
371 
372 static inline u32 TLan_DioRead32(u16 base_addr, u16 internal_addr)
373 {
374  outw(internal_addr, base_addr + TLAN_DIO_ADR);
375  return (inl(base_addr + TLAN_DIO_DATA));
376 
377 } /* TLan_DioRead32 */
378 
379 
380 
381 
382 static inline void TLan_DioWrite8(u16 base_addr, u16 internal_addr, u8 data)
383 {
384  outw(internal_addr, base_addr + TLAN_DIO_ADR);
385  outb(data, base_addr + TLAN_DIO_DATA + (internal_addr & 0x3));
386 
387 }
388 
389 
390 
391 
392 static inline void TLan_DioWrite16(u16 base_addr, u16 internal_addr, u16 data)
393 {
394  outw(internal_addr, base_addr + TLAN_DIO_ADR);
395  outw(data, base_addr + TLAN_DIO_DATA + (internal_addr & 0x2));
396 
397 }
398 
399 
400 
401 
402 static inline void TLan_DioWrite32(u16 base_addr, u16 internal_addr, u32 data)
403 {
404  outw(internal_addr, base_addr + TLAN_DIO_ADR);
405  outl(data, base_addr + TLAN_DIO_DATA + (internal_addr & 0x2));
406 
407 }
408 
409 
410 
411 #if 0
412 static inline void TLan_ClearBit(u8 bit, u16 port)
413 {
414  outb_p(inb_p(port) & ~bit, port);
415 }
416 
417 
418 
419 
420 static inline int TLan_GetBit(u8 bit, u16 port)
421 {
422  return ((int) (inb_p(port) & bit));
423 }
424 
425 
426 
427 
428 static inline void TLan_SetBit(u8 bit, u16 port)
429 {
430  outb_p(inb_p(port) | bit, port);
431 }
432 #endif
433 
434 #define TLan_ClearBit( bit, port ) outb_p(inb_p(port) & ~bit, port)
435 #define TLan_GetBit( bit, port ) ((int) (inb_p(port) & bit))
436 #define TLan_SetBit( bit, port ) outb_p(inb_p(port) | bit, port)
437 
438 #ifdef I_LIKE_A_FAST_HASH_FUNCTION
439 /* given 6 bytes, view them as 8 6-bit numbers and return the XOR of those */
440 /* the code below is about seven times as fast as the original code */
441 static inline u32 TLan_HashFunc(u8 * a)
442 {
443  u8 hash;
444 
445  hash = (a[0] ^ a[3]); /* & 077 */
446  hash ^= ((a[0] ^ a[3]) >> 6); /* & 003 */
447  hash ^= ((a[1] ^ a[4]) << 2); /* & 074 */
448  hash ^= ((a[1] ^ a[4]) >> 4); /* & 017 */
449  hash ^= ((a[2] ^ a[5]) << 4); /* & 060 */
450  hash ^= ((a[2] ^ a[5]) >> 2); /* & 077 */
451 
452  return (hash & 077);
453 }
454 
455 #else /* original code */
456 
457 static inline u32 xor(u32 a, u32 b)
458 {
459  return ((a && !b) || (!a && b));
460 }
461 
462 #define XOR8( a, b, c, d, e, f, g, h ) xor( a, xor( b, xor( c, xor( d, xor( e, xor( f, xor( g, h ) ) ) ) ) ) )
463 #define DA( a, bit ) ( ( (u8) a[bit/8] ) & ( (u8) ( 1 << bit%8 ) ) )
464 
465 static inline u32 TLan_HashFunc(u8 * a)
466 {
467  u32 hash;
468 
469  hash =
470  XOR8(DA(a, 0), DA(a, 6), DA(a, 12), DA(a, 18), DA(a, 24),
471  DA(a, 30), DA(a, 36), DA(a, 42));
472  hash |=
473  XOR8(DA(a, 1), DA(a, 7), DA(a, 13), DA(a, 19), DA(a, 25),
474  DA(a, 31), DA(a, 37), DA(a, 43)) << 1;
475  hash |=
476  XOR8(DA(a, 2), DA(a, 8), DA(a, 14), DA(a, 20), DA(a, 26),
477  DA(a, 32), DA(a, 38), DA(a, 44)) << 2;
478  hash |=
479  XOR8(DA(a, 3), DA(a, 9), DA(a, 15), DA(a, 21), DA(a, 27),
480  DA(a, 33), DA(a, 39), DA(a, 45)) << 3;
481  hash |=
482  XOR8(DA(a, 4), DA(a, 10), DA(a, 16), DA(a, 22), DA(a, 28),
483  DA(a, 34), DA(a, 40), DA(a, 46)) << 4;
484  hash |=
485  XOR8(DA(a, 5), DA(a, 11), DA(a, 17), DA(a, 23), DA(a, 29),
486  DA(a, 35), DA(a, 41), DA(a, 47)) << 5;
487 
488  return hash;
489 
490 }
491 
492 #endif /* I_LIKE_A_FAST_HASH_FUNCTION */
uint16_t u16
Definition: stdint.h:21
u32 flags
Definition: tlan.h:90
static u32 TLan_DioRead32(u16 base_addr, u16 internal_addr)
Definition: tlan.h:372
#define TLAN_DIO_ADR
Definition: tlan.h:210
#define outb_p(data, io_addr)
Write byte to I/O-mapped device, slowly.
Definition: io.h:461
static u16 TLan_DioRead16(u16 base_addr, u16 internal_addr)
Definition: tlan.h:362
uint16_t inw(volatile uint16_t *io_addr)
Read 16-bit word from I/O-mapped device.
#define TLan_ClearBit(bit, port)
Definition: tlan.h:434
static unsigned int unsigned int bit
Definition: bigint.h:196
#define outw(data, io_addr)
Definition: io.h:319
static u8 TLan_DioRead8(u16 base_addr, u16 internal_addr)
Definition: tlan.h:352
struct tlan_adapter_entry TLanAdapterEntry
static void TLan_DioWrite16(u16 base_addr, u16 internal_addr, u16 data)
Definition: tlan.h:392
uint32_t a
Definition: md4.c:28
#define TLan_SetBit(bit, port)
Definition: tlan.h:436
static u32 xor(u32 a, u32 b)
Definition: tlan.h:457
Definition: tlan.h:86
#define inb_p(io_addr)
Read byte from I/O-mapped device.
Definition: io.h:425
FILE_LICENCE(GPL2_OR_LATER)
u8 port
Port number.
Definition: CIB_PRM.h:31
u16 deviceId
Definition: tlan.h:88
#define DA(a, bit)
Definition: tlan.h:463
pseudo_bit_t hash[0x00010]
Hash algorithm.
Definition: arbel.h:13
#define outl(data, io_addr)
Definition: io.h:329
char * deviceLabel
Definition: tlan.h:89
#define XOR8(a, b, c, d, e, f, g, h)
Definition: tlan.h:462
uint64_t base_addr
Definition: multiboot.h:13
#define TLan_GetBit(bit, port)
Definition: tlan.h:435
static u32 TLan_HashFunc(u8 *a)
Definition: tlan.h:465
uint8_t inb(volatile uint8_t *io_addr)
Read byte from I/O-mapped device.
#define outb(data, io_addr)
Definition: io.h:309
u16 addrOfs
Definition: tlan.h:91
uint32_t inl(volatile uint32_t *io_addr)
Read 32-bit dword from I/O-mapped device.
uint32_t b
Definition: md4.c:29
#define TLAN_DIO_DATA
Definition: tlan.h:216
static void TLan_DioWrite8(u16 base_addr, u16 internal_addr, u8 data)
Definition: tlan.h:382
struct arbelprm_port_state_change_st data
Message.
Definition: arbel.h:12
uint8_t u8
Definition: stdint.h:19
uint32_t u32
Definition: stdint.h:23
static void TLan_DioWrite32(u16 base_addr, u16 internal_addr, u32 data)
Definition: tlan.h:402
u16 vendorId
Definition: tlan.h:87