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| #define | u8 unsigned char |
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| #define | u16 unsigned short |
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| #define | u32 unsigned int |
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| #define | __u32 u32 |
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| #define | VERROR -1 |
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| #define | CHAR_HEIGHT 16 |
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| #define | LINES 25 |
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| #define | COLS 80 |
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| #define | write_crtc(data, addr) outb(addr,CRT_IC); outb(data,CRT_DC) |
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| #define | write_att(data, addr) inb(IS1_RC); inb(0x80); outb(addr,ATT_IW); inb(0x80); outb(data,ATT_IW); inb(0x80) |
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| #define | write_seq(data, addr) outb(addr,SEQ_I); outb(data,SEQ_D) |
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| #define | write_gra(data, addr) outb(addr,GRA_I); outb(data,GRA_D) |
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| #define | vga_hardware_fixup() do{} while(0) |
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| #define | SYNC_HOR_HIGH_ACT 1 /* horizontal sync high active */ |
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| #define | SYNC_VERT_HIGH_ACT 2 /* vertical sync high active */ |
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| #define | SYNC_EXT 4 /* external sync */ |
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| #define | SYNC_COMP_HIGH_ACT 8 /* composite sync high active */ |
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| #define | SYNC_BROADCAST 16 /* broadcast video timings */ |
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| #define | SYNC_ON_GREEN 32 /* sync on green */ |
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| #define | VMODE_NONINTERLACED 0 /* non interlaced */ |
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| #define | VMODE_INTERLACED 1 /* interlaced */ |
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| #define | VMODE_DOUBLE 2 /* double scan */ |
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| #define | VMODE_MASK 255 |
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| #define | VMODE_YWRAP 256 /* ywrap instead of panning */ |
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| #define | VMODE_SMOOTH_XPAN 512 /* smooth xpan possible (internally used) */ |
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| #define | VMODE_CONUPDATE 512 /* don't update x/yoffset */ |
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| #define | CRT_DC 0x3D5 /* CRT Controller Data Register - color emulation */ |
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| #define | CRT_DM 0x3B5 /* CRT Controller Data Register - mono emulation */ |
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| #define | ATT_R 0x3C1 /* Attribute Controller Data Read Register */ |
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| #define | GRA_D 0x3CF /* Graphics Controller Data Register */ |
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| #define | SEQ_D 0x3C5 /* Sequencer Data Register */ |
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| #define | MIS_R 0x3CC |
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| #define | MIS_W 0x3C2 |
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| #define | IS1_RC 0x3DA /* Input Status Register 1 - color emulation */ |
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| #define | IS1_RM 0x3BA /* Input Status Register 1 - mono emulation */ |
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| #define | PEL_D 0x3C9 /* PEL Data Register */ |
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| #define | PEL_MSK 0x3C6 /* PEL mask register */ |
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| #define | GRA_E0 0x3CC /* Graphics enable processor 0 */ |
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| #define | GRA_E1 0x3CA /* Graphics enable processor 1 */ |
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| #define | CRT_IC 0x3D4 /* CRT Controller Index - color emulation */ |
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| #define | CRT_IM 0x3B4 /* CRT Controller Index - mono emulation */ |
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| #define | ATT_IW 0x3C0 /* Attribute Controller Index & Data Write Register */ |
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| #define | GRA_I 0x3CE /* Graphics Controller Index */ |
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| #define | SEQ_I 0x3C4 /* Sequencer Index */ |
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| #define | PEL_IW 0x3C8 /* PEL Write Index */ |
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| #define | PEL_IR 0x3C7 /* PEL Read Index */ |
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| #define | CRTC_C 25 /* 25 CRT Controller Registers sequentially set*/ |
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| #define | ATT_C 21 /* 21 Attribute Controller Registers */ |
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| #define | GRA_C 9 /* 9 Graphics Controller Registers */ |
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| #define | SEQ_C 5 /* 5 Sequencer Registers */ |
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| #define | MIS_C 1 /* 1 Misc Output Register */ |
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| #define | CRTC_H_TOTAL 0 |
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| #define | CRTC_H_DISP 1 |
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| #define | CRTC_H_BLANK_START 2 |
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| #define | CRTC_H_BLANK_END 3 |
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| #define | CRTC_H_SYNC_START 4 |
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| #define | CRTC_H_SYNC_END 5 |
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| #define | CRTC_V_TOTAL 6 |
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| #define | CRTC_OVERFLOW 7 |
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| #define | CRTC_PRESET_ROW 8 |
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| #define | CRTC_MAX_SCAN 9 |
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| #define | CRTC_CURSOR_START 0x0A |
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| #define | CRTC_CURSOR_END 0x0B |
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| #define | CRTC_START_HI 0x0C |
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| #define | CRTC_START_LO 0x0D |
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| #define | CRTC_CURSOR_HI 0x0E |
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| #define | CRTC_CURSOR_LO 0x0F |
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| #define | CRTC_V_SYNC_START 0x10 |
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| #define | CRTC_V_SYNC_END 0x11 |
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| #define | CRTC_V_DISP_END 0x12 |
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| #define | CRTC_OFFSET 0x13 |
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| #define | CRTC_UNDERLINE 0x14 |
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| #define | CRTC_V_BLANK_START 0x15 |
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| #define | CRTC_V_BLANK_END 0x16 |
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| #define | CRTC_MODE 0x17 |
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| #define | CRTC_LINE_COMPARE 0x18 |
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| #define | ATC_MODE 0x10 |
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| #define | ATC_OVERSCAN 0x11 |
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| #define | ATC_PLANE_ENABLE 0x12 |
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| #define | ATC_PEL 0x13 |
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| #define | ATC_COLOR_PAGE 0x14 |
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| #define | SEQ_CLOCK_MODE 0x01 |
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| #define | SEQ_PLANE_WRITE 0x02 |
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| #define | SEQ_CHARACTER_MAP 0x03 |
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| #define | SEQ_MEMORY_MODE 0x04 |
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| #define | GDC_SR_VALUE 0x00 |
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| #define | GDC_SR_ENABLE 0x01 |
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| #define | GDC_COMPARE_VALUE 0x02 |
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| #define | GDC_DATA_ROTATE 0x03 |
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| #define | GDC_PLANE_READ 0x04 |
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| #define | GDC_MODE 0x05 |
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| #define | GDC_MISC 0x06 |
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| #define | GDC_COMPARE_MASK 0x07 |
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| #define | GDC_BIT_MASK 0x08 |
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| #define | VGA_ATTR_CLR_RED 0x4 |
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| #define | VGA_ATTR_CLR_GRN 0x2 |
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| #define | VGA_ATTR_CLR_BLU 0x1 |
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| #define | VGA_ATTR_CLR_YEL (VGA_ATTR_CLR_RED | VGA_ATTR_CLR_GRN) |
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| #define | VGA_ATTR_CLR_CYN (VGA_ATTR_CLR_GRN | VGA_ATTR_CLR_BLU) |
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| #define | VGA_ATTR_CLR_MAG (VGA_ATTR_CLR_BLU | VGA_ATTR_CLR_RED) |
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| #define | VGA_ATTR_CLR_BLK 0 |
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| #define | VGA_ATTR_CLR_WHT (VGA_ATTR_CLR_RED | VGA_ATTR_CLR_GRN | VGA_ATTR_CLR_BLU) |
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| #define | VGA_ATTR_BNK 0x80 |
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| #define | VGA_ATTR_ITN 0x08 |
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