iPXE
vga.h File Reference

Go to the source code of this file.

Data Structures

struct  vga_par
struct  fb_bitfield
struct  screeninfo

Macros

#define u8   unsigned char
#define u16   unsigned short
#define u32   unsigned int
#define __u32   u32
#define VERROR   -1
#define CHAR_HEIGHT   16
#define LINES   25
#define COLS   80
#define write_crtc(data, addr)
#define write_att(data, addr)
#define write_seq(data, addr)
#define write_gra(data, addr)
#define vga_hardware_fixup()
#define SYNC_HOR_HIGH_ACT   1 /* horizontal sync high active */
#define SYNC_VERT_HIGH_ACT   2 /* vertical sync high active */
#define SYNC_EXT   4 /* external sync */
#define SYNC_COMP_HIGH_ACT   8 /* composite sync high active */
#define SYNC_BROADCAST   16 /* broadcast video timings */
#define SYNC_ON_GREEN   32 /* sync on green */
#define VMODE_NONINTERLACED   0 /* non interlaced */
#define VMODE_INTERLACED   1 /* interlaced */
#define VMODE_DOUBLE   2 /* double scan */
#define VMODE_MASK   255
#define VMODE_YWRAP   256 /* ywrap instead of panning */
#define VMODE_SMOOTH_XPAN   512 /* smooth xpan possible (internally used) */
#define VMODE_CONUPDATE   512 /* don't update x/yoffset */
#define CRT_DC   0x3D5 /* CRT Controller Data Register - color emulation */
#define CRT_DM   0x3B5 /* CRT Controller Data Register - mono emulation */
#define ATT_R   0x3C1 /* Attribute Controller Data Read Register */
#define GRA_D   0x3CF /* Graphics Controller Data Register */
#define SEQ_D   0x3C5 /* Sequencer Data Register */
#define MIS_R   0x3CC
#define MIS_W   0x3C2
#define IS1_RC   0x3DA /* Input Status Register 1 - color emulation */
#define IS1_RM   0x3BA /* Input Status Register 1 - mono emulation */
#define PEL_D   0x3C9 /* PEL Data Register */
#define PEL_MSK   0x3C6 /* PEL mask register */
#define GRA_E0   0x3CC /* Graphics enable processor 0 */
#define GRA_E1   0x3CA /* Graphics enable processor 1 */
#define CRT_IC   0x3D4 /* CRT Controller Index - color emulation */
#define CRT_IM   0x3B4 /* CRT Controller Index - mono emulation */
#define ATT_IW   0x3C0 /* Attribute Controller Index & Data Write Register */
#define GRA_I   0x3CE /* Graphics Controller Index */
#define SEQ_I   0x3C4 /* Sequencer Index */
#define PEL_IW   0x3C8 /* PEL Write Index */
#define PEL_IR   0x3C7 /* PEL Read Index */
#define CRTC_C   25 /* 25 CRT Controller Registers sequentially set*/
#define ATT_C   21 /* 21 Attribute Controller Registers */
#define GRA_C   9 /* 9 Graphics Controller Registers */
#define SEQ_C   5 /* 5 Sequencer Registers */
#define MIS_C   1 /* 1 Misc Output Register */
#define CRTC_H_TOTAL   0
#define CRTC_H_DISP   1
#define CRTC_H_BLANK_START   2
#define CRTC_H_BLANK_END   3
#define CRTC_H_SYNC_START   4
#define CRTC_H_SYNC_END   5
#define CRTC_V_TOTAL   6
#define CRTC_OVERFLOW   7
#define CRTC_PRESET_ROW   8
#define CRTC_MAX_SCAN   9
#define CRTC_CURSOR_START   0x0A
#define CRTC_CURSOR_END   0x0B
#define CRTC_START_HI   0x0C
#define CRTC_START_LO   0x0D
#define CRTC_CURSOR_HI   0x0E
#define CRTC_CURSOR_LO   0x0F
#define CRTC_V_SYNC_START   0x10
#define CRTC_V_SYNC_END   0x11
#define CRTC_V_DISP_END   0x12
#define CRTC_OFFSET   0x13
#define CRTC_UNDERLINE   0x14
#define CRTC_V_BLANK_START   0x15
#define CRTC_V_BLANK_END   0x16
#define CRTC_MODE   0x17
#define CRTC_LINE_COMPARE   0x18
#define ATC_MODE   0x10
#define ATC_OVERSCAN   0x11
#define ATC_PLANE_ENABLE   0x12
#define ATC_PEL   0x13
#define ATC_COLOR_PAGE   0x14
#define SEQ_CLOCK_MODE   0x01
#define SEQ_PLANE_WRITE   0x02
#define SEQ_CHARACTER_MAP   0x03
#define SEQ_MEMORY_MODE   0x04
#define GDC_SR_VALUE   0x00
#define GDC_SR_ENABLE   0x01
#define GDC_COMPARE_VALUE   0x02
#define GDC_DATA_ROTATE   0x03
#define GDC_PLANE_READ   0x04
#define GDC_MODE   0x05
#define GDC_MISC   0x06
#define GDC_COMPARE_MASK   0x07
#define GDC_BIT_MASK   0x08
#define VGA_ATTR_CLR_RED   0x4
#define VGA_ATTR_CLR_GRN   0x2
#define VGA_ATTR_CLR_BLU   0x1
#define VGA_ATTR_CLR_YEL   (VGA_ATTR_CLR_RED | VGA_ATTR_CLR_GRN)
#define VGA_ATTR_CLR_CYN   (VGA_ATTR_CLR_GRN | VGA_ATTR_CLR_BLU)
#define VGA_ATTR_CLR_MAG   (VGA_ATTR_CLR_BLU | VGA_ATTR_CLR_RED)
#define VGA_ATTR_CLR_BLK   0
#define VGA_ATTR_CLR_WHT   (VGA_ATTR_CLR_RED | VGA_ATTR_CLR_GRN | VGA_ATTR_CLR_BLU)
#define VGA_ATTR_BNK   0x80
#define VGA_ATTR_ITN   0x08

Functions

u8 read_seq_b (u16 addr)
u8 read_gra_b (u16 addr)
u8 read_crtc_b (u16 addr)
u8 read_att_b (u16 addr)

Macro Definition Documentation

◆ u8

#define u8   unsigned char

Definition at line 19 of file vga.h.

◆ u16

uint16_t u16   unsigned short

Definition at line 20 of file vga.h.

Referenced by __ath9k_hw_4k_fill_eeprom(), __ath9k_hw_ar9287_fill_eeprom(), __ath9k_hw_def_fill_eeprom(), __ath9k_hw_usb_4k_fill_eeprom(), __ath9k_hw_usb_ar9287_fill_eeprom(), __ath9k_hw_usb_def_fill_eeprom(), __attribute__(), bnx2::__attribute__(), __get_unaligned_le16(), __gm_phy_read(), __gm_phy_read(), __vxge_hw_desc_offset_up(), __vxge_hw_device_pci_e_init(), __xm_phy_read(), amd79c901_read_mode(), amd8111e_poll(), amd8111e_wait_tx_ring(), ar5008_hw_force_bias(), ar5008_hw_set_channel(), ar5008_hw_set_rf_regs(), ar9002_hw_set_channel(), ar9003_calc_ptr_chksum(), ar9003_hw_ant_ctrl_chain_get(), ar9003_hw_atten_apply(), ar9003_hw_atten_chain_get(), ar9003_hw_atten_chain_get_margin(), ar9003_hw_eeprom_get_cck_tgt_pwr(), ar9003_hw_eeprom_get_ht20_tgt_pwr(), ar9003_hw_eeprom_get_ht40_tgt_pwr(), ar9003_hw_eeprom_get_tgt_pwr(), ar9003_hw_get_direct_edge_power(), ar9003_hw_get_indirect_edge_power(), ar9003_hw_get_max_edge_power(), ar9003_hw_set_channel(), ar9003_hw_set_power_per_rate_table(), ar9003_hw_set_target_power_eeprom(), ar9287_eeprom_get_tx_gain_index(), ar9287_eeprom_olpc_set_pdadcs(), ar9300_comp_cksum(), ar9300_eeprom_read_byte(), ar9300_eeprom_read_word(), ar9300_eeprom_restore_flash(), ar9300_eeprom_restore_internal(), ath5k_channel_ok(), ath5k_config(), ath5k_create_power_curve(), ath5k_eeprom_bin2freq(), ath5k_eeprom_init_11a_pcal_freq(), ath5k_eeprom_init_header(), ath5k_eeprom_is_hb63(), ath5k_eeprom_read_ants(), ath5k_eeprom_read_ctl_info(), ath5k_eeprom_read_freq_list(), ath5k_eeprom_read_mac(), ath5k_eeprom_read_modes(), ath5k_eeprom_read_pcal_info_2413(), ath5k_eeprom_read_pcal_info_5111(), ath5k_eeprom_read_pcal_info_5112(), ath5k_eeprom_read_target_rate_pwr_info(), ath5k_eeprom_read_turbo_modes(), ath5k_get_pcdac_intercepts(), ath5k_hw_disable_pspoll(), ath5k_hw_eeprom_read(), ath5k_hw_enable_pspoll(), ath5k_hw_get_txdp(), ath5k_hw_post(), ath5k_hw_radio_revision(), ath5k_hw_reg_read(), ath5k_hw_reg_write(), ath5k_hw_reset_key(), ath5k_hw_rf2425_channel(), ath5k_hw_rf5112_channel(), ath5k_hw_rfb_op(), ath5k_hw_set_associd(), ath5k_hw_set_capabilities(), ath5k_hw_set_power(), ath5k_hw_set_txdp(), ath5k_hw_write_rate_duration(), ath5k_setup_channel_powertable(), ath5k_setup_rate_powertable(), ath5k_txbuf_setup(), ath9k_adjust_pdadc_values(), ath9k_change_gain_boundary_setting(), ath9k_cmn_update_txpow(), ath9k_config(), ath9k_get_txgain_index(), ath9k_hw_4k_check_eeprom(), ath9k_hw_4k_get_eeprom(), ath9k_hw_4k_get_spur_channel(), ath9k_hw_4k_set_txpower(), ath9k_hw_ar9287_check_eeprom(), ath9k_hw_ar9287_get_eeprom(), ath9k_hw_ar9287_get_spur_channel(), ath9k_hw_ar9287_set_txpower(), ath9k_hw_ar9300_get_spur_channel(), ath9k_hw_ar9300_set_txpower(), ath9k_hw_computetxtime(), ath9k_hw_def_check_eeprom(), ath9k_hw_def_get_spur_channel(), ath9k_hw_def_set_addac(), ath9k_hw_def_set_txpower(), ath9k_hw_fbin2freq(), ath9k_hw_fbin2freq(), ath9k_hw_fill_cap_info(), ath9k_hw_fill_vpd_table(), ath9k_hw_get_gain_boundaries_pdadcs(), ath9k_hw_get_legacy_target_powers(), ath9k_hw_get_lower_upper_index(), ath9k_hw_get_max_edge_power(), ath9k_hw_get_target_powers(), ath9k_hw_init_macaddr(), ath9k_hw_interpolate(), ath9k_hw_nvram_read(), ath9k_hw_probe(), ath9k_hw_rf_name(), ath9k_hw_set_4k_power_cal_table(), ath9k_hw_set_4k_power_per_rate_table(), ath9k_hw_set_ar9287_power_cal_table(), ath9k_hw_set_ar9287_power_per_rate_table(), ath9k_hw_set_def_power_cal_table(), ath9k_hw_set_def_power_per_rate_table(), ath9k_hw_set_rf_regs(), ath9k_hw_set_rx_bufsize(), ath9k_hw_usb_gen_fill_eeprom(), ath9k_init_crypto(), ath9k_init_device(), ath9k_init_softc(), ath_hw_keyreset(), ath_is_49ghz_allowed(), ath_pci_eeprom_read(), ath_pci_probe(), atl1e_auto_get_fc(), atl1e_check_link(), atl1e_clean_rx_irq(), atl1e_clean_rx_ring(), atl1e_clean_tx_irq(), atl1e_clean_tx_ring(), atl1e_clear_phy_int(), atl1e_configure_des_ring(), atl1e_configure_rx(), atl1e_get_speed_and_duplex(), atl1e_get_tpd(), atl1e_mdio_read(), atl1e_phy_commit(), atl1e_phy_init(), atl1e_phy_setup_autoneg_adv(), atl1e_read_phy_reg(), atl1e_reset_hw(), atl1e_setup_pcicmd(), atl1e_tpd_avail(), atl1e_tx_map(), atl1e_tx_queue(), atl1e_write_phy_reg(), atl1e_xmit_frame(), b44_process_rx_packets(), b44_read_eeprom(), bcom_check_link(), bcom_phy_init(), bcom_phy_intr(), bnx2_alloc_bad_rbuf(), bnx2_init_chip(), bnx2_init_rx_ring(), bnx2_poll(), bnx2_set_power_state_0(), bnx2_transmit(), bnxt_add_vlan(), bnxt_adv_cq_index(), bnxt_adv_nq_index(), bnxt_alloc_rx_iob(), bnxt_get_link_speed(), bnxt_get_pci_info(), bnxt_get_phy_link(), bnxt_get_pkt_vlan(), bnxt_hwrm_backing_store_cfg(), bnxt_hwrm_backing_store_qcfg(), bnxt_hwrm_cfa_l2_filter_alloc(), bnxt_hwrm_cfa_l2_filter_free(), bnxt_hwrm_error_recovery_req(), bnxt_hwrm_func_cfg_req(), bnxt_hwrm_func_drv_rgtr(), bnxt_hwrm_func_drv_unrgtr(), bnxt_hwrm_func_qcaps_req(), bnxt_hwrm_func_qcfg_req(), bnxt_hwrm_func_reset_req(), bnxt_hwrm_func_resource_qcaps(), bnxt_hwrm_nvm_get_variable_req(), bnxt_hwrm_port_mac_cfg(), bnxt_hwrm_port_phy_cfg(), bnxt_hwrm_port_phy_qcaps_req(), bnxt_hwrm_port_phy_qcfg(), bnxt_hwrm_queue_qportcfg(), bnxt_hwrm_ring_alloc(), bnxt_hwrm_ring_alloc_grp(), bnxt_hwrm_ring_free(), bnxt_hwrm_ring_free_grp(), bnxt_hwrm_set_async_event(), bnxt_hwrm_set_rx_mask(), bnxt_hwrm_stat_ctx_alloc(), bnxt_hwrm_stat_ctx_free(), bnxt_hwrm_ver_get(), bnxt_hwrm_vnic_alloc(), bnxt_hwrm_vnic_cfg(), bnxt_hwrm_vnic_free(), bnxt_post_rx_buffers(), bnxt_query_phy_link(), bnxt_rx_drop(), bnxt_service_cq(), bnxt_service_nq(), bnxt_set_rx_desc(), bnxt_tx(), bnxt_tx_adjust_pkt(), bnxt_tx_complete(), ccmp_cbc_mac(), ccmp_ctr_xor(), ccmp_kie_decrypt(), cmdif_rev(), davicom_disable(), dm9132_id_table(), dm9132_id_table(), dmfe_parse_srom(), dmfe_probe(), dmfe_set_phyxcer(), dmfe_transmit(), FILE_LICENCE(), fw_rev_min(), fw_rev_sub(), genesis_link_up(), genesis_stop(), get_hw_packet_type(), get_unaligned_le16(), gm_phy_read(), gm_phy_read(), gm_phy_write(), gm_phy_write(), gma_read16(), gma_read16(), gma_set_addr(), gma_set_addr(), gma_write16(), gma_write16(), golan_complete(), hwrm_init(), igbvf_check_for_ack_vf(), igbvf_check_for_msg_vf(), igbvf_check_for_rst_vf(), igbvf_get_link_up_info_vf(), igbvf_hash_mc_addr_vf(), igbvf_poll_for_ack(), igbvf_poll_for_msg(), igbvf_read_mbx_vf(), igbvf_read_pcie_cap_reg(), igbvf_read_posted_mbx(), igbvf_rlpml_set_vf(), igbvf_update_mc_addr_list_vf(), igbvf_vfta_set_vf(), igbvf_write_mbx_vf(), igbvf_write_posted_mbx(), jme_phy_init(), mdio_read(), mdio_read_latched(), memsetw(), mii_resolve_flowctrl_fdx(), net80211_cts_duration(), net80211_duration(), net80211_handle_mgmt(), net80211_ll_pull(), net80211_probe_step(), net80211_process_capab(), net80211_process_ie(), net80211_rate_is_erp(), net80211_rx(), net80211_set_rtscts_rate(), net80211_set_state(), net80211_tx_mgmt(), net80211_tx_mgmt(), nv_restore_phy(), parse_eeprom(), pcnet32_dwio_read_bcr(), pcnet32_dwio_read_csr(), pcnet32_dwio_read_rap(), pcnet32_dwio_write_bcr(), pcnet32_dwio_write_csr(), pcnet32_dwio_write_rap(), pcnet32_irq_enable(), pcnet32_mdio_read(), pcnet32_open(), pcnet32_poll(), pcnet32_process_rx_packets(), pcnet32_process_tx_packets(), pcnet32_refill_rx_ring(), pcnet32_setup_if_duplex(), pcnet32_wio_read_bcr(), pcnet32_wio_read_csr(), pcnet32_wio_read_rap(), pcnet32_wio_write_bcr(), pcnet32_wio_write_csr(), pcnet32_wio_write_rap(), phy_length(), phy_read(), phy_read(), phy_read_1bit(), phy_write(), phy_write(), rc80211_init(), rc80211_update_rx(), read_att_b(), read_crtc_b(), read_gra_b(), read_seq_b(), read_srom_word(), ror16(), rtl818x_init_hw(), rtl818x_ioread16(), rtl818x_iowrite16(), rtl818x_poll(), rtl818x_probe(), rtl818x_set_hwaddr(), rtl818x_tx(), rtl8225_read(), rtl8225_write(), rtl8225x_rf_init(), S(), sec80211_find_rsn(), select_media(), set_rx_mode(), short_hwrm_cmd_req(), sis190_default_phy(), sis190_get_mac_addr_from_eeprom(), sis190_init_phy(), sis190_init_rxfilter(), sis190_mii_probe(), sis190_mii_probe_88e1111_fixup(), sis190_phy_task(), sis190_read_eeprom(), sis190_set_rx_mode(), sis635_get_mac_addr(), sis900_get_mac_addr(), sis900_init_rxfilter(), sis900_mdio_read(), sis900_probe(), sis900_read_eeprom(), sis900_read_mode(), sis900_set_rx_mode(), sis96x_get_mac_addr(), skge_qset(), skge_ramset(), skge_read16(), skge_reset(), skge_rx_done(), skge_write16(), sky2_autoneg_done(), sky2_down(), sky2_gmac_reset(), sky2_hw_intr(), sky2_le_error(), sky2_link_down(), sky2_link_up(), sky2_mac_init(), sky2_pci_read16(), sky2_pci_write16(), sky2_phy_init(), sky2_phy_intr(), sky2_phy_power_down(), sky2_phy_speed(), sky2_poll(), sky2_put_idx(), sky2_qset(), sky2_ramset(), sky2_read16(), sky2_receive(), sky2_reset(), sky2_set_multicast(), sky2_status_intr(), sky2_tx_complete(), sky2_tx_done(), sky2_write16(), sundance_probe(), sundance_reset(), sundance_transmit(), tg3_advert_flowctrl_1000T(), tg3_advert_flowctrl_1000X(), tg3_aux_stat_to_speed_duplex(), tg3_chip_reset(), tg3_fiber_aneg_smachine(), tg3_get_eeprom_hw_cfg(), tg3_get_invariants(), tg3_reset_hw(), tg3_resolve_flowctrl_1000X(), tg3_restore_pci_state(), tg3_rx_complete(), tg3_setup_copper_phy(), tg3_setup_fiber_hw_autoneg(), tg3_setup_fiber_mii_phy(), tg3_setup_fiber_phy(), tkip_decrypt(), tkip_kie_decrypt(), tkip_mix_2(), TLan_DioRead16(), TLan_DioRead32(), TLan_DioRead8(), TLan_DioWrite16(), TLan_DioWrite32(), TLan_DioWrite8(), TLan_EeReadByte(), TLan_EeReceiveByte(), TLan_EeSendByte(), TLan_EeSendStart(), TLan_FinishReset(), TLan_FinishReset(), TLan_MiiReadReg(), TLan_MiiSendData(), TLan_MiiSync(), TLan_MiiWriteReg(), TLan_PhyDetect(), TLan_PhyFinishAutoNeg(), TLan_PhyPowerDown(), TLan_PhyPowerUp(), TLan_PhyReset(), TLan_PhyStartLink(), tlan_poll(), tlan_probe(), TLan_ResetAdapter(), tlan_transmit(), tulip_probe(), tulip_reset(), tulip_transmit(), virtnet_probe_legacy(), virtnet_probe_modern(), vp_alloc_vq(), vp_find_vq(), vpm_find_vqs(), vpm_ioread16(), vpm_iowrite16(), vpm_notify(), vxge_hw_fifo_txd_offset_up(), vxge_hw_ring_rxd_offset_up(), vxge_hw_vpath_poll_rx(), w89c840_probe(), w89c840_transmit(), wait_resp(), xm_check_link(), xm_link_timer(), xm_outaddr(), xm_outhash(), xm_phy_init(), xm_phy_read(), xm_phy_write(), xm_read16(), xm_write16(), yukon_init(), yukon_link_down(), yukon_link_up(), yukon_phy_intr(), yukon_speed(), and yukon_suspend().

◆ u32

uint32_t u32   unsigned int

Definition at line 21 of file vga.h.

Referenced by __attribute__(), bnx2::__attribute__(), __er32(), __ew32(), __get_unaligned_le32(), __mdio_cmd(), __tg3_set_coalesce(), __tg3_set_mac_addr(), __tg3_set_rx_mode(), __vxge_hw_device_access_rights_get(), __vxge_hw_device_host_info_get(), __vxge_hw_device_initialize(), __vxge_hw_device_reg_addr_get(), __vxge_hw_device_register_poll(), __vxge_hw_non_offload_db_post(), __vxge_hw_pio_mem_write32_lower(), __vxge_hw_pio_mem_write32_upper(), __vxge_hw_pio_mem_write64(), __vxge_hw_ring_create(), __vxge_hw_vp_initialize(), __vxge_hw_vpath_addr_get(), __vxge_hw_vpath_addr_get(), __vxge_hw_vpath_card_info_get(), __vxge_hw_vpath_enable(), __vxge_hw_vpath_func_id_get(), __vxge_hw_vpath_fw_ver_get(), __vxge_hw_vpath_initialize(), __vxge_hw_vpath_kdfc_configure(), __vxge_hw_vpath_mgmt_read(), __vxge_hw_vpath_pci_func_mode_get(), __vxge_hw_vpath_pci_read(), __vxge_hw_vpath_reset(), __vxge_hw_vpath_tim_configure(), _tw32_flush(), amd8111e_poll_link(), amd8111e_probe_ext_phy(), amd8111e_read_phy(), amd8111e_wait_link(), ar5008_hw_ani_cache_ini_regs(), ar5008_hw_ani_control_new(), ar5008_hw_ani_control_old(), ar5008_hw_attach_phy_ops(), ar5008_hw_compute_pll_control(), ar5008_hw_force_bias(), ar5008_hw_init_bb(), ar5008_hw_override_ini(), ar5008_hw_phy_modify_rx_buffer(), ar5008_hw_process_ini(), ar5008_hw_rfbus_done(), ar5008_hw_set_channel(), ar5008_hw_set_channel_regs(), ar5008_hw_set_delta_slope(), ar5008_hw_set_radar_params(), ar5008_hw_set_rf_regs(), ar5008_hw_set_rfmode(), ar5008_rf_bank_setup(), ar5008_set_diversity(), ar5008_write_rf_array(), ar9002_hw_adc_dccal_calibrate(), ar9002_hw_adc_gaincal_calibrate(), ar9002_hw_antdiv_comb_conf_get(), ar9002_hw_antdiv_comb_conf_set(), ar9002_hw_compute_pll_control(), ar9002_hw_configpcipowersave(), ar9002_hw_fill_txdesc(), ar9002_hw_get_desc_link(), ar9002_hw_get_isr(), ar9002_hw_get_radiorev(), ar9002_hw_init_mode_gain_regs(), ar9002_hw_iqcalibrate(), ar9002_hw_load_ani_reg(), ar9002_hw_proc_txdesc(), ar9002_hw_rf_claim(), ar9002_hw_set11n_aggr_first(), ar9002_hw_set11n_aggr_middle(), ar9002_hw_set11n_ratescenario(), ar9002_hw_set11n_txdesc(), ar9002_hw_set_channel(), ar9002_hw_set_desc_link(), ar9002_olc_init(), ar9003_get_pll_sqsum_dvc(), ar9003_hw_ani_cache_ini_regs(), ar9003_hw_ani_control(), ar9003_hw_ant_ctrl_apply(), ar9003_hw_ant_ctrl_common_2_get(), ar9003_hw_ant_ctrl_common_get(), ar9003_hw_antdiv_comb_conf_get(), ar9003_hw_antdiv_comb_conf_set(), ar9003_hw_attach_phy_ops(), ar9003_hw_compute_pll_control(), ar9003_hw_disable_phy_restart(), ar9003_hw_fill_txdesc(), ar9003_hw_get_desc_link(), ar9003_hw_get_isr(), ar9003_hw_init_bb(), ar9003_hw_iqcalibrate(), ar9003_hw_override_ini(), ar9003_hw_proc_txdesc(), ar9003_hw_process_ini(), ar9003_hw_prog_ini(), ar9003_hw_rfbus_done(), ar9003_hw_set11n_aggr_first(), ar9003_hw_set11n_aggr_middle(), ar9003_hw_set11n_ratescenario(), ar9003_hw_set11n_txdesc(), ar9003_hw_set_channel(), ar9003_hw_set_channel_regs(), ar9003_hw_set_delta_slope(), ar9003_hw_set_desc_link(), ar9003_hw_set_diversity(), ar9003_hw_set_radar_params(), ar9003_hw_set_rfmode(), ar9003_hw_spur_mitigate_mrc_cck(), ar9003_hw_tx_iq_cal_post_proc(), ar9003_hw_tx_iqcal_load_avg_2_passes(), ar9100_hw_compute_pll_control(), ar9160_hw_compute_pll_control(), ar9271_hw_pa_cal(), ar9280_20_hw_init_rxgain_ini(), ar9280_20_hw_init_txgain_ini(), ar9280_hw_olc_temp_compensation(), ar9285_hw_pa_cal(), ar9287_eeprom_olpc_set_pdadcs(), ar9287_hw_olc_temp_compensation(), ar9300_check_header(), ar9300_otp_read_word(), ar9300_read_otp(), ath5k_cal_data_offset_2413(), ath5k_configure_filter(), ath5k_desc_alloc(), ath5k_eeprom_init_modes(), ath5k_eeprom_read_ants(), ath5k_eeprom_read_ctl_info(), ath5k_eeprom_read_mac(), ath5k_eeprom_read_modes(), ath5k_eeprom_read_pcal_info_2413(), ath5k_eeprom_read_pcal_info_5112(), ath5k_eeprom_read_target_rate_pwr_info(), ath5k_eeprom_read_turbo_modes(), ath5k_get_chan_pcal_surrounding_piers(), ath5k_get_max_ctl_power(), ath5k_get_rate_pcal_data(), ath5k_handle_rx(), ath5k_hw_attach(), ath5k_hw_bitswap(), ath5k_hw_eeprom_read(), ath5k_hw_gainf_calibrate(), ath5k_hw_get_capability(), ath5k_hw_get_gpio(), ath5k_hw_get_isr(), ath5k_hw_get_rx_filter(), ath5k_hw_get_rxdp(), ath5k_hw_get_txdp(), ath5k_hw_ini_mode_registers(), ath5k_hw_nic_reset(), ath5k_hw_nic_wakeup(), ath5k_hw_num_tx_pending(), ath5k_hw_post(), ath5k_hw_radio_revision(), ath5k_hw_reg_read(), ath5k_hw_reg_write(), ath5k_hw_reset(), ath5k_hw_reset_tx_queue(), ath5k_hw_rf2425_channel(), ath5k_hw_rf5110_calibrate(), ath5k_hw_rf5110_chan2athchan(), ath5k_hw_rf5110_channel(), ath5k_hw_rf5111_channel(), ath5k_hw_rf5112_channel(), ath5k_hw_rf511x_calibrate(), ath5k_hw_rf_check_gainf_readback(), ath5k_hw_rf_gainf_corr(), ath5k_hw_rfb_op(), ath5k_hw_rfgain_init(), ath5k_hw_rfregs_init(), ath5k_hw_set_ack_bitrate_high(), ath5k_hw_set_associd(), ath5k_hw_set_bssid_mask(), ath5k_hw_set_gpio(), ath5k_hw_set_gpio_input(), ath5k_hw_set_gpio_intr(), ath5k_hw_set_gpio_output(), ath5k_hw_set_imr(), ath5k_hw_set_lladdr(), ath5k_hw_set_mcast_filter(), ath5k_hw_set_opmode(), ath5k_hw_set_power(), ath5k_hw_set_rx_filter(), ath5k_hw_set_rxdp(), ath5k_hw_set_txdp(), ath5k_hw_setup_2word_tx_desc(), ath5k_hw_setup_rx_desc(), ath5k_hw_start_tx_dma(), ath5k_hw_stop_tx_dma(), ath5k_hw_tweak_initval_settings(), ath5k_hw_update_tx_triglevel(), ath5k_hw_wake(), ath5k_hw_write_ofdm_timings(), ath5k_hw_write_rate_duration(), ath5k_mode_setup(), ath5k_rfkill_set_intr(), ath5k_rx_iob_alloc(), ath5k_setup_channel_powertable(), ath5k_setup_pwr_to_pdadc_table(), ath9k_ani_restart(), ath9k_bss_info_changed(), ath9k_hw_4k_check_eeprom(), ath9k_hw_4k_get_eeprom(), ath9k_hw_4k_set_board_values(), ath9k_hw_addrxbuf_edma(), ath9k_hw_analog_shift_regwrite(), ath9k_hw_analog_shift_rmw(), ath9k_hw_ani_monitor(), ath9k_hw_ani_read_counters(), ath9k_hw_apply_gpio_override(), ath9k_hw_ar9287_check_eeprom(), ath9k_hw_ar9287_get_eeprom(), ath9k_hw_ar9287_set_board_values(), ath9k_hw_ar9300_get_eeprom(), ath9k_hw_cfg_gpio_input(), ath9k_hw_cfg_output(), ath9k_hw_channel_change(), ath9k_hw_check_alive(), ath9k_hw_chip_test(), ath9k_hw_cleartxdesc(), ath9k_hw_compute_pll_control(), ath9k_hw_computetxtime(), ath9k_hw_def_check_eeprom(), ath9k_hw_def_get_eeprom(), ath9k_hw_enable_interrupts(), ath9k_hw_filltxdesc(), ath9k_hw_get_channel_centers(), ath9k_hw_get_delta_slope_vals(), ath9k_hw_get_delta_slope_vals(), ath9k_hw_get_desc_link(), ath9k_hw_get_txq_props(), ath9k_hw_getdefantenna(), ath9k_hw_getrxfilter(), ath9k_hw_gettxbuf(), ath9k_hw_gettxintrtxqs(), ath9k_hw_gpio_cfg_output_mux(), ath9k_hw_gpio_get(), ath9k_hw_init_defaults(), ath9k_hw_init_global_settings(), ath9k_hw_init_interrupt_masks(), ath9k_hw_init_macaddr(), ath9k_hw_init_pll(), ath9k_hw_intrpend(), ath9k_hw_loadnf(), ath9k_hw_mac_bb_name(), ath9k_hw_mac_to_clks(), ath9k_hw_numtxpending(), ath9k_hw_nvram_read(), ath9k_hw_probe(), ath9k_hw_process_rxdesc_edma(), ath9k_hw_putrxbuf(), ath9k_hw_puttxbuf(), ath9k_hw_read_revisions(), ath9k_hw_releasetxqueue(), ath9k_hw_reset(), ath9k_hw_resettxqueue(), ath9k_hw_reverse_bits(), ath9k_hw_rxprocdesc(), ath9k_hw_set11n_aggr_first(), ath9k_hw_set11n_aggr_middle(), ath9k_hw_set11n_ratescenario(), ath9k_hw_set11n_txdesc(), ath9k_hw_set11nmac2040(), ath9k_hw_set_4k_power_cal_table(), ath9k_hw_set_ack_timeout(), ath9k_hw_set_ar9287_power_cal_table(), ath9k_hw_set_cts_timeout(), ath9k_hw_set_def_power_cal_table(), ath9k_hw_set_desc_link(), ath9k_hw_set_global_txtimeout(), ath9k_hw_set_gpio(), ath9k_hw_set_interrupts(), ath9k_hw_set_operating_mode(), ath9k_hw_set_power_awake(), ath9k_hw_set_reset(), ath9k_hw_set_reset_reg(), ath9k_hw_set_txpowerlimit(), ath9k_hw_set_txq_props(), ath9k_hw_setantenna(), ath9k_hw_setbssidmask(), ath9k_hw_setmcastfilter(), ath9k_hw_setrxabort(), ath9k_hw_setrxfilter(), ath9k_hw_setslottime(), ath9k_hw_setup_statusring(), ath9k_hw_setuprxdesc(), ath9k_hw_stop_dma_queue(), ath9k_hw_stopdmarecv(), ath9k_hw_txstart(), ath9k_hw_updatetxtriglevel(), ath9k_hw_usb_gen_fill_eeprom(), ath9k_hw_wait(), ath9k_ioread32(), ath9k_iowrite32(), ath9k_olc_get_pdadcs(), ath9k_reg_rmw(), ath9k_regd_get_ctl(), ath9k_tasklet(), ath9k_uses_beacons(), ath_ani_calibrate(), ath_calcrxfilter(), ath_descdma_setup(), ath_hw_cycle_counters_update(), ath_hw_keyreset(), ath_hw_pll_rx_hang_check(), ath_hw_pll_work(), ath_is_49ghz_allowed(), ath_opmode_init(), ath_pci_eeprom_read(), ath_pci_probe(), ath_regd_get_band_ctl(), ath_setdefantenna(), ath_tx_tasklet(), ath_txchainmask_reduction(), atl1e_auto_get_fc(), atl1e_cal_ring_size(), atl1e_check_eeprom_exist(), atl1e_check_link(), atl1e_clean_rx_irq(), atl1e_configure(), atl1e_configure_des_ring(), atl1e_configure_dma(), atl1e_configure_rx(), atl1e_configure_tx(), atl1e_get_permanent_address(), atl1e_hw_set_mac_addr(), atl1e_init_pcie(), atl1e_phy_commit(), atl1e_poll(), atl1e_read_phy_reg(), atl1e_reset_hw(), atl1e_setup_mac_ctrl(), atl1e_setup_ring_resources(), atl1e_sw_init(), atl1e_up(), atl1e_write_phy_reg(), atl_hw_reset_flb_(), atl_hw_reset_rbl_(), b44_cam_write(), b44_chip_reset(), b44_free_rx_ring(), b44_init_hw(), b44_phy_read(), b44_phy_read(), b44_phy_reset(), b44_phy_write(), b44_phy_write(), b44_poll(), b44_populate_rx_descriptor(), b44_populate_rx_descriptor(), b44_process_rx_packets(), b44_rx_refill(), b44_rx_refill(), b44_set_mac_addr(), b44_set_rx_mode(), b44_transmit(), b44_tx_complete(), b44_wait_bit(), bad_phy_status(), bflush(), bnx2_5706s_linkup(), bnx2_5708s_linkup(), bnx2_alloc_bad_rbuf(), bnx2_copper_linkup(), bnx2_ctx_wr(), bnx2_ctx_wr(), bnx2_disable_nvram_access(), bnx2_enable_nvram_access(), bnx2_fw_sync(), bnx2_init_5706s_phy(), bnx2_init_5708s_phy(), bnx2_init_board(), bnx2_init_chip(), bnx2_init_context(), bnx2_init_copper_phy(), bnx2_init_nvram(), bnx2_init_phy(), bnx2_init_rx_ring(), bnx2_init_tx_ring(), bnx2_phy_get_pause_adv(), bnx2_poll(), bnx2_poll_link(), bnx2_read_phy(), bnx2_reg_rd_ind(), bnx2_reg_rd_ind(), bnx2_reg_wr_ind(), bnx2_reg_wr_ind(), bnx2_report_fw_link(), bnx2_reset_chip(), bnx2_reset_nic(), bnx2_reset_phy(), bnx2_resolve_flow_ctrl(), bnx2_set_link(), bnx2_set_mac_addr(), bnx2_set_mac_link(), bnx2_set_power_state_0(), bnx2_set_rx_mode(), bnx2_setup_copper_phy(), bnx2_setup_serdes_phy(), bnx2_write_phy(), bnxt_alloc_rx_iob(), bnxt_db_cq(), bnxt_db_nq(), bnxt_db_rx(), bnxt_db_tx(), bnxt_er_get_reg_val(), bnxt_er_reg_read(), bnxt_er_reg_write(), bnxt_er_task(), bnxt_get_link_speed(), bnxt_get_phy_link(), bnxt_hwrm_assign_resources(), bnxt_hwrm_cfa_l2_filter_alloc(), bnxt_hwrm_port_phy_cfg(), bnxt_hwrm_ring_alloc(), bnxt_hwrm_ring_free_grp(), bnxt_hwrm_set_rx_mask(), bnxt_hwrm_stat_ctx_free(), bnxt_hwrm_ver_get(), bnxt_post_rx_buffers(), bnxt_rst_er_registers(), bnxt_rst_reg_val(), bnxt_rx_process(), bnxt_service_cq(), bnxt_service_nq(), bnxt_set_ring_info(), bnxt_set_rx_desc(), bnxt_set_txq(), bnxt_tx(), bnxt_tx_avail(), br32(), bw32(), crc32_le(), davicom_disable(), dev_p5_db(), dev_p7_db(), dm9132_id_table(), dm9132_id_table(), dmfe_descriptor_init(), dmfe_poll(), dmfe_probe(), dmfe_program_DM9801(), dmfe_program_DM9802(), eapol_key_rx(), ethtool_adv_to_mii_adv_x(), fdt_test_exec(), fiber_autoneg(), FILE_LICENCE(), FILE_LICENCE(), FILE_SECBOOT(), FILE_SECBOOT(), forcedeth_map_regs(), forcedeth_open(), forcedeth_poll(), forcedeth_transmit(), genesis_link_up(), genesis_mac_init(), genesis_reset(), genesis_stop(), get_unaligned_le32(), gma_read32(), gma_read32(), golan_destroy_mkey(), golan_eq_update_ci(), golan_poll_eq(), golan_post_send(), grf5101_rf_set_channel(), grf5101_rf_stop(), hunt_mcdi_copyin(), hwkhz(), hwrm_write_req(), ics1893_read_mode(), ifec_rfd_init(), ifec_rfd_init(), ifec_scb_cmd(), ifec_scb_cmd(), igbvf_check_for_bit_vf(), igbvf_check_for_link_vf(), igbvf_config_collision_dist(), igbvf_configure_rx(), igbvf_configure_tx(), igbvf_get_hw_control(), igbvf_hash_mc_addr_vf(), igbvf_promisc_set_vf(), igbvf_rar_set_vf(), igbvf_rar_set_vf(), igbvf_read_mbx_vf(), igbvf_read_pcie_cap_reg(), igbvf_read_posted_mbx(), igbvf_read_v2p_mailbox(), igbvf_reset_hw_vf(), igbvf_rlpml_set_vf(), igbvf_setup_srrctl(), igbvf_update_mc_addr_list_vf(), igbvf_vfta_set_vf(), igbvf_write_mbx_vf(), igbvf_write_posted_mbx(), is_pmu_set(), is_yukon_lite_a0(), jme_check_hw_ver(), jme_check_link(), jme_disable_rx_engine(), jme_disable_tx_engine(), jme_load_macaddr(), jme_poll(), jme_reload_eeprom(), jme_reset_mac_processor(), jme_reset_phy_processor(), jme_set_custom_macaddr(), jme_setup_wakeup_frame(), load_cpu_fw(), load_rv2p_fw(), max2820_rf_set_channel(), mdio_read(), mdio_write(), mii_adv_to_ethtool_adv_x(), mii_rw(), net80211_duration(), net80211_probe_step(), net80211_process_ie(), net80211_rx_frag(), net80211_update_link_quality(), nv_alloc_rx(), nv_mac_reset(), nv_mgmt_acquire_sema(), nv_mgmt_get_version(), nv_mgmt_release_sema(), nv_process_rx_packets(), nv_process_tx_packets(), nv_setup_mac_addr(), nv_setup_phy(), nv_start_rx(), nv_start_tx(), nv_stop_rx(), nv_stop_tx(), nv_txrx_gate(), nv_update_linkspeed(), nv_update_pause(), parse_eeprom(), pbkdf2_sha1(), pbkdf2_sha1_f(), pcnet32_process_rx_packets(), pending_rx_index(), pending_tx_index(), phy_init(), phy_length(), phy_read(), phy_read(), phy_read_1bit(), phy_reset(), phy_write(), phy_write(), phy_write_1bit(), phy_write_1bit(), pnic_do_nway(), prep_pci_cfg_cap(), prf_sha1(), rc80211_calc_net_goodness(), rc80211_update(), reg_delay(), rol32(), ror32(), rsn_get_desc(), rtl818x_handle_rx(), rtl818x_handle_tx(), rtl818x_ioread32(), rtl818x_iowrite32(), rtl818x_probe(), rtl818x_set_anaparam(), rtl818x_set_hwaddr(), rtl818x_start(), rtl818x_tx(), rtl818x_write_phy(), rtl8201_read_mode(), rtl8225_rf_init(), rtl8225_rf_set_tx_power(), rtl8225_write(), rtl8225z2_rf_init(), sa2400_rf_init(), sa2400_rf_set_channel(), sec80211_rsn_get_akm_desc(), sec80211_rsn_get_crypto_desc(), sec80211_rsn_get_net80211_crypt(), select_media(), set_rx_mask(), set_rx_mode(), set_rx_mode(), sis190_alloc_rx_iob(), sis190_give_to_asic(), sis190_map_to_asic(), sis190_phy_task(), sis190_poll(), sis190_process_rx(), sis190_process_tx(), sis190_read_eeprom(), sis190_rx_fill(), sis190_rx_pkt_err(), sis190_set_rx_mode(), sis190_transmit(), sis190_tx_pkt_err(), sis635_get_mac_addr(), sis900_check_mode(), sis900_init_rxd(), sis900_init_rxfilter(), sis900_init_txd(), sis900_poll(), sis900_read_eeprom(), sis900_read_mode(), sis900_reset(), sis900_set_rx_mode(), sis900_transmit(), sis96x_get_mac_addr(), skge_poll(), skge_qset(), skge_ramset(), skge_read32(), skge_reset(), skge_ring_alloc(), skge_rx_done(), skge_rx_refill(), skge_supported_modes(), skge_tx_done(), skge_up(), skge_usecs2clk(), skge_write32(), skge_xmit_frame(), sky2_clk2us(), sky2_down(), sky2_err_intr(), sky2_hw_error(), sky2_hw_intr(), sky2_mac_init(), sky2_mhz(), sky2_net_irq(), sky2_pci_read32(), sky2_pci_write32(), sky2_phy_power_down(), sky2_phy_power_up(), sky2_poll(), sky2_power_on(), sky2_prefetch_init(), sky2_ramset(), sky2_read32(), sky2_receive(), sky2_reset(), sky2_rx_add(), sky2_rx_start(), sky2_status_intr(), sky2_supported_modes(), sky2_up(), sky2_us2clk(), sky2_write32(), sky2_xmit_frame(), ssb_core_reset(), ssb_get_core_rev(), ssb_pci_setup(), ssb_pci_setup(), sundance_poll(), sundance_transmit(), tg3_5700_link_polarity(), tg3_adv_1000T_flowctrl_ok(), tg3_alloc_rx_iob(), tg3_aux_stat_to_speed_duplex(), tg3_bmcr_reset(), tg3_chip_reset(), tg3_copper_is_advertising_all(), tg3_disable_nvram_access(), tg3_do_test_dma(), tg3_enable_nvram_access(), tg3_fiber_aneg_smachine(), tg3_generate_fw_event(), tg3_get_device_address(), tg3_get_eeprom_hw_cfg(), tg3_get_invariants(), tg3_init_bcm8002(), tg3_issue_otp_command(), tg3_mdio_init(), tg3_nvram_exec_cmd(), tg3_nvram_phys_addr(), tg3_nvram_read(), tg3_nvram_read_be32(), tg3_nvram_read_using_eeprom(), tg3_phy_apply_otp(), tg3_phy_autoneg_cfg(), tg3_phy_auxctl_read(), tg3_phy_auxctl_write(), tg3_phy_copper_begin(), tg3_phy_init_link_config(), tg3_phy_probe(), tg3_phy_reset(), tg3_phy_reset_5703_4_5(), tg3_phy_set_wirespeed(), tg3_phy_toggle_automdix(), tg3_phy_write_and_check_testpat(), tg3_phydsp_write(), tg3_poll_fw(), tg3_read32_mbox_5906(), tg3_read_indirect_mbox(), tg3_read_indirect_reg32(), tg3_read_mem(), tg3_read_otp_phycfg(), tg3_readphy(), tg3_refill_prod_ring(), tg3_reset_hw(), tg3_restore_pci_state(), tg3_rings_reset(), tg3_rx_complete(), tg3_rx_prodring_alloc(), tg3_set_bdinfo(), tg3_set_txd(), tg3_setup_copper_phy(), tg3_setup_fiber_by_hand(), tg3_setup_fiber_hw_autoneg(), tg3_setup_fiber_mii_phy(), tg3_setup_fiber_phy(), tg3_setup_flow_control(), tg3_setup_phy(), tg3_setup_rxbd_thresholds(), tg3_stop_block(), tg3_switch_clocks(), tg3_test_dma(), tg3_transmit(), tg3_tx_avail(), tg3_tx_complete(), tg3_ump_link_report(), tg3_wait_macro_done(), tg3_write32_mbox_5906(), tg3_write_indirect_mbox(), tg3_write_indirect_reg32(), tg3_write_mem(), tg3_writephy(), tkip_decrypt(), tkip_encrypt(), tkip_feed_michael(), tkip_michael(), TLan_DioRead32(), TLan_DioWrite32(), TLan_FinishReset(), TLan_FinishReset(), TLan_HashFunc(), TLan_MiiReadReg(), TLan_MiiSendData(), TLan_PhyDetect(), tlan_poll(), tlan_probe(), TLan_ResetAdapter(), tlan_transmit(), tulip_probe(), tulip_reset(), tulip_transmit(), tw32_mailbox_flush(), update_cr6(), virtio_pci_map_capability(), virtnet_open_legacy(), virtnet_probe_legacy(), vp_get_features(), vp_set_features(), vpm_find_vqs(), vpm_get_features(), vpm_ioread32(), vpm_iowrite32(), vpm_iowrite64(), vpm_set_features(), vring_get_buf(), vt6103_read_mode(), vxge_hw_device_hw_info_get(), vxge_hw_device_intr_enable(), vxge_hw_device_mask_all(), vxge_hw_device_unmask_all(), vxge_hw_get_func_mode(), vxge_hw_ring_rxd_1b_set(), vxge_hw_ring_rxd_post(), vxge_hw_set_fw_api(), vxge_hw_vpath_close(), vxge_hw_vpath_doorbell_rx(), vxge_hw_vpath_enable(), vxge_hw_vpath_intr_disable(), vxge_hw_vpath_intr_enable(), vxge_hw_vpath_mtu_set(), vxge_hw_vpath_recover_from_reset(), vxge_hw_vpath_reset(), vxge_probe(), w89c840_poll(), w89c840_transmit(), wait_resp(), wep_decrypt(), wep_encrypt(), wpa_handle_3_of_4(), wpa_make_rsn_ie(), write_grf5101(), write_max2820(), write_sa2400(), xm_read32(), xm_write32(), xor(), and yukon_mac_init().

◆ __u32

#define __u32   u32

Definition at line 22 of file vga.h.

◆ VERROR

#define VERROR   -1

Definition at line 24 of file vga.h.

◆ CHAR_HEIGHT

#define CHAR_HEIGHT   16

Definition at line 25 of file vga.h.

◆ LINES

#define LINES   25

Definition at line 26 of file vga.h.

◆ COLS

◆ write_crtc

#define write_crtc ( data,
addr )
Value:
uint32_t addr
Buffer address.
Definition dwmac.h:9
uint8_t data[48]
Additional event data.
Definition ena.h:11
#define outb(data, io_addr)
Definition io.h:310
#define CRT_IC
Definition vga.h:86
#define CRT_DC
Definition vga.h:66

Definition at line 30 of file vga.h.

Referenced by vga_putc().

◆ write_att

#define write_att ( data,
addr )
Value:
inb(IS1_RC); inb(0x80); outb(addr,ATT_IW); inb(0x80); outb(data,ATT_IW); inb(0x80)
#define inb(io_addr)
Definition io.h:283
#define IS1_RC
Definition vga.h:75
#define ATT_IW
Definition vga.h:88

Definition at line 31 of file vga.h.

◆ write_seq

#define write_seq ( data,
addr )
Value:
#define SEQ_I
Definition vga.h:90
#define SEQ_D
Definition vga.h:70

Definition at line 32 of file vga.h.

◆ write_gra

#define write_gra ( data,
addr )
Value:
#define GRA_D
Definition vga.h:69
#define GRA_I
Definition vga.h:89

Definition at line 33 of file vga.h.

◆ vga_hardware_fixup

#define vga_hardware_fixup ( )
Value:
do{} while(0)

Definition at line 43 of file vga.h.

◆ SYNC_HOR_HIGH_ACT

#define SYNC_HOR_HIGH_ACT   1 /* horizontal sync high active */

Definition at line 46 of file vga.h.

◆ SYNC_VERT_HIGH_ACT

#define SYNC_VERT_HIGH_ACT   2 /* vertical sync high active */

Definition at line 47 of file vga.h.

◆ SYNC_EXT

#define SYNC_EXT   4 /* external sync */

Definition at line 48 of file vga.h.

◆ SYNC_COMP_HIGH_ACT

#define SYNC_COMP_HIGH_ACT   8 /* composite sync high active */

Definition at line 49 of file vga.h.

◆ SYNC_BROADCAST

#define SYNC_BROADCAST   16 /* broadcast video timings */

Definition at line 50 of file vga.h.

◆ SYNC_ON_GREEN

#define SYNC_ON_GREEN   32 /* sync on green */

Definition at line 54 of file vga.h.

◆ VMODE_NONINTERLACED

#define VMODE_NONINTERLACED   0 /* non interlaced */

Definition at line 56 of file vga.h.

◆ VMODE_INTERLACED

#define VMODE_INTERLACED   1 /* interlaced */

Definition at line 57 of file vga.h.

◆ VMODE_DOUBLE

#define VMODE_DOUBLE   2 /* double scan */

Definition at line 58 of file vga.h.

◆ VMODE_MASK

#define VMODE_MASK   255

Definition at line 59 of file vga.h.

◆ VMODE_YWRAP

#define VMODE_YWRAP   256 /* ywrap instead of panning */

Definition at line 61 of file vga.h.

◆ VMODE_SMOOTH_XPAN

#define VMODE_SMOOTH_XPAN   512 /* smooth xpan possible (internally used) */

Definition at line 62 of file vga.h.

◆ VMODE_CONUPDATE

#define VMODE_CONUPDATE   512 /* don't update x/yoffset */

Definition at line 63 of file vga.h.

◆ CRT_DC

#define CRT_DC   0x3D5 /* CRT Controller Data Register - color emulation */

Definition at line 66 of file vga.h.

◆ CRT_DM

#define CRT_DM   0x3B5 /* CRT Controller Data Register - mono emulation */

Definition at line 67 of file vga.h.

◆ ATT_R

#define ATT_R   0x3C1 /* Attribute Controller Data Read Register */

Definition at line 68 of file vga.h.

◆ GRA_D

#define GRA_D   0x3CF /* Graphics Controller Data Register */

Definition at line 69 of file vga.h.

◆ SEQ_D

#define SEQ_D   0x3C5 /* Sequencer Data Register */

Definition at line 70 of file vga.h.

◆ MIS_R

#define MIS_R   0x3CC

Definition at line 72 of file vga.h.

◆ MIS_W

#define MIS_W   0x3C2

Definition at line 73 of file vga.h.

◆ IS1_RC

#define IS1_RC   0x3DA /* Input Status Register 1 - color emulation */

Definition at line 75 of file vga.h.

◆ IS1_RM

#define IS1_RM   0x3BA /* Input Status Register 1 - mono emulation */

Definition at line 76 of file vga.h.

◆ PEL_D

#define PEL_D   0x3C9 /* PEL Data Register */

Definition at line 77 of file vga.h.

◆ PEL_MSK

#define PEL_MSK   0x3C6 /* PEL mask register */

Definition at line 78 of file vga.h.

◆ GRA_E0

#define GRA_E0   0x3CC /* Graphics enable processor 0 */

Definition at line 81 of file vga.h.

◆ GRA_E1

#define GRA_E1   0x3CA /* Graphics enable processor 1 */

Definition at line 82 of file vga.h.

◆ CRT_IC

#define CRT_IC   0x3D4 /* CRT Controller Index - color emulation */

Definition at line 86 of file vga.h.

◆ CRT_IM

#define CRT_IM   0x3B4 /* CRT Controller Index - mono emulation */

Definition at line 87 of file vga.h.

◆ ATT_IW

#define ATT_IW   0x3C0 /* Attribute Controller Index & Data Write Register */

Definition at line 88 of file vga.h.

◆ GRA_I

#define GRA_I   0x3CE /* Graphics Controller Index */

Definition at line 89 of file vga.h.

◆ SEQ_I

#define SEQ_I   0x3C4 /* Sequencer Index */

Definition at line 90 of file vga.h.

◆ PEL_IW

#define PEL_IW   0x3C8 /* PEL Write Index */

Definition at line 91 of file vga.h.

◆ PEL_IR

#define PEL_IR   0x3C7 /* PEL Read Index */

Definition at line 92 of file vga.h.

◆ CRTC_C

#define CRTC_C   25 /* 25 CRT Controller Registers sequentially set*/

Definition at line 95 of file vga.h.

◆ ATT_C

#define ATT_C   21 /* 21 Attribute Controller Registers */

Definition at line 97 of file vga.h.

◆ GRA_C

#define GRA_C   9 /* 9 Graphics Controller Registers */

Definition at line 98 of file vga.h.

◆ SEQ_C

#define SEQ_C   5 /* 5 Sequencer Registers */

Definition at line 99 of file vga.h.

◆ MIS_C

#define MIS_C   1 /* 1 Misc Output Register */

Definition at line 100 of file vga.h.

◆ CRTC_H_TOTAL

#define CRTC_H_TOTAL   0

Definition at line 102 of file vga.h.

◆ CRTC_H_DISP

#define CRTC_H_DISP   1

Definition at line 103 of file vga.h.

◆ CRTC_H_BLANK_START

#define CRTC_H_BLANK_START   2

Definition at line 104 of file vga.h.

◆ CRTC_H_BLANK_END

#define CRTC_H_BLANK_END   3

Definition at line 105 of file vga.h.

◆ CRTC_H_SYNC_START

#define CRTC_H_SYNC_START   4

Definition at line 106 of file vga.h.

◆ CRTC_H_SYNC_END

#define CRTC_H_SYNC_END   5

Definition at line 107 of file vga.h.

◆ CRTC_V_TOTAL

#define CRTC_V_TOTAL   6

Definition at line 108 of file vga.h.

◆ CRTC_OVERFLOW

#define CRTC_OVERFLOW   7

Definition at line 109 of file vga.h.

◆ CRTC_PRESET_ROW

#define CRTC_PRESET_ROW   8

Definition at line 110 of file vga.h.

◆ CRTC_MAX_SCAN

#define CRTC_MAX_SCAN   9

Definition at line 111 of file vga.h.

◆ CRTC_CURSOR_START

#define CRTC_CURSOR_START   0x0A

Definition at line 112 of file vga.h.

◆ CRTC_CURSOR_END

#define CRTC_CURSOR_END   0x0B

Definition at line 113 of file vga.h.

◆ CRTC_START_HI

#define CRTC_START_HI   0x0C

Definition at line 114 of file vga.h.

◆ CRTC_START_LO

#define CRTC_START_LO   0x0D

Definition at line 115 of file vga.h.

◆ CRTC_CURSOR_HI

#define CRTC_CURSOR_HI   0x0E

Definition at line 116 of file vga.h.

Referenced by vga_putc().

◆ CRTC_CURSOR_LO

#define CRTC_CURSOR_LO   0x0F

Definition at line 117 of file vga.h.

Referenced by vga_putc().

◆ CRTC_V_SYNC_START

#define CRTC_V_SYNC_START   0x10

Definition at line 118 of file vga.h.

◆ CRTC_V_SYNC_END

#define CRTC_V_SYNC_END   0x11

Definition at line 119 of file vga.h.

◆ CRTC_V_DISP_END

#define CRTC_V_DISP_END   0x12

Definition at line 120 of file vga.h.

◆ CRTC_OFFSET

#define CRTC_OFFSET   0x13

Definition at line 121 of file vga.h.

◆ CRTC_UNDERLINE

#define CRTC_UNDERLINE   0x14

Definition at line 122 of file vga.h.

◆ CRTC_V_BLANK_START

#define CRTC_V_BLANK_START   0x15

Definition at line 123 of file vga.h.

◆ CRTC_V_BLANK_END

#define CRTC_V_BLANK_END   0x16

Definition at line 124 of file vga.h.

◆ CRTC_MODE

#define CRTC_MODE   0x17

Definition at line 125 of file vga.h.

◆ CRTC_LINE_COMPARE

#define CRTC_LINE_COMPARE   0x18

Definition at line 126 of file vga.h.

◆ ATC_MODE

#define ATC_MODE   0x10

Definition at line 128 of file vga.h.

◆ ATC_OVERSCAN

#define ATC_OVERSCAN   0x11

Definition at line 129 of file vga.h.

◆ ATC_PLANE_ENABLE

#define ATC_PLANE_ENABLE   0x12

Definition at line 130 of file vga.h.

◆ ATC_PEL

#define ATC_PEL   0x13

Definition at line 131 of file vga.h.

◆ ATC_COLOR_PAGE

#define ATC_COLOR_PAGE   0x14

Definition at line 132 of file vga.h.

◆ SEQ_CLOCK_MODE

#define SEQ_CLOCK_MODE   0x01

Definition at line 134 of file vga.h.

◆ SEQ_PLANE_WRITE

#define SEQ_PLANE_WRITE   0x02

Definition at line 135 of file vga.h.

◆ SEQ_CHARACTER_MAP

#define SEQ_CHARACTER_MAP   0x03

Definition at line 136 of file vga.h.

◆ SEQ_MEMORY_MODE

#define SEQ_MEMORY_MODE   0x04

Definition at line 137 of file vga.h.

◆ GDC_SR_VALUE

#define GDC_SR_VALUE   0x00

Definition at line 139 of file vga.h.

◆ GDC_SR_ENABLE

#define GDC_SR_ENABLE   0x01

Definition at line 140 of file vga.h.

◆ GDC_COMPARE_VALUE

#define GDC_COMPARE_VALUE   0x02

Definition at line 141 of file vga.h.

◆ GDC_DATA_ROTATE

#define GDC_DATA_ROTATE   0x03

Definition at line 142 of file vga.h.

◆ GDC_PLANE_READ

#define GDC_PLANE_READ   0x04

Definition at line 143 of file vga.h.

◆ GDC_MODE

#define GDC_MODE   0x05

Definition at line 144 of file vga.h.

◆ GDC_MISC

#define GDC_MISC   0x06

Definition at line 145 of file vga.h.

◆ GDC_COMPARE_MASK

#define GDC_COMPARE_MASK   0x07

Definition at line 146 of file vga.h.

◆ GDC_BIT_MASK

#define GDC_BIT_MASK   0x08

Definition at line 147 of file vga.h.

◆ VGA_ATTR_CLR_RED

#define VGA_ATTR_CLR_RED   0x4

Definition at line 150 of file vga.h.

◆ VGA_ATTR_CLR_GRN

#define VGA_ATTR_CLR_GRN   0x2

Definition at line 151 of file vga.h.

◆ VGA_ATTR_CLR_BLU

#define VGA_ATTR_CLR_BLU   0x1

Definition at line 152 of file vga.h.

◆ VGA_ATTR_CLR_YEL

#define VGA_ATTR_CLR_YEL   (VGA_ATTR_CLR_RED | VGA_ATTR_CLR_GRN)

Definition at line 153 of file vga.h.

◆ VGA_ATTR_CLR_CYN

#define VGA_ATTR_CLR_CYN   (VGA_ATTR_CLR_GRN | VGA_ATTR_CLR_BLU)

Definition at line 154 of file vga.h.

◆ VGA_ATTR_CLR_MAG

#define VGA_ATTR_CLR_MAG   (VGA_ATTR_CLR_BLU | VGA_ATTR_CLR_RED)

Definition at line 155 of file vga.h.

◆ VGA_ATTR_CLR_BLK

#define VGA_ATTR_CLR_BLK   0

Definition at line 156 of file vga.h.

◆ VGA_ATTR_CLR_WHT

#define VGA_ATTR_CLR_WHT   (VGA_ATTR_CLR_RED | VGA_ATTR_CLR_GRN | VGA_ATTR_CLR_BLU)

Definition at line 157 of file vga.h.

Referenced by vga_putc(), and video_init().

◆ VGA_ATTR_BNK

#define VGA_ATTR_BNK   0x80

Definition at line 158 of file vga.h.

◆ VGA_ATTR_ITN

#define VGA_ATTR_ITN   0x08

Definition at line 159 of file vga.h.

Function Documentation

◆ read_seq_b()

u8 read_seq_b ( u16 addr)

References addr, u16, and u8.

◆ read_gra_b()

u8 read_gra_b ( u16 addr)

References addr, u16, and u8.

◆ read_crtc_b()

u8 read_crtc_b ( u16 addr)

References addr, u16, and u8.

◆ read_att_b()

u8 read_att_b ( u16 addr)

References addr, u16, and u8.