19 #define u8 unsigned char 20 #define u16 unsigned short 21 #define u32 unsigned int 25 #define CHAR_HEIGHT 16 30 #define write_crtc(data,addr) outb(addr,CRT_IC); outb(data,CRT_DC) 31 #define write_att(data,addr) inb(IS1_RC); inb(0x80); outb(addr,ATT_IW); inb(0x80); outb(data,ATT_IW); inb(0x80) 32 #define write_seq(data,addr) outb(addr,SEQ_I); outb(data,SEQ_D) 33 #define write_gra(data,addr) outb(addr,GRA_I); outb(data,GRA_D) 40 #ifdef VGA_HARDWARE_FIXUP 43 #define vga_hardware_fixup() do{} while(0) 46 #define SYNC_HOR_HIGH_ACT 1 47 #define SYNC_VERT_HIGH_ACT 2 49 #define SYNC_COMP_HIGH_ACT 8 50 #define SYNC_BROADCAST 16 54 #define SYNC_ON_GREEN 32 56 #define VMODE_NONINTERLACED 0 57 #define VMODE_INTERLACED 1 58 #define VMODE_DOUBLE 2 59 #define VMODE_MASK 255 61 #define VMODE_YWRAP 256 62 #define VMODE_SMOOTH_XPAN 512 63 #define VMODE_CONUPDATE 512 72 #define MIS_R 0x3CC // Misc Output Read Register 73 #define MIS_W 0x3C2 // Misc Output Write Register 102 #define CRTC_H_TOTAL 0 103 #define CRTC_H_DISP 1 104 #define CRTC_H_BLANK_START 2 105 #define CRTC_H_BLANK_END 3 106 #define CRTC_H_SYNC_START 4 107 #define CRTC_H_SYNC_END 5 108 #define CRTC_V_TOTAL 6 109 #define CRTC_OVERFLOW 7 110 #define CRTC_PRESET_ROW 8 111 #define CRTC_MAX_SCAN 9 112 #define CRTC_CURSOR_START 0x0A 113 #define CRTC_CURSOR_END 0x0B 114 #define CRTC_START_HI 0x0C 115 #define CRTC_START_LO 0x0D 116 #define CRTC_CURSOR_HI 0x0E 117 #define CRTC_CURSOR_LO 0x0F 118 #define CRTC_V_SYNC_START 0x10 119 #define CRTC_V_SYNC_END 0x11 120 #define CRTC_V_DISP_END 0x12 121 #define CRTC_OFFSET 0x13 122 #define CRTC_UNDERLINE 0x14 123 #define CRTC_V_BLANK_START 0x15 124 #define CRTC_V_BLANK_END 0x16 125 #define CRTC_MODE 0x17 126 #define CRTC_LINE_COMPARE 0x18 128 #define ATC_MODE 0x10 129 #define ATC_OVERSCAN 0x11 130 #define ATC_PLANE_ENABLE 0x12 132 #define ATC_COLOR_PAGE 0x14 134 #define SEQ_CLOCK_MODE 0x01 135 #define SEQ_PLANE_WRITE 0x02 136 #define SEQ_CHARACTER_MAP 0x03 137 #define SEQ_MEMORY_MODE 0x04 139 #define GDC_SR_VALUE 0x00 140 #define GDC_SR_ENABLE 0x01 141 #define GDC_COMPARE_VALUE 0x02 142 #define GDC_DATA_ROTATE 0x03 143 #define GDC_PLANE_READ 0x04 144 #define GDC_MODE 0x05 145 #define GDC_MISC 0x06 146 #define GDC_COMPARE_MASK 0x07 147 #define GDC_BIT_MASK 0x08 150 #define VGA_ATTR_CLR_RED 0x4 151 #define VGA_ATTR_CLR_GRN 0x2 152 #define VGA_ATTR_CLR_BLU 0x1 153 #define VGA_ATTR_CLR_YEL (VGA_ATTR_CLR_RED | VGA_ATTR_CLR_GRN) 154 #define VGA_ATTR_CLR_CYN (VGA_ATTR_CLR_GRN | VGA_ATTR_CLR_BLU) 155 #define VGA_ATTR_CLR_MAG (VGA_ATTR_CLR_BLU | VGA_ATTR_CLR_RED) 156 #define VGA_ATTR_CLR_BLK 0 157 #define VGA_ATTR_CLR_WHT (VGA_ATTR_CLR_RED | VGA_ATTR_CLR_GRN | VGA_ATTR_CLR_BLU) 158 #define VGA_ATTR_BNK 0x80 159 #define VGA_ATTR_ITN 0x08
#define vga_hardware_fixup()
struct fb_bitfield transp