37 #define UART_THRE_TIMEOUT_MS 100 40 #define UART_TEMT_TIMEOUT_MS 1000 struct arbelprm_rc_send_wqe rc
void uart_flush(struct uart *uart)
Flush data.
int uart_exists(struct uart *uart)
Check for existence of UART.
uint16_t divisor
Baud rate divisor.
FILE_LICENCE(GPL2_OR_LATER_OR_UBDL)
#define UART_LSR
Line status register.
void uart_transmit(struct uart *uart, uint8_t data)
Transmit data.
uint8_t lcr
Line control register.
void * base
I/O port base address.
int uart_init(struct uart *uart, unsigned int baud, uint8_t lcr)
Initialise UART.
#define UART_DLL
Divisor latch (least significant byte)
#define UART_LSR_THRE
Transmitter holding register empty.
#define UART_MAX_BAUD
Maximum baud rate.
#define UART_THR
Transmitter holding register.
#define UART_RBR
Receiver buffer register.
#define UART_DLM
Divisor latch (most significant byte)
void uart_write(struct uart *uart, unsigned int addr, uint8_t data)
uint8_t uart_read(struct uart *uart, unsigned int addr)
#define ENODEV
No such device.
#define UART_FCR
FIFO control register.
#define UART_SCR
Scratch register.
#define UART_LSR_TEMT
Transmitter empty.
#define UART_THRE_TIMEOUT_MS
Timeout for transmit holding register to become empty.
#define UART_MCR
Modem control register.
#define UART_IER
Interrupt enable register.
void mdelay(unsigned long msecs)
Delay for a fixed number of milliseconds.
#define UART_TEMT_TIMEOUT_MS
Timeout for transmitter to become empty.
#define UART_MCR_RTS
Request to send.
uint8_t data[48]
Additional event data.
#define UART_LCR
Line control register.
#define UART_FCR_FE
FIFO enable.
#define UART_MCR_DTR
Data terminal ready.
#define UART_LCR_DLAB
Divisor latch access bit.
#define UART_LSR_DR
Data ready.