iPXE
Macros | Functions | Variables
ath9k_hw.c File Reference
#include <ipxe/vsprintf.h>
#include <ipxe/io.h>
#include "hw.h"
#include "hw-ops.h"
#include "ar9003_mac.h"

Go to the source code of this file.

Macros

#define MS_REG_READ(x, y)   (MS(REG_READ(ah, AR_GPIO_IN_OUT), x##_GPIO_IN_VAL) & (AR_GPIO_BIT(y)))
 

Functions

static int ath9k_hw_set_reset_reg (struct ath_hw *ah, u32 type)
 
static void ath9k_hw_init_cal_settings (struct ath_hw *ah)
 
static void ath9k_hw_init_mode_regs (struct ath_hw *ah)
 
static u32 ath9k_hw_compute_pll_control (struct ath_hw *ah, struct ath9k_channel *chan)
 
static void ath9k_hw_init_mode_gain_regs (struct ath_hw *ah)
 
static void ath9k_hw_ani_cache_ini_regs (struct ath_hw *ah)
 
static void ath9k_hw_set_clockrate (struct ath_hw *ah)
 
static u32 ath9k_hw_mac_to_clks (struct ath_hw *ah, u32 usecs)
 
int ath9k_hw_wait (struct ath_hw *ah, u32 reg, u32 mask, u32 val, u32 timeout)
 
void ath9k_hw_write_array (struct ath_hw *ah, struct ar5416IniArray *array, int column, unsigned int *writecnt)
 
u32 ath9k_hw_reverse_bits (u32 val, u32 n)
 
u16 ath9k_hw_computetxtime (struct ath_hw *ah, u8 phy, int kbps, u32 frameLen, u16 rateix, int shortPreamble)
 
void ath9k_hw_get_channel_centers (struct ath_hw *ah __unused, struct ath9k_channel *chan, struct chan_centers *centers)
 
static void ath9k_hw_read_revisions (struct ath_hw *ah)
 
static void ath9k_hw_disablepcie (struct ath_hw *ah)
 
static int ath9k_hw_chip_test (struct ath_hw *ah)
 
static void ath9k_hw_init_config (struct ath_hw *ah)
 
static void ath9k_hw_init_defaults (struct ath_hw *ah)
 
static int ath9k_hw_init_macaddr (struct ath_hw *ah)
 
static int ath9k_hw_post_init (struct ath_hw *ah)
 
static void ath9k_hw_attach_ops (struct ath_hw *ah)
 
static int __ath9k_hw_init (struct ath_hw *ah)
 
int ath9k_hw_init (struct ath_hw *ah)
 
u32 ar9003_get_pll_sqsum_dvc (struct ath_hw *ah)
 
static void ath9k_hw_init_pll (struct ath_hw *ah, struct ath9k_channel *chan)
 
static void ath9k_hw_init_interrupt_masks (struct ath_hw *ah)
 
static void ath9k_hw_setslottime (struct ath_hw *ah, u32 us)
 
static void ath9k_hw_set_ack_timeout (struct ath_hw *ah, u32 us)
 
static void ath9k_hw_set_cts_timeout (struct ath_hw *ah, u32 us)
 
static int ath9k_hw_set_global_txtimeout (struct ath_hw *ah, u32 tu)
 
void ath9k_hw_init_global_settings (struct ath_hw *ah)
 
void ath9k_hw_deinit (struct ath_hw *ah)
 
u32 ath9k_regd_get_ctl (struct ath_regulatory *reg, struct ath9k_channel *chan)
 
static void ath9k_hw_set_dma (struct ath_hw *ah)
 
static void ath9k_hw_set_operating_mode (struct ath_hw *ah)
 
void ath9k_hw_get_delta_slope_vals (struct ath_hw *ah __unused, u32 coef_scaled, u32 *coef_mantissa, u32 *coef_exponent)
 
static int ath9k_hw_set_reset (struct ath_hw *ah, int type)
 
static int ath9k_hw_set_reset_power_on (struct ath_hw *ah)
 
static int ath9k_hw_chip_reset (struct ath_hw *ah, struct ath9k_channel *chan)
 
static int ath9k_hw_channel_change (struct ath_hw *ah, struct ath9k_channel *chan)
 
static void ath9k_hw_apply_gpio_override (struct ath_hw *ah)
 
int ath9k_hw_check_alive (struct ath_hw *ah)
 
int ath9k_hw_reset (struct ath_hw *ah, struct ath9k_channel *chan, struct ath9k_hw_cal_data *caldata, int bChannelChange)
 
static void ath9k_set_power_sleep (struct ath_hw *ah, int setChip)
 
static int ath9k_hw_set_power_awake (struct ath_hw *ah, int setChip)
 
int ath9k_hw_setpower (struct ath_hw *ah, enum ath9k_power_mode mode)
 
int ath9k_hw_fill_cap_info (struct ath_hw *ah)
 
static void ath9k_hw_gpio_cfg_output_mux (struct ath_hw *ah, u32 gpio, u32 type)
 
void ath9k_hw_cfg_gpio_input (struct ath_hw *ah, u32 gpio)
 
u32 ath9k_hw_gpio_get (struct ath_hw *ah, u32 gpio)
 
void ath9k_hw_cfg_output (struct ath_hw *ah, u32 gpio, u32 ah_signal_type)
 
void ath9k_hw_set_gpio (struct ath_hw *ah, u32 gpio, u32 val)
 
u32 ath9k_hw_getdefantenna (struct ath_hw *ah)
 
void ath9k_hw_setantenna (struct ath_hw *ah, u32 antenna)
 
u32 ath9k_hw_getrxfilter (struct ath_hw *ah)
 
void ath9k_hw_setrxfilter (struct ath_hw *ah, u32 bits)
 
int ath9k_hw_phy_disable (struct ath_hw *ah)
 
int ath9k_hw_disable (struct ath_hw *ah)
 
void ath9k_hw_set_txpowerlimit (struct ath_hw *ah, u32 limit, int test)
 
void ath9k_hw_setopmode (struct ath_hw *ah)
 
void ath9k_hw_setmcastfilter (struct ath_hw *ah, u32 filter0, u32 filter1)
 
void ath9k_hw_write_associd (struct ath_hw *ah)
 
void ath9k_hw_set11nmac2040 (struct ath_hw *ah)
 
static const char * ath9k_hw_mac_bb_name (u32 mac_bb_version)
 
static const char * ath9k_hw_rf_name (u16 rf_version)
 
void ath9k_hw_name (struct ath_hw *ah, char *hw_name, size_t len)
 

Variables

struct {
   u32   version
 
   const char *   name
 
ath_mac_bb_names []
 
struct {
   u16   version
 
   const char *   name
 
ath_rf_names []
 

Macro Definition Documentation

◆ MS_REG_READ

#define MS_REG_READ (   x,
 
)    (MS(REG_READ(ah, AR_GPIO_IN_OUT), x##_GPIO_IN_VAL) & (AR_GPIO_BIT(y)))

Function Documentation

◆ ath9k_hw_set_reset_reg()

static int ath9k_hw_set_reset_reg ( struct ath_hw ah,
u32  type 
)
static

Definition at line 1088 of file ath9k_hw.c.

1089 {
1091  REG_WRITE(ah, AR_WA, ah->WARegVal);
1092  udelay(10);
1093  }
1094 
1097 
1098  switch (type) {
1099  case ATH9K_RESET_POWER_ON:
1101  case ATH9K_RESET_WARM:
1102  case ATH9K_RESET_COLD:
1103  return ath9k_hw_set_reset(ah, type);
1104  default:
1105  return 0;
1106  }
1107 }
uint8_t type
Type.
Definition: ena.h:16
#define AR_SREV_9300_20_OR_LATER(_ah)
Definition: reg.h:864
#define AR_RTC_FORCE_WAKE_EN
Definition: reg.h:1219
static int ath9k_hw_set_reset_power_on(struct ath_hw *ah)
Definition: ath9k_hw.c:1048
void udelay(unsigned long usecs)
Delay for a fixed number of microseconds.
Definition: timer.c:60
#define AR_RTC_FORCE_WAKE_ON_INT
Definition: reg.h:1220
#define REG_WRITE(_ah, _reg, _val)
Definition: hw.h:77
static int ath9k_hw_set_reset(struct ath_hw *ah, int type)
Definition: ath9k_hw.c:981
#define AR_WA
Definition: reg.h:698
uint8_t ah
Definition: registers.h:85
#define AR_RTC_FORCE_WAKE
Definition: reg.h:1217

References ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN, AR_RTC_FORCE_WAKE_ON_INT, AR_SREV_9300_20_OR_LATER, AR_WA, ath9k_hw_set_reset(), ath9k_hw_set_reset_power_on(), ATH9K_RESET_COLD, ATH9K_RESET_POWER_ON, ATH9K_RESET_WARM, REG_WRITE, type, and udelay().

Referenced by __ath9k_hw_init(), ath9k_hw_chip_reset(), ath9k_hw_disable(), ath9k_hw_phy_disable(), and ath9k_hw_set_power_awake().

◆ ath9k_hw_init_cal_settings()

static void ath9k_hw_init_cal_settings ( struct ath_hw ah)
static

Definition at line 31 of file ath9k_hw.c.

32 {
34 }
void(* init_cal_settings)(struct ath_hw *ah)
Definition: hw.h:552
uint8_t ah
Definition: registers.h:85
static struct ath_hw_private_ops * ath9k_hw_private_ops(struct ath_hw *ah)
Definition: hw.h:879

References ah, ath9k_hw_private_ops(), and ath_hw_private_ops::init_cal_settings.

Referenced by __ath9k_hw_init().

◆ ath9k_hw_init_mode_regs()

static void ath9k_hw_init_mode_regs ( struct ath_hw ah)
static

Definition at line 36 of file ath9k_hw.c.

37 {
39 }
void(* init_mode_regs)(struct ath_hw *ah)
Definition: hw.h:555
uint8_t ah
Definition: registers.h:85
static struct ath_hw_private_ops * ath9k_hw_private_ops(struct ath_hw *ah)
Definition: hw.h:879

References ah, ath9k_hw_private_ops(), and ath_hw_private_ops::init_mode_regs.

Referenced by __ath9k_hw_init().

◆ ath9k_hw_compute_pll_control()

static u32 ath9k_hw_compute_pll_control ( struct ath_hw ah,
struct ath9k_channel chan 
)
static

Definition at line 41 of file ath9k_hw.c.

43 {
45 }
uint8_t ah
Definition: registers.h:85
u32(* compute_pll_control)(struct ath_hw *ah, struct ath9k_channel *chan)
Definition: hw.h:582
static struct ath_hw_private_ops * ath9k_hw_private_ops(struct ath_hw *ah)
Definition: hw.h:879

References ah, ath9k_hw_private_ops(), and ath_hw_private_ops::compute_pll_control.

Referenced by ath9k_hw_init_pll().

◆ ath9k_hw_init_mode_gain_regs()

static void ath9k_hw_init_mode_gain_regs ( struct ath_hw ah)
static

Definition at line 47 of file ath9k_hw.c.

48 {
49  if (!ath9k_hw_private_ops(ah)->init_mode_gain_regs)
50  return;
51 
53 }
void(* init_mode_gain_regs)(struct ath_hw *ah)
Definition: hw.h:556
uint8_t ah
Definition: registers.h:85
static struct ath_hw_private_ops * ath9k_hw_private_ops(struct ath_hw *ah)
Definition: hw.h:879

References ah, ath9k_hw_private_ops(), and ath_hw_private_ops::init_mode_gain_regs.

Referenced by __ath9k_hw_init().

◆ ath9k_hw_ani_cache_ini_regs()

static void ath9k_hw_ani_cache_ini_regs ( struct ath_hw ah)
static

Definition at line 55 of file ath9k_hw.c.

56 {
57  /* You will not have this callback if using the old ANI */
58  if (!ath9k_hw_private_ops(ah)->ani_cache_ini_regs)
59  return;
60 
62 }
void(* ani_cache_ini_regs)(struct ath_hw *ah)
Definition: hw.h:591
uint8_t ah
Definition: registers.h:85
static struct ath_hw_private_ops * ath9k_hw_private_ops(struct ath_hw *ah)
Definition: hw.h:879

References ah, ath_hw_private_ops::ani_cache_ini_regs, and ath9k_hw_private_ops().

Referenced by ath9k_hw_reset().

◆ ath9k_hw_set_clockrate()

static void ath9k_hw_set_clockrate ( struct ath_hw ah)
static

Definition at line 68 of file ath9k_hw.c.

69 {
71  struct net80211_device *dev = common->dev;
72  unsigned int clockrate;
73 
74  if (!ah->curchan) /* should really check for CCK instead */
75  clockrate = ATH9K_CLOCK_RATE_CCK;
76  else if ((dev->channels + dev->channel)->band == NET80211_BAND_2GHZ)
77  clockrate = ATH9K_CLOCK_RATE_2GHZ_OFDM;
78  else if (ah->caps.hw_caps & ATH9K_HW_CAP_FASTCLOCK)
80  else
81  clockrate = ATH9K_CLOCK_RATE_5GHZ_OFDM;
82 
83  common->clockrate = clockrate;
84 }
u8 channel
The channel currently in use, as an index into the channels array.
Definition: net80211.h:812
#define ATH9K_CLOCK_RATE_5GHZ_OFDM
Definition: hw.h:993
#define NET80211_BAND_2GHZ
The 2.4 GHz ISM band, unlicensed in most countries.
Definition: net80211.h:45
#define ATH9K_CLOCK_RATE_2GHZ_OFDM
Definition: hw.h:994
Structure encapsulating the complete state of an 802.11 device.
Definition: net80211.h:786
static struct ath_common * ath9k_hw_common(struct ath_hw *ah)
Definition: hw.h:869
struct ib_cm_common common
Definition: ib_mad.h:11
struct net80211_channel channels[NET80211_MAX_CHANNELS]
A list of all possible channels we might use.
Definition: net80211.h:806
uint8_t ah
Definition: registers.h:85
#define ATH9K_CLOCK_RATE_CCK
Definition: hw.h:992
#define ATH9K_CLOCK_FAST_RATE_5GHZ_OFDM
Definition: hw.h:995

References ah, ATH9K_CLOCK_FAST_RATE_5GHZ_OFDM, ATH9K_CLOCK_RATE_2GHZ_OFDM, ATH9K_CLOCK_RATE_5GHZ_OFDM, ATH9K_CLOCK_RATE_CCK, ATH9K_HW_CAP_FASTCLOCK, ath9k_hw_common(), net80211_device::channel, net80211_device::channels, common, and NET80211_BAND_2GHZ.

Referenced by ath9k_hw_channel_change(), and ath9k_hw_reset().

◆ ath9k_hw_mac_to_clks()

static u32 ath9k_hw_mac_to_clks ( struct ath_hw ah,
u32  usecs 
)
static

Definition at line 86 of file ath9k_hw.c.

87 {
89 
90  return usecs * common->clockrate;
91 }
static struct ath_common * ath9k_hw_common(struct ath_hw *ah)
Definition: hw.h:869
struct ib_cm_common common
Definition: ib_mad.h:11
uint8_t ah
Definition: registers.h:85

References ah, ath9k_hw_common(), and common.

Referenced by ath9k_hw_set_ack_timeout(), ath9k_hw_set_cts_timeout(), and ath9k_hw_setslottime().

◆ ath9k_hw_wait()

int ath9k_hw_wait ( struct ath_hw ah,
u32  reg,
u32  mask,
u32  val,
u32  timeout 
)

Definition at line 93 of file ath9k_hw.c.

94 {
95  unsigned int i;
96 
97  for (i = 0; i < (timeout / AH_TIME_QUANTUM); i++) {
98  if ((REG_READ(ah, reg) & mask) == val)
99  return 1;
100 
102  }
103 
104  DBG("ath9k: "
105  "timeout (%d us) on reg 0x%x: 0x%08x & 0x%08x != 0x%08x\n",
106  timeout, reg, REG_READ(ah, reg), mask, val);
107 
108  return 0;
109 }
void udelay(unsigned long usecs)
Delay for a fixed number of microseconds.
Definition: timer.c:60
static unsigned int unsigned int reg
Definition: intel.h:245
#define REG_READ(_ah, _reg)
Definition: hw.h:80
void __asmcall int val
Definition: setjmp.h:28
#define AH_TIME_QUANTUM
Definition: hw.h:147
uint8_t ah
Definition: registers.h:85
void timeout(int)
#define DBG(...)
Print a debugging message.
Definition: compiler.h:498

References ah, AH_TIME_QUANTUM, DBG, reg, REG_READ, timeout(), udelay(), and val.

Referenced by ar5008_hw_rfbus_req(), ar9002_hw_init_cal(), ar9003_hw_init_cal(), ar9003_hw_rfbus_req(), ar9003_hw_tx_iq_cal_run(), ar9285_hw_cl_cal(), ar9300_otp_read_word(), ath9k_hw_set_reset(), ath9k_hw_set_reset_power_on(), ath9k_hw_setrxabort(), and ath_pci_eeprom_read().

◆ ath9k_hw_write_array()

void ath9k_hw_write_array ( struct ath_hw ah,
struct ar5416IniArray array,
int  column,
unsigned int *  writecnt 
)

Definition at line 111 of file ath9k_hw.c.

113 {
114  unsigned int r;
115 
117  for (r = 0; r < array->ia_rows; r++) {
118  REG_WRITE(ah, INI_RA(array, r, 0),
119  INI_RA(array, r, column));
120  DO_DELAY(*writecnt);
121  }
123 }
#define DO_DELAY(x)
Definition: hw.h:112
#define INI_RA(iniarray, row, column)
Definition: calib.h:45
#define REGWRITE_BUFFER_FLUSH(_ah)
Definition: hw.h:95
uint32_t array
Array number.
Definition: edd.h:30
uint32_t column[4]
Viewed as an array of four-byte columns.
Definition: aes.h:14
#define REG_WRITE(_ah, _reg, _val)
Definition: hw.h:77
uint8_t ah
Definition: registers.h:85
#define ENABLE_REGWRITE_BUFFER(_ah)
Definition: hw.h:89
static const uint8_t r[3][4]
MD4 shift amounts.
Definition: md4.c:53

References ah, array, column, DO_DELAY, ENABLE_REGWRITE_BUFFER, INI_RA, r, REG_WRITE, and REGWRITE_BUFFER_FLUSH.

◆ ath9k_hw_reverse_bits()

u32 ath9k_hw_reverse_bits ( u32  val,
u32  n 
)

Definition at line 125 of file ath9k_hw.c.

126 {
127  u32 retval;
128  unsigned int i;
129 
130  for (i = 0, retval = 0; i < n; i++) {
131  retval = (retval << 1) | (val & 1);
132  val >>= 1;
133  }
134  return retval;
135 }
void __asmcall int val
Definition: setjmp.h:28
unsigned long retval
Definition: xen.h:45
unsigned int n
Definition: entropy.h:159
uint32_t u32
Definition: stdint.h:23

References n, retval, and val.

Referenced by ar5008_hw_force_bias(), ar5008_hw_phy_modify_rx_buffer(), ar5008_hw_set_channel(), and ar9002_hw_get_radiorev().

◆ ath9k_hw_computetxtime()

u16 ath9k_hw_computetxtime ( struct ath_hw ah,
u8  phy,
int  kbps,
u32  frameLen,
u16  rateix,
int  shortPreamble 
)

Definition at line 137 of file ath9k_hw.c.

141 {
142  u32 bitsPerSymbol, numBits, numSymbols, phyTime, txTime;
143 
144  if (kbps == 0)
145  return 0;
146 
147  switch (phy) {
148  case CHANNEL_CCK:
149  phyTime = CCK_PREAMBLE_BITS + CCK_PLCP_BITS;
150  if (shortPreamble)
151  phyTime >>= 1;
152  numBits = frameLen << 3;
153  txTime = CCK_SIFS_TIME + phyTime + ((numBits * 1000) / kbps);
154  break;
155  case CHANNEL_OFDM:
156  if (ah->curchan && IS_CHAN_QUARTER_RATE(ah->curchan)) {
157  bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME_QUARTER) / 1000;
158  numBits = OFDM_PLCP_BITS + (frameLen << 3);
159  numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
160  txTime = OFDM_SIFS_TIME_QUARTER
162  + (numSymbols * OFDM_SYMBOL_TIME_QUARTER);
163  } else if (ah->curchan &&
164  IS_CHAN_HALF_RATE(ah->curchan)) {
165  bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME_HALF) / 1000;
166  numBits = OFDM_PLCP_BITS + (frameLen << 3);
167  numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
168  txTime = OFDM_SIFS_TIME_HALF +
170  + (numSymbols * OFDM_SYMBOL_TIME_HALF);
171  } else {
172  bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME) / 1000;
173  numBits = OFDM_PLCP_BITS + (frameLen << 3);
174  numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
176  + (numSymbols * OFDM_SYMBOL_TIME);
177  }
178  break;
179  default:
180  DBG("ath9k: "
181  "Unknown phy %d (rate ix %d)\n", phy, rateix);
182  txTime = 0;
183  break;
184  }
185 
186  return txTime;
187 }
#define OFDM_SYMBOL_TIME_QUARTER
Definition: mac.h:68
#define OFDM_SIFS_TIME_HALF
Definition: mac.h:60
#define OFDM_SIFS_TIME
Definition: mac.h:55
#define IS_CHAN_HALF_RATE(_c)
Definition: hw.h:362
#define OFDM_SIFS_TIME_QUARTER
Definition: mac.h:65
#define IS_CHAN_QUARTER_RATE(_c)
Definition: hw.h:363
#define CHANNEL_CCK
Definition: ath5k.h:630
#define OFDM_PREAMBLE_TIME
Definition: mac.h:56
#define OFDM_PREAMBLE_TIME_HALF
Definition: mac.h:61
#define CHANNEL_OFDM
Definition: ath5k.h:631
#define OFDM_PLCP_BITS
Definition: ath9k_xmit.c:26
#define CCK_PREAMBLE_BITS
Definition: mac.h:52
#define CCK_SIFS_TIME
Definition: mac.h:51
#define OFDM_PREAMBLE_TIME_QUARTER
Definition: mac.h:66
#define OFDM_SYMBOL_TIME_HALF
Definition: mac.h:63
#define CCK_PLCP_BITS
Definition: mac.h:53
uint8_t ah
Definition: registers.h:85
#define DBG(...)
Print a debugging message.
Definition: compiler.h:498
#define OFDM_SYMBOL_TIME
Definition: mac.h:58
uint32_t u32
Definition: stdint.h:23
#define DIV_ROUND_UP(n, d)
Definition: ath.h:29

References ah, CCK_PLCP_BITS, CCK_PREAMBLE_BITS, CCK_SIFS_TIME, CHANNEL_CCK, CHANNEL_OFDM, DBG, DIV_ROUND_UP, IS_CHAN_HALF_RATE, IS_CHAN_QUARTER_RATE, OFDM_PLCP_BITS, OFDM_PREAMBLE_TIME, OFDM_PREAMBLE_TIME_HALF, OFDM_PREAMBLE_TIME_QUARTER, OFDM_SIFS_TIME, OFDM_SIFS_TIME_HALF, OFDM_SIFS_TIME_QUARTER, OFDM_SYMBOL_TIME, OFDM_SYMBOL_TIME_HALF, and OFDM_SYMBOL_TIME_QUARTER.

Referenced by ath_buf_set_rate().

◆ ath9k_hw_get_channel_centers()

void ath9k_hw_get_channel_centers ( struct ath_hw *ah  __unused,
struct ath9k_channel chan,
struct chan_centers centers 
)

Definition at line 189 of file ath9k_hw.c.

192 {
193  int8_t extoff;
194 
195  if (!IS_CHAN_HT40(chan)) {
196  centers->ctl_center = centers->ext_center =
197  centers->synth_center = chan->channel;
198  return;
199  }
200 
201  if ((chan->chanmode == CHANNEL_A_HT40PLUS) ||
202  (chan->chanmode == CHANNEL_G_HT40PLUS)) {
203  centers->synth_center =
205  extoff = 1;
206  } else {
207  centers->synth_center =
209  extoff = -1;
210  }
211 
212  centers->ctl_center =
213  centers->synth_center - (extoff * HT40_CHANNEL_CENTER_SHIFT);
214  /* 25 MHz spacing is supported by hw but not on upper layers */
215  centers->ext_center =
216  centers->synth_center + (extoff * HT40_CHANNEL_CENTER_SHIFT);
217 }
u16 channel
Definition: hw.h:349
u32 chanmode
Definition: hw.h:351
u16 synth_center
Definition: hw.h:422
u16 ext_center
Definition: hw.h:424
signed char int8_t
Definition: stdint.h:15
#define HT40_CHANNEL_CENTER_SHIFT
Definition: hw.h:136
#define CHANNEL_A_HT40PLUS
Definition: hw.h:321
#define IS_CHAN_HT40(_c)
Definition: hw.h:372
#define CHANNEL_G_HT40PLUS
Definition: hw.h:319
u16 ctl_center
Definition: hw.h:423

References ath9k_channel::chanmode, ath9k_channel::channel, CHANNEL_A_HT40PLUS, CHANNEL_G_HT40PLUS, chan_centers::ctl_center, chan_centers::ext_center, HT40_CHANNEL_CENTER_SHIFT, IS_CHAN_HT40, and chan_centers::synth_center.

Referenced by ar5008_hw_set_channel(), ar5008_hw_set_delta_slope(), ar9002_hw_set_channel(), ar9002_hw_spur_mitigate(), ar9003_hw_set_channel(), ar9003_hw_set_delta_slope(), ar9003_hw_set_power_per_rate_table(), ar9287_eeprom_get_tx_gain_index(), ath9k_get_txgain_index(), ath9k_hw_def_set_addac(), ath9k_hw_get_gain_boundaries_pdadcs(), ath9k_hw_get_legacy_target_powers(), ath9k_hw_get_target_powers(), ath9k_hw_set_4k_power_per_rate_table(), ath9k_hw_set_ar9287_power_per_rate_table(), and ath9k_hw_set_def_power_per_rate_table().

◆ ath9k_hw_read_revisions()

static void ath9k_hw_read_revisions ( struct ath_hw ah)
static

Definition at line 223 of file ath9k_hw.c.

224 {
225  u32 val;
226 
227  switch (ah->hw_version.devid) {
228  case AR5416_AR9100_DEVID:
229  ah->hw_version.macVersion = AR_SREV_VERSION_9100;
230  break;
231  case AR9300_DEVID_AR9340:
232  ah->hw_version.macVersion = AR_SREV_VERSION_9340;
233  val = REG_READ(ah, AR_SREV);
234  ah->hw_version.macRev = MS(val, AR_SREV_REVISION2);
235  return;
236  }
237 
239 
240  if (val == 0xFF) {
241  val = REG_READ(ah, AR_SREV);
242  ah->hw_version.macVersion =
244  ah->hw_version.macRev = MS(val, AR_SREV_REVISION2);
245  ah->is_pciexpress = (val & AR_SREV_TYPE2_HOST_MODE) ? 0 : 1;
246  } else {
247  if (!AR_SREV_9100(ah))
248  ah->hw_version.macVersion = MS(val, AR_SREV_VERSION);
249 
250  ah->hw_version.macRev = val & AR_SREV_REVISION;
251 
252  if (ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCIE)
253  ah->is_pciexpress = 1;
254  }
255 }
#define AR_SREV_TYPE2_HOST_MODE
Definition: reg.h:762
#define AR_SREV_ID
Definition: reg.h:750
#define MS(_v, _f)
Definition: hw.h:102
#define AR5416_AR9100_DEVID
Definition: hw.h:55
#define AR_SREV_9100(ah)
Definition: reg.h:810
#define AR_SREV_VERSION2
Definition: reg.h:757
#define AR_SREV_VERSION_9340
Definition: reg.h:796
#define REG_READ(_ah, _reg)
Definition: hw.h:80
void __asmcall int val
Definition: setjmp.h:28
#define AR_SREV_TYPE2_S
Definition: reg.h:760
#define AR_SREV_REVISION2
Definition: reg.h:763
#define AR_SREV
Definition: reg.h:746
uint8_t ah
Definition: registers.h:85
#define AR_SREV_VERSION_5416_PCIE
Definition: reg.h:767
#define AR9300_DEVID_AR9340
Definition: hw.h:52
#define AR_SREV_REVISION
Definition: reg.h:754
#define AR_SREV_VERSION_9100
Definition: reg.h:771
#define AR_SREV_VERSION
Definition: reg.h:752
uint32_t u32
Definition: stdint.h:23

References ah, AR5416_AR9100_DEVID, AR9300_DEVID_AR9340, AR_SREV, AR_SREV_9100, AR_SREV_ID, AR_SREV_REVISION, AR_SREV_REVISION2, AR_SREV_TYPE2_HOST_MODE, AR_SREV_TYPE2_S, AR_SREV_VERSION, AR_SREV_VERSION2, AR_SREV_VERSION_5416_PCIE, AR_SREV_VERSION_9100, AR_SREV_VERSION_9340, MS, REG_READ, and val.

Referenced by __ath9k_hw_init().

◆ ath9k_hw_disablepcie()

static void ath9k_hw_disablepcie ( struct ath_hw ah)
static

Definition at line 261 of file ath9k_hw.c.

262 {
263  if (!AR_SREV_5416(ah))
264  return;
265 
266  REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fc00);
267  REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924);
268  REG_WRITE(ah, AR_PCIE_SERDES, 0x28000029);
269  REG_WRITE(ah, AR_PCIE_SERDES, 0x57160824);
270  REG_WRITE(ah, AR_PCIE_SERDES, 0x25980579);
271  REG_WRITE(ah, AR_PCIE_SERDES, 0x00000000);
272  REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40);
273  REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554);
274  REG_WRITE(ah, AR_PCIE_SERDES, 0x000e1007);
275 
276  REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);
277 }
#define AR_PCIE_SERDES
Definition: reg.h:981
#define AR_PCIE_SERDES2
Definition: reg.h:982
#define AR_SREV_5416(_ah)
Definition: reg.h:798
#define REG_WRITE(_ah, _reg, _val)
Definition: hw.h:77
uint8_t ah
Definition: registers.h:85

References ah, AR_PCIE_SERDES, AR_PCIE_SERDES2, AR_SREV_5416, and REG_WRITE.

Referenced by __ath9k_hw_init().

◆ ath9k_hw_chip_test()

static int ath9k_hw_chip_test ( struct ath_hw ah)
static

Definition at line 280 of file ath9k_hw.c.

281 {
282  u32 regAddr[2] = { AR_STA_ID0 };
283  u32 regHold[2];
284  static const u32 patternData[4] = {
285  0x55555555, 0xaaaaaaaa, 0x66666666, 0x99999999
286  };
287  int i, j, loop_max;
288 
290  loop_max = 2;
291  regAddr[1] = AR_PHY_BASE + (8 << 2);
292  } else
293  loop_max = 1;
294 
295  for (i = 0; i < loop_max; i++) {
296  u32 addr = regAddr[i];
297  u32 wrData, rdData;
298 
299  regHold[i] = REG_READ(ah, addr);
300  for (j = 0; j < 0x100; j++) {
301  wrData = (j << 16) | j;
302  REG_WRITE(ah, addr, wrData);
303  rdData = REG_READ(ah, addr);
304  if (rdData != wrData) {
305  DBG("ath9k: "
306  "address test failed addr: 0x%08x - wr:0x%08x != rd:0x%08x\n",
307  addr, wrData, rdData);
308  return 0;
309  }
310  }
311  for (j = 0; j < 4; j++) {
312  wrData = patternData[j];
313  REG_WRITE(ah, addr, wrData);
314  rdData = REG_READ(ah, addr);
315  if (wrData != rdData) {
316  DBG("ath9k: "
317  "address test failed addr: 0x%08x - wr:0x%08x != rd:0x%08x\n",
318  addr, wrData, rdData);
319  return 0;
320  }
321  }
322  REG_WRITE(ah, regAddr[i], regHold[i]);
323  }
324  udelay(100);
325 
326  return 1;
327 }
#define AR_SREV_9300_20_OR_LATER(_ah)
Definition: reg.h:864
void udelay(unsigned long usecs)
Delay for a fixed number of microseconds.
Definition: timer.c:60
#define AR_STA_ID0
Definition: reg.h:1431
u32 addr
Definition: sky2.h:8
#define REG_READ(_ah, _reg)
Definition: hw.h:80
#define REG_WRITE(_ah, _reg, _val)
Definition: hw.h:77
#define AR_PHY_BASE
Definition: phy.h:26
uint8_t ah
Definition: registers.h:85
#define DBG(...)
Print a debugging message.
Definition: compiler.h:498
uint32_t u32
Definition: stdint.h:23

References addr, ah, AR_PHY_BASE, AR_SREV_9300_20_OR_LATER, AR_STA_ID0, DBG, REG_READ, REG_WRITE, and udelay().

Referenced by ath9k_hw_post_init().

◆ ath9k_hw_init_config()

static void ath9k_hw_init_config ( struct ath_hw ah)
static

Definition at line 329 of file ath9k_hw.c.

330 {
331  int i;
332 
333  ah->config.dma_beacon_response_time = 2;
334  ah->config.sw_beacon_response_time = 10;
335  ah->config.additional_swba_backoff = 0;
336  ah->config.ack_6mb = 0x0;
337  ah->config.cwm_ignore_extcca = 0;
338  ah->config.pcie_powersave_enable = 0;
339  ah->config.pcie_clock_req = 0;
340  ah->config.pcie_waen = 0;
341  ah->config.analog_shiftreg = 1;
342  ah->config.enable_ani = 1;
343 
344  for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) {
345  ah->config.spurchans[i][0] = AR_NO_SPUR;
346  ah->config.spurchans[i][1] = AR_NO_SPUR;
347  }
348 
349  /* PAPRD needs some more work to be enabled */
350  ah->config.paprd_disable = 1;
351 
352  ah->config.rx_intr_mitigation = 1;
353  ah->config.pcieSerDesWrite = 1;
354 }
#define AR_EEPROM_MODAL_SPURS
Definition: eeprom.h:25
#define AR_NO_SPUR
Definition: hw.h:240
uint8_t ah
Definition: registers.h:85

References ah, AR_EEPROM_MODAL_SPURS, and AR_NO_SPUR.

Referenced by __ath9k_hw_init().

◆ ath9k_hw_init_defaults()

static void ath9k_hw_init_defaults ( struct ath_hw ah)
static

Definition at line 356 of file ath9k_hw.c.

357 {
358  struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
359 
360  regulatory->country_code = CTRY_DEFAULT;
361  regulatory->power_limit = MAX_RATE_POWER;
362  regulatory->tp_scale = ATH9K_TP_SCALE_MAX;
363 
364  ah->hw_version.magic = AR5416_MAGIC;
365  ah->hw_version.subvendorid = 0;
366 
367  ah->atim_window = 0;
368  ah->sta_id1_defaults =
371  if (AR_SREV_9100(ah))
372  ah->sta_id1_defaults |= AR_STA_ID1_AR9100_BA_FIX;
373  ah->enable_32kHz_clock = DONT_USE_32KHZ;
374  ah->slottime = 20;
375  ah->globaltxtimeout = (u32) -1;
376  ah->power_mode = ATH9K_PM_UNDEFINED;
377 }
u16 country_code
Definition: ath.h:138
#define AR5416_MAGIC
Definition: hw.h:59
#define AR_SREV_9100(ah)
Definition: reg.h:810
#define CTRY_DEFAULT
Definition: eeprom.h:37
static struct ath_regulatory * ath9k_hw_regulatory(struct ath_hw *ah)
Definition: hw.h:874
#define u32
Definition: vga.h:21
int16_t power_limit
Definition: ath.h:143
#define AR_STA_ID1_MCAST_KSRCH
Definition: reg.h:1450
uint8_t ah
Definition: registers.h:85
#define AR_STA_ID1_AR9100_BA_FIX
Definition: reg.h:1441
#define AR_STA_ID1_CRPT_MIC_ENABLE
Definition: reg.h:1446
#define MAX_RATE_POWER
Definition: hw.h:144
u32 tp_scale
Definition: ath.h:140

References ah, AR5416_MAGIC, AR_SREV_9100, AR_STA_ID1_AR9100_BA_FIX, AR_STA_ID1_CRPT_MIC_ENABLE, AR_STA_ID1_MCAST_KSRCH, ath9k_hw_regulatory(), ATH9K_PM_UNDEFINED, ATH9K_TP_SCALE_MAX, ath_regulatory::country_code, CTRY_DEFAULT, MAX_RATE_POWER, ath_regulatory::power_limit, ath_regulatory::tp_scale, and u32.

Referenced by __ath9k_hw_init().

◆ ath9k_hw_init_macaddr()

static int ath9k_hw_init_macaddr ( struct ath_hw ah)
static

Definition at line 379 of file ath9k_hw.c.

380 {
381  struct ath_common *common = ath9k_hw_common(ah);
382  u32 sum;
383  int i;
384  u16 eeval;
385  static const u32 EEP_MAC[] = { EEP_MAC_LSW, EEP_MAC_MID, EEP_MAC_MSW };
386 
387  sum = 0;
388  for (i = 0; i < 3; i++) {
389  eeval = ah->eep_ops->get_eeprom(ah, EEP_MAC[i]);
390  sum += eeval;
391  common->macaddr[2 * i] = eeval >> 8;
392  common->macaddr[2 * i + 1] = eeval & 0xff;
393  }
394  if (sum == 0 || sum == 0xffff * 3)
395  return -EADDRNOTAVAIL;
396 
397  return 0;
398 }
uint16_t u16
Definition: stdint.h:21
static struct ath_common * ath9k_hw_common(struct ath_hw *ah)
Definition: hw.h:869
struct ib_cm_common common
Definition: ib_mad.h:11
#define EADDRNOTAVAIL
Address not available.
Definition: errno.h:308
uint8_t ah
Definition: registers.h:85
uint32_t u32
Definition: stdint.h:23

References ah, ath9k_hw_common(), common, EADDRNOTAVAIL, EEP_MAC_LSW, EEP_MAC_MID, and EEP_MAC_MSW.

Referenced by __ath9k_hw_init().

◆ ath9k_hw_post_init()

static int ath9k_hw_post_init ( struct ath_hw ah)
static

Definition at line 400 of file ath9k_hw.c.

401 {
402  struct ath_common *common = ath9k_hw_common(ah);
403  int ecode;
404 
405  if (common->bus_ops->ath_bus_type != ATH_USB) {
406  if (!ath9k_hw_chip_test(ah))
407  return -ENODEV;
408  }
409 
411  ecode = ar9002_hw_rf_claim(ah);
412  if (ecode != 0)
413  return ecode;
414  }
415 
416  ecode = ath9k_hw_eeprom_init(ah);
417  if (ecode != 0)
418  return ecode;
419 
420  DBG("ath9k: "
421  "Eeprom VER: %d, REV: %d\n",
422  ah->eep_ops->get_eeprom_ver(ah),
423  ah->eep_ops->get_eeprom_rev(ah));
424 
426  if (ecode) {
427  DBG("ath9k: "
428  "Failed allocating banks for external radio\n");
430  return ecode;
431  }
432 
433  if (!AR_SREV_9100(ah) && !AR_SREV_9340(ah)) {
436  }
437 
438  return 0;
439 }
int ath9k_hw_eeprom_init(struct ath_hw *ah)
Definition: ath9k_eeprom.c:530
#define AR_SREV_9100(ah)
Definition: reg.h:810
static int ath9k_hw_rf_alloc_ext_banks(struct ath_hw *ah)
Definition: hw-ops.h:154
Definition: ath.h:127
#define AR_SREV_9300_20_OR_LATER(_ah)
Definition: reg.h:864
int ar9002_hw_rf_claim(struct ath_hw *ah)
#define AR_SREV_9340(_ah)
Definition: reg.h:878
static int ath9k_hw_chip_test(struct ath_hw *ah)
Definition: ath9k_hw.c:280
#define ENODEV
No such device.
Definition: errno.h:509
static struct ath_common * ath9k_hw_common(struct ath_hw *ah)
Definition: hw.h:869
struct ib_cm_common common
Definition: ib_mad.h:11
static void ath9k_hw_rf_free_ext_banks(struct ath_hw *ah)
Definition: hw-ops.h:162
void ath9k_hw_ani_init(struct ath_hw *ah)
Definition: ath9k_ani.c:664
uint8_t ah
Definition: registers.h:85
#define DBG(...)
Print a debugging message.
Definition: compiler.h:498
void ath9k_hw_ani_setup(struct ath_hw *ah)
Definition: ath9k_ani.c:647

References ah, ar9002_hw_rf_claim(), AR_SREV_9100, AR_SREV_9300_20_OR_LATER, AR_SREV_9340, ath9k_hw_ani_init(), ath9k_hw_ani_setup(), ath9k_hw_chip_test(), ath9k_hw_common(), ath9k_hw_eeprom_init(), ath9k_hw_rf_alloc_ext_banks(), ath9k_hw_rf_free_ext_banks(), ATH_USB, common, DBG, and ENODEV.

Referenced by __ath9k_hw_init().

◆ ath9k_hw_attach_ops()

static void ath9k_hw_attach_ops ( struct ath_hw ah)
static

Definition at line 441 of file ath9k_hw.c.

442 {
445  else
447 }
void ar9003_hw_attach_ops(struct ath_hw *ah)
#define AR_SREV_9300_20_OR_LATER(_ah)
Definition: reg.h:864
void ar9002_hw_attach_ops(struct ath_hw *ah)
uint8_t ah
Definition: registers.h:85

References ah, ar9002_hw_attach_ops(), ar9003_hw_attach_ops(), and AR_SREV_9300_20_OR_LATER.

Referenced by __ath9k_hw_init().

◆ __ath9k_hw_init()

static int __ath9k_hw_init ( struct ath_hw ah)
static

Definition at line 450 of file ath9k_hw.c.

451 {
452  struct ath_common *common = ath9k_hw_common(ah);
453  int r = 0;
454 
456 
457  /*
458  * Read back AR_WA into a permanent copy and set bits 14 and 17.
459  * We need to do this to avoid RMW of this register. We cannot
460  * read the reg when chip is asleep.
461  */
462  ah->WARegVal = REG_READ(ah, AR_WA);
463  ah->WARegVal |= (AR_WA_D3_L1_DISABLE |
465 
467  DBG("ath9k: Couldn't reset chip\n");
468  return -EIO;
469  }
470 
473 
475 
477  DBG("ath9k: Couldn't wakeup chip\n");
478  return -EIO;
479  }
480 
481  if (ah->config.serialize_regmode == SER_REG_MODE_AUTO) {
482  if (ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCI ||
483  ((AR_SREV_9160(ah) || AR_SREV_9280(ah)) &&
484  !ah->is_pciexpress)) {
485  ah->config.serialize_regmode =
487  } else {
488  ah->config.serialize_regmode =
490  }
491  }
492 
493  DBG2("ath9k: serialize_regmode is %d\n",
494  ah->config.serialize_regmode);
495 
496  if (AR_SREV_9285(ah) || AR_SREV_9271(ah))
497  ah->config.max_txtrig_level = MAX_TX_FIFO_THRESHOLD >> 1;
498  else
499  ah->config.max_txtrig_level = MAX_TX_FIFO_THRESHOLD;
500 
501  switch (ah->hw_version.macVersion) {
513  break;
514  default:
515  DBG("ath9k: "
516  "Mac Chip Rev 0x%02x.%x is not supported by this driver\n",
517  ah->hw_version.macVersion, ah->hw_version.macRev);
518  return -EOPNOTSUPP;
519  }
520 
522  ah->is_pciexpress = 0;
523 
524  ah->hw_version.phyRev = REG_READ(ah, AR_PHY_CHIP_ID);
526 
527  ah->ani_function = ATH9K_ANI_ALL;
529  ah->ani_function &= ~ATH9K_ANI_NOISE_IMMUNITY_LEVEL;
531  ah->ani_function &= ~ATH9K_ANI_MRC_CCK;
532 
534 
535 
536  if (ah->is_pciexpress)
538  else
540 
543 
545  if (r)
546  return r;
547 
550  if (r)
551  return r;
552 
554  if (r) {
555  DBG("ath9k: Failed to initialize MAC address\n");
556  return r;
557  }
558 
559  if (AR_SREV_9285(ah) || AR_SREV_9271(ah))
560  ah->tx_trig_level = (AR_FTRIG_256B >> AR_FTRIG_S);
561  else
562  ah->tx_trig_level = (AR_FTRIG_512B >> AR_FTRIG_S);
563 
564  common->state = ATH_HW_INITIALIZED;
565 
566  return 0;
567 }
#define AR_SREV_VERSION_9485
Definition: reg.h:793
static void ath9k_hw_attach_ops(struct ath_hw *ah)
Definition: ath9k_hw.c:441
#define AR_SREV_9280_20_OR_LATER(_ah)
Definition: reg.h:824
#define AR_FTRIG_512B
Definition: reg.h:96
static void ath9k_hw_init_mode_gain_regs(struct ath_hw *ah)
Definition: ath9k_hw.c:47
#define AR_SREV_VERSION_9300
Definition: reg.h:791
#define AR_SREV_9100(ah)
Definition: reg.h:810
#define AR_SREV_9285(_ah)
Definition: reg.h:829
static void ath9k_hw_configpcipowersave(struct ath_hw *ah, int restore, int power_off)
Definition: hw-ops.h:26
static void ath9k_hw_init_defaults(struct ath_hw *ah)
Definition: ath9k_hw.c:356
#define AR_FTRIG_256B
Definition: reg.h:95
#define AR_SREV_VERSION_9340
Definition: reg.h:796
#define AR_SREV_VERSION_9160
Definition: reg.h:772
static void ath9k_hw_init_cal_settings(struct ath_hw *ah)
Definition: ath9k_hw.c:31
#define AR_SREV_9300_20_OR_LATER(_ah)
Definition: reg.h:864
int ath9k_hw_fill_cap_info(struct ath_hw *ah)
Definition: ath9k_hw.c:1569
#define AR_WA_D3_L1_DISABLE
Definition: reg.h:702
#define AR_SREV_9160(_ah)
Definition: reg.h:815
static void ath9k_hw_read_revisions(struct ath_hw *ah)
Definition: ath9k_hw.c:223
static int ath9k_hw_init_macaddr(struct ath_hw *ah)
Definition: ath9k_hw.c:379
#define AR_SREV_9340(_ah)
Definition: reg.h:878
#define AR_SREV_VERSION_5416_PCI
Definition: reg.h:766
#define AR_SREV_VERSION_9271
Definition: reg.h:788
#define AR_SREV_VERSION_9280
Definition: reg.h:775
#define AR_SREV_9280(_ah)
Definition: reg.h:822
#define EOPNOTSUPP
Operation not supported on socket.
Definition: errno.h:604
static struct ath_common * ath9k_hw_common(struct ath_hw *ah)
Definition: hw.h:869
static int ath9k_hw_post_init(struct ath_hw *ah)
Definition: ath9k_hw.c:400
static int ath9k_hw_set_reset_reg(struct ath_hw *ah, u32 type)
Definition: ath9k_hw.c:1088
struct ib_cm_common common
Definition: ib_mad.h:11
#define REG_READ(_ah, _reg)
Definition: hw.h:80
int ath9k_hw_setpower(struct ath_hw *ah, enum ath9k_power_mode mode)
Definition: ath9k_hw.c:1532
#define AR_FTRIG_S
Definition: reg.h:90
static void ath9k_hw_disablepcie(struct ath_hw *ah)
Definition: ath9k_hw.c:261
void ar9002_hw_cck_chan14_spread(struct ath_hw *ah)
#define AR_SREV_VERSION_9285
Definition: reg.h:779
#define EIO
Input/output error.
Definition: errno.h:433
#define AR_SREV_9271(_ah)
Definition: reg.h:853
static void ath9k_hw_init_config(struct ath_hw *ah)
Definition: ath9k_hw.c:329
#define AR_WA_ASPM_TIMER_BASED_DISABLE
Definition: reg.h:704
#define AR_WA
Definition: reg.h:698
uint8_t ah
Definition: registers.h:85
#define AR_SREV_VERSION_5416_PCIE
Definition: reg.h:767
#define DBG(...)
Print a debugging message.
Definition: compiler.h:498
#define AR_SREV_VERSION_9100
Definition: reg.h:771
static void ath9k_hw_init_mode_regs(struct ath_hw *ah)
Definition: ath9k_hw.c:36
#define AR_SREV_VERSION_9287
Definition: reg.h:783
#define AR_PHY_CHIP_ID
Definition: phy.h:45
#define MAX_TX_FIFO_THRESHOLD
Definition: mac.h:108
#define DBG2(...)
Definition: compiler.h:515
static const uint8_t r[3][4]
MD4 shift amounts.
Definition: md4.c:53

References ah, ar9002_hw_cck_chan14_spread(), AR_FTRIG_256B, AR_FTRIG_512B, AR_FTRIG_S, AR_PHY_CHIP_ID, AR_SREV_9100, AR_SREV_9160, AR_SREV_9271, AR_SREV_9280, AR_SREV_9280_20_OR_LATER, AR_SREV_9285, AR_SREV_9300_20_OR_LATER, AR_SREV_9340, AR_SREV_VERSION_5416_PCI, AR_SREV_VERSION_5416_PCIE, AR_SREV_VERSION_9100, AR_SREV_VERSION_9160, AR_SREV_VERSION_9271, AR_SREV_VERSION_9280, AR_SREV_VERSION_9285, AR_SREV_VERSION_9287, AR_SREV_VERSION_9300, AR_SREV_VERSION_9340, AR_SREV_VERSION_9485, AR_WA, AR_WA_ASPM_TIMER_BASED_DISABLE, AR_WA_D3_L1_DISABLE, ATH9K_ANI_ALL, ATH9K_ANI_MRC_CCK, ATH9K_ANI_NOISE_IMMUNITY_LEVEL, ath9k_hw_attach_ops(), ath9k_hw_common(), ath9k_hw_configpcipowersave(), ath9k_hw_disablepcie(), ath9k_hw_fill_cap_info(), ath9k_hw_init_cal_settings(), ath9k_hw_init_config(), ath9k_hw_init_defaults(), ath9k_hw_init_macaddr(), ath9k_hw_init_mode_gain_regs(), ath9k_hw_init_mode_regs(), ath9k_hw_post_init(), ath9k_hw_read_revisions(), ath9k_hw_set_reset_reg(), ath9k_hw_setpower(), ATH9K_PM_AWAKE, ATH9K_RESET_POWER_ON, ATH_HW_INITIALIZED, common, DBG, DBG2, EIO, EOPNOTSUPP, MAX_TX_FIFO_THRESHOLD, r, REG_READ, SER_REG_MODE_AUTO, SER_REG_MODE_OFF, and SER_REG_MODE_ON.

Referenced by ath9k_hw_init().

◆ ath9k_hw_init()

int ath9k_hw_init ( struct ath_hw ah)

Definition at line 569 of file ath9k_hw.c.

570 {
571  int ret;
572  struct ath_common *common = ath9k_hw_common(ah);
573 
574  /* These are all the AR5008/AR9001/AR9002 hardware family of chipsets */
575  switch (ah->hw_version.devid) {
576  case AR5416_DEVID_PCI:
577  case AR5416_DEVID_PCIE:
578  case AR5416_AR9100_DEVID:
579  case AR9160_DEVID_PCI:
580  case AR9280_DEVID_PCI:
581  case AR9280_DEVID_PCIE:
582  case AR9285_DEVID_PCIE:
583  case AR9287_DEVID_PCI:
584  case AR9287_DEVID_PCIE:
585  case AR2427_DEVID_PCIE:
586  case AR9300_DEVID_PCIE:
588  case AR9300_DEVID_AR9340:
589  break;
590  default:
591  if (common->bus_ops->ath_bus_type == ATH_USB)
592  break;
593  DBG("ath9k: Hardware device ID 0x%04x not supported\n",
594  ah->hw_version.devid);
595  return -EOPNOTSUPP;
596  }
597 
598  ret = __ath9k_hw_init(ah);
599  if (ret) {
600  DBG("ath9k: "
601  "Unable to initialize hardware; initialization status: %d\n",
602  ret);
603  return ret;
604  }
605 
606  return 0;
607 }
#define AR5416_AR9100_DEVID
Definition: hw.h:55
#define AR5416_DEVID_PCIE
Definition: hw.h:43
#define AR9300_DEVID_AR9485_PCIE
Definition: hw.h:53
Definition: ath.h:127
#define AR9300_DEVID_PCIE
Definition: hw.h:51
#define AR9287_DEVID_PCI
Definition: hw.h:49
static int __ath9k_hw_init(struct ath_hw *ah)
Definition: ath9k_hw.c:450
#define EOPNOTSUPP
Operation not supported on socket.
Definition: errno.h:604
static struct ath_common * ath9k_hw_common(struct ath_hw *ah)
Definition: hw.h:869
#define AR9280_DEVID_PCIE
Definition: hw.h:46
struct ib_cm_common common
Definition: ib_mad.h:11
#define AR9287_DEVID_PCIE
Definition: hw.h:50
#define AR9160_DEVID_PCI
Definition: hw.h:44
#define AR9280_DEVID_PCI
Definition: hw.h:45
uint8_t ah
Definition: registers.h:85
#define AR9300_DEVID_AR9340
Definition: hw.h:52
#define DBG(...)
Print a debugging message.
Definition: compiler.h:498
#define AR2427_DEVID_PCIE
Definition: hw.h:48
#define AR9285_DEVID_PCIE
Definition: hw.h:47
#define AR5416_DEVID_PCI
Definition: hw.h:42

References __ath9k_hw_init(), ah, AR2427_DEVID_PCIE, AR5416_AR9100_DEVID, AR5416_DEVID_PCI, AR5416_DEVID_PCIE, AR9160_DEVID_PCI, AR9280_DEVID_PCI, AR9280_DEVID_PCIE, AR9285_DEVID_PCIE, AR9287_DEVID_PCI, AR9287_DEVID_PCIE, AR9300_DEVID_AR9340, AR9300_DEVID_AR9485_PCIE, AR9300_DEVID_PCIE, ath9k_hw_common(), ATH_USB, common, DBG, and EOPNOTSUPP.

Referenced by ath9k_init_softc().

◆ ar9003_get_pll_sqsum_dvc()

u32 ar9003_get_pll_sqsum_dvc ( struct ath_hw ah)

Definition at line 609 of file ath9k_hw.c.

610 {
612  udelay(100);
614 
615  while ((REG_READ(ah, PLL4) & PLL4_MEAS_DONE) == 0)
616  udelay(100);
617 
618  return (REG_READ(ah, PLL3) & SQSUM_DVC_MASK) >> 3;
619 }
#define REG_CLR_BIT(_a, _r, _f)
Definition: hw.h:109
#define PLL4
Definition: reg.h:1191
void udelay(unsigned long usecs)
Delay for a fixed number of microseconds.
Definition: timer.c:60
#define PLL3_DO_MEAS_MASK
Definition: reg.h:1190
#define PLL3
Definition: reg.h:1189
#define REG_READ(_ah, _reg)
Definition: hw.h:80
#define REG_SET_BIT(_a, _r, _f)
Definition: hw.h:107
uint8_t ah
Definition: registers.h:85
#define PLL4_MEAS_DONE
Definition: reg.h:1192
#define SQSUM_DVC_MASK
Definition: reg.h:1193

References ah, PLL3, PLL3_DO_MEAS_MASK, PLL4, PLL4_MEAS_DONE, REG_CLR_BIT, REG_READ, REG_SET_BIT, SQSUM_DVC_MASK, and udelay().

Referenced by ath_hw_pll_work().

◆ ath9k_hw_init_pll()

static void ath9k_hw_init_pll ( struct ath_hw ah,
struct ath9k_channel chan 
)
static

Definition at line 621 of file ath9k_hw.c.

623 {
624  u32 pll;
625 
626  if (AR_SREV_9485(ah)) {
627 
628  /* program BB PLL ki and kd value, ki=0x4, kd=0x40 */
632  AR_CH0_DPLL2_KD, 0x40);
634  AR_CH0_DPLL2_KI, 0x4);
635 
639  AR_CH0_BB_DPLL1_NINI, 0x58);
641  AR_CH0_BB_DPLL1_NFRAC, 0x0);
642 
649 
650  /* program BB PLL phase_shift to 0x6 */
653 
656  udelay(1000);
657  } else if (AR_SREV_9340(ah)) {
658  u32 regval, pll2_divint, pll2_divfrac, refdiv;
659 
660  REG_WRITE(ah, AR_RTC_PLL_CONTROL, 0x1142c);
661  udelay(1000);
662 
663  REG_SET_BIT(ah, AR_PHY_PLL_MODE, 0x1 << 16);
664  udelay(100);
665 
666  if (ah->is_clk_25mhz) {
667  pll2_divint = 0x54;
668  pll2_divfrac = 0x1eb85;
669  refdiv = 3;
670  } else {
671  pll2_divint = 88;
672  pll2_divfrac = 0;
673  refdiv = 5;
674  }
675 
676  regval = REG_READ(ah, AR_PHY_PLL_MODE);
677  regval |= (0x1 << 16);
678  REG_WRITE(ah, AR_PHY_PLL_MODE, regval);
679  udelay(100);
680 
681  REG_WRITE(ah, AR_PHY_PLL_CONTROL, (refdiv << 27) |
682  (pll2_divint << 18) | pll2_divfrac);
683  udelay(100);
684 
685  regval = REG_READ(ah, AR_PHY_PLL_MODE);
686  regval = (regval & 0x80071fff) | (0x1 << 30) | (0x1 << 13) |
687  (0x4 << 26) | (0x18 << 19);
688  REG_WRITE(ah, AR_PHY_PLL_MODE, regval);
690  REG_READ(ah, AR_PHY_PLL_MODE) & 0xfffeffff);
691  udelay(1000);
692  }
693 
694  pll = ath9k_hw_compute_pll_control(ah, chan);
695 
697 
698  if (AR_SREV_9485(ah) || AR_SREV_9340(ah))
699  udelay(1000);
700 
701  /* Switch the core clock for ar9271 to 117Mhz */
702  if (AR_SREV_9271(ah)) {
703  udelay(500);
704  REG_WRITE(ah, 0x50040, 0x304);
705  }
706 
708 
710 
711  if (AR_SREV_9340(ah)) {
712  if (ah->is_clk_25mhz) {
713  REG_WRITE(ah, AR_RTC_DERIVED_CLK, 0x17c << 1);
714  REG_WRITE(ah, AR_SLP32_MODE, 0x0010f3d7);
715  REG_WRITE(ah, AR_SLP32_INC, 0x0001e7ae);
716  } else {
717  REG_WRITE(ah, AR_RTC_DERIVED_CLK, 0x261 << 1);
718  REG_WRITE(ah, AR_SLP32_MODE, 0x0010f400);
719  REG_WRITE(ah, AR_SLP32_INC, 0x0001e800);
720  }
721  udelay(100);
722  }
723 }
#define AR_CH0_BB_DPLL2
Definition: reg.h:1119
#define AR_PHY_PLL_CONTROL
Definition: phy.h:50
#define RTC_PLL_SETTLE_DELAY
Definition: hw.h:134
#define AR_SLP32_INC
Definition: reg.h:1803
#define AR_CH0_DPLL2_KD
Definition: reg.h:1124
#define AR_SREV_9485(_ah)
Definition: reg.h:867
#define REG_RMW_FIELD(_a, _r, _f, _v)
Definition: hw.h:103
#define AR_RTC_FORCE_DERIVED_CLK
Definition: reg.h:1214
#define AR_RTC_SLEEP_CLK
Definition: reg.h:1212
#define AR_CH0_DPLL2_KI
Definition: reg.h:1122
void udelay(unsigned long usecs)
Delay for a fixed number of microseconds.
Definition: timer.c:60
#define AR_SREV_9340(_ah)
Definition: reg.h:878
#define AR_CH0_BB_DPLL3_PHASE_SHIFT
Definition: reg.h:1134
#define AR_CH0_BB_DPLL1_NINI
Definition: reg.h:1114
#define AR_CH0_BB_DPLL1_NFRAC
Definition: reg.h:1116
static u32 ath9k_hw_compute_pll_control(struct ath_hw *ah, struct ath9k_channel *chan)
Definition: ath9k_hw.c:41
#define AR_CH0_BB_DPLL2_PLL_PWD
Definition: reg.h:1128
#define REG_READ(_ah, _reg)
Definition: hw.h:80
#define REG_SET_BIT(_a, _r, _f)
Definition: hw.h:107
#define AR_SLP32_MODE
Definition: reg.h:1795
#define AR_CH0_BB_DPLL2_OUTDIV
Definition: reg.h:1130
#define REG_WRITE(_ah, _reg, _val)
Definition: hw.h:77
#define AR_CH0_BB_DPLL1_REFDIV
Definition: reg.h:1112
#define AR_CH0_BB_DPLL2_LOCAL_PLL
Definition: reg.h:1120
#define AR_SREV_9271(_ah)
Definition: reg.h:853
#define AR_CH0_BB_DPLL3
Definition: reg.h:1133
uint8_t ah
Definition: registers.h:85
#define AR_PHY_PLL_MODE
Definition: phy.h:51
#define AR_RTC_PLL_CONTROL
Definition: reg.h:1176
#define AR_CH0_BB_DPLL2_EN_NEGTRIG
Definition: reg.h:1126
#define AR_CH0_BB_DPLL1
Definition: reg.h:1111
uint32_t u32
Definition: stdint.h:23
#define AR_RTC_DERIVED_CLK
Definition: reg.h:1234

References ah, AR_CH0_BB_DPLL1, AR_CH0_BB_DPLL1_NFRAC, AR_CH0_BB_DPLL1_NINI, AR_CH0_BB_DPLL1_REFDIV, AR_CH0_BB_DPLL2, AR_CH0_BB_DPLL2_EN_NEGTRIG, AR_CH0_BB_DPLL2_LOCAL_PLL, AR_CH0_BB_DPLL2_OUTDIV, AR_CH0_BB_DPLL2_PLL_PWD, AR_CH0_BB_DPLL3, AR_CH0_BB_DPLL3_PHASE_SHIFT, AR_CH0_DPLL2_KD, AR_CH0_DPLL2_KI, AR_PHY_PLL_CONTROL, AR_PHY_PLL_MODE, AR_RTC_DERIVED_CLK, AR_RTC_FORCE_DERIVED_CLK, AR_RTC_PLL_CONTROL, AR_RTC_SLEEP_CLK, AR_SLP32_INC, AR_SLP32_MODE, AR_SREV_9271, AR_SREV_9340, AR_SREV_9485, ath9k_hw_compute_pll_control(), REG_READ, REG_RMW_FIELD, REG_SET_BIT, REG_WRITE, RTC_PLL_SETTLE_DELAY, and udelay().

Referenced by ath9k_hw_chip_reset(), ath9k_hw_disable(), ath9k_hw_phy_disable(), and ath9k_hw_set_power_awake().

◆ ath9k_hw_init_interrupt_masks()

static void ath9k_hw_init_interrupt_masks ( struct ath_hw ah)
static

Definition at line 725 of file ath9k_hw.c.

726 {
727  u32 sync_default = AR_INTR_SYNC_DEFAULT;
728  u32 imr_reg = AR_IMR_TXERR |
729  AR_IMR_TXURN |
730  AR_IMR_RXERR |
731  AR_IMR_RXORN;;
732 
733  if (AR_SREV_9340(ah))
734  sync_default &= ~AR_INTR_SYNC_HOST1_FATAL;
735 
737  imr_reg |= AR_IMR_RXOK_HP;
738  if (ah->config.rx_intr_mitigation)
739  imr_reg |= AR_IMR_RXINTM | AR_IMR_RXMINTR;
740  else
741  imr_reg |= AR_IMR_RXOK_LP;
742 
743  } else {
744  if (ah->config.rx_intr_mitigation)
745  imr_reg |= AR_IMR_RXINTM | AR_IMR_RXMINTR;
746  else
747  imr_reg |= AR_IMR_RXOK;
748  }
749 
750  if (ah->config.tx_intr_mitigation)
751  imr_reg |= AR_IMR_TXINTM | AR_IMR_TXMINTR;
752  else
753  imr_reg |= AR_IMR_TXOK;
754 
756 
757  REG_WRITE(ah, AR_IMR, imr_reg);
758 // ah->imrs2_reg |= AR_IMR_S2_GTT;
759  REG_WRITE(ah, AR_IMR_S2, ah->imrs2_reg);
760 
761  if (!AR_SREV_9100(ah)) {
762  REG_WRITE(ah, AR_INTR_SYNC_CAUSE, 0xFFFFFFFF);
763  REG_WRITE(ah, AR_INTR_SYNC_ENABLE, sync_default);
765  }
766 
768 
774  }
775 }
#define AR_IMR_RXMINTR
Definition: reg.h:290
#define AR_IMR_RXOK_HP
Definition: reg.h:261
#define AR_IMR_TXERR
Definition: reg.h:269
#define REGWRITE_BUFFER_FLUSH(_ah)
Definition: hw.h:95
#define AR_SREV_9100(ah)
Definition: reg.h:810
#define AR_IMR_TXURN
Definition: reg.h:272
#define AR_IMR_TXINTM
Definition: reg.h:291
#define AR_INTR_PRIO_SYNC_MASK
Definition: reg.h:1105
#define AR_IMR_RXOK
Definition: reg.h:259
#define AR_SREV_9300_20_OR_LATER(_ah)
Definition: reg.h:864
#define AR_IMR_TXOK
Definition: reg.h:267
#define AR_IMR_RXORN
Definition: reg.h:266
#define AR_SREV_9340(_ah)
Definition: reg.h:878
#define AR_INTR_PRIO_ASYNC_ENABLE
Definition: reg.h:1106
#define AR_INTR_SYNC_CAUSE
Definition: reg.h:922
#define AR_IMR_RXOK_LP
Definition: reg.h:262
#define AR_IMR_S2
Definition: reg.h:306
#define AR_INTR_PRIO_SYNC_ENABLE
Definition: reg.h:1103
#define AR_IMR_RXERR
Definition: reg.h:263
#define REG_WRITE(_ah, _reg, _val)
Definition: hw.h:77
#define AR_INTR_SYNC_ENABLE
Definition: reg.h:926
#define AR_IMR_RXINTM
Definition: reg.h:292
uint8_t ah
Definition: registers.h:85
#define AR_IMR_TXMINTR
Definition: reg.h:289
#define AR_INTR_SYNC_MASK
Definition: reg.h:970
uint32_t u32
Definition: stdint.h:23
#define AR_IMR
Definition: reg.h:258
#define ENABLE_REGWRITE_BUFFER(_ah)
Definition: hw.h:89
#define AR_INTR_PRIO_ASYNC_MASK
Definition: reg.h:1104

References ah, AR_IMR, AR_IMR_RXERR, AR_IMR_RXINTM, AR_IMR_RXMINTR, AR_IMR_RXOK, AR_IMR_RXOK_HP, AR_IMR_RXOK_LP, AR_IMR_RXORN, AR_IMR_S2, AR_IMR_TXERR, AR_IMR_TXINTM, AR_IMR_TXMINTR, AR_IMR_TXOK, AR_IMR_TXURN, AR_INTR_PRIO_ASYNC_ENABLE, AR_INTR_PRIO_ASYNC_MASK, AR_INTR_PRIO_SYNC_ENABLE, AR_INTR_PRIO_SYNC_MASK, AR_INTR_SYNC_CAUSE, AR_INTR_SYNC_DEFAULT, AR_INTR_SYNC_ENABLE, AR_INTR_SYNC_HOST1_FATAL, AR_INTR_SYNC_MASK, AR_SREV_9100, AR_SREV_9300_20_OR_LATER, AR_SREV_9340, ENABLE_REGWRITE_BUFFER, REG_WRITE, and REGWRITE_BUFFER_FLUSH.

Referenced by ath9k_hw_reset().

◆ ath9k_hw_setslottime()

static void ath9k_hw_setslottime ( struct ath_hw ah,
u32  us 
)
static

Definition at line 777 of file ath9k_hw.c.

778 {
780  val = min(val, (u32) 0xFFFF);
782 }
#define min(x, y)
Definition: ath.h:34
static u32 ath9k_hw_mac_to_clks(struct ath_hw *ah, u32 usecs)
Definition: ath9k_hw.c:86
void __asmcall int val
Definition: setjmp.h:28
#define REG_WRITE(_ah, _reg, _val)
Definition: hw.h:77
uint8_t ah
Definition: registers.h:85
#define AR_D_GBL_IFS_SLOT
Definition: reg.h:618
uint32_t u32
Definition: stdint.h:23

References ah, AR_D_GBL_IFS_SLOT, ath9k_hw_mac_to_clks(), min, REG_WRITE, and val.

Referenced by ath9k_hw_init_global_settings().

◆ ath9k_hw_set_ack_timeout()

static void ath9k_hw_set_ack_timeout ( struct ath_hw ah,
u32  us 
)
static

Definition at line 784 of file ath9k_hw.c.

785 {
787  val = min(val, (u32) MS(0xFFFFFFFF, AR_TIME_OUT_ACK));
789 }
#define MS(_v, _f)
Definition: hw.h:102
#define min(x, y)
Definition: ath.h:34
#define REG_RMW_FIELD(_a, _r, _f, _v)
Definition: hw.h:103
#define AR_TIME_OUT
Definition: reg.h:1461
static u32 ath9k_hw_mac_to_clks(struct ath_hw *ah, u32 usecs)
Definition: ath9k_hw.c:86
void __asmcall int val
Definition: setjmp.h:28
uint8_t ah
Definition: registers.h:85
#define AR_TIME_OUT_ACK
Definition: reg.h:1462
uint32_t u32
Definition: stdint.h:23

References ah, AR_TIME_OUT, AR_TIME_OUT_ACK, ath9k_hw_mac_to_clks(), min, MS, REG_RMW_FIELD, and val.

Referenced by ath9k_hw_init_global_settings().

◆ ath9k_hw_set_cts_timeout()

static void ath9k_hw_set_cts_timeout ( struct ath_hw ah,
u32  us 
)
static

Definition at line 791 of file ath9k_hw.c.

792 {
794  val = min(val, (u32) MS(0xFFFFFFFF, AR_TIME_OUT_CTS));
796 }
#define MS(_v, _f)
Definition: hw.h:102
#define min(x, y)
Definition: ath.h:34
#define REG_RMW_FIELD(_a, _r, _f, _v)
Definition: hw.h:103
#define AR_TIME_OUT
Definition: reg.h:1461
static u32 ath9k_hw_mac_to_clks(struct ath_hw *ah, u32 usecs)
Definition: ath9k_hw.c:86
void __asmcall int val
Definition: setjmp.h:28
uint8_t ah
Definition: registers.h:85
uint32_t u32
Definition: stdint.h:23
#define AR_TIME_OUT_CTS
Definition: reg.h:1464

References ah, AR_TIME_OUT, AR_TIME_OUT_CTS, ath9k_hw_mac_to_clks(), min, MS, REG_RMW_FIELD, and val.

Referenced by ath9k_hw_init_global_settings().

◆ ath9k_hw_set_global_txtimeout()

static int ath9k_hw_set_global_txtimeout ( struct ath_hw ah,
u32  tu 
)
static

Definition at line 798 of file ath9k_hw.c.

799 {
800  if (tu > 0xFFFF) {
801  DBG("ath9k: "
802  "bad global tx timeout %d\n", tu);
803  ah->globaltxtimeout = (u32) -1;
804  return 0;
805  } else {
807  ah->globaltxtimeout = tu;
808  return 1;
809  }
810 }
#define AR_GTXTO_TIMEOUT_LIMIT
Definition: reg.h:154
#define REG_RMW_FIELD(_a, _r, _f, _v)
Definition: hw.h:103
#define u32
Definition: vga.h:21
#define AR_GTXTO
Definition: reg.h:152
uint8_t ah
Definition: registers.h:85
#define DBG(...)
Print a debugging message.
Definition: compiler.h:498

References ah, AR_GTXTO, AR_GTXTO_TIMEOUT_LIMIT, DBG, REG_RMW_FIELD, and u32.

Referenced by ath9k_hw_init_global_settings().

◆ ath9k_hw_init_global_settings()

void ath9k_hw_init_global_settings ( struct ath_hw ah)

Definition at line 812 of file ath9k_hw.c.

813 {
814  int acktimeout;
815  int slottime;
816  int sifstime;
817 
818  DBG2("ath9k: ah->misc_mode 0x%x\n",
819  ah->misc_mode);
820 
821  if (ah->misc_mode != 0)
822  REG_SET_BIT(ah, AR_PCU_MISC, ah->misc_mode);
823 
824  if ((ah->dev->channels + ah->dev->channel)->band == NET80211_BAND_5GHZ)
825  sifstime = 16;
826  else
827  sifstime = 10;
828 
829  /* As defined by IEEE 802.11-2007 17.3.8.6 */
830  slottime = ah->slottime + 3 * ah->coverage_class;
831  acktimeout = slottime + sifstime;
832 
833  /*
834  * Workaround for early ACK timeouts, add an offset to match the
835  * initval's 64us ack timeout value.
836  * This was initially only meant to work around an issue with delayed
837  * BA frames in some implementations, but it has been found to fix ACK
838  * timeout issues in other cases as well.
839  */
840  if ((ah->dev->channels + ah->dev->channel)->band == NET80211_BAND_2GHZ)
841  acktimeout += 64 - sifstime - ah->slottime;
842 
843  ath9k_hw_setslottime(ah, ah->slottime);
844  ath9k_hw_set_ack_timeout(ah, acktimeout);
845  ath9k_hw_set_cts_timeout(ah, acktimeout);
846  if (ah->globaltxtimeout != (u32) -1)
847  ath9k_hw_set_global_txtimeout(ah, ah->globaltxtimeout);
848 }
static int ath9k_hw_set_global_txtimeout(struct ath_hw *ah, u32 tu)
Definition: ath9k_hw.c:798
static void ath9k_hw_set_ack_timeout(struct ath_hw *ah, u32 us)
Definition: ath9k_hw.c:784
static void ath9k_hw_setslottime(struct ath_hw *ah, u32 us)
Definition: ath9k_hw.c:777
#define NET80211_BAND_2GHZ
The 2.4 GHz ISM band, unlicensed in most countries.
Definition: net80211.h:45
static void ath9k_hw_set_cts_timeout(struct ath_hw *ah, u32 us)
Definition: ath9k_hw.c:791
#define AR_PCU_MISC
Definition: reg.h:1640
#define NET80211_BAND_5GHZ
The band from 4.9 GHz to 5.7 GHz, which tends to be more restricted.
Definition: net80211.h:47
#define REG_SET_BIT(_a, _r, _f)
Definition: hw.h:107
uint8_t ah
Definition: registers.h:85
uint32_t u32
Definition: stdint.h:23
#define DBG2(...)
Definition: compiler.h:515

References ah, AR_PCU_MISC, ath9k_hw_set_ack_timeout(), ath9k_hw_set_cts_timeout(), ath9k_hw_set_global_txtimeout(), ath9k_hw_setslottime(), DBG2, NET80211_BAND_2GHZ, NET80211_BAND_5GHZ, and REG_SET_BIT.

Referenced by ath9k_bss_info_changed(), and ath9k_hw_reset().

◆ ath9k_hw_deinit()

void ath9k_hw_deinit ( struct ath_hw ah)

Definition at line 850 of file ath9k_hw.c.

851 {
852  struct ath_common *common = ath9k_hw_common(ah);
853 
854  if (common->state < ATH_HW_INITIALIZED)
855  goto free_hw;
856 
858 
859 free_hw:
861 }
static struct ath_common * ath9k_hw_common(struct ath_hw *ah)
Definition: hw.h:869
struct ib_cm_common common
Definition: ib_mad.h:11
static void ath9k_hw_rf_free_ext_banks(struct ath_hw *ah)
Definition: hw-ops.h:162
int ath9k_hw_setpower(struct ath_hw *ah, enum ath9k_power_mode mode)
Definition: ath9k_hw.c:1532
uint8_t ah
Definition: registers.h:85

References ah, ath9k_hw_common(), ath9k_hw_rf_free_ext_banks(), ath9k_hw_setpower(), ATH9K_PM_FULL_SLEEP, ATH_HW_INITIALIZED, and common.

Referenced by ath9k_deinit_softc(), and ath9k_init_softc().

◆ ath9k_regd_get_ctl()

u32 ath9k_regd_get_ctl ( struct ath_regulatory reg,
struct ath9k_channel chan 
)

Definition at line 867 of file ath9k_hw.c.

868 {
869  u32 ctl = ath_regd_get_band_ctl(reg, chan->chan->band);
870 
871  if (IS_CHAN_B(chan))
872  ctl |= CTL_11B;
873  else if (IS_CHAN_G(chan))
874  ctl |= CTL_11G;
875  else
876  ctl |= CTL_11A;
877 
878  return ctl;
879 }
#define IS_CHAN_B(_c)
Definition: ath5k.h:658
struct net80211_channel * chan
Definition: hw.h:347
static unsigned int unsigned int reg
Definition: intel.h:245
u8 band
The band with which this channel is associated.
Definition: net80211.h:388
#define CTL_11A
Definition: eeprom.h:70
#define CTL_11G
Definition: eeprom.h:72
#define IS_CHAN_G(_c)
Definition: hw.h:355
#define CTL_11B
Definition: eeprom.h:71
u32 ath_regd_get_band_ctl(struct ath_regulatory *reg, int band)
Definition: ath_regd.c:584
uint32_t u32
Definition: stdint.h:23

References ath_regd_get_band_ctl(), net80211_channel::band, ath9k_channel::chan, CTL_11A, CTL_11B, CTL_11G, IS_CHAN_B, IS_CHAN_G, and reg.

Referenced by ar5008_hw_process_ini(), ar9003_hw_process_ini(), ath9k_hw_channel_change(), and ath9k_hw_set_txpowerlimit().

◆ ath9k_hw_set_dma()

static void ath9k_hw_set_dma ( struct ath_hw ah)
inlinestatic

Definition at line 885 of file ath9k_hw.c.

886 {
887  struct ath_common *common = ath9k_hw_common(ah);
888 
890 
891  /*
892  * set AHB_MODE not to do cacheline prefetches
893  */
896 
897  /*
898  * let mac dma reads be in 128 byte chunks
899  */
901 
903 
904  /*
905  * Restore TX Trigger Level to its pre-reset value.
906  * The initial value depends on whether aggregation is enabled, and is
907  * adjusted whenever underruns are detected.
908  */
910  REG_RMW_FIELD(ah, AR_TXCFG, AR_FTRIG, ah->tx_trig_level);
911 
913 
914  /*
915  * let mac dma writes be in 128 byte chunks
916  */
918 
919  /*
920  * Setup receive FIFO threshold to hold off TX activities
921  */
922  REG_WRITE(ah, AR_RXFIFO_CFG, 0x200);
923 
927 
928  ath9k_hw_set_rx_bufsize(ah, common->rx_bufsize -
929  ah->caps.rx_status_len);
930  }
931 
932  /*
933  * reduce the number of usable entries in PCU TXBUF to avoid
934  * wrap around issues.
935  */
936  if (AR_SREV_9285(ah)) {
937  /* For AR9285 the number of Fifos are reduced to half.
938  * So set the usable tx buf size also to half to
939  * avoid data/delimiter underruns
940  */
943  } else if (!AR_SREV_9271(ah)) {
946  }
947 
949 
952 }
#define AR_PCU_TXBUF_CTRL
Definition: reg.h:1825
#define AR_FTRIG
Definition: reg.h:89
#define AR_AHB_MODE
Definition: reg.h:901
#define AR_RXFIFO_CFG
Definition: reg.h:1634
#define REGWRITE_BUFFER_FLUSH(_ah)
Definition: hw.h:95
#define REG_RMW(_ah, _reg, _set, _clr)
Definition: hw.h:86
#define AR_AHB_PREFETCH_RD_EN
Definition: reg.h:906
#define AR_SREV_9285(_ah)
Definition: reg.h:829
#define AR_PCU_TXBUF_CTRL_USABLE_SIZE
Definition: reg.h:1827
#define AR_RXCFG
Definition: reg.h:99
#define REG_RMW_FIELD(_a, _r, _f, _v)
Definition: hw.h:103
#define AR_SREV_9300_20_OR_LATER(_ah)
Definition: reg.h:864
#define AR_TXCFG_DMASZ_MASK
Definition: reg.h:80
void ath9k_hw_set_rx_bufsize(struct ath_hw *ah, u16 buf_size)
#define AR_TXCFG
Definition: reg.h:79
#define AR_9285_PCU_TXBUF_CTRL_USABLE_SIZE
Definition: reg.h:1828
#define AR_TXCFG_DMASZ_128B
Definition: reg.h:86
#define AR_RXBP_THRESH_LP
Definition: reg.h:47
void ath9k_hw_reset_txstatus_ring(struct ath_hw *ah)
static struct ath_common * ath9k_hw_common(struct ath_hw *ah)
Definition: hw.h:869
struct ib_cm_common common
Definition: ib_mad.h:11
#define REG_SET_BIT(_a, _r, _f)
Definition: hw.h:107
#define AR_RXCFG_DMASZ_128B
Definition: reg.h:108
#define AR_RXBP_THRESH_HP
Definition: reg.h:45
#define REG_WRITE(_ah, _reg, _val)
Definition: hw.h:77
#define AR_SREV_9271(_ah)
Definition: reg.h:853
uint8_t ah
Definition: registers.h:85
#define AR_RXBP_THRESH
Definition: reg.h:44
#define ENABLE_REGWRITE_BUFFER(_ah)
Definition: hw.h:89
#define AR_RXCFG_DMASZ_MASK
Definition: reg.h:102

References ah, AR_9285_PCU_TXBUF_CTRL_USABLE_SIZE, AR_AHB_MODE, AR_AHB_PREFETCH_RD_EN, AR_FTRIG, AR_PCU_TXBUF_CTRL, AR_PCU_TXBUF_CTRL_USABLE_SIZE, AR_RXBP_THRESH, AR_RXBP_THRESH_HP, AR_RXBP_THRESH_LP, AR_RXCFG, AR_RXCFG_DMASZ_128B, AR_RXCFG_DMASZ_MASK, AR_RXFIFO_CFG, AR_SREV_9271, AR_SREV_9285, AR_SREV_9300_20_OR_LATER, AR_TXCFG, AR_TXCFG_DMASZ_128B, AR_TXCFG_DMASZ_MASK, ath9k_hw_common(), ath9k_hw_reset_txstatus_ring(), ath9k_hw_set_rx_bufsize(), common, ENABLE_REGWRITE_BUFFER, REG_RMW, REG_RMW_FIELD, REG_SET_BIT, REG_WRITE, and REGWRITE_BUFFER_FLUSH.

Referenced by ath9k_hw_reset().

◆ ath9k_hw_set_operating_mode()

static void ath9k_hw_set_operating_mode ( struct ath_hw ah)
static

Definition at line 954 of file ath9k_hw.c.

955 {
958 
960 
961  REG_RMW(ah, AR_STA_ID1, set, mask);
962 }
#define REG_CLR_BIT(_a, _r, _f)
Definition: hw.h:109
#define REG_RMW(_ah, _reg, _set, _clr)
Definition: hw.h:86
#define AR_STA_ID1_STA_AP
Definition: reg.h:1434
#define AR_STA_ID1
Definition: reg.h:1432
#define AR_STA_ID1_KSRCH_MODE
Definition: reg.h:1447
static fd_set * set
Definition: posix_io.h:48
uint8_t ah
Definition: registers.h:85
#define AR_CFG
Definition: reg.h:31
#define AR_CFG_AP_ADHOC_INDICATION
Definition: reg.h:37
uint32_t u32
Definition: stdint.h:23
#define AR_STA_ID1_ADHOC
Definition: reg.h:1435

References ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION, AR_STA_ID1, AR_STA_ID1_ADHOC, AR_STA_ID1_KSRCH_MODE, AR_STA_ID1_STA_AP, REG_CLR_BIT, REG_RMW, and set.

Referenced by ath9k_hw_reset(), and ath9k_hw_setopmode().

◆ ath9k_hw_get_delta_slope_vals()

void ath9k_hw_get_delta_slope_vals ( struct ath_hw *ah  __unused,
u32  coef_scaled,
u32 coef_mantissa,
u32 coef_exponent 
)

Definition at line 964 of file ath9k_hw.c.

966 {
967  u32 coef_exp, coef_man;
968 
969  for (coef_exp = 31; coef_exp > 0; coef_exp--)
970  if ((coef_scaled >> coef_exp) & 0x1)
971  break;
972 
973  coef_exp = 14 - (coef_exp - COEF_SCALE_S);
974 
975  coef_man = coef_scaled + (1 << (COEF_SCALE_S - coef_exp - 1));
976 
977  *coef_mantissa = coef_man >> (COEF_SCALE_S - coef_exp);
978  *coef_exponent = coef_exp - 16;
979 }
#define COEF_SCALE_S
Definition: hw.h:135
uint32_t u32
Definition: stdint.h:23

References COEF_SCALE_S.

Referenced by ar5008_hw_set_delta_slope(), and ar9003_hw_set_delta_slope().

◆ ath9k_hw_set_reset()

static int ath9k_hw_set_reset ( struct ath_hw ah,
int  type 
)
static

Definition at line 981 of file ath9k_hw.c.

982 {
983  u32 rst_flags;
984  u32 tmpReg;
985 
986  if (AR_SREV_9100(ah)) {
990  }
991 
993 
995  REG_WRITE(ah, AR_WA, ah->WARegVal);
996  udelay(10);
997  }
998 
1001 
1002  if (AR_SREV_9100(ah)) {
1003  rst_flags = AR_RTC_RC_MAC_WARM | AR_RTC_RC_MAC_COLD |
1005  } else {
1006  tmpReg = REG_READ(ah, AR_INTR_SYNC_CAUSE);
1007  if (tmpReg &
1010  u32 val;
1012 
1013  val = AR_RC_HOSTIF;
1015  val |= AR_RC_AHB;
1016  REG_WRITE(ah, AR_RC, val);
1017 
1018  } else if (!AR_SREV_9300_20_OR_LATER(ah))
1020 
1021  rst_flags = AR_RTC_RC_MAC_WARM;
1022  if (type == ATH9K_RESET_COLD)
1023  rst_flags |= AR_RTC_RC_MAC_COLD;
1024  }
1025 
1026  REG_WRITE(ah, AR_RTC_RC, rst_flags);
1027 
1029 
1030  udelay(50);
1031 
1032  REG_WRITE(ah, AR_RTC_RC, 0);
1034  DBG("ath9k: "
1035  "RTC stuck in MAC reset\n");
1036  return 0;
1037  }
1038 
1039  if (!AR_SREV_9100(ah))
1040  REG_WRITE(ah, AR_RC, 0);
1041 
1042  if (AR_SREV_9100(ah))
1043  udelay(50);
1044 
1045  return 1;
1046 }
#define AR_RTC_RC_M
Definition: reg.h:1160
#define AR_RTC_RC_COLD_RESET
Definition: reg.h:1163
uint8_t type
Type.
Definition: ena.h:16
#define AR_RTC_RC_MAC_WARM
Definition: reg.h:1161
#define REGWRITE_BUFFER_FLUSH(_ah)
Definition: hw.h:95
#define AR_RTC_RC_MAC_COLD
Definition: reg.h:1162
#define AR_SREV_9100(ah)
Definition: reg.h:810
#define AR_RC_HOSTIF
Definition: reg.h:696
#define REG_RMW_FIELD(_a, _r, _f, _v)
Definition: hw.h:103
#define AR_SREV_9300_20_OR_LATER(_ah)
Definition: reg.h:864
#define AR_RTC_RC
Definition: reg.h:1158
#define AR_RTC_FORCE_WAKE_EN
Definition: reg.h:1219
void udelay(unsigned long usecs)
Delay for a fixed number of microseconds.
Definition: timer.c:60
#define AR_RTC_FORCE_WAKE_ON_INT
Definition: reg.h:1220
#define AR_INTR_SYNC_CAUSE
Definition: reg.h:922
#define AR_RTC_DERIVED_CLK_PERIOD
Definition: reg.h:1236
#define REG_READ(_ah, _reg)
Definition: hw.h:80
void __asmcall int val
Definition: setjmp.h:28
#define AR_RTC_RC_WARM_RESET
Definition: reg.h:1164
int ath9k_hw_wait(struct ath_hw *ah, u32 reg, u32 mask, u32 val, u32 timeout)
Definition: ath9k_hw.c:93
#define REG_WRITE(_ah, _reg, _val)
Definition: hw.h:77
#define AR_INTR_SYNC_ENABLE
Definition: reg.h:926
#define AH_WAIT_TIMEOUT
Definition: hw.h:145
#define AR_WA
Definition: reg.h:698
uint8_t ah
Definition: registers.h:85
#define DBG(...)
Print a debugging message.
Definition: compiler.h:498
#define AR_RC_AHB
Definition: reg.h:694
#define AR_RC
Definition: reg.h:693
#define AR_RTC_FORCE_WAKE
Definition: reg.h:1217
uint32_t u32
Definition: stdint.h:23
#define ENABLE_REGWRITE_BUFFER(_ah)
Definition: hw.h:89
#define AR_RTC_DERIVED_CLK
Definition: reg.h:1234

References ah, AH_WAIT_TIMEOUT, AR_INTR_SYNC_CAUSE, AR_INTR_SYNC_ENABLE, AR_INTR_SYNC_LOCAL_TIMEOUT, AR_INTR_SYNC_RADM_CPL_TIMEOUT, AR_RC, AR_RC_AHB, AR_RC_HOSTIF, AR_RTC_DERIVED_CLK, AR_RTC_DERIVED_CLK_PERIOD, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN, AR_RTC_FORCE_WAKE_ON_INT, AR_RTC_RC, AR_RTC_RC_COLD_RESET, AR_RTC_RC_M, AR_RTC_RC_MAC_COLD, AR_RTC_RC_MAC_WARM, AR_RTC_RC_WARM_RESET, AR_SREV_9100, AR_SREV_9300_20_OR_LATER, AR_WA, ath9k_hw_wait(), ATH9K_RESET_COLD, DBG, ENABLE_REGWRITE_BUFFER, REG_READ, REG_RMW_FIELD, REG_WRITE, REGWRITE_BUFFER_FLUSH, type, udelay(), and val.

Referenced by ath9k_hw_set_reset_power_on(), and ath9k_hw_set_reset_reg().

◆ ath9k_hw_set_reset_power_on()

static int ath9k_hw_set_reset_power_on ( struct ath_hw ah)
static

Definition at line 1048 of file ath9k_hw.c.

1049 {
1051 
1053  REG_WRITE(ah, AR_WA, ah->WARegVal);
1054  udelay(10);
1055  }
1056 
1059 
1062 
1063  REG_WRITE(ah, AR_RTC_RESET, 0);
1064 
1066 
1068  udelay(2);
1069 
1071  REG_WRITE(ah, AR_RC, 0);
1072 
1073  REG_WRITE(ah, AR_RTC_RESET, 1);
1074 
1075  if (!ath9k_hw_wait(ah,
1076  AR_RTC_STATUS,
1079  AH_WAIT_TIMEOUT)) {
1080  DBG("ath9k: "
1081  "RTC not waking up\n");
1082  return 0;
1083  }
1084 
1086 }
#define AR_RTC_STATUS_ON
Definition: reg.h:1208
#define AR_RTC_STATUS
Definition: reg.h:1199
#define REGWRITE_BUFFER_FLUSH(_ah)
Definition: hw.h:95
#define AR_SREV_9100(ah)
Definition: reg.h:810
#define AR_RTC_STATUS_M
Definition: reg.h:1202
#define AR_SREV_9300_20_OR_LATER(_ah)
Definition: reg.h:864
#define AR_RTC_RESET
Definition: reg.h:1195
#define AR_RTC_FORCE_WAKE_EN
Definition: reg.h:1219
void udelay(unsigned long usecs)
Delay for a fixed number of microseconds.
Definition: timer.c:60
#define AR_RTC_FORCE_WAKE_ON_INT
Definition: reg.h:1220
int ath9k_hw_wait(struct ath_hw *ah, u32 reg, u32 mask, u32 val, u32 timeout)
Definition: ath9k_hw.c:93
#define REG_WRITE(_ah, _reg, _val)
Definition: hw.h:77
#define AH_WAIT_TIMEOUT
Definition: hw.h:145
static int ath9k_hw_set_reset(struct ath_hw *ah, int type)
Definition: ath9k_hw.c:981
#define AR_WA
Definition: reg.h:698
uint8_t ah
Definition: registers.h:85
#define DBG(...)
Print a debugging message.
Definition: compiler.h:498
#define AR_RC_AHB
Definition: reg.h:694
#define AR_RC
Definition: reg.h:693
#define AR_RTC_FORCE_WAKE
Definition: reg.h:1217
#define ENABLE_REGWRITE_BUFFER(_ah)
Definition: hw.h:89

References ah, AH_WAIT_TIMEOUT, AR_RC, AR_RC_AHB, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN, AR_RTC_FORCE_WAKE_ON_INT, AR_RTC_RESET, AR_RTC_STATUS, AR_RTC_STATUS_M, AR_RTC_STATUS_ON, AR_SREV_9100, AR_SREV_9300_20_OR_LATER, AR_WA, ath9k_hw_set_reset(), ath9k_hw_wait(), ATH9K_RESET_WARM, DBG, ENABLE_REGWRITE_BUFFER, REG_WRITE, REGWRITE_BUFFER_FLUSH, and udelay().

Referenced by ath9k_hw_set_reset_reg().

◆ ath9k_hw_chip_reset()

static int ath9k_hw_chip_reset ( struct ath_hw ah,
struct ath9k_channel chan 
)
static

Definition at line 1109 of file ath9k_hw.c.

1111 {
1112  if (AR_SREV_9280(ah) && ah->eep_ops->get_eeprom(ah, EEP_OL_PWRCTRL)) {
1114  return 0;
1116  return 0;
1117 
1119  return 0;
1120 
1121  ah->chip_fullsleep = 0;
1122  ath9k_hw_init_pll(ah, chan);
1123  ath9k_hw_set_rfmode(ah, chan);
1124 
1125  return 1;
1126 }
static void ath9k_hw_init_pll(struct ath_hw *ah, struct ath9k_channel *chan)
Definition: ath9k_hw.c:621
#define AR_SREV_9280(_ah)
Definition: reg.h:822
static int ath9k_hw_set_reset_reg(struct ath_hw *ah, u32 type)
Definition: ath9k_hw.c:1088
static void ath9k_hw_set_rfmode(struct ath_hw *ah, struct ath9k_channel *chan)
Definition: hw-ops.h:206
int ath9k_hw_setpower(struct ath_hw *ah, enum ath9k_power_mode mode)
Definition: ath9k_hw.c:1532
uint8_t ah
Definition: registers.h:85

References ah, AR_SREV_9280, ath9k_hw_init_pll(), ath9k_hw_set_reset_reg(), ath9k_hw_set_rfmode(), ath9k_hw_setpower(), ATH9K_PM_AWAKE, ATH9K_RESET_POWER_ON, ATH9K_RESET_WARM, and EEP_OL_PWRCTRL.

Referenced by ath9k_hw_reset().

◆ ath9k_hw_channel_change()

static int ath9k_hw_channel_change ( struct ath_hw ah,
struct ath9k_channel chan 
)
static

Definition at line 1128 of file ath9k_hw.c.

1130 {
1131  struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
1132  struct net80211_channel *channel = chan->chan;
1133  u32 qnum;
1134  int r;
1135 
1136  for (qnum = 0; qnum < AR_NUM_QCU; qnum++) {
1137  if (ath9k_hw_numtxpending(ah, qnum)) {
1138  DBG("ath9k: "
1139  "Transmit frames pending on queue %d\n", qnum);
1140  return 0;
1141  }
1142  }
1143 
1144  if (!ath9k_hw_rfbus_req(ah)) {
1145  DBG("ath9k: Could not kill baseband RX\n");
1146  return 0;
1147  }
1148 
1150 
1151  r = ath9k_hw_rf_set_freq(ah, chan);
1152  if (r) {
1153  DBG("ath9k: Failed to set channel\n");
1154  return 0;
1155  }
1157 
1158  ah->eep_ops->set_txpower(ah, chan,
1159  ath9k_regd_get_ctl(regulatory, chan),
1160  0,
1161  channel->maxpower * 2,
1163  (u32) regulatory->power_limit), 0);
1164 
1166 
1167  if (IS_CHAN_OFDM(chan) || IS_CHAN_HT(chan))
1169 
1171 
1172  return 1;
1173 }
#define IS_CHAN_OFDM(_c)
Definition: hw.h:359
u32 ath9k_hw_numtxpending(struct ath_hw *ah, u32 q)
Definition: ath9k_mac.c:62
#define min(x, y)
Definition: ath.h:34
struct net80211_channel * chan
Definition: hw.h:347
static int ath9k_hw_rfbus_req(struct ath_hw *ah)
Definition: hw-ops.h:223
u32 ath9k_regd_get_ctl(struct ath_regulatory *reg, struct ath9k_channel *chan)
Definition: ath9k_hw.c:867
static void ath9k_hw_set_channel_regs(struct ath_hw *ah, struct ath9k_channel *chan)
Definition: hw-ops.h:186
static struct ath_regulatory * ath9k_hw_regulatory(struct ath_hw *ah)
Definition: hw.h:874
int16_t power_limit
Definition: ath.h:143
uint32_t channel
RNDIS channel.
Definition: netvsc.h:14
An 802.11 RF channel.
Definition: net80211.h:385
static void ath9k_hw_spur_mitigate_freq(struct ath_hw *ah, struct ath9k_channel *chan)
Definition: hw-ops.h:148
static void ath9k_hw_set_delta_slope(struct ath_hw *ah, struct ath9k_channel *chan)
Definition: hw-ops.h:217
static int ath9k_hw_rf_set_freq(struct ath_hw *ah, struct ath9k_channel *chan)
Definition: hw-ops.h:142
static void ath9k_hw_rfbus_done(struct ath_hw *ah)
Definition: hw-ops.h:228
#define AR_NUM_QCU
Definition: reg.h:359
uint8_t ah
Definition: registers.h:85
#define DBG(...)
Print a debugging message.
Definition: compiler.h:498
#define MAX_RATE_POWER
Definition: hw.h:144
uint32_t u32
Definition: stdint.h:23
static void ath9k_hw_set_clockrate(struct ath_hw *ah)
Definition: ath9k_hw.c:68
static const uint8_t r[3][4]
MD4 shift amounts.
Definition: md4.c:53
#define IS_CHAN_HT(_c)
Definition: hw.h:376

References ah, AR_NUM_QCU, ath9k_hw_numtxpending(), ath9k_hw_regulatory(), ath9k_hw_rf_set_freq(), ath9k_hw_rfbus_done(), ath9k_hw_rfbus_req(), ath9k_hw_set_channel_regs(), ath9k_hw_set_clockrate(), ath9k_hw_set_delta_slope(), ath9k_hw_spur_mitigate_freq(), ath9k_regd_get_ctl(), ath9k_channel::chan, channel, DBG, IS_CHAN_HT, IS_CHAN_OFDM, MAX_RATE_POWER, min, ath_regulatory::power_limit, and r.

Referenced by ath9k_hw_reset().

◆ ath9k_hw_apply_gpio_override()

static void ath9k_hw_apply_gpio_override ( struct ath_hw ah)
static

Definition at line 1175 of file ath9k_hw.c.

1176 {
1177  u32 gpio_mask = ah->gpio_mask;
1178  int i;
1179 
1180  for (i = 0; gpio_mask; i++, gpio_mask >>= 1) {
1181  if (!(gpio_mask & 1))
1182  continue;
1183 
1185  ath9k_hw_set_gpio(ah, i, !!(ah->gpio_val & BIT(i)));
1186  }
1187 }
void ath9k_hw_cfg_output(struct ath_hw *ah, u32 gpio, u32 ah_signal_type)
Definition: ath9k_hw.c:1829
#define AR_GPIO_OUTPUT_MUX_AS_OUTPUT
Definition: hw.h:122
void ath9k_hw_set_gpio(struct ath_hw *ah, u32 gpio, u32 val)
Definition: ath9k_hw.c:1850
#define BIT(nr)
Definition: ath.h:32
uint8_t ah
Definition: registers.h:85
uint32_t u32
Definition: stdint.h:23

References ah, AR_GPIO_OUTPUT_MUX_AS_OUTPUT, ath9k_hw_cfg_output(), ath9k_hw_set_gpio(), and BIT.

Referenced by ath9k_hw_reset().

◆ ath9k_hw_check_alive()

int ath9k_hw_check_alive ( struct ath_hw ah)

Definition at line 1189 of file ath9k_hw.c.

1190 {
1191  int count = 50;
1192  u32 reg;
1193 
1195  return 1;
1196 
1197  do {
1199 
1200  if ((reg & 0x7E7FFFEF) == 0x00702400)
1201  continue;
1202 
1203  switch (reg & 0x7E000B00) {
1204  case 0x1E000000:
1205  case 0x52000B00:
1206  case 0x18000B00:
1207  continue;
1208  default:
1209  return 1;
1210  }
1211  } while (count-- > 0);
1212 
1213  return 0;
1214 }
#define AR_OBS_BUS_1
Definition: reg.h:1558
static unsigned int unsigned int reg
Definition: intel.h:245
#define AR_SREV_9285_12_OR_LATER(_ah)
Definition: reg.h:831
#define REG_READ(_ah, _reg)
Definition: hw.h:80
uint16_t count
Number of entries.
Definition: ena.h:22
uint8_t ah
Definition: registers.h:85
uint32_t u32
Definition: stdint.h:23

References ah, AR_OBS_BUS_1, AR_SREV_9285_12_OR_LATER, count, reg, and REG_READ.

Referenced by ath_hw_check(), and ath_set_channel().

◆ ath9k_hw_reset()

int ath9k_hw_reset ( struct ath_hw ah,
struct ath9k_channel chan,
struct ath9k_hw_cal_data caldata,
int  bChannelChange 
)

Definition at line 1216 of file ath9k_hw.c.

1218 {
1219  struct ath_common *common = ath9k_hw_common(ah);
1220  u32 saveLedState;
1221  struct ath9k_channel *curchan = ah->curchan;
1222  u32 saveDefAntenna;
1223  u32 macStaId1;
1224  int i, r;
1225 
1226  ah->txchainmask = common->tx_chainmask;
1227  ah->rxchainmask = common->rx_chainmask;
1228 
1230  return -EIO;
1231 
1232  if (curchan && !ah->chip_fullsleep)
1233  ath9k_hw_getnf(ah, curchan);
1234 
1235  ah->caldata = caldata;
1236  if (caldata &&
1237  (chan->channel != caldata->channel ||
1238  (chan->channelFlags & ~CHANNEL_CW_INT) !=
1239  (caldata->channelFlags & ~CHANNEL_CW_INT))) {
1240  /* Operating channel changed, reset channel calibration data */
1241  memset(caldata, 0, sizeof(*caldata));
1243  }
1244 
1245  if (bChannelChange &&
1246  (ah->chip_fullsleep != 1) &&
1247  (ah->curchan != NULL) &&
1248  (chan->channel != ah->curchan->channel) &&
1249  ((chan->channelFlags & CHANNEL_ALL) ==
1250  (ah->curchan->channelFlags & CHANNEL_ALL)) &&
1251  (!AR_SREV_9280(ah) || AR_DEVID_7010(ah))) {
1252 
1254  ath9k_hw_loadnf(ah, ah->curchan);
1256  if (AR_SREV_9271(ah))
1258  return 0;
1259  }
1260  }
1261 
1262  saveDefAntenna = REG_READ(ah, AR_DEF_ANTENNA);
1263  if (saveDefAntenna == 0)
1264  saveDefAntenna = 1;
1265 
1267 
1268  saveLedState = REG_READ(ah, AR_CFG_LED) &
1271 
1273 
1274  ah->paprd_table_write_done = 0;
1275 
1276  /* Only required on the first reset */
1277  if (AR_SREV_9271(ah) && ah->htc_reset_init) {
1278  REG_WRITE(ah,
1281  udelay(50);
1282  }
1283 
1284  if (!ath9k_hw_chip_reset(ah, chan)) {
1285  DBG("ath9k: Chip reset failed\n");
1286  return -EINVAL;
1287  }
1288 
1289  /* Only required on the first reset */
1290  if (AR_SREV_9271(ah) && ah->htc_reset_init) {
1291  ah->htc_reset_init = 0;
1292  REG_WRITE(ah,
1295  udelay(50);
1296  }
1297 
1300 
1303 
1305  if (r)
1306  return r;
1307 
1308  /* Setup MFP options for CCMP */
1310  /* Mask Retry(b11), PwrMgt(b12), MoreData(b13) to 0 in mgmt
1311  * frames when constructing CCMP AAD. */
1313  0xc7ff);
1314  ah->sw_mgmt_crypto = 0;
1315  } else if (AR_SREV_9160_10_OR_LATER(ah)) {
1316  /* Disable hardware crypto for management frames */
1321  ah->sw_mgmt_crypto = 1;
1322  } else
1323  ah->sw_mgmt_crypto = 1;
1324 
1325  if (IS_CHAN_OFDM(chan) || IS_CHAN_HT(chan))
1327 
1329  ah->eep_ops->set_board_values(ah, chan);
1330 
1332 
1335  | macStaId1
1337  | (ah->config.
1338  ack_6mb ? AR_STA_ID1_ACKCTS_6MB : 0)
1339  | ah->sta_id1_defaults);
1341  REG_WRITE(ah, AR_DEF_ANTENNA, saveDefAntenna);
1343  REG_WRITE(ah, AR_ISR, ~0);
1345 
1347 
1349 
1351  if (r)
1352  return r;
1353 
1355 
1357 
1358  for (i = 0; i < AR_NUM_DCU; i++)
1359  REG_WRITE(ah, AR_DQCUMASK(i), 1 << i);
1360 
1362 
1363  ah->intr_txqs = 0;
1364  for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++)
1366 
1369 
1370  if (ah->caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
1371  ath9k_hw_cfg_gpio_input(ah, ah->rfkill_gpio);
1372 
1374 
1375  if (!AR_SREV_9300_20_OR_LATER(ah)) {
1378  }
1379 
1381 
1383 
1384  REG_WRITE(ah, AR_OBS, 8);
1385 
1386  if (ah->config.rx_intr_mitigation) {
1389  }
1390 
1391  if (ah->config.tx_intr_mitigation) {
1394  }
1395 
1397 
1398  if (!ath9k_hw_init_cal(ah, chan))
1399  return -EIO;
1400 
1402 
1404  REG_WRITE(ah, AR_CFG_LED, saveLedState | AR_CFG_SCLK_32KHZ);
1405 
1407 
1408  /*
1409  * For big endian systems turn on swapping for descriptors
1410  */
1411  if (AR_SREV_9100(ah)) {
1412  u32 mask;
1413  mask = REG_READ(ah, AR_CFG);
1414  if (mask & (AR_CFG_SWRB | AR_CFG_SWTB | AR_CFG_SWRG)) {
1415  DBG2("ath9k: "
1416  "CFG Byte Swap Set 0x%x\n", mask);
1417  } else {
1418  mask =
1420  REG_WRITE(ah, AR_CFG, mask);
1421  DBG2("ath9k: "
1422  "Setting CFG 0x%x\n", REG_READ(ah, AR_CFG));
1423  }
1424  } else {
1425  if (common->bus_ops->ath_bus_type == ATH_USB) {
1426  /* Configure AR9271 target WLAN */
1427  if (AR_SREV_9271(ah))
1429  else
1431  }
1432 #if __BYTE_ORDER == __BIG_ENDIAN
1433  else if (AR_SREV_9340(ah))
1435  else
1437 #endif
1438  }
1439 
1442  }
1443 
1445 
1446  return 0;
1447 }
int ath9k_hw_resettxqueue(struct ath_hw *ah, u32 q)
Definition: ath9k_mac.c:283
#define AR_CFG_LED_MODE_SEL
Definition: reg.h:663
#define EINVAL
Invalid argument.
Definition: errno.h:428
u16 channel
Definition: hw.h:333
void ath9k_hw_write_associd(struct ath_hw *ah)
Definition: ath9k_hw.c:1964
#define AR_AES_MUTE_MASK1_FC_MGMT
Definition: reg.h:1858
#define AR_TIMT_LAST
Definition: reg.h:59
void ar9002_hw_enable_async_fifo(struct ath_hw *ah)
#define INIT_RSSI_THR
Definition: hw.h:158
#define AR_AES_MUTE_MASK1
Definition: reg.h:1855
#define AR_SREV_9280_20_OR_LATER(_ah)
Definition: reg.h:824
#define AR_CFG_LED_ASSOC_CTL
Definition: reg.h:677
#define AR_RIMT_LAST
Definition: reg.h:65
#define AR_TIMT
Definition: reg.h:58
#define INIT_CONFIG_STATUS
Definition: hw.h:157
#define CHANNEL_ALL
Definition: ath5k.h:647
void ath9k_hw_init_global_settings(struct ath_hw *ah)
Definition: ath9k_hw.c:812
static void ath9k_hw_ani_cache_ini_regs(struct ath_hw *ah)
Definition: ath9k_hw.c:55
void ath9k_hw_start_nfcal(struct ath_hw *ah, int update)
Definition: ath9k_calib.c:206
#define IS_CHAN_OFDM(_c)
Definition: hw.h:359
#define REG_CLR_BIT(_a, _r, _f)
Definition: hw.h:109
#define REGWRITE_BUFFER_FLUSH(_ah)
Definition: hw.h:95
#define AR_STA_ID1_ACKCTS_6MB
Definition: reg.h:1443
void ath_hw_setbssidmask(struct ath_common *common)
ath_hw_set_bssid_mask - filter out bssids we listen
Definition: ath_hw.c:120
static void ath9k_hw_mark_phy_inactive(struct ath_hw *ah)
Definition: hw-ops.h:212
#define REG_RMW(_ah, _reg, _set, _clr)
Definition: hw.h:86
void ar9002_hw_enable_wep_aggregation(struct ath_hw *ah)
#define AR_SREV_9100(ah)
Definition: reg.h:810
#define AR_OBS
Definition: reg.h:1094
#define AR_CFG_SWRB
Definition: reg.h:35
struct net80211_channel * chan
Definition: hw.h:347
#define AR_NUM_DCU
Definition: reg.h:483
#define REG_RMW_FIELD(_a, _r, _f, _v)
Definition: hw.h:103
#define AR_RIMT
Definition: reg.h:64
#define AR_CFG_LED
Definition: reg.h:654
static u32 get_unaligned_le32(const void *p)
Definition: ath.h:87
Definition: ath.h:127
#define AR_STA_ID1
Definition: reg.h:1432
#define AR_SREV_9300_20_OR_LATER(_ah)
Definition: reg.h:864
void ar9002_hw_update_async_fifo(struct ath_hw *ah)
#define AR_STA_ID1_BASE_RATE_11B
Definition: reg.h:1444
#define AR_PCU_MISC_MODE2_MGMT_CRYPTO_ENABLE
Definition: reg.h:1831
#define AR_PCU_MISC_MODE2_NO_CRYPTO_FOR_NON_DATA_PKT
Definition: reg.h:1832
static int ath9k_hw_init_cal(struct ath_hw *ah, struct ath9k_channel *chan)
Definition: hw-ops.h:258
#define AR_PCU_MISC_MODE2
Definition: reg.h:1830
void udelay(unsigned long usecs)
Delay for a fixed number of microseconds.
Definition: timer.c:60
void ath9k_hw_loadnf(struct ath_hw *ah, struct ath9k_channel *chan)
Definition: ath9k_calib.c:224
#define AR_CFG_SWRD
Definition: reg.h:34
#define AR_CFG_SCLK_32KHZ
Definition: reg.h:660
#define AR_STA_ID1_PRESERVE_SEQNUM
Definition: reg.h:1448
#define CHANNEL_CW_INT
Definition: ath5k.h:628
#define AR_SREV_9340(_ah)
Definition: reg.h:878
#define AR9271_RADIO_RF_RST
Definition: reg.h:1428
static void ath9k_hw_init_bb(struct ath_hw *ah, struct ath9k_channel *chan)
Definition: hw-ops.h:180
static u16 get_unaligned_le16(const void *p)
Definition: ath.h:83
static void ath9k_hw_init_interrupt_masks(struct ath_hw *ah)
Definition: ath9k_hw.c:725
#define AR_SREV_9280(_ah)
Definition: reg.h:822
void ar9003_hw_disable_phy_restart(struct ath_hw *ah)
void ath9k_hw_cfg_gpio_input(struct ath_hw *ah, u32 gpio)
Definition: ath9k_hw.c:1783
static void ath9k_hw_spur_mitigate_freq(struct ath_hw *ah, struct ath9k_channel *chan)
Definition: hw-ops.h:148
static void ath9k_hw_set_operating_mode(struct ath_hw *ah)
Definition: ath9k_hw.c:954
#define AR_STA_ID0
Definition: reg.h:1431
#define AR_STA_ID1_RTS_USE_DEF
Definition: reg.h:1442
#define ATH9K_NUM_TX_QUEUES
Definition: mac.h:580
static struct ath_common * ath9k_hw_common(struct ath_hw *ah)
Definition: hw.h:869
#define AR_TIMT_FIRST
Definition: reg.h:61
#define AR_CFG_SWRG
Definition: reg.h:36
struct ib_cm_common common
Definition: ib_mad.h:11
#define AR_GPIO_JTAG_DISABLE
Definition: reg.h:1057
static int ath9k_hw_process_ini(struct ath_hw *ah, struct ath9k_channel *chan)
Definition: hw-ops.h:192
#define REG_READ(_ah, _reg)
Definition: hw.h:80
static void ath9k_hw_set_delta_slope(struct ath_hw *ah, struct ath9k_channel *chan)
Definition: hw-ops.h:217
static int ath9k_hw_channel_change(struct ath_hw *ah, struct ath9k_channel *chan)
Definition: ath9k_hw.c:1128
#define REG_SET_BIT(_a, _r, _f)
Definition: hw.h:107
#define AR_CFG_SWTD
Definition: reg.h:32
int ath9k_hw_setpower(struct ath_hw *ah, enum ath9k_power_mode mode)
Definition: ath9k_hw.c:1532
static int ath9k_hw_rf_set_freq(struct ath_hw *ah, struct ath9k_channel *chan)
Definition: hw-ops.h:142
static void ath9k_hw_restore_chainmask(struct ath_hw *ah)
Definition: hw-ops.h:233
#define AR_CFG_SWTB
Definition: reg.h:33
#define REG_WRITE(_ah, _reg, _val)
Definition: hw.h:77
#define AR_RSSI_THR
Definition: reg.h:1468
#define AR_GPIO_INPUT_EN_VAL
Definition: reg.h:1040
#define EIO
Input/output error.
Definition: errno.h:433
#define AR_RIMT_FIRST
Definition: reg.h:67
#define AR_SREV_9271(_ah)
Definition: reg.h:853
static void ath9k_hw_set_dma(struct ath_hw *ah)
Definition: ath9k_hw.c:885
u32 channelFlags
Definition: hw.h:334
#define AR_DEVID_7010(_ah)
Definition: reg.h:891
#define AR_CFG_LED_BLINK_THRESH_SEL
Definition: reg.h:686
#define AR_ISR
Definition: reg.h:171
static int ath9k_hw_chip_reset(struct ath_hw *ah, struct ath9k_channel *chan)
Definition: ath9k_hw.c:1109
int ath9k_hw_getnf(struct ath_hw *ah, struct ath9k_channel *chan)
Definition: ath9k_calib.c:346
uint8_t ah
Definition: registers.h:85
#define AR_SREV_9160_10_OR_LATER(_ah)
Definition: reg.h:817
#define AR9271_GATE_MAC_CTL
Definition: reg.h:1429
#define AR_DEF_ANTENNA
Definition: reg.h:1534
static void ath9k_hw_apply_gpio_override(struct ath_hw *ah)
Definition: ath9k_hw.c:1175
#define DBG(...)
Print a debugging message.
Definition: compiler.h:498
#define AR_CFG
Definition: reg.h:31
#define NULL
NULL pointer (VOID *)
Definition: Base.h:362
#define AR9271_RESET_POWER_DOWN_CONTROL
Definition: reg.h:1427
#define AR_DQCUMASK(_i)
Definition: reg.h:505
uint32_t u32
Definition: stdint.h:23
static void ath9k_hw_set_clockrate(struct ath_hw *ah)
Definition: ath9k_hw.c:68
#define ENABLE_REGWRITE_BUFFER(_ah)
Definition: hw.h:89
#define DBG2(...)
Definition: compiler.h:515
#define AR_CFG_LED_BLINK_SLOW
Definition: reg.h:683
void * memset(void *dest, int character, size_t len) __nonnull
void ar9002_hw_load_ani_reg(struct ath_hw *ah, struct ath9k_channel *chan)
static const uint8_t r[3][4]
MD4 shift amounts.
Definition: md4.c:53
#define IS_CHAN_HT(_c)
Definition: hw.h:376
void ath9k_init_nfcal_hist_buffer(struct ath_hw *ah, struct ath9k_channel *chan)
Definition: ath9k_calib.c:384

References ah, ar9002_hw_enable_async_fifo(), ar9002_hw_enable_wep_aggregation(), ar9002_hw_load_ani_reg(), ar9002_hw_update_async_fifo(), ar9003_hw_disable_phy_restart(), AR9271_GATE_MAC_CTL, AR9271_RADIO_RF_RST, AR9271_RESET_POWER_DOWN_CONTROL, AR_AES_MUTE_MASK1, AR_AES_MUTE_MASK1_FC_MGMT, AR_CFG, AR_CFG_LED, AR_CFG_LED_ASSOC_CTL, AR_CFG_LED_BLINK_SLOW, AR_CFG_LED_BLINK_THRESH_SEL, AR_CFG_LED_MODE_SEL, AR_CFG_SCLK_32KHZ, AR_CFG_SWRB, AR_CFG_SWRD, AR_CFG_SWRG, AR_CFG_SWTB, AR_CFG_SWTD, AR_DEF_ANTENNA, AR_DEVID_7010, AR_DQCUMASK, AR_GPIO_INPUT_EN_VAL, AR_GPIO_JTAG_DISABLE, AR_ISR, AR_NUM_DCU, AR_OBS, AR_PCU_MISC_MODE2, AR_PCU_MISC_MODE2_MGMT_CRYPTO_ENABLE, AR_PCU_MISC_MODE2_NO_CRYPTO_FOR_NON_DATA_PKT, AR_RIMT, AR_RIMT_FIRST, AR_RIMT_LAST, AR_RSSI_THR, AR_SREV_9100, AR_SREV_9160_10_OR_LATER, AR_SREV_9271, AR_SREV_9280, AR_SREV_9280_20_OR_LATER, AR_SREV_9300_20_OR_LATER, AR_SREV_9340, AR_STA_ID0, AR_STA_ID1, AR_STA_ID1_ACKCTS_6MB, AR_STA_ID1_BASE_RATE_11B, AR_STA_ID1_PRESERVE_SEQNUM, AR_STA_ID1_RTS_USE_DEF, AR_TIMT, AR_TIMT_FIRST, AR_TIMT_LAST, ath9k_hw_ani_cache_ini_regs(), ath9k_hw_apply_gpio_override(), ATH9K_HW_CAP_RFSILENT, ath9k_hw_cfg_gpio_input(), ath9k_hw_channel_change(), ath9k_hw_chip_reset(), ath9k_hw_common(), ath9k_hw_getnf(), ath9k_hw_init_bb(), ath9k_hw_init_cal(), ath9k_hw_init_global_settings(), ath9k_hw_init_interrupt_masks(), ath9k_hw_loadnf(), ath9k_hw_mark_phy_inactive(), ath9k_hw_process_ini(), ath9k_hw_resettxqueue(), ath9k_hw_restore_chainmask(), ath9k_hw_rf_set_freq(), ath9k_hw_set_clockrate(), ath9k_hw_set_delta_slope(), ath9k_hw_set_dma(), ath9k_hw_set_operating_mode(), ath9k_hw_setpower(), ath9k_hw_spur_mitigate_freq(), ath9k_hw_start_nfcal(), ath9k_hw_write_associd(), ath9k_init_nfcal_hist_buffer(), ATH9K_NUM_TX_QUEUES, ATH9K_PM_AWAKE, ath_hw_setbssidmask(), ATH_USB, ath9k_channel::chan, ath9k_hw_cal_data::channel, CHANNEL_ALL, CHANNEL_CW_INT, ath9k_hw_cal_data::channelFlags, common, DBG, DBG2, EINVAL, EIO, ENABLE_REGWRITE_BUFFER, get_unaligned_le16(), get_unaligned_le32(), INIT_CONFIG_STATUS, INIT_RSSI_THR, IS_CHAN_HT, IS_CHAN_OFDM, memset(), NULL, r, REG_CLR_BIT, REG_READ, REG_RMW, REG_RMW_FIELD, REG_SET_BIT, REG_WRITE, REGWRITE_BUFFER_FLUSH, and udelay().

Referenced by ath9k_start(), ath_radio_disable(), ath_reset(), and ath_set_channel().

◆ ath9k_set_power_sleep()

static void ath9k_set_power_sleep ( struct ath_hw ah,
int  setChip 
)
static

Definition at line 1457 of file ath9k_hw.c.

1458 {
1460  if (setChip) {
1461  /*
1462  * Clear the RTC force wake bit to allow the
1463  * mac to go to sleep.
1464  */
1469 
1470  /* Shutdown chip. Active low */
1471  if (!AR_SREV_5416(ah) && !AR_SREV_9271(ah))
1473  AR_RTC_RESET_EN);
1474  }
1475 
1476  /* Clear Bit 14 of AR_WA after putting chip into Full Sleep mode. */
1478  REG_WRITE(ah, AR_WA,
1479  ah->WARegVal & ~AR_WA_D3_L1_DISABLE);
1480 }
#define AR_RTC_RESET_EN
Definition: reg.h:1197
#define REG_CLR_BIT(_a, _r, _f)
Definition: hw.h:109
#define AR_SREV_9100(ah)
Definition: reg.h:810
#define AR_RC_HOSTIF
Definition: reg.h:696
#define AR_STA_ID1
Definition: reg.h:1432
#define AR_SREV_9300_20_OR_LATER(_ah)
Definition: reg.h:864
#define AR_RTC_RESET
Definition: reg.h:1195
#define AR_WA_D3_L1_DISABLE
Definition: reg.h:702
#define AR_RTC_FORCE_WAKE_EN
Definition: reg.h:1219
#define REG_SET_BIT(_a, _r, _f)
Definition: hw.h:107
#define AR_SREV_5416(_ah)
Definition: reg.h:798
#define REG_WRITE(_ah, _reg, _val)
Definition: hw.h:77
#define AR_STA_ID1_PWR_SAV
Definition: reg.h:1436
#define AR_SREV_9271(_ah)
Definition: reg.h:853
#define AR_WA
Definition: reg.h:698
uint8_t ah
Definition: registers.h:85
#define AR_RC_AHB
Definition: reg.h:694
#define AR_RC
Definition: reg.h:693
#define AR_RTC_FORCE_WAKE
Definition: reg.h:1217

References ah, AR_RC, AR_RC_AHB, AR_RC_HOSTIF, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN, AR_RTC_RESET, AR_RTC_RESET_EN, AR_SREV_5416, AR_SREV_9100, AR_SREV_9271, AR_SREV_9300_20_OR_LATER, AR_STA_ID1, AR_STA_ID1_PWR_SAV, AR_WA, AR_WA_D3_L1_DISABLE, REG_CLR_BIT, REG_SET_BIT, and REG_WRITE.

Referenced by ath9k_hw_setpower().

◆ ath9k_hw_set_power_awake()

static int ath9k_hw_set_power_awake ( struct ath_hw ah,
int  setChip 
)
static

Definition at line 1482 of file ath9k_hw.c.

1483 {
1484  u32 val;
1485  int i;
1486 
1487  /* Set Bits 14 and 17 of AR_WA before powering on the chip. */
1489  REG_WRITE(ah, AR_WA, ah->WARegVal);
1490  udelay(10);
1491  }
1492 
1493  if (setChip) {
1494  if ((REG_READ(ah, AR_RTC_STATUS) &
1497  ATH9K_RESET_POWER_ON) != 1) {
1498  return 0;
1499  }
1502  }
1503  if (AR_SREV_9100(ah))
1505  AR_RTC_RESET_EN);
1506 
1509  udelay(50);
1510 
1511  for (i = POWER_UP_TIME / 50; i > 0; i--) {
1513  if (val == AR_RTC_STATUS_ON)
1514  break;
1515  udelay(50);
1518  }
1519  if (i == 0) {
1520  DBG("ath9k: "
1521  "Failed to wakeup in %dus\n",
1522  POWER_UP_TIME / 20);
1523  return 0;
1524  }
1525  }
1526 
1528 
1529  return 1;
1530 }
#define AR_RTC_STATUS_ON
Definition: reg.h:1208
#define AR_RTC_STATUS
Definition: reg.h:1199
#define AR_RTC_RESET_EN
Definition: reg.h:1197
#define POWER_UP_TIME
Definition: hw.h:149
#define REG_CLR_BIT(_a, _r, _f)
Definition: hw.h:109
#define AR_SREV_9100(ah)
Definition: reg.h:810
#define AR_RTC_STATUS_M
Definition: reg.h:1202
static void ath9k_hw_init_pll(struct ath_hw *ah, struct ath9k_channel *chan)
Definition: ath9k_hw.c:621
#define AR_STA_ID1
Definition: reg.h:1432
#define AR_SREV_9300_20_OR_LATER(_ah)
Definition: reg.h:864
#define AR_RTC_RESET
Definition: reg.h:1195
#define AR_RTC_FORCE_WAKE_EN
Definition: reg.h:1219
void udelay(unsigned long usecs)
Delay for a fixed number of microseconds.
Definition: timer.c:60
static int ath9k_hw_set_reset_reg(struct ath_hw *ah, u32 type)
Definition: ath9k_hw.c:1088
#define REG_READ(_ah, _reg)
Definition: hw.h:80
void __asmcall int val
Definition: setjmp.h:28
#define REG_SET_BIT(_a, _r, _f)
Definition: hw.h:107
#define AR_RTC_STATUS_SHUTDOWN
Definition: reg.h:1207
#define REG_WRITE(_ah, _reg, _val)
Definition: hw.h:77
#define AR_STA_ID1_PWR_SAV
Definition: reg.h:1436
#define AR_WA
Definition: reg.h:698
uint8_t ah
Definition: registers.h:85
#define DBG(...)
Print a debugging message.
Definition: compiler.h:498
#define NULL
NULL pointer (VOID *)
Definition: Base.h:362
#define AR_RTC_FORCE_WAKE
Definition: reg.h:1217
uint32_t u32
Definition: stdint.h:23

References ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN, AR_RTC_RESET, AR_RTC_RESET_EN, AR_RTC_STATUS, AR_RTC_STATUS_M, AR_RTC_STATUS_ON, AR_RTC_STATUS_SHUTDOWN, AR_SREV_9100, AR_SREV_9300_20_OR_LATER, AR_STA_ID1, AR_STA_ID1_PWR_SAV, AR_WA, ath9k_hw_init_pll(), ath9k_hw_set_reset_reg(), ATH9K_RESET_POWER_ON, DBG, NULL, POWER_UP_TIME, REG_CLR_BIT, REG_READ, REG_SET_BIT, REG_WRITE, udelay(), and val.

Referenced by ath9k_hw_setpower().

◆ ath9k_hw_setpower()

int ath9k_hw_setpower ( struct ath_hw ah,
enum ath9k_power_mode  mode 
)

Definition at line 1532 of file ath9k_hw.c.

1533 {
1534  int status = 1, setChip = 1;
1535  static const char *modes[] = {
1536  "AWAKE",
1537  "FULL-SLEEP",
1538  "NETWORK SLEEP",
1539  "UNDEFINED"
1540  };
1541 
1542  if (ah->power_mode == mode)
1543  return status;
1544 
1545  DBG2("ath9k: %s -> %s\n",
1546  modes[ah->power_mode], modes[mode]);
1547 
1548  switch (mode) {
1549  case ATH9K_PM_AWAKE:
1550  status = ath9k_hw_set_power_awake(ah, setChip);
1551  break;
1552  case ATH9K_PM_FULL_SLEEP:
1553  ath9k_set_power_sleep(ah, setChip);
1554  ah->chip_fullsleep = 1;
1555  break;
1556  default:
1557  DBG("ath9k: Unknown power mode %d\n", mode);
1558  return 0;
1559  }
1560  ah->power_mode = mode;
1561 
1562  return status;
1563 }
uint8_t status
Status.
Definition: ena.h:16
static int ath9k_hw_set_power_awake(struct ath_hw *ah, int setChip)
Definition: ath9k_hw.c:1482
static void ath9k_set_power_sleep(struct ath_hw *ah, int setChip)
Definition: ath9k_hw.c:1457
uint8_t ah
Definition: registers.h:85
#define DBG(...)
Print a debugging message.
Definition: compiler.h:498
#define DBG2(...)
Definition: compiler.h:515

References ah, ath9k_hw_set_power_awake(), ATH9K_PM_AWAKE, ATH9K_PM_FULL_SLEEP, ath9k_set_power_sleep(), DBG, DBG2, and status.

Referenced by __ath9k_hw_init(), ath9k_hw_chip_reset(), ath9k_hw_deinit(), ath9k_hw_disable(), ath9k_hw_reset(), and ath9k_setpower().

◆ ath9k_hw_fill_cap_info()

int ath9k_hw_fill_cap_info ( struct ath_hw ah)

Definition at line 1569 of file ath9k_hw.c.

1570 {
1571  struct ath9k_hw_capabilities *pCap = &ah->caps;
1572  struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
1573  struct ath_common *common = ath9k_hw_common(ah);
1574 
1575  u16 eeval;
1576  u8 ant_div_ctl1, tx_chainmask, rx_chainmask;
1577 
1578  eeval = ah->eep_ops->get_eeprom(ah, EEP_REG_0);
1579  regulatory->current_rd = eeval;
1580 
1581  eeval = ah->eep_ops->get_eeprom(ah, EEP_REG_1);
1583  eeval |= AR9285_RDEXT_DEFAULT;
1584  regulatory->current_rd_ext = eeval;
1585 
1586  if (ah->hw_version.subvendorid == AR_SUBVENDOR_ID_NEW_A) {
1587  if (regulatory->current_rd == 0x64 ||
1588  regulatory->current_rd == 0x65)
1589  regulatory->current_rd += 5;
1590  else if (regulatory->current_rd == 0x41)
1591  regulatory->current_rd = 0x43;
1592  DBG2("ath9k: "
1593  "regdomain mapped to 0x%x\n", regulatory->current_rd);
1594  }
1595 
1596  eeval = ah->eep_ops->get_eeprom(ah, EEP_OP_MODE);
1597  if ((eeval & (AR5416_OPFLAGS_11G | AR5416_OPFLAGS_11A)) == 0) {
1598  DBG("ath9k: "
1599  "no band has been marked as supported in EEPROM\n");
1600  return -EINVAL;
1601  }
1602 
1603  if (eeval & AR5416_OPFLAGS_11A)
1604  pCap->hw_caps |= ATH9K_HW_CAP_5GHZ;
1605 
1606  if (eeval & AR5416_OPFLAGS_11G)
1607  pCap->hw_caps |= ATH9K_HW_CAP_2GHZ;
1608 
1609  pCap->tx_chainmask = ah->eep_ops->get_eeprom(ah, EEP_TX_MASK);
1610  /*
1611  * For AR9271 we will temporarilly uses the rx chainmax as read from
1612  * the EEPROM.
1613  */
1614  if ((ah->hw_version.devid == AR5416_DEVID_PCI) &&
1615  !(eeval & AR5416_OPFLAGS_11A) &&
1616  !(AR_SREV_9271(ah)))
1617  /* CB71: GPIO 0 is pulled down to indicate 3 rx chains */
1618  pCap->rx_chainmask = ath9k_hw_gpio_get(ah, 0) ? 0x5 : 0x7;
1619  else if (AR_SREV_9100(ah))
1620  pCap->rx_chainmask = 0x7;
1621  else
1622  /* Use rx_chainmask from EEPROM. */
1623  pCap->rx_chainmask = ah->eep_ops->get_eeprom(ah, EEP_RX_MASK);
1624 
1625  ah->misc_mode |= AR_PCU_MIC_NEW_LOC_ENA;
1626 
1627  /* enable key search for every frame in an aggregate */
1629  ah->misc_mode |= AR_PCU_ALWAYS_PERFORM_KEYSEARCH;
1630 
1631  common->crypt_caps |= ATH_CRYPT_CAP_CIPHER_AESCCM;
1632 
1633  pCap->hw_caps &= ~ATH9K_HW_CAP_HT;
1634 
1635  if (AR_SREV_9271(ah))
1637  else if (AR_DEVID_7010(ah))
1639  else if (AR_SREV_9285_12_OR_LATER(ah))
1641  else if (AR_SREV_9280_20_OR_LATER(ah))
1643  else
1644  pCap->num_gpio_pins = AR_NUM_GPIO;
1645 
1647  pCap->hw_caps |= ATH9K_HW_CAP_CST;
1649  } else {
1650  pCap->rts_aggr_limit = (8 * 1024);
1651  }
1652 
1653  ah->rfsilent = ah->eep_ops->get_eeprom(ah, EEP_RF_SILENT);
1654  if (ah->rfsilent & EEP_RFSILENT_ENABLED) {
1655  ah->rfkill_gpio =
1656  MS(ah->rfsilent, EEP_RFSILENT_GPIO_SEL);
1657  ah->rfkill_polarity =
1658  MS(ah->rfsilent, EEP_RFSILENT_POLARITY);
1659 
1660  pCap->hw_caps |= ATH9K_HW_CAP_RFSILENT;
1661  }
1662 
1663  pCap->hw_caps &= ~ATH9K_HW_CAP_AUTOSLEEP;
1664 
1665  if (AR_SREV_9280(ah) || AR_SREV_9285(ah))
1667  else
1669 
1672  if (!AR_SREV_9485(ah))
1673  pCap->hw_caps |= ATH9K_HW_CAP_LDPC;
1674 
1677  pCap->rx_status_len = sizeof(struct ar9003_rxs);
1678  pCap->tx_desc_len = sizeof(struct ar9003_txc);
1679  pCap->txs_len = sizeof(struct ar9003_txs);
1680  if (!ah->config.paprd_disable &&
1681  ah->eep_ops->get_eeprom(ah, EEP_PAPRD))
1682  pCap->hw_caps |= ATH9K_HW_CAP_PAPRD;
1683  } else {
1684  pCap->tx_desc_len = sizeof(struct ath_desc);
1685  if (AR_SREV_9280_20(ah) &&
1686  ((ah->eep_ops->get_eeprom(ah, EEP_MINOR_REV) <=
1688  ah->eep_ops->get_eeprom(ah, EEP_FSTCLK_5G)))
1690  }
1691 
1694 
1696  ah->ent_mode = REG_READ(ah, AR_ENT_OTP);
1697 
1699  pCap->hw_caps |= ATH9K_HW_CAP_SGI_20;
1700 
1701  if (AR_SREV_9285(ah))
1702  if (ah->eep_ops->get_eeprom(ah, EEP_MODAL_VER) >= 3) {
1703  ant_div_ctl1 =
1704  ah->eep_ops->get_eeprom(ah, EEP_ANT_DIV_CTL1);
1705  if ((ant_div_ctl1 & 0x1) && ((ant_div_ctl1 >> 3) & 0x1))
1707  }
1709  if (ah->eep_ops->get_eeprom(ah, EEP_CHAIN_MASK_REDUCE))
1710  pCap->hw_caps |= ATH9K_HW_CAP_APM;
1711  }
1712 
1713 
1714  if (AR_SREV_9485(ah)) {
1715  ant_div_ctl1 = ah->eep_ops->get_eeprom(ah, EEP_ANT_DIV_CTL1);
1716  /*
1717  * enable the diversity-combining algorithm only when
1718  * both enable_lna_div and enable_fast_div are set
1719  * Table for Diversity
1720  * ant_div_alt_lnaconf bit 0-1
1721  * ant_div_main_lnaconf bit 2-3
1722  * ant_div_alt_gaintb bit 4
1723  * ant_div_main_gaintb bit 5
1724  * enable_ant_div_lnadiv bit 6
1725  * enable_ant_fast_div bit 7
1726  */
1727  if ((ant_div_ctl1 >> 0x6) == 0x3)
1729  }
1730 
1731  if (AR_SREV_9485_10(ah)) {
1732  pCap->pcie_lcr_extsync_en = 1;
1733  pCap->pcie_lcr_offset = 0x80;
1734  }
1735 
1736  tx_chainmask = pCap->tx_chainmask;
1737  rx_chainmask = pCap->rx_chainmask;
1738  while (tx_chainmask || rx_chainmask) {
1739  if (tx_chainmask & BIT(0))
1740  pCap->max_txchains++;
1741  if (rx_chainmask & BIT(0))
1742  pCap->max_rxchains++;
1743 
1744  tx_chainmask >>= 1;
1745  rx_chainmask >>= 1;
1746  }
1747 
1748  return 0;
1749 }
uint16_t u16
Definition: stdint.h:21
#define EINVAL
Invalid argument.
Definition: errno.h:428
#define AR_PCU_MIC_NEW_LOC_ENA
Definition: reg.h:1642
#define AR_SREV_9287_11_OR_LATER(_ah)
Definition: reg.h:836
struct ath_regulatory regulatory
Definition: ath.h:222
#define AR_NUM_GPIO
Definition: reg.h:986
#define AR_SREV_9280_20_OR_LATER(_ah)
Definition: reg.h:824
u16 rts_aggr_limit
Definition: hw.h:200
#define MS(_v, _f)
Definition: hw.h:102
#define AR9285_NUM_GPIO
Definition: reg.h:988
#define AR_SREV_9485(_ah)
Definition: reg.h:867
#define AR_SREV_9100(ah)
Definition: reg.h:810
#define AR_SREV_9485_10(_ah)
Definition: reg.h:869
#define AR_SREV_9285(_ah)
Definition: reg.h:829
#define ATH9K_HW_RX_LP_QDEPTH
Definition: hw.h:164
int pcie_lcr_extsync_en
Definition: hw.h:212
#define EEP_RFSILENT_POLARITY
Definition: eeprom.h:118
Definition: mac.h:240
#define AR_SUBVENDOR_ID_NEW_A
Definition: hw.h:58
#define AR_ENT_OTP
Definition: reg.h:1107
#define AR_SREV_9280_20(_ah)
Definition: reg.h:826
#define AR_SREV_9300_20_OR_LATER(_ah)
Definition: reg.h:864
u16 current_rd_ext
Definition: ath.h:142
#define EEP_RFSILENT_GPIO_SEL
Definition: eeprom.h:120
#define AR5416_EEP_MINOR_VER_16
Definition: eeprom.h:137
#define AR5416_OPFLAGS_11A
Definition: eeprom.h:123
static struct ath_regulatory * ath9k_hw_regulatory(struct ath_hw *ah)
Definition: hw.h:874
u16 current_rd
Definition: ath.h:141
u32 ath9k_hw_gpio_get(struct ath_hw *ah, u32 gpio)
Definition: ath9k_hw.c:1802
#define AR9271_NUM_GPIO
Definition: reg.h:990
#define AR_SREV_9280(_ah)
Definition: reg.h:822
u8 tx_chainmask
Definition: ath.h:209
static struct ath_common * ath9k_hw_common(struct ath_hw *ah)
Definition: hw.h:869
#define AR_SREV_9285_12_OR_LATER(_ah)
Definition: reg.h:831
#define EEP_RFSILENT_ENABLED
Definition: eeprom.h:116
struct ib_cm_common common
Definition: ib_mad.h:11
#define REG_READ(_ah, _reg)
Definition: hw.h:80
u8 rx_chainmask
Definition: ath.h:210
#define AR7010_NUM_GPIO
Definition: reg.h:992
#define AR5416_OPFLAGS_11G
Definition: eeprom.h:124
#define ATH9K_HW_RX_HP_QDEPTH
Definition: hw.h:163
#define BIT(nr)
Definition: ath.h:32
#define ATH_AMPDU_LIMIT_MAX
Definition: hw.h:68
#define AR928X_NUM_GPIO
Definition: reg.h:987
u16 pcie_lcr_offset
Definition: hw.h:211
#define AR_SREV_9271(_ah)
Definition: reg.h:853
#define AR_DEVID_7010(_ah)
Definition: reg.h:891
uint8_t ah
Definition: registers.h:85
#define AR_PCU_ALWAYS_PERFORM_KEYSEARCH
Definition: reg.h:1653
#define AR_SREV_9160_10_OR_LATER(_ah)
Definition: reg.h:817
#define DBG(...)
Print a debugging message.
Definition: compiler.h:498
uint8_t u8
Definition: stdint.h:19
#define AR5416_DEVID_PCI
Definition: hw.h:42
#define AR9285_RDEXT_DEFAULT
Definition: eeprom.h:99
#define DBG2(...)
Definition: compiler.h:515
if(natsemi->flags &NATSEMI_64BIT) return 1

References ah, AR5416_DEVID_PCI, AR5416_EEP_MINOR_VER_16, AR5416_OPFLAGS_11A, AR5416_OPFLAGS_11G, AR7010_NUM_GPIO, AR9271_NUM_GPIO, AR9285_NUM_GPIO, AR9285_RDEXT_DEFAULT, AR928X_NUM_GPIO, AR_DEVID_7010, AR_ENT_OTP, AR_NUM_GPIO, AR_PCU_ALWAYS_PERFORM_KEYSEARCH, AR_PCU_MIC_NEW_LOC_ENA, AR_SREV_9100, AR_SREV_9160_10_OR_LATER, AR_SREV_9271, AR_SREV_9280, AR_SREV_9280_20, AR_SREV_9280_20_OR_LATER, AR_SREV_9285, AR_SREV_9285_12_OR_LATER, AR_SREV_9287_11_OR_LATER, AR_SREV_9300_20_OR_LATER, AR_SREV_9485, AR_SREV_9485_10, AR_SUBVENDOR_ID_NEW_A, ATH9K_HW_CAP_2GHZ, ATH9K_HW_CAP_4KB_SPLITTRANS, ATH9K_HW_CAP_5GHZ, ATH9K_HW_CAP_ANT_DIV_COMB, ATH9K_HW_CAP_APM, ATH9K_HW_CAP_AUTOSLEEP, ATH9K_HW_CAP_CST, ATH9K_HW_CAP_FASTCLOCK, ATH9K_HW_CAP_HT, ATH9K_HW_CAP_LDPC, ATH9K_HW_CAP_PAPRD, ATH9K_HW_CAP_RAC_SUPPORTED, ATH9K_HW_CAP_RFSILENT, ATH9K_HW_CAP_SGI_20, ath9k_hw_common(), ath9k_hw_gpio_get(), ath9k_hw_regulatory(), ATH9K_HW_RX_HP_QDEPTH, ATH9K_HW_RX_LP_QDEPTH, ATH_AMPDU_LIMIT_MAX, ATH_CRYPT_CAP_CIPHER_AESCCM, BIT, common, ath_regulatory::current_rd, ath_regulatory::current_rd_ext, DBG, DBG2, EEP_ANT_DIV_CTL1, EEP_CHAIN_MASK_REDUCE, EEP_FSTCLK_5G, EEP_MINOR_REV, EEP_MODAL_VER, EEP_OP_MODE, EEP_PAPRD, EEP_REG_0, EEP_REG_1, EEP_RF_SILENT, EEP_RFSILENT_ENABLED, EEP_RFSILENT_GPIO_SEL, EEP_RFSILENT_POLARITY, EEP_RX_MASK, EEP_TX_MASK, EINVAL, ath9k_hw_capabilities::hw_caps, if(), ath9k_hw_capabilities::max_rxchains, ath9k_hw_capabilities::max_txchains, MS, ath9k_hw_capabilities::num_gpio_pins, ath9k_hw_capabilities::pcie_lcr_extsync_en, ath9k_hw_capabilities::pcie_lcr_offset, REG_READ, ath_common::regulatory, ath9k_hw_capabilities::rts_aggr_limit, ath9k_hw_capabilities::rx_chainmask, ath_common::rx_chainmask, ath9k_hw_capabilities::rx_hp_qdepth, ath9k_hw_capabilities::rx_lp_qdepth, ath9k_hw_capabilities::rx_status_len, ath9k_hw_capabilities::tx_chainmask, ath_common::tx_chainmask, ath9k_hw_capabilities::tx_desc_len, and ath9k_hw_capabilities::txs_len.

Referenced by __ath9k_hw_init().

◆ ath9k_hw_gpio_cfg_output_mux()

static void ath9k_hw_gpio_cfg_output_mux ( struct ath_hw ah,
u32  gpio,
u32  type 
)
static

Definition at line 1755 of file ath9k_hw.c.

1757 {
1758  int addr;
1759  u32 gpio_shift, tmp;
1760 
1761  if (gpio > 11)
1763  else if (gpio > 5)
1765  else
1767 
1768  gpio_shift = (gpio % 6) * 5;
1769 
1771  || (addr != AR_GPIO_OUTPUT_MUX1)) {
1772  REG_RMW(ah, addr, (type << gpio_shift),
1773  (0x1f << gpio_shift));
1774  } else {
1775  tmp = REG_READ(ah, addr);
1776  tmp = ((tmp & 0x1F0) << 1) | (tmp & ~0x1F0);
1777  tmp &= ~(0x1f << gpio_shift);
1778  tmp |= (type << gpio_shift);
1779  REG_WRITE(ah, addr, tmp);
1780  }
1781 }
#define AR_SREV_9280_20_OR_LATER(_ah)
Definition: reg.h:824
uint8_t type
Type.
Definition: ena.h:16
#define REG_RMW(_ah, _reg, _set, _clr)
Definition: hw.h:86
#define AR_GPIO_OUTPUT_MUX3
Definition: reg.h:1079
pseudo_bit_t gpio[0x00001]
Definition: arbel.h:30
uint8_t * tmp
Definition: entropy.h:156
u32 addr
Definition: sky2.h:8
#define AR_GPIO_OUTPUT_MUX2
Definition: reg.h:1077
#define REG_READ(_ah, _reg)
Definition: hw.h:80
#define REG_WRITE(_ah, _reg, _val)
Definition: hw.h:77
uint8_t ah
Definition: registers.h:85
uint32_t u32
Definition: stdint.h:23
#define AR_GPIO_OUTPUT_MUX1
Definition: reg.h:1075

References addr, ah, AR_GPIO_OUTPUT_MUX1, AR_GPIO_OUTPUT_MUX2, AR_GPIO_OUTPUT_MUX3, AR_SREV_9280_20_OR_LATER, gpio, REG_READ, REG_RMW, REG_WRITE, tmp, and type.

Referenced by ath9k_hw_cfg_output().

◆ ath9k_hw_cfg_gpio_input()

void ath9k_hw_cfg_gpio_input ( struct ath_hw ah,
u32  gpio 
)

Definition at line 1783 of file ath9k_hw.c.

1784 {
1785  u32 gpio_shift;
1786 
1787  if (AR_DEVID_7010(ah)) {
1788  gpio_shift = gpio;
1790  (AR7010_GPIO_OE_AS_INPUT << gpio_shift),
1791  (AR7010_GPIO_OE_MASK << gpio_shift));
1792  return;
1793  }
1794 
1795  gpio_shift = gpio << 1;
1796  REG_RMW(ah,
1798  (AR_GPIO_OE_OUT_DRV_NO << gpio_shift),
1799  (AR_GPIO_OE_OUT_DRV << gpio_shift));
1800 }
#define AR7010_GPIO_OE_AS_INPUT
Definition: reg.h:1023
#define AR7010_GPIO_OE_MASK
Definition: reg.h:1021
#define REG_RMW(_ah, _reg, _set, _clr)
Definition: hw.h:86
pseudo_bit_t gpio[0x00001]
Definition: arbel.h:30
#define AR_GPIO_OE_OUT_DRV_NO
Definition: reg.h:1015
#define AR_GPIO_OE_OUT_DRV
Definition: reg.h:1014
#define AR_DEVID_7010(_ah)
Definition: reg.h:891
uint8_t ah
Definition: registers.h:85
#define AR_GPIO_OE_OUT
Definition: reg.h:1012
#define AR7010_GPIO_OE
Definition: reg.h:1020
uint32_t u32
Definition: stdint.h:23

References ah, AR7010_GPIO_OE, AR7010_GPIO_OE_AS_INPUT, AR7010_GPIO_OE_MASK, AR_DEVID_7010, AR_GPIO_OE_OUT, AR_GPIO_OE_OUT_DRV, AR_GPIO_OE_OUT_DRV_NO, gpio, and REG_RMW.

Referenced by ath9k_hw_reset(), and ath_radio_disable().

◆ ath9k_hw_gpio_get()

u32 ath9k_hw_gpio_get ( struct ath_hw ah,
u32  gpio 
)

Definition at line 1802 of file ath9k_hw.c.

1803 {
1804 #define MS_REG_READ(x, y) \
1805  (MS(REG_READ(ah, AR_GPIO_IN_OUT), x##_GPIO_IN_VAL) & (AR_GPIO_BIT(y)))
1806 
1807  if (gpio >= ah->caps.num_gpio_pins)
1808  return 0xffffffff;
1809 
1810  if (AR_DEVID_7010(ah)) {
1811  u32 val;
1813  return (MS(val, AR7010_GPIO_IN_VAL) & AR_GPIO_BIT(gpio)) == 0;
1814  } else if (AR_SREV_9300_20_OR_LATER(ah))
1816  AR_GPIO_BIT(gpio)) != 0;
1817  else if (AR_SREV_9271(ah))
1818  return MS_REG_READ(AR9271, gpio) != 0;
1819  else if (AR_SREV_9287_11_OR_LATER(ah))
1820  return MS_REG_READ(AR9287, gpio) != 0;
1821  else if (AR_SREV_9285_12_OR_LATER(ah))
1822  return MS_REG_READ(AR9285, gpio) != 0;
1823  else if (AR_SREV_9280_20_OR_LATER(ah))
1824  return MS_REG_READ(AR928X, gpio) != 0;
1825  else
1826  return MS_REG_READ(AR, gpio) != 0;
1827 }
#define AR_SREV_9287_11_OR_LATER(_ah)
Definition: reg.h:836
#define AR_SREV_9280_20_OR_LATER(_ah)
Definition: reg.h:824
#define MS(_v, _f)
Definition: hw.h:102
#define AR_GPIO_BIT(_gpio)
Definition: hw.h:131
pseudo_bit_t gpio[0x00001]
Definition: arbel.h:30
#define AR_SREV_9300_20_OR_LATER(_ah)
Definition: reg.h:864
#define AR_GPIO_IN
Definition: reg.h:1008
#define AR_SREV_9285_12_OR_LATER(_ah)
Definition: reg.h:831
#define MS_REG_READ(x, y)
#define REG_READ(_ah, _reg)
Definition: hw.h:80
void __asmcall int val
Definition: setjmp.h:28
#define AR7010_GPIO_IN_VAL
Definition: reg.h:1005
#define AR_SREV_9271(_ah)
Definition: reg.h:853
#define AR_DEVID_7010(_ah)
Definition: reg.h:891
#define AR9300_GPIO_IN_VAL
Definition: reg.h:1009
uint8_t ah
Definition: registers.h:85
uint32_t u32
Definition: stdint.h:23
#define AR7010_GPIO_IN
Definition: reg.h:1024

References ah, AR7010_GPIO_IN, AR7010_GPIO_IN_VAL, AR9300_GPIO_IN_VAL, AR_DEVID_7010, AR_GPIO_BIT, AR_GPIO_IN, AR_SREV_9271, AR_SREV_9280_20_OR_LATER, AR_SREV_9285_12_OR_LATER, AR_SREV_9287_11_OR_LATER, AR_SREV_9300_20_OR_LATER, gpio, MS, MS_REG_READ, REG_READ, and val.

Referenced by ath9k_hw_fill_cap_info().

◆ ath9k_hw_cfg_output()

void ath9k_hw_cfg_output ( struct ath_hw ah,
u32  gpio,
u32  ah_signal_type 
)

Definition at line 1829 of file ath9k_hw.c.

1831 {
1832  u32 gpio_shift;
1833 
1834  if (AR_DEVID_7010(ah)) {
1835  gpio_shift = gpio;
1837  (AR7010_GPIO_OE_AS_OUTPUT << gpio_shift),
1838  (AR7010_GPIO_OE_MASK << gpio_shift));
1839  return;
1840  }
1841 
1842  ath9k_hw_gpio_cfg_output_mux(ah, gpio, ah_signal_type);
1843  gpio_shift = 2 * gpio;
1844  REG_RMW(ah,
1846  (AR_GPIO_OE_OUT_DRV_ALL << gpio_shift),
1847  (AR_GPIO_OE_OUT_DRV << gpio_shift));
1848 }
#define AR_GPIO_OE_OUT_DRV_ALL
Definition: reg.h:1018
#define AR7010_GPIO_OE_MASK
Definition: reg.h:1021
#define REG_RMW(_ah, _reg, _set, _clr)
Definition: hw.h:86
pseudo_bit_t gpio[0x00001]
Definition: arbel.h:30
#define AR_GPIO_OE_OUT_DRV
Definition: reg.h:1014
#define AR7010_GPIO_OE_AS_OUTPUT
Definition: reg.h:1022
#define AR_DEVID_7010(_ah)
Definition: reg.h:891
uint8_t ah
Definition: registers.h:85
#define AR_GPIO_OE_OUT
Definition: reg.h:1012
static void ath9k_hw_gpio_cfg_output_mux(struct ath_hw *ah, u32 gpio, u32 type)
Definition: ath9k_hw.c:1755
#define AR7010_GPIO_OE
Definition: reg.h:1020
uint32_t u32
Definition: stdint.h:23

References ah, AR7010_GPIO_OE, AR7010_GPIO_OE_AS_OUTPUT, AR7010_GPIO_OE_MASK, AR_DEVID_7010, AR_GPIO_OE_OUT, AR_GPIO_OE_OUT_DRV, AR_GPIO_OE_OUT_DRV_ALL, ath9k_hw_gpio_cfg_output_mux(), gpio, and REG_RMW.

Referenced by ath9k_hw_apply_gpio_override().

◆ ath9k_hw_set_gpio()

void ath9k_hw_set_gpio ( struct ath_hw ah,
u32  gpio,
u32  val 
)

Definition at line 1850 of file ath9k_hw.c.

1851 {
1852  if (AR_DEVID_7010(ah)) {
1853  val = val ? 0 : 1;
1854  REG_RMW(ah, AR7010_GPIO_OUT, ((val&1) << gpio),
1855  AR_GPIO_BIT(gpio));
1856  return;
1857  }
1858 
1859  if (AR_SREV_9271(ah))
1860  val = ~val;
1861 
1862  REG_RMW(ah, AR_GPIO_IN_OUT, ((val & 1) << gpio),
1863  AR_GPIO_BIT(gpio));
1864 }
#define AR_GPIO_BIT(_gpio)
Definition: hw.h:131
#define REG_RMW(_ah, _reg, _set, _clr)
Definition: hw.h:86
pseudo_bit_t gpio[0x00001]
Definition: arbel.h:30
#define AR_GPIO_IN_OUT
Definition: reg.h:994
#define AR7010_GPIO_OUT
Definition: reg.h:1025
void __asmcall int val
Definition: setjmp.h:28
#define AR_SREV_9271(_ah)
Definition: reg.h:853
#define AR_DEVID_7010(_ah)
Definition: reg.h:891
uint8_t ah
Definition: registers.h:85

References ah, AR7010_GPIO_OUT, AR_DEVID_7010, AR_GPIO_BIT, AR_GPIO_IN_OUT, AR_SREV_9271, gpio, REG_RMW, and val.

Referenced by ath9k_hw_apply_gpio_override(), and ath_radio_disable().

◆ ath9k_hw_getdefantenna()

u32 ath9k_hw_getdefantenna ( struct ath_hw ah)

Definition at line 1866 of file ath9k_hw.c.

1867 {
1868  return REG_READ(ah, AR_DEF_ANTENNA) & 0x7;
1869 }
#define REG_READ(_ah, _reg)
Definition: hw.h:80
uint8_t ah
Definition: registers.h:85
#define AR_DEF_ANTENNA
Definition: reg.h:1534

References ah, AR_DEF_ANTENNA, and REG_READ.

Referenced by ath9k_init_misc().

◆ ath9k_hw_setantenna()

void ath9k_hw_setantenna ( struct ath_hw ah,
u32  antenna 
)

Definition at line 1871 of file ath9k_hw.c.

1872 {
1873  REG_WRITE(ah, AR_DEF_ANTENNA, (antenna & 0x7));
1874 }
#define REG_WRITE(_ah, _reg, _val)
Definition: hw.h:77
uint8_t ah
Definition: registers.h:85
#define AR_DEF_ANTENNA
Definition: reg.h:1534

References ah, AR_DEF_ANTENNA, and REG_WRITE.

Referenced by ath_setdefantenna().

◆ ath9k_hw_getrxfilter()

u32 ath9k_hw_getrxfilter ( struct ath_hw ah)

Definition at line 1880 of file ath9k_hw.c.

1881 {
1883  u32 phybits = REG_READ(ah, AR_PHY_ERR);
1884 
1885  if (phybits & AR_PHY_ERR_RADAR)
1889 
1890  return bits;
1891 }
#define AR_PHY_ERR_RADAR
Definition: reg.h:1630
#define AR_PHY_ERR_CCK_TIMING
Definition: reg.h:1632
#define AR_RX_FILTER
Definition: reg.h:1490
#define AR_PHY_ERR
Definition: reg.h:1627
#define REG_READ(_ah, _reg)
Definition: hw.h:80
static volatile void * bits
Definition: bitops.h:27
uint8_t ah
Definition: registers.h:85
#define AR_PHY_ERR_OFDM_TIMING
Definition: reg.h:1631
uint32_t u32
Definition: stdint.h:23

References ah, AR_PHY_ERR, AR_PHY_ERR_CCK_TIMING, AR_PHY_ERR_OFDM_TIMING, AR_PHY_ERR_RADAR, AR_RX_FILTER, ATH9K_RX_FILTER_PHYERR, ATH9K_RX_FILTER_PHYRADAR, bits, and REG_READ.

Referenced by ath9k_ani_reset_old(), and ath_calcrxfilter().

◆ ath9k_hw_setrxfilter()

void ath9k_hw_setrxfilter ( struct ath_hw ah,
u32  bits 
)

Definition at line 1893 of file ath9k_hw.c.

1894 {
1895  u32 phybits;
1896 
1898 
1900 
1901  phybits = 0;
1903  phybits |= AR_PHY_ERR_RADAR;
1906  REG_WRITE(ah, AR_PHY_ERR, phybits);
1907 
1908  if (phybits)
1910  else
1912 
1914 }
#define REG_CLR_BIT(_a, _r, _f)
Definition: hw.h:109
#define REGWRITE_BUFFER_FLUSH(_ah)
Definition: hw.h:95
#define AR_PHY_ERR_RADAR
Definition: reg.h:1630
#define AR_PHY_ERR_CCK_TIMING
Definition: reg.h:1632
#define AR_RX_FILTER
Definition: reg.h:1490
#define AR_RXCFG
Definition: reg.h:99
#define AR_RXCFG_ZLFDMA
Definition: reg.h:101
#define AR_PHY_ERR
Definition: reg.h:1627
#define REG_SET_BIT(_a, _r, _f)
Definition: hw.h:107
static volatile void * bits
Definition: bitops.h:27
#define REG_WRITE(_ah, _reg, _val)
Definition: hw.h:77
uint8_t ah
Definition: registers.h:85
#define AR_PHY_ERR_OFDM_TIMING
Definition: reg.h:1631
uint32_t u32
Definition: stdint.h:23
#define ENABLE_REGWRITE_BUFFER(_ah)
Definition: hw.h:89

References ah, AR_PHY_ERR, AR_PHY_ERR_CCK_TIMING, AR_PHY_ERR_OFDM_TIMING, AR_PHY_ERR_RADAR, AR_RX_FILTER, AR_RXCFG, AR_RXCFG_ZLFDMA, ATH9K_RX_FILTER_PHYERR, ATH9K_RX_FILTER_PHYRADAR, bits, ENABLE_REGWRITE_BUFFER, REG_CLR_BIT, REG_SET_BIT, REG_WRITE, and REGWRITE_BUFFER_FLUSH.

Referenced by ath9k_ani_reset_old(), ath_opmode_init(), and ath_stoprecv().

◆ ath9k_hw_phy_disable()

int ath9k_hw_phy_disable ( struct ath_hw ah)

Definition at line 1916 of file ath9k_hw.c.

1917 {
1919  return 0;
1920 
1922  return 1;
1923 }
static void ath9k_hw_init_pll(struct ath_hw *ah, struct ath9k_channel *chan)
Definition: ath9k_hw.c:621
static int ath9k_hw_set_reset_reg(struct ath_hw *ah, u32 type)
Definition: ath9k_hw.c:1088
uint8_t ah
Definition: registers.h:85
#define NULL
NULL pointer (VOID *)
Definition: Base.h:362

References ah, ath9k_hw_init_pll(), ath9k_hw_set_reset_reg(), ATH9K_RESET_WARM, and NULL.

Referenced by ath9k_stop(), and ath_radio_disable().

◆ ath9k_hw_disable()

int ath9k_hw_disable ( struct ath_hw ah)

Definition at line 1925 of file ath9k_hw.c.

1926 {
1928  return 0;
1929 
1931  return 0;
1932 
1934  return 1;
1935 }
static void ath9k_hw_init_pll(struct ath_hw *ah, struct ath9k_channel *chan)
Definition: ath9k_hw.c:621
static int ath9k_hw_set_reset_reg(struct ath_hw *ah, u32 type)
Definition: ath9k_hw.c:1088
int ath9k_hw_setpower(struct ath_hw *ah, enum ath9k_power_mode mode)
Definition: ath9k_hw.c:1532
uint8_t ah
Definition: registers.h:85
#define NULL
NULL pointer (VOID *)
Definition: Base.h:362

References ah, ath9k_hw_init_pll(), ath9k_hw_set_reset_reg(), ath9k_hw_setpower(), ATH9K_PM_AWAKE, ATH9K_RESET_COLD, and NULL.

Referenced by ath9k_stop().

◆ ath9k_hw_set_txpowerlimit()

void ath9k_hw_set_txpowerlimit ( struct ath_hw ah,
u32  limit,
int  test 
)

Definition at line 1937 of file ath9k_hw.c.

1938 {
1939  struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
1940  struct ath9k_channel *chan = ah->curchan;
1941  struct net80211_channel *channel = chan->chan;
1942 
1943  regulatory->power_limit = min(limit, (u32) MAX_RATE_POWER);
1944 
1945  ah->eep_ops->set_txpower(ah, chan,
1946  ath9k_regd_get_ctl(regulatory, chan),
1947  0,
1948  channel->maxpower * 2,
1950  (u32) regulatory->power_limit), test);
1951 }
#define min(x, y)
Definition: ath.h:34
struct net80211_channel * chan
Definition: hw.h:347
u32 ath9k_regd_get_ctl(struct ath_regulatory *reg, struct ath9k_channel *chan)
Definition: ath9k_hw.c:867
static struct ath_regulatory * ath9k_hw_regulatory(struct ath_hw *ah)
Definition: hw.h:874
int16_t power_limit
Definition: ath.h:143
uint32_t channel
RNDIS channel.
Definition: netvsc.h:14
uint16_t limit
Limit.
Definition: librm.h:250
An 802.11 RF channel.
Definition: net80211.h:385
uint8_t ah
Definition: registers.h:85
static int test
Definition: epic100.c:73
#define MAX_RATE_POWER
Definition: hw.h:144
uint32_t u32
Definition: stdint.h:23

References ah, ath9k_hw_regulatory(), ath9k_regd_get_ctl(), ath9k_channel::chan, channel, limit, MAX_RATE_POWER, min, ath_regulatory::power_limit, and test.

Referenced by ath9k_cmn_update_txpow(), and ath9k_init_band_txpower().

◆ ath9k_hw_setopmode()

void ath9k_hw_setopmode ( struct ath_hw ah)

Definition at line 1953 of file ath9k_hw.c.

1954 {
1956 }
static void ath9k_hw_set_operating_mode(struct ath_hw *ah)
Definition: ath9k_hw.c:954
uint8_t ah
Definition: registers.h:85

References ah, and ath9k_hw_set_operating_mode().

Referenced by ath_opmode_init().

◆ ath9k_hw_setmcastfilter()

void ath9k_hw_setmcastfilter ( struct ath_hw ah,
u32  filter0,
u32  filter1 
)

Definition at line 1958 of file ath9k_hw.c.

1959 {
1960  REG_WRITE(ah, AR_MCAST_FIL0, filter0);
1961  REG_WRITE(ah, AR_MCAST_FIL1, filter1);
1962 }
#define AR_MCAST_FIL1
Definition: reg.h:1493
#define AR_MCAST_FIL0
Definition: reg.h:1492
#define REG_WRITE(_ah, _reg, _val)
Definition: hw.h:77
uint8_t ah
Definition: registers.h:85

References ah, AR_MCAST_FIL0, AR_MCAST_FIL1, and REG_WRITE.

Referenced by ath_opmode_init().

◆ ath9k_hw_write_associd()

void ath9k_hw_write_associd ( struct ath_hw ah)

Definition at line 1964 of file ath9k_hw.c.

1965 {
1966  struct ath_common *common = ath9k_hw_common(ah);
1967 
1969  REG_WRITE(ah, AR_BSS_ID1, get_unaligned_le16(common->curbssid + 4) |
1970  ((common->curaid & 0x3fff) << AR_BSS_ID1_AID_S));
1971 }
static u32 get_unaligned_le32(const void *p)
Definition: ath.h:87
static u16 get_unaligned_le16(const void *p)
Definition: ath.h:83
static struct ath_common * ath9k_hw_common(struct ath_hw *ah)
Definition: hw.h:869
#define AR_BSS_ID1
Definition: reg.h:1453
struct ib_cm_common common
Definition: ib_mad.h:11
#define AR_BSS_ID1_AID_S
Definition: reg.h:1456
#define REG_WRITE(_ah, _reg, _val)
Definition: hw.h:77
uint8_t ah
Definition: registers.h:85
#define AR_BSS_ID0
Definition: reg.h:1452

References ah, AR_BSS_ID0, AR_BSS_ID1, AR_BSS_ID1_AID_S, ath9k_hw_common(), common, get_unaligned_le16(), get_unaligned_le32(), and REG_WRITE.

Referenced by ath9k_bss_iter(), ath9k_config_bss(), and ath9k_hw_reset().

◆ ath9k_hw_set11nmac2040()

void ath9k_hw_set11nmac2040 ( struct ath_hw ah)

Definition at line 1973 of file ath9k_hw.c.

1974 {
1975  u32 macmode;
1976 
1977  macmode = 0;
1978 
1979  REG_WRITE(ah, AR_2040_MODE, macmode);
1980 }
#define AR_2040_MODE
Definition: reg.h:1817
#define REG_WRITE(_ah, _reg, _val)
Definition: hw.h:77
uint8_t ah
Definition: registers.h:85
uint32_t u32
Definition: stdint.h:23

References ah, AR_2040_MODE, and REG_WRITE.

Referenced by ar5008_hw_set_channel_regs(), and ar9003_hw_set_channel_regs().

◆ ath9k_hw_mac_bb_name()

static const char* ath9k_hw_mac_bb_name ( u32  mac_bb_version)
static

Definition at line 2015 of file ath9k_hw.c.

2016 {
2017  unsigned int i;
2018 
2019  for (i=0; i<ARRAY_SIZE(ath_mac_bb_names); i++) {
2020  if (ath_mac_bb_names[i].version == mac_bb_version) {
2021  return ath_mac_bb_names[i].name;
2022  }
2023  }
2024 
2025  return "????";
2026 }
u32 version
Version number.
Definition: ath9k_hw.c:1983
#define ARRAY_SIZE(x)
Definition: efx_common.h:43
static struct @22 ath_mac_bb_names[]

References ARRAY_SIZE, ath_mac_bb_names, and version.

Referenced by ath9k_hw_name().

◆ ath9k_hw_rf_name()

static const char* ath9k_hw_rf_name ( u16  rf_version)
static

Definition at line 2032 of file ath9k_hw.c.

2033 {
2034  unsigned int i;
2035 
2036  for (i=0; i<ARRAY_SIZE(ath_rf_names); i++) {
2037  if (ath_rf_names[i].version == rf_version) {
2038  return ath_rf_names[i].name;
2039  }
2040  }
2041 
2042  return "????";
2043 }
u32 version
Version number.
Definition: ath9k_hw.c:1983
#define ARRAY_SIZE(x)
Definition: efx_common.h:43
static struct @23 ath_rf_names[]

References ARRAY_SIZE, ath_rf_names, and version.

Referenced by ath9k_hw_name().

◆ ath9k_hw_name()

void ath9k_hw_name ( struct ath_hw ah,
char *  hw_name,
size_t  len 
)

Definition at line 2045 of file ath9k_hw.c.

2046 {
2047  int used;
2048 
2049  /* chipsets >= AR9280 are single-chip */
2051  used = snprintf(hw_name, len,
2052  "Atheros AR%s Rev:%x",
2053  ath9k_hw_mac_bb_name(ah->hw_version.macVersion),
2054  ah->hw_version.macRev);
2055  }
2056  else {
2057  used = snprintf(hw_name, len,
2058  "Atheros AR%s MAC/BB Rev:%x AR%s RF Rev:%x",
2059  ath9k_hw_mac_bb_name(ah->hw_version.macVersion),
2060  ah->hw_version.macRev,
2061  ath9k_hw_rf_name((ah->hw_version.analog5GhzRev &
2063  ah->hw_version.phyRev);
2064  }
2065 
2066  hw_name[used] = '\0';
2067 }
#define AR_SREV_9280_20_OR_LATER(_ah)
Definition: reg.h:824
static const char * ath9k_hw_mac_bb_name(u32 mac_bb_version)
Definition: ath9k_hw.c:2015
static const char * ath9k_hw_rf_name(u16 rf_version)
Definition: ath9k_hw.c:2032
uint32_t len
Length.
Definition: ena.h:14
int snprintf(char *buf, size_t size, const char *fmt,...)
Write a formatted string to a buffer.
Definition: vsprintf.c:382
uint8_t ah
Definition: registers.h:85
#define AR_RADIO_SREV_MAJOR
Definition: reg.h:895

References ah, AR_RADIO_SREV_MAJOR, AR_SREV_9280_20_OR_LATER, ath9k_hw_mac_bb_name(), ath9k_hw_rf_name(), len, and snprintf().

Referenced by ath_pci_probe().

Variable Documentation

◆ version

static struct gnttab_get_version * version
Initial value:
{
return xen_hypercall_3 ( xen, __HYPERVISOR_grant_table_op,
GNTTABOP_get_version,
static __always_inline unsigned long virt_to_phys(volatile const void *addr)
Convert virtual address to a physical address.
Definition: uaccess.h:287
u32 version
Version number.
Definition: ath9k_hw.c:1983
#define __HYPERVISOR_grant_table_op
Definition: xen.h:86

Version number.

Version string.

Definition at line 1983 of file ath9k_hw.c.

Referenced by ath9k_hw_mac_bb_name(), ath9k_hw_rf_name(), hermon_start(), http_parse_status(), hv_map_hypercall(), hvm_cpuid_base(), hvm_map_hypercall(), intelxl_admin_version(), intelxvf_mbox_version(), myri10ge_nv_init(), ntlm_response(), nvconfig_nvdata_access(), nvconfig_nvdata_default_access(), nvconfig_read_rom_ini_values(), peerdist_info(), tls_new_server_hello(), tls_send_client_hello(), tls_version(), vmbus_initiate_contact(), vmware_present(), vmxnet3_check_version(), wpa_find_kie(), x509_parse_version(), and xengrant_init().

◆ name

const char* name

Definition at line 1984 of file ath9k_hw.c.

Referenced by acpi_name(), add_tls(), apply_dns_settings(), ath_descdma_setup(), autovivify_child_settings(), cms_verify(), cms_verify_fail_okx(), cms_verify_okx(), comboot_resolv(), create_menu(), create_parameters(), dhcp_tag_name(), dns_decode(), dns_encode(), dns_encode_fail_okx(), dns_encode_okx(), dns_label(), dns_list_okx(), dns_name(), dns_question(), dns_resolv(), dns_skip(), dns_skip_search(), dns_xfer_deliver(), draw_title_row(), eepro_probe(), efi_blacklist_dell_ip4config(), efi_driver_name(), efi_driver_name2(), efi_file_find(), efi_file_info(), efi_file_varlen(), efi_handle_name(), efi_local_open_resolved(), efi_open_attributes_name(), efi_pecoff_debug_name(), efi_snp_hii_package_list(), eoib_create(), expand_settings(), fc_port_find(), fc_port_open(), fdt_alias(), fdt_child(), fdt_property(), fdt_string(), find_child_settings(), find_gdb_transport(), find_image(), find_menu(), find_netdev(), find_netdev_configurator(), find_parameters(), find_setting(), find_setting_type(), find_settings(), format_dnssl_setting(), gdbudp_configure(), http_authentication(), http_parse_header(), http_parse_www_authenticate(), hvm_map_xenstore(), ib_cmrc_open(), ib_create_mi(), ib_create_qp(), ib_create_service_madx(), image_set_name(), image_set_uri(), imgverify(), nslookup(), nslookup_exec(), numeric_resolv(), parse_eeprom(), parse_kv(), parse_setting_name(), parse_setting_tag(), parse_settings_name(), peerdist_discovery_reply_values(), png_type_name(), register_image(), register_settings(), resolv(), resolv_setting(), setting_name(), sis900_probe(), syslog_fix_name(), t515_reset(), tftp_process_option(), tftp_rx_oack(), tlan_probe(), tls_session(), tulip_probe(), vxgetlink(), vxsetlink(), x509_check_alt_name(), x509_check_dnsname(), x509_check_ipaddress(), x509_check_name(), x509_check_name_fail_okx(), x509_check_name_okx(), xfer_open_named_socket(), xhci_port_protocol(), xsmp_rx_xve_install(), and xve_create().

◆ ath_mac_bb_names

struct { ... } ath_mac_bb_names[]
Initial value:
= {
{ AR_SREV_VERSION_9100, "9100" },
{ AR_SREV_VERSION_9160, "9160" },
{ AR_SREV_VERSION_9280, "9280" },
{ AR_SREV_VERSION_9285, "9285" },
{ AR_SREV_VERSION_9287, "9287" },
{ AR_SREV_VERSION_9271, "9271" },
{ AR_SREV_VERSION_9300, "9300" },
{ AR_SREV_VERSION_9485, "9485" },
}
#define AR_SREV_VERSION_9485
Definition: reg.h:793
#define AR_SREV_VERSION_9300
Definition: reg.h:791
#define AR_SREV_VERSION_9160
Definition: reg.h:772
#define AR_SREV_VERSION_5416_PCI
Definition: reg.h:766
#define AR_SREV_VERSION_9271
Definition: reg.h:788
#define AR_SREV_VERSION_9280
Definition: reg.h:775
#define AR_SREV_VERSION_9285
Definition: reg.h:779
#define AR_SREV_VERSION_5416_PCIE
Definition: reg.h:767
#define AR_SREV_VERSION_9100
Definition: reg.h:771
#define AR_SREV_VERSION_9287
Definition: reg.h:783

Referenced by ath9k_hw_mac_bb_name().

◆ ath_rf_names

struct { ... } ath_rf_names[]
Initial value:
= {
{ 0, "5133" },
{ AR_RAD5133_SREV_MAJOR, "5133" },
{ AR_RAD5122_SREV_MAJOR, "5122" },
{ AR_RAD2133_SREV_MAJOR, "2133" },
}
#define AR_RAD5133_SREV_MAJOR
Definition: reg.h:896
#define AR_RAD5122_SREV_MAJOR
Definition: reg.h:898
#define AR_RAD2122_SREV_MAJOR
Definition: reg.h:899
#define AR_RAD2133_SREV_MAJOR
Definition: reg.h:897

Referenced by ath9k_hw_rf_name().