72 unsigned int clockrate;
83 common->clockrate = clockrate;
90 return usecs *
common->clockrate;
105 "timeout (%d us) on reg 0x%x: 0x%08x & 0x%08x != 0x%08x\n",
112 int column,
unsigned int *writecnt)
117 for (
r = 0;
r <
array->ia_rows;
r++) {
130 for (i = 0,
retval = 0; i < n; i++) {
142 u32 bitsPerSymbol, numBits, numSymbols, phyTime, txTime;
152 numBits = frameLen << 3;
153 txTime =
CCK_SIFS_TIME + phyTime + ((numBits * 1000) / kbps);
163 }
else if (
ah->curchan &&
181 "Unknown phy %d (rate ix %d)\n", phy, rateix);
227 switch (
ah->hw_version.devid) {
242 ah->hw_version.macVersion =
253 ah->is_pciexpress = 1;
284 static const u32 patternData[4] = {
285 0x55555555, 0xaaaaaaaa, 0x66666666, 0x99999999
295 for (i = 0; i < loop_max; i++) {
300 for (j = 0; j < 0x100; j++) {
301 wrData = (j << 16) | j;
304 if (rdData != wrData) {
306 "address test failed addr: 0x%08x - wr:0x%08x != rd:0x%08x\n",
307 addr, wrData, rdData);
311 for (j = 0; j < 4; j++) {
312 wrData = patternData[j];
315 if (wrData != rdData) {
317 "address test failed addr: 0x%08x - wr:0x%08x != rd:0x%08x\n",
318 addr, wrData, rdData);
333 ah->config.dma_beacon_response_time = 2;
334 ah->config.sw_beacon_response_time = 10;
335 ah->config.additional_swba_backoff = 0;
336 ah->config.ack_6mb = 0x0;
337 ah->config.cwm_ignore_extcca = 0;
338 ah->config.pcie_powersave_enable = 0;
339 ah->config.pcie_clock_req = 0;
340 ah->config.pcie_waen = 0;
341 ah->config.analog_shiftreg = 1;
342 ah->config.enable_ani = 1;
350 ah->config.paprd_disable = 1;
352 ah->config.rx_intr_mitigation = 1;
353 ah->config.pcieSerDesWrite = 1;
365 ah->hw_version.subvendorid = 0;
368 ah->sta_id1_defaults =
373 ah->enable_32kHz_clock = DONT_USE_32KHZ;
375 ah->globaltxtimeout = (
u32) -1;
388 for (i = 0; i < 3; i++) {
389 eeval =
ah->eep_ops->get_eeprom(
ah, EEP_MAC[i]);
391 common->macaddr[2 * i] = eeval >> 8;
392 common->macaddr[2 * i + 1] = eeval & 0xff;
394 if (sum == 0 || sum == 0xffff * 3)
421 "Eeprom VER: %d, REV: %d\n",
422 ah->eep_ops->get_eeprom_ver(
ah),
423 ah->eep_ops->get_eeprom_rev(
ah));
428 "Failed allocating banks for external radio\n");
467 DBG(
"ath9k: Couldn't reset chip\n");
477 DBG(
"ath9k: Couldn't wakeup chip\n");
484 !
ah->is_pciexpress)) {
485 ah->config.serialize_regmode =
488 ah->config.serialize_regmode =
493 DBG2(
"ath9k: serialize_regmode is %d\n",
494 ah->config.serialize_regmode);
501 switch (
ah->hw_version.macVersion) {
516 "Mac Chip Rev 0x%02x.%x is not supported by this driver\n",
517 ah->hw_version.macVersion,
ah->hw_version.macRev);
522 ah->is_pciexpress = 0;
536 if (
ah->is_pciexpress)
555 DBG(
"ath9k: Failed to initialize MAC address\n");
575 switch (
ah->hw_version.devid) {
593 DBG(
"ath9k: Hardware device ID 0x%04x not supported\n",
594 ah->hw_version.devid);
601 "Unable to initialize hardware; initialization status: %d\n",
658 u32 regval, pll2_divint, pll2_divfrac, refdiv;
666 if (
ah->is_clk_25mhz) {
668 pll2_divfrac = 0x1eb85;
677 regval |= (0x1 << 16);
682 (pll2_divint << 18) | pll2_divfrac);
686 regval = (regval & 0x80071fff) | (0x1 << 30) | (0x1 << 13) |
687 (0x4 << 26) | (0x18 << 19);
712 if (
ah->is_clk_25mhz) {
738 if (
ah->config.rx_intr_mitigation)
744 if (
ah->config.rx_intr_mitigation)
750 if (
ah->config.tx_intr_mitigation)
802 "bad global tx timeout %d\n", tu);
803 ah->globaltxtimeout = (
u32) -1;
807 ah->globaltxtimeout = tu;
818 DBG2(
"ath9k: ah->misc_mode 0x%x\n",
821 if (
ah->misc_mode != 0)
830 slottime =
ah->slottime + 3 *
ah->coverage_class;
831 acktimeout = slottime + sifstime;
841 acktimeout += 64 - sifstime -
ah->slottime;
846 if (
ah->globaltxtimeout != (
u32) -1)
929 ah->caps.rx_status_len);
965 u32 *coef_mantissa,
u32 *coef_exponent)
967 u32 coef_exp, coef_man;
969 for (coef_exp = 31; coef_exp > 0; coef_exp--)
970 if ((coef_scaled >> coef_exp) & 0x1)
975 coef_man = coef_scaled + (1 << (
COEF_SCALE_S - coef_exp - 1));
978 *coef_exponent = coef_exp - 16;
1035 "RTC stuck in MAC reset\n");
1081 "RTC not waking up\n");
1121 ah->chip_fullsleep = 0;
1139 "Transmit frames pending on queue %d\n", qnum);
1145 DBG(
"ath9k: Could not kill baseband RX\n");
1153 DBG(
"ath9k: Failed to set channel\n");
1158 ah->eep_ops->set_txpower(
ah, chan,
1177 u32 gpio_mask =
ah->gpio_mask;
1180 for (i = 0; gpio_mask; i++, gpio_mask >>= 1) {
1181 if (!(gpio_mask & 1))
1200 if ((
reg & 0x7E7FFFEF) == 0x00702400)
1203 switch (
reg & 0x7E000B00) {
1211 }
while (
count-- > 0);
1226 ah->txchainmask =
common->tx_chainmask;
1227 ah->rxchainmask =
common->rx_chainmask;
1232 if (curchan && !
ah->chip_fullsleep)
1235 ah->caldata = caldata;
1241 memset(caldata, 0,
sizeof(*caldata));
1245 if (bChannelChange &&
1246 (
ah->chip_fullsleep != 1) &&
1248 (
chan->channel !=
ah->curchan->channel) &&
1263 if (saveDefAntenna == 0)
1274 ah->paprd_table_write_done = 0;
1285 DBG(
"ath9k: Chip reset failed\n");
1291 ah->htc_reset_init = 0;
1314 ah->sw_mgmt_crypto = 0;
1321 ah->sw_mgmt_crypto = 1;
1323 ah->sw_mgmt_crypto = 1;
1329 ah->eep_ops->set_board_values(
ah,
chan);
1339 |
ah->sta_id1_defaults);
1386 if (
ah->config.rx_intr_mitigation) {
1391 if (
ah->config.tx_intr_mitigation) {
1416 "CFG Byte Swap Set 0x%x\n", mask);
1432 #if __BYTE_ORDER == __BIG_ENDIAN 1521 "Failed to wakeup in %dus\n",
1534 int status = 1, setChip = 1;
1535 static const char *modes[] = {
1542 if (
ah->power_mode == mode)
1545 DBG2(
"ath9k: %s -> %s\n",
1546 modes[
ah->power_mode], modes[mode]);
1554 ah->chip_fullsleep = 1;
1557 DBG(
"ath9k: Unknown power mode %d\n", mode);
1560 ah->power_mode = mode;
1599 "no band has been marked as supported in EEPROM\n");
1657 ah->rfkill_polarity =
1680 if (!
ah->config.paprd_disable &&
1705 if ((ant_div_ctl1 & 0x1) && ((ant_div_ctl1 >> 3) & 0x1))
1727 if ((ant_div_ctl1 >> 0x6) == 0x3)
1738 while (tx_chainmask || rx_chainmask) {
1739 if (tx_chainmask &
BIT(0))
1741 if (rx_chainmask &
BIT(0))
1768 gpio_shift = (
gpio % 6) * 5;
1773 (0x1f << gpio_shift));
1776 tmp = ((
tmp & 0x1F0) << 1) | (
tmp & ~0x1F0);
1777 tmp &= ~(0x1f << gpio_shift);
1795 gpio_shift =
gpio << 1;
1804 #define MS_REG_READ(x, y) \ 1805 (MS(REG_READ(ah, AR_GPIO_IN_OUT), x##_GPIO_IN_VAL) & (AR_GPIO_BIT(y))) 1807 if (
gpio >=
ah->caps.num_gpio_pins)
1843 gpio_shift = 2 *
gpio;
1945 ah->eep_ops->set_txpower(
ah, chan,
2052 "Atheros AR%s Rev:%x",
2054 ah->hw_version.macRev);
2058 "Atheros AR%s MAC/BB Rev:%x AR%s RF Rev:%x",
2060 ah->hw_version.macRev,
2063 ah->hw_version.phyRev);
2066 hw_name[used] =
'\0';
int ath9k_hw_resettxqueue(struct ath_hw *ah, u32 q)
#define OFDM_SYMBOL_TIME_QUARTER
#define AR_CFG_LED_MODE_SEL
#define AR_PCU_TXBUF_CTRL
#define AR_SREV_VERSION_9485
#define EINVAL
Invalid argument.
#define AR_PCU_MIC_NEW_LOC_ENA
int ath9k_hw_disable(struct ath_hw *ah)
void ath9k_hw_write_associd(struct ath_hw *ah)
#define AR_GPIO_OE_OUT_DRV_ALL
#define OFDM_SIFS_TIME_HALF
#define AR_RAD5133_SREV_MAJOR
#define AR_SREV_9287_11_OR_LATER(_ah)
#define AR_AES_MUTE_MASK1_FC_MGMT
struct ath_regulatory regulatory
#define AR_GTXTO_TIMEOUT_LIMIT
#define AR_PHY_PLL_CONTROL
int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan, struct ath9k_hw_cal_data *caldata, int bChannelChange)
#define AR_SREV_TYPE2_HOST_MODE
void ar9002_hw_enable_async_fifo(struct ath_hw *ah)
static void ath9k_hw_attach_ops(struct ath_hw *ah)
#define AR_RAD5122_SREV_MAJOR
#define AR_AES_MUTE_MASK1
#define AR_SREV_9280_20_OR_LATER(_ah)
static unsigned int unsigned int reg
#define AR7010_GPIO_OE_AS_INPUT
#define AR_CFG_LED_ASSOC_CTL
#define AR7010_GPIO_OE_MASK
u8 channel
The channel currently in use, as an index into the channels array.
#define INIT_CONFIG_STATUS
struct option_descriptor set[0]
#define AR_RTC_RC_COLD_RESET
void ath9k_hw_init_global_settings(struct ath_hw *ah)
static void ath9k_hw_init_mode_gain_regs(struct ath_hw *ah)
u32 ar9003_get_pll_sqsum_dvc(struct ath_hw *ah)
int ath9k_hw_eeprom_init(struct ath_hw *ah)
static void ath9k_hw_ani_cache_ini_regs(struct ath_hw *ah)
#define ATH9K_CLOCK_RATE_5GHZ_OFDM
void ath9k_hw_start_nfcal(struct ath_hw *ah, int update)
static const char * ath9k_hw_mac_bb_name(u32 mac_bb_version)
static int ath9k_hw_set_global_txtimeout(struct ath_hw *ah, u32 tu)
#define AR_EEPROM_MODAL_SPURS
u32 ath9k_hw_numtxpending(struct ath_hw *ah, u32 q)
u32 ath9k_hw_getdefantenna(struct ath_hw *ah)
#define INI_RA(iniarray, row, column)
void ar9003_hw_attach_ops(struct ath_hw *ah)
#define REG_CLR_BIT(_a, _r, _f)
uint32_t type
Operating system type.
#define AR_RTC_RC_MAC_WARM
void(* init_cal_settings)(struct ath_hw *ah)
#define REGWRITE_BUFFER_FLUSH(_ah)
#define AR_STA_ID1_ACKCTS_6MB
#define RTC_PLL_SETTLE_DELAY
void ath_hw_setbssidmask(struct ath_common *common)
ath_hw_set_bssid_mask - filter out bssids we listen
static void ath9k_hw_mark_phy_inactive(struct ath_hw *ah)
#define AR_RTC_RC_MAC_COLD
void ath9k_hw_get_delta_slope_vals(struct ath_hw *ah __unused, u32 coef_scaled, u32 *coef_mantissa, u32 *coef_exponent)
#define AR_GPIO_BIT(_gpio)
#define AR5416_AR9100_DEVID
#define IS_CHAN_HALF_RATE(_c)
#define REG_RMW(_ah, _reg, _set, _clr)
void ar9002_hw_enable_wep_aggregation(struct ath_hw *ah)
#define AR_SREV_9485(_ah)
static void ath9k_hw_set_ack_timeout(struct ath_hw *ah, u32 us)
static const char * ath9k_hw_rf_name(u16 rf_version)
#define AR_SREV_VERSION_9300
#define AR_SREV_9485_10(_ah)
#define AR_AHB_PREFETCH_RD_EN
#define AR_PHY_ERR_CCK_TIMING
#define AR_GPIO_OUTPUT_MUX3
#define AR_SREV_9285(_ah)
#define AR_PCU_TXBUF_CTRL_USABLE_SIZE
#define AR5416_DEVID_PCIE
static void ath9k_hw_configpcipowersave(struct ath_hw *ah, int restore, int power_off)
static void ath9k_hw_init_defaults(struct ath_hw *ah)
#define AR_INTR_PRIO_SYNC_MASK
#define ATH9K_HW_RX_LP_QDEPTH
struct net80211_channel * chan
#define EEP_RFSILENT_POLARITY
#define AR_SUBVENDOR_ID_NEW_A
void ath9k_hw_cfg_output(struct ath_hw *ah, u32 gpio, u32 ah_signal_type)
#define AR_STA_ID1_STA_AP
void ath9k_hw_write_array(struct ath_hw *ah, struct ar5416IniArray *array, int column, unsigned int *writecnt)
void ath9k_hw_setopmode(struct ath_hw *ah)
static int ath9k_hw_rf_alloc_ext_banks(struct ath_hw *ah)
#define REG_RMW_FIELD(_a, _r, _f, _v)
static void ath9k_hw_init_pll(struct ath_hw *ah, struct ath9k_channel *chan)
#define AR_RTC_FORCE_DERIVED_CLK
static void ath9k_hw_setslottime(struct ath_hw *ah, u32 us)
#define AR9300_DEVID_AR9485_PCIE
static u32 get_unaligned_le32(const void *p)
#define AR_SREV_9280_20(_ah)
#define OFDM_SIFS_TIME_QUARTER
pseudo_bit_t gpio[0x00001]
#define IS_CHAN_QUARTER_RATE(_c)
#define NET80211_BAND_2GHZ
The 2.4 GHz ISM band, unlicensed in most countries.
#define AR_SREV_VERSION_9340
#define AR_SREV_VERSION_9160
static void ath9k_hw_init_cal_settings(struct ath_hw *ah)
#define AR_SREV_9300_20_OR_LATER(_ah)
static void ath9k_hw_set_cts_timeout(struct ath_hw *ah, u32 us)
#define AR9300_DEVID_PCIE
static int ath9k_hw_rfbus_req(struct ath_hw *ah)
#define AR_TXCFG_DMASZ_MASK
int ath9k_hw_fill_cap_info(struct ath_hw *ah)
void ar9002_hw_update_async_fifo(struct ath_hw *ah)
void ar9002_hw_attach_ops(struct ath_hw *ah)
#define AR_STA_ID1_BASE_RATE_11B
#define OFDM_PREAMBLE_TIME
u32 ath9k_regd_get_ctl(struct ath_regulatory *reg, struct ath9k_channel *chan)
u32 version
Driver version.
#define EEP_RFSILENT_GPIO_SEL
#define ATH9K_CLOCK_RATE_2GHZ_OFDM
uint32_t array
Array number.
#define AR_PCU_MISC_MODE2_MGMT_CRYPTO_ENABLE
#define AR_PCU_MISC_MODE2_NO_CRYPTO_FOR_NON_DATA_PKT
void ath9k_hw_set_rx_bufsize(struct ath_hw *ah, u16 buf_size)
#define AR5416_EEP_MINOR_VER_16
static int ath9k_hw_init_cal(struct ath_hw *ah, struct ath9k_channel *chan)
static void ath9k_hw_set_channel_regs(struct ath_hw *ah, struct ath9k_channel *chan)
#define AR_GPIO_OUTPUT_MUX_AS_OUTPUT
#define AR_WA_D3_L1_DISABLE
#define AR_RTC_FORCE_WAKE_EN
void ath9k_hw_setantenna(struct ath_hw *ah, u32 antenna)
static int ath9k_hw_set_reset_power_on(struct ath_hw *ah)
#define AR_SREV_9160(_ah)
#define AR_9285_PCU_TXBUF_CTRL_USABLE_SIZE
#define AR5416_OPFLAGS_11A
#define __unused
Declare a variable or data structure as unused.
#define AR_RAD2122_SREV_MAJOR
static int ath9k_hw_set_power_awake(struct ath_hw *ah, int setChip)
static struct ath_regulatory * ath9k_hw_regulatory(struct ath_hw *ah)
#define AR_RAD2133_SREV_MAJOR
#define AR_PCU_MISC_MODE2
void ath9k_hw_set_gpio(struct ath_hw *ah, u32 gpio, u32 val)
void udelay(unsigned long usecs)
Delay for a fixed number of microseconds.
void ath9k_hw_loadnf(struct ath_hw *ah, struct ath9k_channel *chan)
static void ath9k_hw_read_revisions(struct ath_hw *ah)
int ar9002_hw_rf_claim(struct ath_hw *ah)
#define PLL3_DO_MEAS_MASK
uint16_t count
Number of entries.
#define AR_RTC_FORCE_WAKE_ON_INT
void(* ani_cache_ini_regs)(struct ath_hw *ah)
#define AR_CFG_SCLK_32KHZ
uint32_t channel
RNDIS channel.
#define AR_TXCFG_DMASZ_128B
static int ath9k_hw_init_macaddr(struct ath_hw *ah)
#define AR_STA_ID1_PRESERVE_SEQNUM
int ath9k_hw_phy_disable(struct ath_hw *ah)
#define AR_SREV_9340(_ah)
#define AR_CH0_BB_DPLL3_PHASE_SHIFT
#define AR_SREV_VERSION_5416_PCI
#define NET80211_BAND_5GHZ
The band from 4.9 GHz to 5.7 GHz, which tends to be more restricted.
#define OFDM_PREAMBLE_TIME_HALF
#define AR_INTR_PRIO_ASYNC_ENABLE
#define AR9271_RADIO_RF_RST
#define AR_SREV_VERSION_9271
static void ath9k_hw_init_bb(struct ath_hw *ah, struct ath9k_channel *chan)
static int __ath9k_hw_init(struct ath_hw *ah)
static u16 get_unaligned_le16(const void *p)
#define AR_INTR_SYNC_CAUSE
#define AR_CH0_BB_DPLL1_NINI
u32 ath9k_hw_gpio_get(struct ath_hw *ah, u32 gpio)
#define AR_SREV_VERSION_9280
static u32 ath9k_hw_mac_to_clks(struct ath_hw *ah, u32 usecs)
void ath9k_hw_deinit(struct ath_hw *ah)
void(* init_mode_regs)(struct ath_hw *ah)
static void ath9k_hw_init_interrupt_masks(struct ath_hw *ah)
static int ath9k_hw_chip_test(struct ath_hw *ah)
u8 band
The band with which this channel is associated.
#define AR_SREV_9280(_ah)
void ar9003_hw_disable_phy_restart(struct ath_hw *ah)
u16 ath9k_hw_computetxtime(struct ath_hw *ah, u8 phy, int kbps, u32 frameLen, u16 rateix, int shortPreamble)
#define AR_CH0_BB_DPLL1_NFRAC
void ath9k_hw_cfg_gpio_input(struct ath_hw *ah, u32 gpio)
static u32 ath9k_hw_compute_pll_control(struct ath_hw *ah, struct ath9k_channel *chan)
Structure encapsulating the complete state of an 802.11 device.
#define AR_STA_ID1_KSRCH_MODE
static void ath9k_hw_spur_mitigate_freq(struct ath_hw *ah, struct ath9k_channel *chan)
static void ath9k_hw_set_operating_mode(struct ath_hw *ah)
#define EOPNOTSUPP
Operation not supported on socket.
static void ath9k_set_power_sleep(struct ath_hw *ah, int setChip)
#define AR_RXBP_THRESH_LP
#define AR_STA_ID1_RTS_USE_DEF
#define ATH9K_NUM_TX_QUEUES
#define ENODEV
No such device.
void ath9k_hw_reset_txstatus_ring(struct ath_hw *ah)
static struct ath_common * ath9k_hw_common(struct ath_hw *ah)
#define HT40_CHANNEL_CENTER_SHIFT
static int ath9k_hw_post_init(struct ath_hw *ah)
#define AR_SREV_9285_12_OR_LATER(_ah)
#define AR_CH0_BB_DPLL2_PLL_PWD
#define AR_GPIO_OUTPUT_MUX2
void(* init_mode_gain_regs)(struct ath_hw *ah)
static int ath9k_hw_set_reset_reg(struct ath_hw *ah, u32 type)
#define AR_RTC_DERIVED_CLK_PERIOD
#define AR_INTR_PRIO_SYNC_ENABLE
#define AR_GPIO_OE_OUT_DRV_NO
#define AR9280_DEVID_PCIE
#define EEP_RFSILENT_ENABLED
#define MS_REG_READ(x, y)
struct ib_cm_common common
#define AR_GPIO_JTAG_DISABLE
static int ath9k_hw_process_ini(struct ath_hw *ah, struct ath9k_channel *chan)
#define REG_READ(_ah, _reg)
static struct @23 ath_rf_names[]
static void ath9k_hw_set_rfmode(struct ath_hw *ah, struct ath9k_channel *chan)
static void ath9k_hw_set_delta_slope(struct ath_hw *ah, struct ath9k_channel *chan)
static int ath9k_hw_channel_change(struct ath_hw *ah, struct ath9k_channel *chan)
#define EADDRNOTAVAIL
Address not available.
static void ath9k_hw_rf_free_ext_banks(struct ath_hw *ah)
#define CCK_PREAMBLE_BITS
#define REG_SET_BIT(_a, _r, _f)
#define AR5416_OPFLAGS_11G
#define AR_SREV_5416(_ah)
#define ATH9K_HW_RX_HP_QDEPTH
void ath9k_hw_setrxfilter(struct ath_hw *ah, u32 bits)
int ath9k_hw_setpower(struct ath_hw *ah, enum ath9k_power_mode mode)
void ath9k_hw_set_txpowerlimit(struct ath_hw *ah, u32 limit, int test)
#define AR_RTC_RC_WARM_RESET
static int ath9k_hw_rf_set_freq(struct ath_hw *ah, struct ath9k_channel *chan)
#define AR_RTC_STATUS_SHUTDOWN
#define AR_GPIO_OE_OUT_DRV
#define AR7010_GPIO_OE_AS_OUTPUT
static void ath9k_hw_restore_chainmask(struct ath_hw *ah)
#define ATH_AMPDU_LIMIT_MAX
static void ath9k_hw_disablepcie(struct ath_hw *ah)
#define AR_CH0_BB_DPLL2_OUTDIV
static volatile void * bits
#define AR_RXCFG_DMASZ_128B
void ar9002_hw_cck_chan14_spread(struct ath_hw *ah)
static void ath9k_hw_rfbus_done(struct ath_hw *ah)
#define AR_RXBP_THRESH_HP
#define AR9287_DEVID_PCIE
int ath9k_hw_wait(struct ath_hw *ah, u32 reg, u32 mask, u32 val, u32 timeout)
#define REG_WRITE(_ah, _reg, _val)
#define AR_SREV_VERSION_9285
int ath9k_hw_init(struct ath_hw *ah)
#define AR_CH0_BB_DPLL1_REFDIV
void ath9k_hw_set11nmac2040(struct ath_hw *ah)
#define AR_GPIO_INPUT_EN_VAL
#define AR7010_GPIO_IN_VAL
#define CHANNEL_A_HT40PLUS
#define AR_SREV_REVISION2
#define AR_CH0_BB_DPLL2_LOCAL_PLL
#define OFDM_PREAMBLE_TIME_QUARTER
#define AR_INTR_SYNC_ENABLE
#define EIO
Input/output error.
#define AR_STA_ID1_PWR_SAV
struct net80211_channel channels[NET80211_MAX_CHANNELS]
A list of all possible channels we might use.
#define AR_SREV_9271(_ah)
static void ath9k_hw_set_dma(struct ath_hw *ah)
#define AR_DEVID_7010(_ah)
static struct @22 ath_mac_bb_names[]
#define OFDM_SYMBOL_TIME_HALF
int ath9k_hw_check_alive(struct ath_hw *ah)
#define AR_CFG_LED_BLINK_THRESH_SEL
static void ath9k_hw_init_config(struct ath_hw *ah)
int snprintf(char *buf, size_t size, const char *fmt,...)
Write a formatted string to a buffer.
#define AR_STA_ID1_MCAST_KSRCH
void ath9k_hw_get_channel_centers(struct ath_hw *ah __unused, struct ath9k_channel *chan, struct chan_centers *centers)
void ath9k_hw_ani_init(struct ath_hw *ah)
static int ath9k_hw_set_reset(struct ath_hw *ah, int type)
#define AR9300_GPIO_IN_VAL
#define AR_WA_ASPM_TIMER_BASED_DISABLE
static int ath9k_hw_chip_reset(struct ath_hw *ah, struct ath9k_channel *chan)
int ath9k_hw_getnf(struct ath_hw *ah, struct ath9k_channel *chan)
#define AR_PCU_ALWAYS_PERFORM_KEYSEARCH
#define AR_SREV_VERSION_5416_PCIE
#define AR_STA_ID1_AR9100_BA_FIX
static void ath9k_hw_gpio_cfg_output_mux(struct ath_hw *ah, u32 gpio, u32 type)
u32(* compute_pll_control)(struct ath_hw *ah, struct ath9k_channel *chan)
#define AR_SREV_9160_10_OR_LATER(_ah)
#define AR_STA_ID1_CRPT_MIC_ENABLE
#define AR9300_DEVID_AR9340
#define AR9271_GATE_MAC_CTL
static struct ath_hw_private_ops * ath9k_hw_private_ops(struct ath_hw *ah)
#define AR_PHY_ERR_OFDM_TIMING
static void ath9k_hw_apply_gpio_override(struct ath_hw *ah)
#define AR_INTR_SYNC_MASK
#define DBG(...)
Print a debugging message.
void ath9k_hw_ani_setup(struct ath_hw *ah)
#define ATH9K_CLOCK_RATE_CCK
#define AR_CFG_AP_ADHOC_INDICATION
#define CHANNEL_G_HT40PLUS
#define AR_SREV_VERSION_9100
void ath9k_hw_name(struct ath_hw *ah, char *hw_name, size_t len)
#define AR_RADIO_SREV_MAJOR
static void ath9k_hw_init_mode_regs(struct ath_hw *ah)
#define NULL
NULL pointer (VOID *)
#define AR_D_GBL_IFS_SLOT
#define AR_SREV_VERSION_9287
#define ATH9K_CLOCK_FAST_RATE_5GHZ_OFDM
u32 ath_regd_get_band_ctl(struct ath_regulatory *reg, int band)
#define AR2427_DEVID_PCIE
#define AR_RTC_PLL_CONTROL
#define AR9271_RESET_POWER_DOWN_CONTROL
#define AR_CH0_BB_DPLL2_EN_NEGTRIG
#define AR_RTC_FORCE_WAKE
#define AR9285_DEVID_PCIE
u32 ath9k_hw_getrxfilter(struct ath_hw *ah)
#define AR9285_RDEXT_DEFAULT
#define MAX_TX_FIFO_THRESHOLD
static void ath9k_hw_set_clockrate(struct ath_hw *ah)
#define ENABLE_REGWRITE_BUFFER(_ah)
if(natsemi->flags &NATSEMI_64BIT) return 1
void ath9k_hw_setmcastfilter(struct ath_hw *ah, u32 filter0, u32 filter1)
#define AR_CFG_LED_BLINK_SLOW
void * memset(void *dest, int character, size_t len) __nonnull
void ar9002_hw_load_ani_reg(struct ath_hw *ah, struct ath9k_channel *chan)
u32 ath9k_hw_reverse_bits(u32 val, u32 n)
static const uint8_t r[3][4]
MD4 shift amounts.
#define AR_GPIO_OUTPUT_MUX1
#define AR_INTR_PRIO_ASYNC_MASK
#define DIV_ROUND_UP(n, d)
#define AR_RTC_DERIVED_CLK
void ath9k_init_nfcal_hist_buffer(struct ath_hw *ah, struct ath9k_channel *chan)
#define AR_RXCFG_DMASZ_MASK