iPXE
intel.h
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00001 #ifndef _INTEL_H
00002 #define _INTEL_H
00003 
00004 /** @file
00005  *
00006  * Intel 10/100/1000 network card driver
00007  *
00008  */
00009 
00010 FILE_LICENCE ( GPL2_OR_LATER_OR_UBDL );
00011 
00012 #include <stdint.h>
00013 #include <ipxe/if_ether.h>
00014 #include <ipxe/nvs.h>
00015 
00016 /** Intel BAR size */
00017 #define INTEL_BAR_SIZE ( 128 * 1024 )
00018 
00019 /** A packet descriptor */
00020 struct intel_descriptor {
00021         /** Buffer address */
00022         uint64_t address;
00023         /** Length */
00024         uint16_t length;
00025         /** Flags */
00026         uint8_t flags;
00027         /** Command */
00028         uint8_t command;
00029         /** Status */
00030         uint32_t status;
00031 } __attribute__ (( packed ));
00032 
00033 /** Descriptor type */
00034 #define INTEL_DESC_FL_DTYP( dtyp ) ( (dtyp) << 4 )
00035 #define INTEL_DESC_FL_DTYP_DATA INTEL_DESC_FL_DTYP ( 0x03 )
00036 
00037 /** Descriptor extension */
00038 #define INTEL_DESC_CMD_DEXT 0x20
00039 
00040 /** Report status */
00041 #define INTEL_DESC_CMD_RS 0x08
00042 
00043 /** Insert frame checksum (CRC) */
00044 #define INTEL_DESC_CMD_IFCS 0x02
00045 
00046 /** End of packet */
00047 #define INTEL_DESC_CMD_EOP 0x01
00048 
00049 /** Descriptor done */
00050 #define INTEL_DESC_STATUS_DD 0x00000001UL
00051 
00052 /** Receive error */
00053 #define INTEL_DESC_STATUS_RXE 0x00000100UL
00054 
00055 /** Payload length */
00056 #define INTEL_DESC_STATUS_PAYLEN( len ) ( (len) << 14 )
00057 
00058 /** Device Control Register */
00059 #define INTEL_CTRL 0x00000UL
00060 #define INTEL_CTRL_LRST         0x00000008UL    /**< Link reset */
00061 #define INTEL_CTRL_ASDE         0x00000020UL    /**< Auto-speed detection */
00062 #define INTEL_CTRL_SLU          0x00000040UL    /**< Set link up */
00063 #define INTEL_CTRL_FRCSPD       0x00000800UL    /**< Force speed */
00064 #define INTEL_CTRL_FRCDPLX      0x00001000UL    /**< Force duplex */
00065 #define INTEL_CTRL_RST          0x04000000UL    /**< Device reset */
00066 #define INTEL_CTRL_PHY_RST      0x80000000UL    /**< PHY reset */
00067 
00068 /** Time to delay for device reset, in milliseconds */
00069 #define INTEL_RESET_DELAY_MS 20
00070 
00071 /** Device Status Register */
00072 #define INTEL_STATUS 0x00008UL
00073 #define INTEL_STATUS_LU         0x00000002UL    /**< Link up */
00074 
00075 /** EEPROM Read Register */
00076 #define INTEL_EERD 0x00014UL
00077 #define INTEL_EERD_START        0x00000001UL    /**< Start read */
00078 #define INTEL_EERD_DONE_SMALL   0x00000010UL    /**< Read done (small EERD) */
00079 #define INTEL_EERD_DONE_LARGE   0x00000002UL    /**< Read done (large EERD) */
00080 #define INTEL_EERD_ADDR_SHIFT_SMALL 8           /**< Address shift (small) */
00081 #define INTEL_EERD_ADDR_SHIFT_LARGE 2           /**< Address shift (large) */
00082 #define INTEL_EERD_DATA(value)  ( (value) >> 16 ) /**< Read data */
00083 
00084 /** Maximum time to wait for EEPROM read, in milliseconds */
00085 #define INTEL_EEPROM_MAX_WAIT_MS 100
00086 
00087 /** EEPROM word length */
00088 #define INTEL_EEPROM_WORD_LEN_LOG2 1
00089 
00090 /** Minimum EEPROM size, in words */
00091 #define INTEL_EEPROM_MIN_SIZE_WORDS 64
00092 
00093 /** Offset of MAC address within EEPROM */
00094 #define INTEL_EEPROM_MAC 0x00
00095 
00096 /** Interrupt Cause Read Register */
00097 #define INTEL_ICR 0x000c0UL
00098 #define INTEL_IRQ_TXDW          0x00000001UL    /**< Transmit descriptor done */
00099 #define INTEL_IRQ_TXQE          0x00000002UL    /**< Transmit queue empty */
00100 #define INTEL_IRQ_LSC           0x00000004UL    /**< Link status change */
00101 #define INTEL_IRQ_RXDMT0        0x00000010UL    /**< Receive queue low */
00102 #define INTEL_IRQ_RXO           0x00000040UL    /**< Receive overrun */
00103 #define INTEL_IRQ_RXT0          0x00000080UL    /**< Receive timer */
00104 
00105 /** Interrupt Mask Set/Read Register */
00106 #define INTEL_IMS 0x000d0UL
00107 
00108 /** Interrupt Mask Clear Register */
00109 #define INTEL_IMC 0x000d8UL
00110 
00111 /** Receive Control Register */
00112 #define INTEL_RCTL 0x00100UL
00113 #define INTEL_RCTL_EN           0x00000002UL    /**< Receive enable */
00114 #define INTEL_RCTL_UPE          0x00000008UL    /**< Unicast promiscuous mode */
00115 #define INTEL_RCTL_MPE          0x00000010UL    /**< Multicast promiscuous */
00116 #define INTEL_RCTL_BAM          0x00008000UL    /**< Broadcast accept mode */
00117 #define INTEL_RCTL_BSIZE_BSEX(bsex,bsize) \
00118         ( ( (bsize) << 16 ) | ( (bsex) << 25 ) ) /**< Buffer size */
00119 #define INTEL_RCTL_BSIZE_2048   INTEL_RCTL_BSIZE_BSEX ( 0, 0 )
00120 #define INTEL_RCTL_BSIZE_BSEX_MASK INTEL_RCTL_BSIZE_BSEX ( 1, 3 )
00121 #define INTEL_RCTL_SECRC        0x04000000UL    /**< Strip CRC */
00122 
00123 /** Transmit Control Register */
00124 #define INTEL_TCTL 0x00400UL
00125 #define INTEL_TCTL_EN           0x00000002UL    /**< Transmit enable */
00126 #define INTEL_TCTL_PSP          0x00000008UL    /**< Pad short packets */
00127 #define INTEL_TCTL_CT(x)        ( (x) << 4 )    /**< Collision threshold */
00128 #define INTEL_TCTL_CT_DEFAULT   INTEL_TCTL_CT ( 0x0f )
00129 #define INTEL_TCTL_CT_MASK      INTEL_TCTL_CT ( 0xff )
00130 #define INTEL_TCTL_COLD(x)      ( (x) << 12 )   /**< Collision distance */
00131 #define INTEL_TCTL_COLD_DEFAULT INTEL_TCTL_COLD ( 0x040 )
00132 #define INTEL_TCTL_COLD_MASK    INTEL_TCTL_COLD ( 0x3ff )
00133 
00134 /** Packet Buffer Allocation */
00135 #define INTEL_PBA 0x01000UL
00136 
00137 /** Packet Buffer Size */
00138 #define INTEL_PBS 0x01008UL
00139 
00140 /** Receive Descriptor register block */
00141 #define INTEL_RD 0x02800UL
00142 
00143 /** Number of receive descriptors
00144  *
00145  * Minimum value is 8, since the descriptor ring length must be a
00146  * multiple of 128.
00147  */
00148 #define INTEL_NUM_RX_DESC 16
00149 
00150 /** Receive descriptor ring fill level */
00151 #define INTEL_RX_FILL 8
00152 
00153 /** Receive buffer length */
00154 #define INTEL_RX_MAX_LEN 2048
00155 
00156 /** Transmit Descriptor register block */
00157 #define INTEL_TD 0x03800UL
00158 
00159 /** Number of transmit descriptors
00160  *
00161  * Descriptor ring length must be a multiple of 16.  ICH8/9/10
00162  * requires a minimum of 16 TX descriptors.
00163  */
00164 #define INTEL_NUM_TX_DESC 16
00165 
00166 /** Transmit descriptor ring maximum fill level */
00167 #define INTEL_TX_FILL ( INTEL_NUM_TX_DESC - 1 )
00168 
00169 /** Receive/Transmit Descriptor Base Address Low (offset) */
00170 #define INTEL_xDBAL 0x00
00171 
00172 /** Receive/Transmit Descriptor Base Address High (offset) */
00173 #define INTEL_xDBAH 0x04
00174 
00175 /** Receive/Transmit Descriptor Length (offset) */
00176 #define INTEL_xDLEN 0x08
00177 
00178 /** Receive/Transmit Descriptor Head (offset) */
00179 #define INTEL_xDH 0x10
00180 
00181 /** Receive/Transmit Descriptor Tail (offset) */
00182 #define INTEL_xDT 0x18
00183 
00184 /** Receive/Transmit Descriptor Control (offset) */
00185 #define INTEL_xDCTL 0x28
00186 #define INTEL_xDCTL_ENABLE      0x02000000UL    /**< Queue enable */
00187 
00188 /** Maximum time to wait for queue disable, in milliseconds */
00189 #define INTEL_DISABLE_MAX_WAIT_MS 100
00190 
00191 /** Receive Address Low */
00192 #define INTEL_RAL0 0x05400UL
00193 
00194 /** Receive Address High */
00195 #define INTEL_RAH0 0x05404UL
00196 #define INTEL_RAH0_AV           0x80000000UL    /**< Address valid */
00197 
00198 /** Future Extended NVM register 11 */
00199 #define INTEL_FEXTNVM11 0x05bbcUL
00200 #define INTEL_FEXTNVM11_WTF     0x00002000UL    /**< Don't ask */
00201 
00202 /** Receive address */
00203 union intel_receive_address {
00204         struct {
00205                 uint32_t low;
00206                 uint32_t high;
00207         } __attribute__ (( packed )) reg;
00208         uint8_t raw[ETH_ALEN];
00209 };
00210 
00211 /** An Intel descriptor ring */
00212 struct intel_ring {
00213         /** Descriptors */
00214         struct intel_descriptor *desc;
00215         /** Producer index */
00216         unsigned int prod;
00217         /** Consumer index */
00218         unsigned int cons;
00219 
00220         /** Register block */
00221         unsigned int reg;
00222         /** Length (in bytes) */
00223         size_t len;
00224 
00225         /** Populate descriptor
00226          *
00227          * @v desc              Descriptor
00228          * @v addr              Data buffer address
00229          * @v len               Length of data
00230          */
00231         void ( * describe ) ( struct intel_descriptor *desc, physaddr_t addr,
00232                               size_t len );
00233 };
00234 
00235 /**
00236  * Initialise descriptor ring
00237  *
00238  * @v ring              Descriptor ring
00239  * @v count             Number of descriptors
00240  * @v reg               Descriptor register block
00241  * @v describe          Method to populate descriptor
00242  */
00243 static inline __attribute__ (( always_inline)) void
00244 intel_init_ring ( struct intel_ring *ring, unsigned int count, unsigned int reg,
00245                   void ( * describe ) ( struct intel_descriptor *desc,
00246                                         physaddr_t addr, size_t len ) ) {
00247 
00248         ring->len = ( count * sizeof ( ring->desc[0] ) );
00249         ring->reg = reg;
00250         ring->describe = describe;
00251 }
00252 
00253 /** An Intel virtual function mailbox */
00254 struct intel_mailbox {
00255         /** Mailbox control register */
00256         unsigned int ctrl;
00257         /** Mailbox memory base */
00258         unsigned int mem;
00259 };
00260 
00261 /**
00262  * Initialise mailbox
00263  *
00264  * @v mbox              Mailbox
00265  * @v ctrl              Mailbox control register
00266  * @v mem               Mailbox memory register base
00267  */
00268 static inline __attribute__ (( always_inline )) void
00269 intel_init_mbox ( struct intel_mailbox *mbox, unsigned int ctrl,
00270                   unsigned int mem ) {
00271 
00272         mbox->ctrl = ctrl;
00273         mbox->mem = mem;
00274 }
00275 
00276 /** An Intel network card */
00277 struct intel_nic {
00278         /** Registers */
00279         void *regs;
00280         /** Port number (for multi-port devices) */
00281         unsigned int port;
00282         /** Flags */
00283         unsigned int flags;
00284         /** Forced interrupts */
00285         unsigned int force_icr;
00286 
00287         /** EEPROM */
00288         struct nvs_device eeprom;
00289         /** EEPROM done flag */
00290         uint32_t eerd_done;
00291         /** EEPROM address shift */
00292         unsigned int eerd_addr_shift;
00293 
00294         /** Mailbox */
00295         struct intel_mailbox mbox;
00296 
00297         /** Transmit descriptor ring */
00298         struct intel_ring tx;
00299         /** Receive descriptor ring */
00300         struct intel_ring rx;
00301         /** Receive I/O buffers */
00302         struct io_buffer *rx_iobuf[INTEL_NUM_RX_DESC];
00303 };
00304 
00305 /** Driver flags */
00306 enum intel_flags {
00307         /** PBS/PBA errata workaround required */
00308         INTEL_PBS_ERRATA = 0x0001,
00309         /** VMware missing interrupt workaround required */
00310         INTEL_VMWARE = 0x0002,
00311         /** PHY reset is broken */
00312         INTEL_NO_PHY_RST = 0x0004,
00313         /** ASDE is broken */
00314         INTEL_NO_ASDE = 0x0008,
00315         /** Reset may cause a complete device hang */
00316         INTEL_RST_HANG = 0x0010,
00317 };
00318 
00319 /** The i219 has a seriously broken reset mechanism */
00320 #define INTEL_I219 ( INTEL_NO_PHY_RST | INTEL_RST_HANG )
00321 
00322 /**
00323  * Dump diagnostic information
00324  *
00325  * @v intel             Intel device
00326  */
00327 static inline void intel_diag ( struct intel_nic *intel ) {
00328 
00329         DBGC ( intel, "INTEL %p TX %04x(%02x)/%04x(%02x) "
00330                "RX %04x(%02x)/%04x(%02x)\n", intel,
00331                ( intel->tx.cons & 0xffff ),
00332                readl ( intel->regs + intel->tx.reg + INTEL_xDH ),
00333                ( intel->tx.prod & 0xffff ),
00334                readl ( intel->regs + intel->tx.reg + INTEL_xDT ),
00335                ( intel->rx.cons & 0xffff ),
00336                readl ( intel->regs + intel->rx.reg + INTEL_xDH ),
00337                ( intel->rx.prod & 0xffff ),
00338                readl ( intel->regs + intel->rx.reg + INTEL_xDT ) );
00339 }
00340 
00341 extern void intel_describe_tx ( struct intel_descriptor *tx,
00342                                 physaddr_t addr, size_t len );
00343 extern void intel_describe_tx_adv ( struct intel_descriptor *tx,
00344                                     physaddr_t addr, size_t len );
00345 extern void intel_describe_rx ( struct intel_descriptor *rx,
00346                                 physaddr_t addr, size_t len );
00347 extern void intel_reset_ring ( struct intel_nic *intel, unsigned int reg );
00348 extern int intel_create_ring ( struct intel_nic *intel,
00349                                struct intel_ring *ring );
00350 extern void intel_destroy_ring ( struct intel_nic *intel,
00351                                  struct intel_ring *ring );
00352 extern void intel_refill_rx ( struct intel_nic *intel );
00353 extern void intel_empty_rx ( struct intel_nic *intel );
00354 extern int intel_transmit ( struct net_device *netdev,
00355                             struct io_buffer *iobuf );
00356 extern void intel_poll_tx ( struct net_device *netdev );
00357 extern void intel_poll_rx ( struct net_device *netdev );
00358 
00359 #endif /* _INTEL_H */