iPXE
intel.c
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00001 /*
00002  * Copyright (C) 2012 Michael Brown <mbrown@fensystems.co.uk>.
00003  *
00004  * This program is free software; you can redistribute it and/or
00005  * modify it under the terms of the GNU General Public License as
00006  * published by the Free Software Foundation; either version 2 of the
00007  * License, or (at your option) any later version.
00008  *
00009  * This program is distributed in the hope that it will be useful, but
00010  * WITHOUT ANY WARRANTY; without even the implied warranty of
00011  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
00012  * General Public License for more details.
00013  *
00014  * You should have received a copy of the GNU General Public License
00015  * along with this program; if not, write to the Free Software
00016  * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
00017  * 02110-1301, USA.
00018  *
00019  * You can also choose to distribute this program under the terms of
00020  * the Unmodified Binary Distribution Licence (as given in the file
00021  * COPYING.UBDL), provided that you have satisfied its requirements.
00022  */
00023 
00024 FILE_LICENCE ( GPL2_OR_LATER_OR_UBDL );
00025 
00026 #include <stdint.h>
00027 #include <string.h>
00028 #include <unistd.h>
00029 #include <errno.h>
00030 #include <byteswap.h>
00031 #include <ipxe/netdevice.h>
00032 #include <ipxe/ethernet.h>
00033 #include <ipxe/if_ether.h>
00034 #include <ipxe/iobuf.h>
00035 #include <ipxe/malloc.h>
00036 #include <ipxe/pci.h>
00037 #include <ipxe/profile.h>
00038 #include "intel.h"
00039 
00040 /** @file
00041  *
00042  * Intel 10/100/1000 network card driver
00043  *
00044  */
00045 
00046 /** VM transmit profiler */
00047 static struct profiler intel_vm_tx_profiler __profiler =
00048         { .name = "intel.vm_tx" };
00049 
00050 /** VM receive refill profiler */
00051 static struct profiler intel_vm_refill_profiler __profiler =
00052         { .name = "intel.vm_refill" };
00053 
00054 /** VM poll profiler */
00055 static struct profiler intel_vm_poll_profiler __profiler =
00056         { .name = "intel.vm_poll" };
00057 
00058 /******************************************************************************
00059  *
00060  * EEPROM interface
00061  *
00062  ******************************************************************************
00063  */
00064 
00065 /**
00066  * Read data from EEPROM
00067  *
00068  * @v nvs               NVS device
00069  * @v address           Address from which to read
00070  * @v data              Data buffer
00071  * @v len               Length of data buffer
00072  * @ret rc              Return status code
00073  */
00074 static int intel_read_eeprom ( struct nvs_device *nvs, unsigned int address,
00075                                void *data, size_t len ) {
00076         struct intel_nic *intel =
00077                 container_of ( nvs, struct intel_nic, eeprom );
00078         unsigned int i;
00079         uint32_t value;
00080         uint16_t *data_word = data;
00081 
00082         /* Sanity check.  We advertise a blocksize of one word, so
00083          * should only ever receive single-word requests.
00084          */
00085         assert ( len == sizeof ( *data_word ) );
00086 
00087         /* Initiate read */
00088         writel ( ( INTEL_EERD_START | ( address << intel->eerd_addr_shift ) ),
00089                  intel->regs + INTEL_EERD );
00090 
00091         /* Wait for read to complete */
00092         for ( i = 0 ; i < INTEL_EEPROM_MAX_WAIT_MS ; i++ ) {
00093 
00094                 /* If read is not complete, delay 1ms and retry */
00095                 value = readl ( intel->regs + INTEL_EERD );
00096                 if ( ! ( value & intel->eerd_done ) ) {
00097                         mdelay ( 1 );
00098                         continue;
00099                 }
00100 
00101                 /* Extract data */
00102                 *data_word = cpu_to_le16 ( INTEL_EERD_DATA ( value ) );
00103                 return 0;
00104         }
00105 
00106         DBGC ( intel, "INTEL %p timed out waiting for EEPROM read\n", intel );
00107         return -ETIMEDOUT;
00108 }
00109 
00110 /**
00111  * Write data to EEPROM
00112  *
00113  * @v nvs               NVS device
00114  * @v address           Address to which to write
00115  * @v data              Data buffer
00116  * @v len               Length of data buffer
00117  * @ret rc              Return status code
00118  */
00119 static int intel_write_eeprom ( struct nvs_device *nvs,
00120                                 unsigned int address __unused,
00121                                 const void *data __unused,
00122                                 size_t len __unused ) {
00123         struct intel_nic *intel =
00124                 container_of ( nvs, struct intel_nic, eeprom );
00125 
00126         DBGC ( intel, "INTEL %p EEPROM write not supported\n", intel );
00127         return -ENOTSUP;
00128 }
00129 
00130 /**
00131  * Initialise EEPROM
00132  *
00133  * @v intel             Intel device
00134  * @ret rc              Return status code
00135  */
00136 static int intel_init_eeprom ( struct intel_nic *intel ) {
00137         unsigned int i;
00138         uint32_t value;
00139 
00140         /* The NIC automatically detects the type of attached EEPROM.
00141          * The EERD register provides access to only a single word at
00142          * a time, so we pretend to have a single-word block size.
00143          *
00144          * The EEPROM size may be larger than the minimum size, but
00145          * this doesn't matter to us since we access only the first
00146          * few words.
00147          */
00148         intel->eeprom.word_len_log2 = INTEL_EEPROM_WORD_LEN_LOG2;
00149         intel->eeprom.size = INTEL_EEPROM_MIN_SIZE_WORDS;
00150         intel->eeprom.block_size = 1;
00151         intel->eeprom.read = intel_read_eeprom;
00152         intel->eeprom.write = intel_write_eeprom;
00153 
00154         /* The layout of the EERD register was changed at some point
00155          * to accommodate larger EEPROMs.  Read from address zero (for
00156          * which the request layouts are compatible) to determine
00157          * which type of register we have.
00158          */
00159         writel ( INTEL_EERD_START, intel->regs + INTEL_EERD );
00160         for ( i = 0 ; i < INTEL_EEPROM_MAX_WAIT_MS ; i++ ) {
00161                 value = readl ( intel->regs + INTEL_EERD );
00162                 if ( value & INTEL_EERD_DONE_LARGE ) {
00163                         DBGC ( intel, "INTEL %p has large-format EERD\n",
00164                                intel );
00165                         intel->eerd_done = INTEL_EERD_DONE_LARGE;
00166                         intel->eerd_addr_shift = INTEL_EERD_ADDR_SHIFT_LARGE;
00167                         return 0;
00168                 }
00169                 if ( value & INTEL_EERD_DONE_SMALL ) {
00170                         DBGC ( intel, "INTEL %p has small-format EERD\n",
00171                                intel );
00172                         intel->eerd_done = INTEL_EERD_DONE_SMALL;
00173                         intel->eerd_addr_shift = INTEL_EERD_ADDR_SHIFT_SMALL;
00174                         return 0;
00175                 }
00176                 mdelay ( 1 );
00177         }
00178 
00179         DBGC ( intel, "INTEL %p timed out waiting for initial EEPROM read "
00180                "(value %08x)\n", intel, value );
00181         return -ETIMEDOUT;
00182 }
00183 
00184 /******************************************************************************
00185  *
00186  * MAC address
00187  *
00188  ******************************************************************************
00189  */
00190 
00191 /**
00192  * Fetch initial MAC address from EEPROM
00193  *
00194  * @v intel             Intel device
00195  * @v hw_addr           Hardware address to fill in
00196  * @ret rc              Return status code
00197  */
00198 static int intel_fetch_mac_eeprom ( struct intel_nic *intel,
00199                                     uint8_t *hw_addr ) {
00200         int rc;
00201 
00202         /* Initialise EEPROM */
00203         if ( ( rc = intel_init_eeprom ( intel ) ) != 0 )
00204                 return rc;
00205 
00206         /* Read base MAC address from EEPROM */
00207         if ( ( rc = nvs_read ( &intel->eeprom, INTEL_EEPROM_MAC,
00208                                hw_addr, ETH_ALEN ) ) != 0 ) {
00209                 DBGC ( intel, "INTEL %p could not read EEPROM base MAC "
00210                        "address: %s\n", intel, strerror ( rc ) );
00211                 return rc;
00212         }
00213 
00214         /* Adjust MAC address for multi-port devices */
00215         hw_addr[ETH_ALEN-1] ^= intel->port;
00216 
00217         DBGC ( intel, "INTEL %p has EEPROM MAC address %s (port %d)\n",
00218                intel, eth_ntoa ( hw_addr ), intel->port );
00219         return 0;
00220 }
00221 
00222 /**
00223  * Fetch initial MAC address
00224  *
00225  * @v intel             Intel device
00226  * @v hw_addr           Hardware address to fill in
00227  * @ret rc              Return status code
00228  */
00229 static int intel_fetch_mac ( struct intel_nic *intel, uint8_t *hw_addr ) {
00230         union intel_receive_address mac;
00231         int rc;
00232 
00233         /* Read current address from RAL0/RAH0 */
00234         mac.reg.low = cpu_to_le32 ( readl ( intel->regs + INTEL_RAL0 ) );
00235         mac.reg.high = cpu_to_le32 ( readl ( intel->regs + INTEL_RAH0 ) );
00236         DBGC ( intel, "INTEL %p has autoloaded MAC address %s\n",
00237                intel, eth_ntoa ( mac.raw ) );
00238 
00239         /* Use current address if valid */
00240         if ( is_valid_ether_addr ( mac.raw ) ) {
00241                 memcpy ( hw_addr, mac.raw, ETH_ALEN );
00242                 return 0;
00243         }
00244 
00245         /* Otherwise, try to read address from EEPROM */
00246         if ( ( rc = intel_fetch_mac_eeprom ( intel, hw_addr ) ) == 0 )
00247                 return 0;
00248 
00249         DBGC ( intel, "INTEL %p has no MAC address to use\n", intel );
00250         return -ENOENT;
00251 }
00252 
00253 /******************************************************************************
00254  *
00255  * Device reset
00256  *
00257  ******************************************************************************
00258  */
00259 
00260 /**
00261  * Reset hardware
00262  *
00263  * @v intel             Intel device
00264  * @ret rc              Return status code
00265  */
00266 static int intel_reset ( struct intel_nic *intel ) {
00267         uint32_t pbs;
00268         uint32_t pba;
00269         uint32_t ctrl;
00270         uint32_t status;
00271         uint32_t orig_ctrl;
00272         uint32_t orig_status;
00273 
00274         /* Record initial control and status register values */
00275         orig_ctrl = ctrl = readl ( intel->regs + INTEL_CTRL );
00276         orig_status = readl ( intel->regs + INTEL_STATUS );
00277 
00278         /* Force RX and TX packet buffer allocation, to work around an
00279          * errata in ICH devices.
00280          */
00281         if ( intel->flags & INTEL_PBS_ERRATA ) {
00282                 DBGC ( intel, "INTEL %p WARNING: applying ICH PBS/PBA errata\n",
00283                        intel );
00284                 pbs = readl ( intel->regs + INTEL_PBS );
00285                 pba = readl ( intel->regs + INTEL_PBA );
00286                 writel ( 0x08, intel->regs + INTEL_PBA );
00287                 writel ( 0x10, intel->regs + INTEL_PBS );
00288                 DBGC ( intel, "INTEL %p PBS %#08x->%#08x PBA %#08x->%#08x\n",
00289                        intel, pbs, readl ( intel->regs + INTEL_PBS ),
00290                        pba, readl ( intel->regs + INTEL_PBA ) );
00291         }
00292 
00293         /* Always reset MAC.  Required to reset the TX and RX rings. */
00294         writel ( ( ctrl | INTEL_CTRL_RST ), intel->regs + INTEL_CTRL );
00295         mdelay ( INTEL_RESET_DELAY_MS );
00296 
00297         /* Set a sensible default configuration */
00298         if ( ! ( intel->flags & INTEL_NO_ASDE ) )
00299                 ctrl |= INTEL_CTRL_ASDE;
00300         ctrl |= INTEL_CTRL_SLU;
00301         ctrl &= ~( INTEL_CTRL_LRST | INTEL_CTRL_FRCSPD | INTEL_CTRL_FRCDPLX );
00302         writel ( ctrl, intel->regs + INTEL_CTRL );
00303         mdelay ( INTEL_RESET_DELAY_MS );
00304 
00305         /* On some models (notably ICH), the PHY reset mechanism
00306          * appears to be broken.  In particular, the PHY_CTRL register
00307          * will be correctly loaded from NVM but the values will not
00308          * be propagated to the "OEM bits" PHY register.  This
00309          * typically has the effect of dropping the link speed to
00310          * 10Mbps.
00311          *
00312          * Work around this problem by skipping the PHY reset if
00313          * either (a) the link is already up, or (b) this particular
00314          * NIC is known to be broken.
00315          */
00316         status = readl ( intel->regs + INTEL_STATUS );
00317         if ( ( intel->flags & INTEL_NO_PHY_RST ) ||
00318              ( status & INTEL_STATUS_LU ) ) {
00319                 DBGC ( intel, "INTEL %p %sMAC reset (%08x/%08x was "
00320                        "%08x/%08x)\n", intel,
00321                        ( ( intel->flags & INTEL_NO_PHY_RST ) ? "forced " : "" ),
00322                        ctrl, status, orig_ctrl, orig_status );
00323                 return 0;
00324         }
00325 
00326         /* Reset PHY and MAC simultaneously */
00327         writel ( ( ctrl | INTEL_CTRL_RST | INTEL_CTRL_PHY_RST ),
00328                  intel->regs + INTEL_CTRL );
00329         mdelay ( INTEL_RESET_DELAY_MS );
00330 
00331         /* PHY reset is not self-clearing on all models */
00332         writel ( ctrl, intel->regs + INTEL_CTRL );
00333         mdelay ( INTEL_RESET_DELAY_MS );
00334         status = readl ( intel->regs + INTEL_STATUS );
00335 
00336         DBGC ( intel, "INTEL %p MAC+PHY reset (%08x/%08x was %08x/%08x)\n",
00337                intel, ctrl, status, orig_ctrl, orig_status );
00338         return 0;
00339 }
00340 
00341 /******************************************************************************
00342  *
00343  * Link state
00344  *
00345  ******************************************************************************
00346  */
00347 
00348 /**
00349  * Check link state
00350  *
00351  * @v netdev            Network device
00352  */
00353 static void intel_check_link ( struct net_device *netdev ) {
00354         struct intel_nic *intel = netdev->priv;
00355         uint32_t status;
00356 
00357         /* Read link status */
00358         status = readl ( intel->regs + INTEL_STATUS );
00359         DBGC ( intel, "INTEL %p link status is %08x\n", intel, status );
00360 
00361         /* Update network device */
00362         if ( status & INTEL_STATUS_LU ) {
00363                 netdev_link_up ( netdev );
00364         } else {
00365                 netdev_link_down ( netdev );
00366         }
00367 }
00368 
00369 /******************************************************************************
00370  *
00371  * Descriptors
00372  *
00373  ******************************************************************************
00374  */
00375 
00376 /**
00377  * Populate transmit descriptor
00378  *
00379  * @v tx                Transmit descriptor
00380  * @v addr              Data buffer address
00381  * @v len               Length of data
00382  */
00383 void intel_describe_tx ( struct intel_descriptor *tx, physaddr_t addr,
00384                          size_t len ) {
00385 
00386         /* Populate transmit descriptor */
00387         tx->address = cpu_to_le64 ( addr );
00388         tx->length = cpu_to_le16 ( len );
00389         tx->flags = 0;
00390         tx->command = ( INTEL_DESC_CMD_RS | INTEL_DESC_CMD_IFCS |
00391                         INTEL_DESC_CMD_EOP );
00392         tx->status = 0;
00393 }
00394 
00395 /**
00396  * Populate advanced transmit descriptor
00397  *
00398  * @v tx                Transmit descriptor
00399  * @v addr              Data buffer address
00400  * @v len               Length of data
00401  */
00402 void intel_describe_tx_adv ( struct intel_descriptor *tx, physaddr_t addr,
00403                              size_t len ) {
00404 
00405         /* Populate advanced transmit descriptor */
00406         tx->address = cpu_to_le64 ( addr );
00407         tx->length = cpu_to_le16 ( len );
00408         tx->flags = INTEL_DESC_FL_DTYP_DATA;
00409         tx->command = ( INTEL_DESC_CMD_DEXT | INTEL_DESC_CMD_RS |
00410                         INTEL_DESC_CMD_IFCS | INTEL_DESC_CMD_EOP );
00411         tx->status = cpu_to_le32 ( INTEL_DESC_STATUS_PAYLEN ( len ) );
00412 }
00413 
00414 /**
00415  * Populate receive descriptor
00416  *
00417  * @v rx                Receive descriptor
00418  * @v addr              Data buffer address
00419  * @v len               Length of data
00420  */
00421 void intel_describe_rx ( struct intel_descriptor *rx, physaddr_t addr,
00422                          size_t len __unused ) {
00423 
00424         /* Populate transmit descriptor */
00425         rx->address = cpu_to_le64 ( addr );
00426         rx->length = 0;
00427         rx->status = 0;
00428 }
00429 
00430 /******************************************************************************
00431  *
00432  * Network device interface
00433  *
00434  ******************************************************************************
00435  */
00436 
00437 /**
00438  * Disable descriptor ring
00439  *
00440  * @v intel             Intel device
00441  * @v reg               Register block
00442  * @ret rc              Return status code
00443  */
00444 static int intel_disable_ring ( struct intel_nic *intel, unsigned int reg ) {
00445         uint32_t dctl;
00446         unsigned int i;
00447 
00448         /* Disable ring */
00449         writel ( 0, ( intel->regs + reg + INTEL_xDCTL ) );
00450 
00451         /* Wait for disable to complete */
00452         for ( i = 0 ; i < INTEL_DISABLE_MAX_WAIT_MS ; i++ ) {
00453 
00454                 /* Check if ring is disabled */
00455                 dctl = readl ( intel->regs + reg + INTEL_xDCTL );
00456                 if ( ! ( dctl & INTEL_xDCTL_ENABLE ) )
00457                         return 0;
00458 
00459                 /* Delay */
00460                 mdelay ( 1 );
00461         }
00462 
00463         DBGC ( intel, "INTEL %p ring %05x timed out waiting for disable "
00464                "(dctl %08x)\n", intel, reg, dctl );
00465         return -ETIMEDOUT;
00466 }
00467 
00468 /**
00469  * Reset descriptor ring
00470  *
00471  * @v intel             Intel device
00472  * @v reg               Register block
00473  * @ret rc              Return status code
00474  */
00475 void intel_reset_ring ( struct intel_nic *intel, unsigned int reg ) {
00476 
00477         /* Disable ring.  Ignore errors and continue to reset the ring anyway */
00478         intel_disable_ring ( intel, reg );
00479 
00480         /* Clear ring length */
00481         writel ( 0, ( intel->regs + reg + INTEL_xDLEN ) );
00482 
00483         /* Clear ring address */
00484         writel ( 0, ( intel->regs + reg + INTEL_xDBAH ) );
00485         writel ( 0, ( intel->regs + reg + INTEL_xDBAL ) );
00486 
00487         /* Reset head and tail pointers */
00488         writel ( 0, ( intel->regs + reg + INTEL_xDH ) );
00489         writel ( 0, ( intel->regs + reg + INTEL_xDT ) );
00490 }
00491 
00492 /**
00493  * Create descriptor ring
00494  *
00495  * @v intel             Intel device
00496  * @v ring              Descriptor ring
00497  * @ret rc              Return status code
00498  */
00499 int intel_create_ring ( struct intel_nic *intel, struct intel_ring *ring ) {
00500         physaddr_t address;
00501         uint32_t dctl;
00502 
00503         /* Allocate descriptor ring.  Align ring on its own size to
00504          * prevent any possible page-crossing errors due to hardware
00505          * errata.
00506          */
00507         ring->desc = malloc_dma ( ring->len, ring->len );
00508         if ( ! ring->desc )
00509                 return -ENOMEM;
00510 
00511         /* Initialise descriptor ring */
00512         memset ( ring->desc, 0, ring->len );
00513 
00514         /* Program ring address */
00515         address = virt_to_bus ( ring->desc );
00516         writel ( ( address & 0xffffffffUL ),
00517                  ( intel->regs + ring->reg + INTEL_xDBAL ) );
00518         if ( sizeof ( physaddr_t ) > sizeof ( uint32_t ) ) {
00519                 writel ( ( ( ( uint64_t ) address ) >> 32 ),
00520                          ( intel->regs + ring->reg + INTEL_xDBAH ) );
00521         } else {
00522                 writel ( 0, intel->regs + ring->reg + INTEL_xDBAH );
00523         }
00524 
00525         /* Program ring length */
00526         writel ( ring->len, ( intel->regs + ring->reg + INTEL_xDLEN ) );
00527 
00528         /* Reset head and tail pointers */
00529         writel ( 0, ( intel->regs + ring->reg + INTEL_xDH ) );
00530         writel ( 0, ( intel->regs + ring->reg + INTEL_xDT ) );
00531 
00532         /* Enable ring */
00533         dctl = readl ( intel->regs + ring->reg + INTEL_xDCTL );
00534         dctl |= INTEL_xDCTL_ENABLE;
00535         writel ( dctl, intel->regs + ring->reg + INTEL_xDCTL );
00536 
00537         DBGC ( intel, "INTEL %p ring %05x is at [%08llx,%08llx)\n",
00538                intel, ring->reg, ( ( unsigned long long ) address ),
00539                ( ( unsigned long long ) address + ring->len ) );
00540 
00541         return 0;
00542 }
00543 
00544 /**
00545  * Destroy descriptor ring
00546  *
00547  * @v intel             Intel device
00548  * @v ring              Descriptor ring
00549  */
00550 void intel_destroy_ring ( struct intel_nic *intel, struct intel_ring *ring ) {
00551 
00552         /* Reset ring */
00553         intel_reset_ring ( intel, ring->reg );
00554 
00555         /* Free descriptor ring */
00556         free_dma ( ring->desc, ring->len );
00557         ring->desc = NULL;
00558         ring->prod = 0;
00559         ring->cons = 0;
00560 }
00561 
00562 /**
00563  * Refill receive descriptor ring
00564  *
00565  * @v intel             Intel device
00566  */
00567 void intel_refill_rx ( struct intel_nic *intel ) {
00568         struct intel_descriptor *rx;
00569         struct io_buffer *iobuf;
00570         unsigned int rx_idx;
00571         unsigned int rx_tail;
00572         physaddr_t address;
00573         unsigned int refilled = 0;
00574 
00575         /* Refill ring */
00576         while ( ( intel->rx.prod - intel->rx.cons ) < INTEL_RX_FILL ) {
00577 
00578                 /* Allocate I/O buffer */
00579                 iobuf = alloc_iob ( INTEL_RX_MAX_LEN );
00580                 if ( ! iobuf ) {
00581                         /* Wait for next refill */
00582                         break;
00583                 }
00584 
00585                 /* Get next receive descriptor */
00586                 rx_idx = ( intel->rx.prod++ % INTEL_NUM_RX_DESC );
00587                 rx = &intel->rx.desc[rx_idx];
00588 
00589                 /* Populate receive descriptor */
00590                 address = virt_to_bus ( iobuf->data );
00591                 intel->rx.describe ( rx, address, 0 );
00592 
00593                 /* Record I/O buffer */
00594                 assert ( intel->rx_iobuf[rx_idx] == NULL );
00595                 intel->rx_iobuf[rx_idx] = iobuf;
00596 
00597                 DBGC2 ( intel, "INTEL %p RX %d is [%llx,%llx)\n", intel, rx_idx,
00598                         ( ( unsigned long long ) address ),
00599                         ( ( unsigned long long ) address + INTEL_RX_MAX_LEN ) );
00600                 refilled++;
00601         }
00602 
00603         /* Push descriptors to card, if applicable */
00604         if ( refilled ) {
00605                 wmb();
00606                 rx_tail = ( intel->rx.prod % INTEL_NUM_RX_DESC );
00607                 profile_start ( &intel_vm_refill_profiler );
00608                 writel ( rx_tail, intel->regs + intel->rx.reg + INTEL_xDT );
00609                 profile_stop ( &intel_vm_refill_profiler );
00610                 profile_exclude ( &intel_vm_refill_profiler );
00611         }
00612 }
00613 
00614 /**
00615  * Discard unused receive I/O buffers
00616  *
00617  * @v intel             Intel device
00618  */
00619 void intel_empty_rx ( struct intel_nic *intel ) {
00620         unsigned int i;
00621 
00622         for ( i = 0 ; i < INTEL_NUM_RX_DESC ; i++ ) {
00623                 if ( intel->rx_iobuf[i] )
00624                         free_iob ( intel->rx_iobuf[i] );
00625                 intel->rx_iobuf[i] = NULL;
00626         }
00627 }
00628 
00629 /**
00630  * Open network device
00631  *
00632  * @v netdev            Network device
00633  * @ret rc              Return status code
00634  */
00635 static int intel_open ( struct net_device *netdev ) {
00636         struct intel_nic *intel = netdev->priv;
00637         union intel_receive_address mac;
00638         uint32_t fextnvm11;
00639         uint32_t tctl;
00640         uint32_t rctl;
00641         int rc;
00642 
00643         /* Set undocumented bit in FEXTNVM11 to work around an errata
00644          * in i219 devices that will otherwise cause a complete
00645          * datapath hang at the next device reset.
00646          */
00647         if ( intel->flags & INTEL_RST_HANG ) {
00648                 DBGC ( intel, "INTEL %p WARNING: applying reset hang "
00649                        "workaround\n", intel );
00650                 fextnvm11 = readl ( intel->regs + INTEL_FEXTNVM11 );
00651                 fextnvm11 |= INTEL_FEXTNVM11_WTF;
00652                 writel ( fextnvm11, intel->regs + INTEL_FEXTNVM11 );
00653         }
00654 
00655         /* Create transmit descriptor ring */
00656         if ( ( rc = intel_create_ring ( intel, &intel->tx ) ) != 0 )
00657                 goto err_create_tx;
00658 
00659         /* Create receive descriptor ring */
00660         if ( ( rc = intel_create_ring ( intel, &intel->rx ) ) != 0 )
00661                 goto err_create_rx;
00662 
00663         /* Program MAC address */
00664         memset ( &mac, 0, sizeof ( mac ) );
00665         memcpy ( mac.raw, netdev->ll_addr, sizeof ( mac.raw ) );
00666         writel ( le32_to_cpu ( mac.reg.low ), intel->regs + INTEL_RAL0 );
00667         writel ( ( le32_to_cpu ( mac.reg.high ) | INTEL_RAH0_AV ),
00668                  intel->regs + INTEL_RAH0 );
00669 
00670         /* Enable transmitter  */
00671         tctl = readl ( intel->regs + INTEL_TCTL );
00672         tctl &= ~( INTEL_TCTL_CT_MASK | INTEL_TCTL_COLD_MASK );
00673         tctl |= ( INTEL_TCTL_EN | INTEL_TCTL_PSP | INTEL_TCTL_CT_DEFAULT |
00674                   INTEL_TCTL_COLD_DEFAULT );
00675         writel ( tctl, intel->regs + INTEL_TCTL );
00676 
00677         /* Enable receiver */
00678         rctl = readl ( intel->regs + INTEL_RCTL );
00679         rctl &= ~( INTEL_RCTL_BSIZE_BSEX_MASK );
00680         rctl |= ( INTEL_RCTL_EN | INTEL_RCTL_UPE | INTEL_RCTL_MPE |
00681                   INTEL_RCTL_BAM | INTEL_RCTL_BSIZE_2048 | INTEL_RCTL_SECRC );
00682         writel ( rctl, intel->regs + INTEL_RCTL );
00683 
00684         /* Fill receive ring */
00685         intel_refill_rx ( intel );
00686 
00687         /* Update link state */
00688         intel_check_link ( netdev );
00689 
00690         /* Apply required errata */
00691         if ( intel->flags & INTEL_VMWARE ) {
00692                 DBGC ( intel, "INTEL %p applying VMware errata workaround\n",
00693                        intel );
00694                 intel->force_icr = INTEL_IRQ_RXT0;
00695         }
00696 
00697         return 0;
00698 
00699         intel_destroy_ring ( intel, &intel->rx );
00700  err_create_rx:
00701         intel_destroy_ring ( intel, &intel->tx );
00702  err_create_tx:
00703         return rc;
00704 }
00705 
00706 /**
00707  * Close network device
00708  *
00709  * @v netdev            Network device
00710  */
00711 static void intel_close ( struct net_device *netdev ) {
00712         struct intel_nic *intel = netdev->priv;
00713 
00714         /* Disable receiver */
00715         writel ( 0, intel->regs + INTEL_RCTL );
00716 
00717         /* Disable transmitter  */
00718         writel ( 0, intel->regs + INTEL_TCTL );
00719 
00720         /* Destroy receive descriptor ring */
00721         intel_destroy_ring ( intel, &intel->rx );
00722 
00723         /* Discard any unused receive buffers */
00724         intel_empty_rx ( intel );
00725 
00726         /* Destroy transmit descriptor ring */
00727         intel_destroy_ring ( intel, &intel->tx );
00728 
00729         /* Reset the NIC, to flush the transmit and receive FIFOs */
00730         intel_reset ( intel );
00731 }
00732 
00733 /**
00734  * Transmit packet
00735  *
00736  * @v netdev            Network device
00737  * @v iobuf             I/O buffer
00738  * @ret rc              Return status code
00739  */
00740 int intel_transmit ( struct net_device *netdev, struct io_buffer *iobuf ) {
00741         struct intel_nic *intel = netdev->priv;
00742         struct intel_descriptor *tx;
00743         unsigned int tx_idx;
00744         unsigned int tx_tail;
00745         physaddr_t address;
00746         size_t len;
00747 
00748         /* Get next transmit descriptor */
00749         if ( ( intel->tx.prod - intel->tx.cons ) >= INTEL_TX_FILL ) {
00750                 DBGC ( intel, "INTEL %p out of transmit descriptors\n", intel );
00751                 return -ENOBUFS;
00752         }
00753         tx_idx = ( intel->tx.prod++ % INTEL_NUM_TX_DESC );
00754         tx_tail = ( intel->tx.prod % INTEL_NUM_TX_DESC );
00755         tx = &intel->tx.desc[tx_idx];
00756 
00757         /* Populate transmit descriptor */
00758         address = virt_to_bus ( iobuf->data );
00759         len = iob_len ( iobuf );
00760         intel->tx.describe ( tx, address, len );
00761         wmb();
00762 
00763         /* Notify card that there are packets ready to transmit */
00764         profile_start ( &intel_vm_tx_profiler );
00765         writel ( tx_tail, intel->regs + intel->tx.reg + INTEL_xDT );
00766         profile_stop ( &intel_vm_tx_profiler );
00767         profile_exclude ( &intel_vm_tx_profiler );
00768 
00769         DBGC2 ( intel, "INTEL %p TX %d is [%llx,%llx)\n", intel, tx_idx,
00770                 ( ( unsigned long long ) address ),
00771                 ( ( unsigned long long ) address + len ) );
00772 
00773         return 0;
00774 }
00775 
00776 /**
00777  * Poll for completed packets
00778  *
00779  * @v netdev            Network device
00780  */
00781 void intel_poll_tx ( struct net_device *netdev ) {
00782         struct intel_nic *intel = netdev->priv;
00783         struct intel_descriptor *tx;
00784         unsigned int tx_idx;
00785 
00786         /* Check for completed packets */
00787         while ( intel->tx.cons != intel->tx.prod ) {
00788 
00789                 /* Get next transmit descriptor */
00790                 tx_idx = ( intel->tx.cons % INTEL_NUM_TX_DESC );
00791                 tx = &intel->tx.desc[tx_idx];
00792 
00793                 /* Stop if descriptor is still in use */
00794                 if ( ! ( tx->status & cpu_to_le32 ( INTEL_DESC_STATUS_DD ) ) )
00795                         return;
00796 
00797                 DBGC2 ( intel, "INTEL %p TX %d complete\n", intel, tx_idx );
00798 
00799                 /* Complete TX descriptor */
00800                 netdev_tx_complete_next ( netdev );
00801                 intel->tx.cons++;
00802         }
00803 }
00804 
00805 /**
00806  * Poll for received packets
00807  *
00808  * @v netdev            Network device
00809  */
00810 void intel_poll_rx ( struct net_device *netdev ) {
00811         struct intel_nic *intel = netdev->priv;
00812         struct intel_descriptor *rx;
00813         struct io_buffer *iobuf;
00814         unsigned int rx_idx;
00815         size_t len;
00816 
00817         /* Check for received packets */
00818         while ( intel->rx.cons != intel->rx.prod ) {
00819 
00820                 /* Get next receive descriptor */
00821                 rx_idx = ( intel->rx.cons % INTEL_NUM_RX_DESC );
00822                 rx = &intel->rx.desc[rx_idx];
00823 
00824                 /* Stop if descriptor is still in use */
00825                 if ( ! ( rx->status & cpu_to_le32 ( INTEL_DESC_STATUS_DD ) ) )
00826                         return;
00827 
00828                 /* Populate I/O buffer */
00829                 iobuf = intel->rx_iobuf[rx_idx];
00830                 intel->rx_iobuf[rx_idx] = NULL;
00831                 len = le16_to_cpu ( rx->length );
00832                 iob_put ( iobuf, len );
00833 
00834                 /* Hand off to network stack */
00835                 if ( rx->status & cpu_to_le32 ( INTEL_DESC_STATUS_RXE ) ) {
00836                         DBGC ( intel, "INTEL %p RX %d error (length %zd, "
00837                                "status %08x)\n", intel, rx_idx, len,
00838                                le32_to_cpu ( rx->status ) );
00839                         netdev_rx_err ( netdev, iobuf, -EIO );
00840                 } else {
00841                         DBGC2 ( intel, "INTEL %p RX %d complete (length %zd)\n",
00842                                 intel, rx_idx, len );
00843                         netdev_rx ( netdev, iobuf );
00844                 }
00845                 intel->rx.cons++;
00846         }
00847 }
00848 
00849 /**
00850  * Poll for completed and received packets
00851  *
00852  * @v netdev            Network device
00853  */
00854 static void intel_poll ( struct net_device *netdev ) {
00855         struct intel_nic *intel = netdev->priv;
00856         uint32_t icr;
00857 
00858         /* Check for and acknowledge interrupts */
00859         profile_start ( &intel_vm_poll_profiler );
00860         icr = readl ( intel->regs + INTEL_ICR );
00861         profile_stop ( &intel_vm_poll_profiler );
00862         profile_exclude ( &intel_vm_poll_profiler );
00863         icr |= intel->force_icr;
00864         if ( ! icr )
00865                 return;
00866 
00867         /* Poll for TX completions, if applicable */
00868         if ( icr & INTEL_IRQ_TXDW )
00869                 intel_poll_tx ( netdev );
00870 
00871         /* Poll for RX completions, if applicable */
00872         if ( icr & ( INTEL_IRQ_RXT0 | INTEL_IRQ_RXO ) )
00873                 intel_poll_rx ( netdev );
00874 
00875         /* Report receive overruns */
00876         if ( icr & INTEL_IRQ_RXO )
00877                 netdev_rx_err ( netdev, NULL, -ENOBUFS );
00878 
00879         /* Check link state, if applicable */
00880         if ( icr & INTEL_IRQ_LSC )
00881                 intel_check_link ( netdev );
00882 
00883         /* Check for unexpected interrupts */
00884         if ( icr & ~( INTEL_IRQ_TXDW | INTEL_IRQ_TXQE | INTEL_IRQ_LSC |
00885                       INTEL_IRQ_RXDMT0 | INTEL_IRQ_RXT0 | INTEL_IRQ_RXO ) ) {
00886                 DBGC ( intel, "INTEL %p unexpected ICR %08x\n", intel, icr );
00887                 /* Report as a TX error */
00888                 netdev_tx_err ( netdev, NULL, -ENOTSUP );
00889         }
00890 
00891         /* Refill RX ring */
00892         intel_refill_rx ( intel );
00893 }
00894 
00895 /**
00896  * Enable or disable interrupts
00897  *
00898  * @v netdev            Network device
00899  * @v enable            Interrupts should be enabled
00900  */
00901 static void intel_irq ( struct net_device *netdev, int enable ) {
00902         struct intel_nic *intel = netdev->priv;
00903         uint32_t mask;
00904 
00905         mask = ( INTEL_IRQ_TXDW | INTEL_IRQ_LSC | INTEL_IRQ_RXT0 );
00906         if ( enable ) {
00907                 writel ( mask, intel->regs + INTEL_IMS );
00908         } else {
00909                 writel ( mask, intel->regs + INTEL_IMC );
00910         }
00911 }
00912 
00913 /** Intel network device operations */
00914 static struct net_device_operations intel_operations = {
00915         .open           = intel_open,
00916         .close          = intel_close,
00917         .transmit       = intel_transmit,
00918         .poll           = intel_poll,
00919         .irq            = intel_irq,
00920 };
00921 
00922 /******************************************************************************
00923  *
00924  * PCI interface
00925  *
00926  ******************************************************************************
00927  */
00928 
00929 /**
00930  * Probe PCI device
00931  *
00932  * @v pci               PCI device
00933  * @ret rc              Return status code
00934  */
00935 static int intel_probe ( struct pci_device *pci ) {
00936         struct net_device *netdev;
00937         struct intel_nic *intel;
00938         int rc;
00939 
00940         /* Allocate and initialise net device */
00941         netdev = alloc_etherdev ( sizeof ( *intel ) );
00942         if ( ! netdev ) {
00943                 rc = -ENOMEM;
00944                 goto err_alloc;
00945         }
00946         netdev_init ( netdev, &intel_operations );
00947         intel = netdev->priv;
00948         pci_set_drvdata ( pci, netdev );
00949         netdev->dev = &pci->dev;
00950         memset ( intel, 0, sizeof ( *intel ) );
00951         intel->port = PCI_FUNC ( pci->busdevfn );
00952         intel->flags = pci->id->driver_data;
00953         intel_init_ring ( &intel->tx, INTEL_NUM_TX_DESC, INTEL_TD,
00954                           intel_describe_tx );
00955         intel_init_ring ( &intel->rx, INTEL_NUM_RX_DESC, INTEL_RD,
00956                           intel_describe_rx );
00957 
00958         /* Fix up PCI device */
00959         adjust_pci_device ( pci );
00960 
00961         /* Map registers */
00962         intel->regs = ioremap ( pci->membase, INTEL_BAR_SIZE );
00963         if ( ! intel->regs ) {
00964                 rc = -ENODEV;
00965                 goto err_ioremap;
00966         }
00967 
00968         /* Reset the NIC */
00969         if ( ( rc = intel_reset ( intel ) ) != 0 )
00970                 goto err_reset;
00971 
00972         /* Fetch MAC address */
00973         if ( ( rc = intel_fetch_mac ( intel, netdev->hw_addr ) ) != 0 )
00974                 goto err_fetch_mac;
00975 
00976         /* Register network device */
00977         if ( ( rc = register_netdev ( netdev ) ) != 0 )
00978                 goto err_register_netdev;
00979 
00980         /* Set initial link state */
00981         intel_check_link ( netdev );
00982 
00983         return 0;
00984 
00985         unregister_netdev ( netdev );
00986  err_register_netdev:
00987  err_fetch_mac:
00988         intel_reset ( intel );
00989  err_reset:
00990         iounmap ( intel->regs );
00991  err_ioremap:
00992         netdev_nullify ( netdev );
00993         netdev_put ( netdev );
00994  err_alloc:
00995         return rc;
00996 }
00997 
00998 /**
00999  * Remove PCI device
01000  *
01001  * @v pci               PCI device
01002  */
01003 static void intel_remove ( struct pci_device *pci ) {
01004         struct net_device *netdev = pci_get_drvdata ( pci );
01005         struct intel_nic *intel = netdev->priv;
01006 
01007         /* Unregister network device */
01008         unregister_netdev ( netdev );
01009 
01010         /* Reset the NIC */
01011         intel_reset ( intel );
01012 
01013         /* Free network device */
01014         iounmap ( intel->regs );
01015         netdev_nullify ( netdev );
01016         netdev_put ( netdev );
01017 }
01018 
01019 /** Intel PCI device IDs */
01020 static struct pci_device_id intel_nics[] = {
01021         PCI_ROM ( 0x8086, 0x0438, "dh8900cc", "DH8900CC", 0 ),
01022         PCI_ROM ( 0x8086, 0x043a, "dh8900cc-f", "DH8900CC Fiber", 0 ),
01023         PCI_ROM ( 0x8086, 0x043c, "dh8900cc-b", "DH8900CC Backplane", 0 ),
01024         PCI_ROM ( 0x8086, 0x0440, "dh8900cc-s", "DH8900CC SFP", 0 ),
01025         PCI_ROM ( 0x8086, 0x1000, "82542-f", "82542 (Fiber)", 0 ),
01026         PCI_ROM ( 0x8086, 0x1001, "82543gc-f", "82543GC (Fiber)", 0 ),
01027         PCI_ROM ( 0x8086, 0x1004, "82543gc", "82543GC (Copper)", 0 ),
01028         PCI_ROM ( 0x8086, 0x1008, "82544ei", "82544EI (Copper)", 0 ),
01029         PCI_ROM ( 0x8086, 0x1009, "82544ei-f", "82544EI (Fiber)", 0 ),
01030         PCI_ROM ( 0x8086, 0x100c, "82544gc", "82544GC (Copper)", 0 ),
01031         PCI_ROM ( 0x8086, 0x100d, "82544gc-l", "82544GC (LOM)", 0 ),
01032         PCI_ROM ( 0x8086, 0x100e, "82540em", "82540EM", 0 ),
01033         PCI_ROM ( 0x8086, 0x100f, "82545em", "82545EM (Copper)", INTEL_VMWARE ),
01034         PCI_ROM ( 0x8086, 0x1010, "82546eb", "82546EB (Copper)", 0 ),
01035         PCI_ROM ( 0x8086, 0x1011, "82545em-f", "82545EM (Fiber)", 0 ),
01036         PCI_ROM ( 0x8086, 0x1012, "82546eb-f", "82546EB (Fiber)", 0 ),
01037         PCI_ROM ( 0x8086, 0x1013, "82541ei", "82541EI", 0 ),
01038         PCI_ROM ( 0x8086, 0x1014, "82541er", "82541ER", 0 ),
01039         PCI_ROM ( 0x8086, 0x1015, "82540em-l", "82540EM (LOM)", 0 ),
01040         PCI_ROM ( 0x8086, 0x1016, "82540ep-m", "82540EP (Mobile)", 0 ),
01041         PCI_ROM ( 0x8086, 0x1017, "82540ep", "82540EP", 0 ),
01042         PCI_ROM ( 0x8086, 0x1018, "82541ei", "82541EI", 0 ),
01043         PCI_ROM ( 0x8086, 0x1019, "82547ei", "82547EI", 0 ),
01044         PCI_ROM ( 0x8086, 0x101a, "82547ei-m", "82547EI (Mobile)", 0 ),
01045         PCI_ROM ( 0x8086, 0x101d, "82546eb", "82546EB", 0 ),
01046         PCI_ROM ( 0x8086, 0x101e, "82540ep-m", "82540EP (Mobile)", 0 ),
01047         PCI_ROM ( 0x8086, 0x1026, "82545gm", "82545GM", 0 ),
01048         PCI_ROM ( 0x8086, 0x1027, "82545gm-1", "82545GM", 0 ),
01049         PCI_ROM ( 0x8086, 0x1028, "82545gm-2", "82545GM", 0 ),
01050         PCI_ROM ( 0x8086, 0x1049, "82566mm", "82566MM", INTEL_PBS_ERRATA ),
01051         PCI_ROM ( 0x8086, 0x104a, "82566dm", "82566DM", INTEL_PBS_ERRATA ),
01052         PCI_ROM ( 0x8086, 0x104b, "82566dc", "82566DC", INTEL_PBS_ERRATA ),
01053         PCI_ROM ( 0x8086, 0x104c, "82562v", "82562V", INTEL_PBS_ERRATA ),
01054         PCI_ROM ( 0x8086, 0x104d, "82566mc", "82566MC", INTEL_PBS_ERRATA ),
01055         PCI_ROM ( 0x8086, 0x105e, "82571eb", "82571EB", 0 ),
01056         PCI_ROM ( 0x8086, 0x105f, "82571eb-1", "82571EB", 0 ),
01057         PCI_ROM ( 0x8086, 0x1060, "82571eb-2", "82571EB", 0 ),
01058         PCI_ROM ( 0x8086, 0x1075, "82547gi", "82547GI", 0 ),
01059         PCI_ROM ( 0x8086, 0x1076, "82541gi", "82541GI", 0 ),
01060         PCI_ROM ( 0x8086, 0x1077, "82541gi-1", "82541GI", 0 ),
01061         PCI_ROM ( 0x8086, 0x1078, "82541er", "82541ER", 0 ),
01062         PCI_ROM ( 0x8086, 0x1079, "82546gb", "82546GB", 0 ),
01063         PCI_ROM ( 0x8086, 0x107a, "82546gb-1", "82546GB", 0 ),
01064         PCI_ROM ( 0x8086, 0x107b, "82546gb-2", "82546GB", 0 ),
01065         PCI_ROM ( 0x8086, 0x107c, "82541pi", "82541PI", 0 ),
01066         PCI_ROM ( 0x8086, 0x107d, "82572ei", "82572EI (Copper)", 0 ),
01067         PCI_ROM ( 0x8086, 0x107e, "82572ei-f", "82572EI (Fiber)", 0 ),
01068         PCI_ROM ( 0x8086, 0x107f, "82572ei", "82572EI", 0 ),
01069         PCI_ROM ( 0x8086, 0x108a, "82546gb-3", "82546GB", 0 ),
01070         PCI_ROM ( 0x8086, 0x108b, "82573v", "82573V (Copper)", 0 ),
01071         PCI_ROM ( 0x8086, 0x108c, "82573e", "82573E (Copper)", 0 ),
01072         PCI_ROM ( 0x8086, 0x1096, "80003es2lan", "80003ES2LAN (Copper)", 0 ),
01073         PCI_ROM ( 0x8086, 0x1098, "80003es2lan-s", "80003ES2LAN (Serdes)", 0 ),
01074         PCI_ROM ( 0x8086, 0x1099, "82546gb-4", "82546GB (Copper)", 0 ),
01075         PCI_ROM ( 0x8086, 0x109a, "82573l", "82573L", 0 ),
01076         PCI_ROM ( 0x8086, 0x10a4, "82571eb", "82571EB", 0 ),
01077         PCI_ROM ( 0x8086, 0x10a5, "82571eb", "82571EB (Fiber)", 0 ),
01078         PCI_ROM ( 0x8086, 0x10a7, "82575eb", "82575EB", 0 ),
01079         PCI_ROM ( 0x8086, 0x10a9, "82575eb", "82575EB Backplane", 0 ),
01080         PCI_ROM ( 0x8086, 0x10b5, "82546gb", "82546GB (Copper)", 0 ),
01081         PCI_ROM ( 0x8086, 0x10b9, "82572ei", "82572EI (Copper)", 0 ),
01082         PCI_ROM ( 0x8086, 0x10ba, "80003es2lan", "80003ES2LAN (Copper)", 0 ),
01083         PCI_ROM ( 0x8086, 0x10bb, "80003es2lan", "80003ES2LAN (Serdes)", 0 ),
01084         PCI_ROM ( 0x8086, 0x10bc, "82571eb", "82571EB (Copper)", 0 ),
01085         PCI_ROM ( 0x8086, 0x10bd, "82566dm-2", "82566DM-2", 0 ),
01086         PCI_ROM ( 0x8086, 0x10bf, "82567lf", "82567LF", 0 ),
01087         PCI_ROM ( 0x8086, 0x10c0, "82562v-2", "82562V-2", 0 ),
01088         PCI_ROM ( 0x8086, 0x10c2, "82562g-2", "82562G-2", 0 ),
01089         PCI_ROM ( 0x8086, 0x10c3, "82562gt-2", "82562GT-2", 0 ),
01090         PCI_ROM ( 0x8086, 0x10c4, "82562gt", "82562GT", INTEL_PBS_ERRATA ),
01091         PCI_ROM ( 0x8086, 0x10c5, "82562g", "82562G", INTEL_PBS_ERRATA ),
01092         PCI_ROM ( 0x8086, 0x10c9, "82576", "82576", 0 ),
01093         PCI_ROM ( 0x8086, 0x10cb, "82567v", "82567V", 0 ),
01094         PCI_ROM ( 0x8086, 0x10cc, "82567lm-2", "82567LM-2", 0 ),
01095         PCI_ROM ( 0x8086, 0x10cd, "82567lf-2", "82567LF-2", 0 ),
01096         PCI_ROM ( 0x8086, 0x10ce, "82567v-2", "82567V-2", 0 ),
01097         PCI_ROM ( 0x8086, 0x10d3, "82574l", "82574L", 0 ),
01098         PCI_ROM ( 0x8086, 0x10d5, "82571pt", "82571PT PT Quad", 0 ),
01099         PCI_ROM ( 0x8086, 0x10d6, "82575gb", "82575GB", 0 ),
01100         PCI_ROM ( 0x8086, 0x10d9, "82571eb-d", "82571EB Dual Mezzanine", 0 ),
01101         PCI_ROM ( 0x8086, 0x10da, "82571eb-q", "82571EB Quad Mezzanine", 0 ),
01102         PCI_ROM ( 0x8086, 0x10de, "82567lm-3", "82567LM-3", 0 ),
01103         PCI_ROM ( 0x8086, 0x10df, "82567lf-3", "82567LF-3", 0 ),
01104         PCI_ROM ( 0x8086, 0x10e5, "82567lm-4", "82567LM-4", 0 ),
01105         PCI_ROM ( 0x8086, 0x10e6, "82576", "82576", 0 ),
01106         PCI_ROM ( 0x8086, 0x10e7, "82576-2", "82576", 0 ),
01107         PCI_ROM ( 0x8086, 0x10e8, "82576-3", "82576", 0 ),
01108         PCI_ROM ( 0x8086, 0x10ea, "82577lm", "82577LM", 0 ),
01109         PCI_ROM ( 0x8086, 0x10eb, "82577lc", "82577LC", 0 ),
01110         PCI_ROM ( 0x8086, 0x10ef, "82578dm", "82578DM", 0 ),
01111         PCI_ROM ( 0x8086, 0x10f0, "82578dc", "82578DC", 0 ),
01112         PCI_ROM ( 0x8086, 0x10f5, "82567lm", "82567LM", 0 ),
01113         PCI_ROM ( 0x8086, 0x10f6, "82574l", "82574L", 0 ),
01114         PCI_ROM ( 0x8086, 0x1501, "82567v-3", "82567V-3", INTEL_PBS_ERRATA ),
01115         PCI_ROM ( 0x8086, 0x1502, "82579lm", "82579LM", INTEL_NO_PHY_RST ),
01116         PCI_ROM ( 0x8086, 0x1503, "82579v", "82579V", 0 ),
01117         PCI_ROM ( 0x8086, 0x150a, "82576ns", "82576NS", 0 ),
01118         PCI_ROM ( 0x8086, 0x150c, "82583v", "82583V", 0 ),
01119         PCI_ROM ( 0x8086, 0x150d, "82576-4", "82576 Backplane", 0 ),
01120         PCI_ROM ( 0x8086, 0x150e, "82580", "82580", 0 ),
01121         PCI_ROM ( 0x8086, 0x150f, "82580-f", "82580 Fiber", 0 ),
01122         PCI_ROM ( 0x8086, 0x1510, "82580-b", "82580 Backplane", 0 ),
01123         PCI_ROM ( 0x8086, 0x1511, "82580-s", "82580 SFP", 0 ),
01124         PCI_ROM ( 0x8086, 0x1516, "82580-2", "82580", 0 ),
01125         PCI_ROM ( 0x8086, 0x1518, "82576ns", "82576NS SerDes", 0 ),
01126         PCI_ROM ( 0x8086, 0x1521, "i350", "I350", 0 ),
01127         PCI_ROM ( 0x8086, 0x1522, "i350-f", "I350 Fiber", 0 ),
01128         PCI_ROM ( 0x8086, 0x1523, "i350-b", "I350 Backplane", INTEL_NO_ASDE ),
01129         PCI_ROM ( 0x8086, 0x1524, "i350-2", "I350", 0 ),
01130         PCI_ROM ( 0x8086, 0x1525, "82567v-4", "82567V-4", 0 ),
01131         PCI_ROM ( 0x8086, 0x1526, "82576-5", "82576", 0 ),
01132         PCI_ROM ( 0x8086, 0x1527, "82580-f2", "82580 Fiber", 0 ),
01133         PCI_ROM ( 0x8086, 0x1533, "i210", "I210", 0 ),
01134         PCI_ROM ( 0x8086, 0x1539, "i211", "I211", 0 ),
01135         PCI_ROM ( 0x8086, 0x153a, "i217lm", "I217-LM", INTEL_NO_PHY_RST ),
01136         PCI_ROM ( 0x8086, 0x153b, "i217v", "I217-V", 0 ),
01137         PCI_ROM ( 0x8086, 0x1559, "i218v", "I218-V", 0),
01138         PCI_ROM ( 0x8086, 0x155a, "i218lm", "I218-LM", 0),
01139         PCI_ROM ( 0x8086, 0x156f, "i219lm", "I219-LM", INTEL_I219 ),
01140         PCI_ROM ( 0x8086, 0x1570, "i219v", "I219-V", INTEL_I219 ),
01141         PCI_ROM ( 0x8086, 0x157b, "i210-2", "I210", 0 ),
01142         PCI_ROM ( 0x8086, 0x15a0, "i218lm-2", "I218-LM", INTEL_NO_PHY_RST ),
01143         PCI_ROM ( 0x8086, 0x15a1, "i218v-2", "I218-V", 0 ),
01144         PCI_ROM ( 0x8086, 0x15a2, "i218lm-3", "I218-LM", INTEL_NO_PHY_RST ),
01145         PCI_ROM ( 0x8086, 0x15a3, "i218v-3", "I218-V", INTEL_NO_PHY_RST ),
01146         PCI_ROM ( 0x8086, 0x15b7, "i219lm-2", "I219-LM (2)", INTEL_I219 ),
01147         PCI_ROM ( 0x8086, 0x15b8, "i219v-2", "I219-V (2)", INTEL_I219 ),
01148         PCI_ROM ( 0x8086, 0x15b9, "i219lm-3", "I219-LM (3)", INTEL_I219 ),
01149         PCI_ROM ( 0x8086, 0x15d6, "i219v-5", "I219-V (5)", INTEL_I219 ),
01150         PCI_ROM ( 0x8086, 0x15d7, "i219lm-4", "I219-LM (4)", INTEL_I219 ),
01151         PCI_ROM ( 0x8086, 0x15d8, "i219v-4", "I219-V (4)", INTEL_I219 ),
01152         PCI_ROM ( 0x8086, 0x15e3, "i219lm-5", "I219-LM (5)", INTEL_I219 ),
01153         PCI_ROM ( 0x8086, 0x1f41, "i354", "I354", INTEL_NO_ASDE ),
01154         PCI_ROM ( 0x8086, 0x294c, "82566dc-2", "82566DC-2", 0 ),
01155         PCI_ROM ( 0x8086, 0x2e6e, "cemedia", "CE Media Processor", 0 ),
01156 };
01157 
01158 /** Intel PCI driver */
01159 struct pci_driver intel_driver __pci_driver = {
01160         .ids = intel_nics,
01161         .id_count = ( sizeof ( intel_nics ) / sizeof ( intel_nics[0] ) ),
01162         .probe = intel_probe,
01163         .remove = intel_remove,
01164 };