iPXE
forcedeth.h
Go to the documentation of this file.
1 /*
2  * forcedeth.h -- Driver for NVIDIA nForce media access controllers for iPXE
3  * Copyright (c) 2010 Andrei Faur <da3drus@gmail.com>
4  *
5  * This program is free software; you can redistribute it and/or
6  * modify it under the terms of the GNU General Public License as
7  * published by the Free Software Foundation; either version 2 of the
8  * License, or any later version.
9  *
10  * This program is distributed in the hope that it will be useful, but
11  * WITHOUT ANY WARRANTY; without even the implied warranty of
12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
13  * General Public License for more details.
14  *
15  * You should have received a copy of the GNU General Public License
16  * along with this program; if not, write to the Free Software
17  * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
18  * 02110-1301, USA.
19  *
20  * Portions of this code are taken from the Linux forcedeth driver that was
21  * based on a cleanroom reimplementation which was based on reverse engineered
22  * documentation written by Carl-Daniel Hailfinger and Andrew de Quincey:
23  * Copyright (C) 2003,4,5 Manfred Spraul
24  * Copyright (C) 2004 Andrew de Quincey (wol support)
25  * Copyright (C) 2004 Carl-Daniel Hailfinger (invalid MAC handling, insane
26  * IRQ rate fixes, bigendian fixes, cleanups, verification)
27  * Copyright (c) 2004,2005,2006,2007,2008,2009 NVIDIA Corporation
28  *
29  * This header is a direct copy of #define lines and structs found in the
30  * above mentioned driver, modified where necessary to make them work for iPXE.
31  *
32  */
33 
34 FILE_LICENCE ( GPL2_OR_LATER );
35 
36 #ifndef _FORCEDETH_H_
37 #define _FORCEDETH_H_
38 
39 struct ring_desc {
42 };
43 
44 struct ring_desc_ex {
49 };
50 
51 #define DESC_VER_1 1
52 #define DESC_VER_2 2
53 #define DESC_VER_3 3
54 
55 #define RX_RING_SIZE 16
56 #define TX_RING_SIZE 32
57 #define RXTX_RING_SIZE ( ( RX_RING_SIZE ) + ( TX_RING_SIZE ) )
58 #define RX_RING_MIN 128
59 #define TX_RING_MIN 64
60 #define RING_MAX_DESC_VER_1 1024
61 #define RING_MAX_DESC_VER_2_3 16384
62 
63 #define NV_RX_ALLOC_PAD (64)
64 
65 #define NV_RX_HEADERS (64)
66 
67 #define RX_BUF_SZ ( ( ETH_FRAME_LEN ) + ( NV_RX_HEADERS ) )
68 
69 #define NV_PKTLIMIT_1 1500
70 #define NV_PKTLIMIT_2 9100
71 
72 #define NV_LINK_POLL_FREQUENCY 128
73 
74 /* PHY defines */
75 #define PHY_OUI_MARVELL 0x5043
76 #define PHY_OUI_CICADA 0x03f1
77 #define PHY_OUI_VITESSE 0x01c1
78 #define PHY_OUI_REALTEK 0x0732
79 #define PHY_OUI_REALTEK2 0x0020
80 #define PHYID1_OUI_MASK 0x03ff
81 #define PHYID1_OUI_SHFT 6
82 #define PHYID2_OUI_MASK 0xfc00
83 #define PHYID2_OUI_SHFT 10
84 #define PHYID2_MODEL_MASK 0x03f0
85 #define PHY_MODEL_REALTEK_8211 0x0110
86 #define PHY_REV_MASK 0x0001
87 #define PHY_REV_REALTEK_8211B 0x0000
88 #define PHY_REV_REALTEK_8211C 0x0001
89 #define PHY_MODEL_REALTEK_8201 0x0200
90 #define PHY_MODEL_MARVELL_E3016 0x0220
91 #define PHY_MARVELL_E3016_INITMASK 0x0300
92 #define PHY_CICADA_INIT1 0x0f000
93 #define PHY_CICADA_INIT2 0x0e00
94 #define PHY_CICADA_INIT3 0x01000
95 #define PHY_CICADA_INIT4 0x0200
96 #define PHY_CICADA_INIT5 0x0004
97 #define PHY_CICADA_INIT6 0x02000
98 #define PHY_VITESSE_INIT_REG1 0x1f
99 #define PHY_VITESSE_INIT_REG2 0x10
100 #define PHY_VITESSE_INIT_REG3 0x11
101 #define PHY_VITESSE_INIT_REG4 0x12
102 #define PHY_VITESSE_INIT_MSK1 0xc
103 #define PHY_VITESSE_INIT_MSK2 0x0180
104 #define PHY_VITESSE_INIT1 0x52b5
105 #define PHY_VITESSE_INIT2 0xaf8a
106 #define PHY_VITESSE_INIT3 0x8
107 #define PHY_VITESSE_INIT4 0x8f8a
108 #define PHY_VITESSE_INIT5 0xaf86
109 #define PHY_VITESSE_INIT6 0x8f86
110 #define PHY_VITESSE_INIT7 0xaf82
111 #define PHY_VITESSE_INIT8 0x0100
112 #define PHY_VITESSE_INIT9 0x8f82
113 #define PHY_VITESSE_INIT10 0x0
114 #define PHY_REALTEK_INIT_REG1 0x1f
115 #define PHY_REALTEK_INIT_REG2 0x19
116 #define PHY_REALTEK_INIT_REG3 0x13
117 #define PHY_REALTEK_INIT_REG4 0x14
118 #define PHY_REALTEK_INIT_REG5 0x18
119 #define PHY_REALTEK_INIT_REG6 0x11
120 #define PHY_REALTEK_INIT_REG7 0x01
121 #define PHY_REALTEK_INIT1 0x0000
122 #define PHY_REALTEK_INIT2 0x8e00
123 #define PHY_REALTEK_INIT3 0x0001
124 #define PHY_REALTEK_INIT4 0xad17
125 #define PHY_REALTEK_INIT5 0xfb54
126 #define PHY_REALTEK_INIT6 0xf5c7
127 #define PHY_REALTEK_INIT7 0x1000
128 #define PHY_REALTEK_INIT8 0x0003
129 #define PHY_REALTEK_INIT9 0x0008
130 #define PHY_REALTEK_INIT10 0x0005
131 #define PHY_REALTEK_INIT11 0x0200
132 #define PHY_REALTEK_INIT_MSK1 0x0003
133 
134 #define PHY_GIGABIT 0x0100
135 
136 #define PHY_TIMEOUT 0x1
137 #define PHY_ERROR 0x2
138 
139 #define PHY_100 0x1
140 #define PHY_1000 0x2
141 #define PHY_HALF 0x100
142 
143 
144 #define NV_PAUSEFRAME_RX_CAPABLE 0x0001
145 #define NV_PAUSEFRAME_TX_CAPABLE 0x0002
146 #define NV_PAUSEFRAME_RX_ENABLE 0x0004
147 #define NV_PAUSEFRAME_TX_ENABLE 0x0008
148 #define NV_PAUSEFRAME_RX_REQ 0x0010
149 #define NV_PAUSEFRAME_TX_REQ 0x0020
150 #define NV_PAUSEFRAME_AUTONEG 0x0040
151 
152 /* MSI/MSI-X defines */
153 #define NV_MSI_X_MAX_VECTORS 8
154 #define NV_MSI_X_VECTORS_MASK 0x000f
155 #define NV_MSI_CAPABLE 0x0010
156 #define NV_MSI_X_CAPABLE 0x0020
157 #define NV_MSI_ENABLED 0x0040
158 #define NV_MSI_X_ENABLED 0x0080
159 
160 #define NV_MSI_X_VECTOR_ALL 0x0
161 #define NV_MSI_X_VECTOR_RX 0x0
162 #define NV_MSI_X_VECTOR_TX 0x1
163 #define NV_MSI_X_VECTOR_OTHER 0x2
164 
165 #define NV_MSI_PRIV_OFFSET 0x68
166 #define NV_MSI_PRIV_VALUE 0xffffffff
167 
168 
169 #define NV_MIIBUSY_DELAY 50
170 #define NV_MIIPHY_DELAY 10
171 #define NV_MIIPHY_DELAYMAX 10000
172 
173 /* Hardware access */
174 #define DEV_NEED_TIMERIRQ 0x0000001 /* set the timer irq flag in the irq mask */
175 #define DEV_NEED_LINKTIMER 0x0000002 /* poll link settings. Relies on the timer irq */
176 #define DEV_HAS_LARGEDESC 0x0000004 /* device supports jumbo frames and needs packet format 2 */
177 #define DEV_HAS_HIGH_DMA 0x0000008 /* device supports 64bit dma */
178 #define DEV_HAS_CHECKSUM 0x0000010 /* device supports tx and rx checksum offloads */
179 #define DEV_HAS_VLAN 0x0000020 /* device supports vlan tagging and striping */
180 #define DEV_HAS_MSI 0x0000040 /* device supports MSI */
181 #define DEV_HAS_MSI_X 0x0000080 /* device supports MSI-X */
182 #define DEV_HAS_POWER_CNTRL 0x0000100 /* device supports power savings */
183 #define DEV_HAS_STATISTICS_V1 0x0000200 /* device supports hw statistics version 1 */
184 #define DEV_HAS_STATISTICS_V2 0x0000600 /* device supports hw statistics version 2 */
185 #define DEV_HAS_STATISTICS_V3 0x0000e00 /* device supports hw statistics version 3 */
186 #define DEV_HAS_TEST_EXTENDED 0x0001000 /* device supports extended diagnostic test */
187 #define DEV_HAS_MGMT_UNIT 0x0002000 /* device supports management unit */
188 #define DEV_HAS_CORRECT_MACADDR 0x0004000 /* device supports correct mac address order */
189 #define DEV_HAS_COLLISION_FIX 0x0008000 /* device supports tx collision fix */
190 #define DEV_HAS_PAUSEFRAME_TX_V1 0x0010000 /* device supports tx pause frames version 1 */
191 #define DEV_HAS_PAUSEFRAME_TX_V2 0x0020000 /* device supports tx pause frames version 2 */
192 #define DEV_HAS_PAUSEFRAME_TX_V3 0x0040000 /* device supports tx pause frames version 3 */
193 #define DEV_NEED_TX_LIMIT 0x0080000 /* device needs to limit tx */
194 #define DEV_NEED_TX_LIMIT2 0x0180000 /* device needs to limit tx, expect for some revs */
195 #define DEV_HAS_GEAR_MODE 0x0200000 /* device supports gear mode */
196 #define DEV_NEED_PHY_INIT_FIX 0x0400000 /* device needs specific phy workaround */
197 #define DEV_NEED_LOW_POWER_FIX 0x0800000 /* device needs special power up workaround */
198 #define DEV_NEED_MSI_FIX 0x1000000 /* device needs msi workaround */
199 
200 #define FLAG_MASK_V1 0xffff0000
201 #define FLAG_MASK_V2 0xffffc000
202 #define LEN_MASK_V1 (0xffffffff ^ FLAG_MASK_V1)
203 #define LEN_MASK_V2 (0xffffffff ^ FLAG_MASK_V2)
204 
205 #define NV_TX_LASTPACKET (1<<16)
206 #define NV_TX_RETRYERROR (1<<19)
207 #define NV_TX_RETRYCOUNT_MASK (0xF<<20)
208 #define NV_TX_FORCED_INTERRUPT (1<<24)
209 #define NV_TX_DEFERRED (1<<26)
210 #define NV_TX_CARRIERLOST (1<<27)
211 #define NV_TX_LATECOLLISION (1<<28)
212 #define NV_TX_UNDERFLOW (1<<29)
213 #define NV_TX_ERROR (1<<30)
214 #define NV_TX_VALID (1<<31)
215 
216 #define NV_TX2_LASTPACKET (1<<29)
217 #define NV_TX2_RETRYERROR (1<<18)
218 #define NV_TX2_RETRYCOUNT_MASK (0xF<<19)
219 #define NV_TX2_FORCED_INTERRUPT (1<<30)
220 #define NV_TX2_DEFERRED (1<<25)
221 #define NV_TX2_CARRIERLOST (1<<26)
222 #define NV_TX2_LATECOLLISION (1<<27)
223 #define NV_TX2_UNDERFLOW (1<<28)
224 /* error and valid are the same for both */
225 #define NV_TX2_ERROR (1<<30)
226 #define NV_TX2_VALID (1<<31)
227 #define NV_TX2_TSO (1<<28)
228 #define NV_TX2_TSO_SHIFT 14
229 #define NV_TX2_TSO_MAX_SHIFT 14
230 #define NV_TX2_TSO_MAX_SIZE (1<<NV_TX2_TSO_MAX_SHIFT)
231 #define NV_TX2_CHECKSUM_L3 (1<<27)
232 #define NV_TX2_CHECKSUM_L4 (1<<26)
233 
234 #define NV_TX3_VLAN_TAG_PRESENT (1<<18)
235 
236 #define NV_RX_DESCRIPTORVALID (1<<16)
237 #define NV_RX_MISSEDFRAME (1<<17)
238 #define NV_RX_SUBSTRACT1 (1<<18)
239 #define NV_RX_ERROR1 (1<<23)
240 #define NV_RX_ERROR2 (1<<24)
241 #define NV_RX_ERROR3 (1<<25)
242 #define NV_RX_ERROR4 (1<<26)
243 #define NV_RX_CRCERR (1<<27)
244 #define NV_RX_OVERFLOW (1<<28)
245 #define NV_RX_FRAMINGERR (1<<29)
246 #define NV_RX_ERROR (1<<30)
247 #define NV_RX_AVAIL (1<<31)
248 #define NV_RX_ERROR_MASK (NV_RX_ERROR1|NV_RX_ERROR2|NV_RX_ERROR3|NV_RX_ERROR4|NV_RX_CRCERR|NV_RX_OVERFLOW|NV_RX_FRAMINGERR)
249 
250 #define NV_RX2_CHECKSUMMASK (0x1C000000)
251 #define NV_RX2_CHECKSUM_IP (0x10000000)
252 #define NV_RX2_CHECKSUM_IP_TCP (0x14000000)
253 #define NV_RX2_CHECKSUM_IP_UDP (0x18000000)
254 #define NV_RX2_DESCRIPTORVALID (1<<29)
255 #define NV_RX2_SUBSTRACT1 (1<<25)
256 #define NV_RX2_ERROR1 (1<<18)
257 #define NV_RX2_ERROR2 (1<<19)
258 #define NV_RX2_ERROR3 (1<<20)
259 #define NV_RX2_ERROR4 (1<<21)
260 #define NV_RX2_CRCERR (1<<22)
261 #define NV_RX2_OVERFLOW (1<<23)
262 #define NV_RX2_FRAMINGERR (1<<24)
263 /* error and avail are the same for both */
264 #define NV_RX2_ERROR (1<<30)
265 #define NV_RX2_AVAIL (1<<31)
266 #define NV_RX2_ERROR_MASK (NV_RX2_ERROR1|NV_RX2_ERROR2|NV_RX2_ERROR3|NV_RX2_ERROR4|NV_RX2_CRCERR|NV_RX2_OVERFLOW|NV_RX2_FRAMINGERR)
267 
268 #define NV_RX3_VLAN_TAG_PRESENT (1<<16)
269 #define NV_RX3_VLAN_TAG_MASK (0x0000FFFF)
270 
271 /* Miscellaneous hardware related defines */
272 #define NV_PCI_REGSZ_VER1 0x270
273 #define NV_PCI_REGSZ_VER2 0x2d4
274 #define NV_PCI_REGSZ_VER3 0x604
275 #define NV_PCI_REGSZ_MAX 0x604
276 
277 /* various timeout delays: all in usec */
278 #define NV_TXRX_RESET_DELAY 4
279 #define NV_TXSTOP_DELAY1 10
280 #define NV_TXSTOP_DELAY1MAX 500000
281 #define NV_TXSTOP_DELAY2 100
282 #define NV_RXSTOP_DELAY1 10
283 #define NV_RXSTOP_DELAY1MAX 500000
284 #define NV_RXSTOP_DELAY2 100
285 #define NV_SETUP5_DELAY 5
286 #define NV_SETUP5_DELAYMAX 50000
287 #define NV_POWERUP_DELAY 5
288 #define NV_POWERUP_DELAYMAX 5000
289 #define NV_MIIBUSY_DELAY 50
290 #define NV_MIIPHY_DELAY 10
291 #define NV_MIIPHY_DELAYMAX 10000
292 #define NV_MAC_RESET_DELAY 64
293 
294 #define NV_MSI_X_CAPABLE 0x0020
295 
296 #define MII_READ (-1)
297 
301 
302  void *mmio_addr;
303 
305  int duplex;
306 
307  int phyaddr;
308  unsigned int phy_oui;
309  unsigned int phy_rev;
310  unsigned int phy_model;
311 
316 
317  /* rx specific fields */
320  int rx_curr;
321 
322  /* tx specific fields */
326  int tx_curr;
327  int tx_tail;
328 
329  /* flow control */
331 
332  unsigned long driver_data;
333 };
334 
335 enum {
336  NvRegIrqStatus = 0x000,
337 #define NVREG_IRQSTAT_MIIEVENT 0x040
338 #define NVREG_IRQSTAT_MASK 0x83ff
339  NvRegIrqMask = 0x004,
340 #define NVREG_IRQ_RX_ERROR 0x0001
341 #define NVREG_IRQ_RX 0x0002
342 #define NVREG_IRQ_RX_NOBUF 0x0004
343 #define NVREG_IRQ_TX_ERR 0x0008
344 #define NVREG_IRQ_TX_OK 0x0010
345 #define NVREG_IRQ_TIMER 0x0020
346 #define NVREG_IRQ_LINK 0x0040
347 #define NVREG_IRQ_RX_FORCED 0x0080
348 #define NVREG_IRQ_TX_FORCED 0x0100
349 #define NVREG_IRQ_RECOVER_ERROR 0x8200
350 #define NVREG_IRQMASK_THROUGHPUT 0x00df
351 #define NVREG_IRQMASK_CPU 0x0060
352 #define NVREG_IRQ_TX_ALL (NVREG_IRQ_TX_ERR|NVREG_IRQ_TX_OK|NVREG_IRQ_TX_FORCED)
353 #define NVREG_IRQ_RX_ALL (NVREG_IRQ_RX_ERROR|NVREG_IRQ_RX|NVREG_IRQ_RX_NOBUF|NVREG_IRQ_RX_FORCED)
354 #define NVREG_IRQ_OTHER (NVREG_IRQ_TIMER|NVREG_IRQ_LINK|NVREG_IRQ_RECOVER_ERROR)
355 
357 #define NVREG_UNKSETUP6_VAL 3
358 
359 /*
360  * NVREG_POLL_DEFAULT is the interval length of the timer source on the nic
361  * NVREG_POLL_DEFAULT=97 would result in an interval length of 1 ms
362  */
364 #define NVREG_POLL_DEFAULT_THROUGHPUT 65535 /* backup tx cleanup if loop max reached */
365 #define NVREG_POLL_DEFAULT_CPU 13
366  NvRegMSIMap0 = 0x020,
367  NvRegMSIMap1 = 0x024,
369 #define NVREG_MSI_VECTOR_0_ENABLED 0x01
370  NvRegMisc1 = 0x080,
371 #define NVREG_MISC1_PAUSE_TX 0x01
372 #define NVREG_MISC1_HD 0x02
373 #define NVREG_MISC1_FORCE 0x3b0f3c
374 
376 #define NVREG_MAC_RESET_ASSERT 0x0F3
378 #define NVREG_XMITCTL_START 0x01
379 #define NVREG_XMITCTL_MGMT_ST 0x40000000
380 #define NVREG_XMITCTL_SYNC_MASK 0x000f0000
381 #define NVREG_XMITCTL_SYNC_NOT_READY 0x0
382 #define NVREG_XMITCTL_SYNC_PHY_INIT 0x00040000
383 #define NVREG_XMITCTL_MGMT_SEMA_MASK 0x00000f00
384 #define NVREG_XMITCTL_MGMT_SEMA_FREE 0x0
385 #define NVREG_XMITCTL_HOST_SEMA_MASK 0x0000f000
386 #define NVREG_XMITCTL_HOST_SEMA_ACQ 0x0000f000
387 #define NVREG_XMITCTL_HOST_LOADED 0x00004000
388 #define NVREG_XMITCTL_TX_PATH_EN 0x01000000
389 #define NVREG_XMITCTL_DATA_START 0x00100000
390 #define NVREG_XMITCTL_DATA_READY 0x00010000
391 #define NVREG_XMITCTL_DATA_ERROR 0x00020000
393 #define NVREG_XMITSTAT_BUSY 0x01
394 
396 #define NVREG_PFF_PAUSE_RX 0x08
397 #define NVREG_PFF_ALWAYS 0x7F0000
398 #define NVREG_PFF_PROMISC 0x80
399 #define NVREG_PFF_MYADDR 0x20
400 #define NVREG_PFF_LOOPBACK 0x10
401 
403 #define NVREG_OFFLOAD_HOMEPHY 0x601
404 #define NVREG_OFFLOAD_NORMAL RX_NIC_BUFSIZE
406 #define NVREG_RCVCTL_START 0x01
407 #define NVREG_RCVCTL_RX_PATH_EN 0x01000000
409 #define NVREG_RCVSTAT_BUSY 0x01
410 
412 #define NVREG_SLOTTIME_LEGBF_ENABLED 0x80000000
413 #define NVREG_SLOTTIME_10_100_FULL 0x00007f00
414 #define NVREG_SLOTTIME_1000_FULL 0x0003ff00
415 #define NVREG_SLOTTIME_HALF 0x0000ff00
416 #define NVREG_SLOTTIME_DEFAULT 0x00007f00
417 #define NVREG_SLOTTIME_MASK 0x000000ff
418 
420 #define NVREG_TX_DEFERRAL_DEFAULT 0x15050f
421 #define NVREG_TX_DEFERRAL_RGMII_10_100 0x16070f
422 #define NVREG_TX_DEFERRAL_RGMII_1000 0x14050f
423 #define NVREG_TX_DEFERRAL_RGMII_STRETCH_10 0x16190f
424 #define NVREG_TX_DEFERRAL_RGMII_STRETCH_100 0x16300f
425 #define NVREG_TX_DEFERRAL_MII_STRETCH 0x152000
427 #define NVREG_RX_DEFERRAL_DEFAULT 0x16
431 #define NVREG_MCASTADDRA_FORCE 0x01
434 #define NVREG_MCASTMASKA_NONE 0xffffffff
436 #define NVREG_MCASTMASKB_NONE 0xffff
437 
439 #define PHY_RGMII 0x10000000
441 #define NVREG_BKOFFCTRL_DEFAULT 0x70000000
442 #define NVREG_BKOFFCTRL_SEED_MASK 0x000003ff
443 #define NVREG_BKOFFCTRL_SELECT 24
444 #define NVREG_BKOFFCTRL_GEAR 12
445 
448  NvRegRingSizes = 0x108,
449 #define NVREG_RINGSZ_TXSHIFT 0
450 #define NVREG_RINGSZ_RXSHIFT 16
452 #define NVREG_TRANSMITPOLL_MAC_ADDR_REV 0x00008000
453  NvRegLinkSpeed = 0x110,
454 #define NVREG_LINKSPEED_FORCE 0x10000
455 #define NVREG_LINKSPEED_10 1000
456 #define NVREG_LINKSPEED_100 100
457 #define NVREG_LINKSPEED_1000 50
458 #define NVREG_LINKSPEED_MASK (0xFFF)
460 #define NVREG_UNKSETUP5_BIT31 (1<<31)
462 #define NVREG_TX_WM_DESC1_DEFAULT 0x0200010
463 #define NVREG_TX_WM_DESC2_3_DEFAULT 0x1e08000
464 #define NVREG_TX_WM_DESC2_3_1000 0xfe08000
466 #define NVREG_TXRXCTL_KICK 0x0001
467 #define NVREG_TXRXCTL_BIT1 0x0002
468 #define NVREG_TXRXCTL_BIT2 0x0004
469 #define NVREG_TXRXCTL_IDLE 0x0008
470 #define NVREG_TXRXCTL_RESET 0x0010
471 #define NVREG_TXRXCTL_RXCHECK 0x0400
472 #define NVREG_TXRXCTL_DESC_1 0
473 #define NVREG_TXRXCTL_DESC_2 0x002100
474 #define NVREG_TXRXCTL_DESC_3 0xc02200
475 #define NVREG_TXRXCTL_VLANSTRIP 0x00040
476 #define NVREG_TXRXCTL_VLANINS 0x00080
480 #define NVREG_TX_PAUSEFRAME_DISABLE 0x0fff0080
481 #define NVREG_TX_PAUSEFRAME_ENABLE_V1 0x01800010
482 #define NVREG_TX_PAUSEFRAME_ENABLE_V2 0x056003f0
483 #define NVREG_TX_PAUSEFRAME_ENABLE_V3 0x09f00880
485 #define NVREG_TX_PAUSEFRAMELIMIT_ENABLE 0x00010000
486  NvRegMIIStatus = 0x180,
487 #define NVREG_MIISTAT_ERROR 0x0001
488 #define NVREG_MIISTAT_LINKCHANGE 0x0008
489 #define NVREG_MIISTAT_MASK_RW 0x0007
490 #define NVREG_MIISTAT_MASK_ALL 0x000f
491  NvRegMIIMask = 0x184,
492 #define NVREG_MII_LINKCHANGE 0x0008
493 
495 #define NVREG_ADAPTCTL_START 0x02
496 #define NVREG_ADAPTCTL_LINKUP 0x04
497 #define NVREG_ADAPTCTL_PHYVALID 0x40000
498 #define NVREG_ADAPTCTL_RUNNING 0x100000
499 #define NVREG_ADAPTCTL_PHYSHIFT 24
500  NvRegMIISpeed = 0x18c,
501 #define NVREG_MIISPEED_BIT8 (1<<8)
502 #define NVREG_MIIDELAY 5
504 #define NVREG_MIICTL_INUSE 0x08000
505 #define NVREG_MIICTL_WRITE 0x00400
506 #define NVREG_MIICTL_ADDRSHIFT 5
507  NvRegMIIData = 0x194,
508  NvRegTxUnicast = 0x1a0,
512 #define NVREG_WAKEUPFLAGS_VAL 0x7770
513 #define NVREG_WAKEUPFLAGS_BUSYSHIFT 24
514 #define NVREG_WAKEUPFLAGS_ENABLESHIFT 16
515 #define NVREG_WAKEUPFLAGS_D3SHIFT 12
516 #define NVREG_WAKEUPFLAGS_D2SHIFT 8
517 #define NVREG_WAKEUPFLAGS_D1SHIFT 4
518 #define NVREG_WAKEUPFLAGS_D0SHIFT 0
519 #define NVREG_WAKEUPFLAGS_ACCEPT_MAGPAT 0x01
520 #define NVREG_WAKEUPFLAGS_ACCEPT_WAKEUPPAT 0x02
521 #define NVREG_WAKEUPFLAGS_ACCEPT_LINKCHANGE 0x04
522 #define NVREG_WAKEUPFLAGS_ENABLE 0x1111
523 
525 #define NVREG_MGMTUNITGETVERSION 0x01
527 #define NVREG_MGMTUNITVERSION 0x08
528  NvRegPowerCap = 0x268,
529 #define NVREG_POWERCAP_D3SUPP (1<<30)
530 #define NVREG_POWERCAP_D2SUPP (1<<26)
531 #define NVREG_POWERCAP_D1SUPP (1<<25)
533 #define NVREG_POWERSTATE_POWEREDUP 0x8000
534 #define NVREG_POWERSTATE_VALID 0x0100
535 #define NVREG_POWERSTATE_MASK 0x0003
536 #define NVREG_POWERSTATE_D0 0x0000
537 #define NVREG_POWERSTATE_D1 0x0001
538 #define NVREG_POWERSTATE_D2 0x0002
539 #define NVREG_POWERSTATE_D3 0x0003
541 #define NVREG_MGMTUNITCONTROL_INUSE 0x20000
542  NvRegTxCnt = 0x280,
546  NvRegTxLateCol = 0x290,
553  NvRegRxLateCol = 0x2ac,
554  NvRegRxRunt = 0x2b0,
557  NvRegRxFCSErr = 0x2bc,
559  NvRegRxLenErr = 0x2c4,
560  NvRegRxUnicast = 0x2c8,
563  NvRegTxDef = 0x2d4,
564  NvRegTxFrame = 0x2d8,
565  NvRegRxCnt = 0x2dc,
566  NvRegTxPause = 0x2e0,
567  NvRegRxPause = 0x2e4,
570 #define NVREG_VLANCONTROL_ENABLE 0x2000
571  NvRegMSIXMap0 = 0x3e0,
572  NvRegMSIXMap1 = 0x3e4,
574 
576 #define NVREG_POWERSTATE2_POWERUP_MASK 0x0F15
577 #define NVREG_POWERSTATE2_POWERUP_REV_A3 0x0001
578 #define NVREG_POWERSTATE2_PHY_RESET 0x0004
579 #define NVREG_POWERSTATE2_GATE_CLOCKS 0x0F00
580 };
581 
582 enum {
586 };
587 
588 enum {
591 };
592 
593 
594 #define NV_SETUP_RX_RING 0x01
595 #define NV_SETUP_TX_RING 0x02
596 
597 #define NV_RESTART_TX 0x1
598 #define NV_RESTART_RX 0x2
599 
600 #endif /* _FORCEDETH_H_ */
uint16_t u16
Definition: stdint.h:21
struct ring_desc * tx_ring
Definition: forcedeth.h:323
unsigned int phy_oui
Definition: forcedeth.h:308
unsigned long driver_data
Definition: forcedeth.h:332
unsigned int phy_rev
Definition: forcedeth.h:309
struct net_device * netdev
Definition: forcedeth.h:300
unsigned int phy_model
Definition: forcedeth.h:310
#define TX_RING_SIZE
Definition: forcedeth.h:56
struct io_buffer * tx_iobuf[TX_RING_SIZE]
Definition: forcedeth.h:324
#define RX_RING_SIZE
Definition: forcedeth.h:55
A PCI device.
Definition: pci.h:187
A network device.
Definition: netdevice.h:348
struct io_buffer * rx_iobuf[RX_RING_SIZE]
Definition: forcedeth.h:319
struct ring_desc * rx_ring
Definition: forcedeth.h:318
FILE_LICENCE(GPL2_OR_LATER)
u32 buf
Definition: forcedeth.h:40
struct pci_device * pci_dev
Definition: forcedeth.h:299
uint32_t u32
Definition: stdint.h:23
u32 flaglen
Definition: forcedeth.h:41
A persistent I/O buffer.
Definition: iobuf.h:32