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#define | RDC_BAR_SIZE 256 |
| RDC BAR size. More...
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#define | RDC_FL_OWNED 0x8000 |
| Descriptor is owned by NIC. More...
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#define | RDC_FL_OK 0x4000 |
| Packet OK. More...
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#define | RDC_MCR0 0x00 |
| MAC control register 0. More...
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#define | RDC_MCR0_FD 0x8000 |
| Full duplex. More...
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#define | RDC_MCR0_TXEN 0x1000 |
| Transmit enable. More...
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#define | RDC_MCR0_PROMISC 0x0020 |
| Promiscuous mode. More...
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#define | RDC_MCR0_RXEN 0x0002 |
| Receive enable. More...
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#define | RDC_MCR1 0x04 |
| MAC control register 1. More...
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#define | RDC_MCR1_RST 0x0001 |
| MAC reset. More...
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#define | RDC_RESET_MAX_WAIT_MS 10 |
| Maximum time to wait for reset. More...
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#define | RDC_MTPR 0x14 |
| MAC transmit poll command register. More...
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#define | RDC_MTPR_TM2TX 0x0001 |
| Trigger MAC to transmit. More...
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#define | RDC_MRBSR 0x18 |
| MAC receive buffer size register. More...
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#define | RDC_MMDIO 0x20 |
| MAC MDIO control register. More...
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#define | RDC_MMDIO_MIIWR 0x4000 |
| MDIO write. More...
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#define | RDC_MMDIO_MIIRD 0x2000 |
| MDIO read. More...
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#define | RDC_MMDIO_PHYAD(x) ( (x) << 8 ) |
| PHY address. More...
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#define | RDC_MMDIO_REGAD(x) ( (x) << 0 ) |
| Register address. More...
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#define | RDC_MII_MAX_WAIT_US 2048 |
| Maximum time to wait for an MII read or write. More...
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#define | RDC_MMRD 0x24 |
| MAC MDIO read data register. More...
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#define | RDC_MMWD 0x28 |
| MAC MDIO write data register. More...
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#define | RDC_MTDSA 0x2c |
| MAC transmit descriptor start address. More...
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#define | RDC_MRDSA 0x34 |
| MAC receive descriptor start address. More...
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#define | RDC_MxDSA_LO 0x0 |
| MAC descriptor start address low half. More...
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#define | RDC_MxDSA_HI 0x4 |
| MAC descriptor start address low half. More...
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#define | RDC_MISR 0x3c |
| MAC interrupt status register. More...
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#define | RDC_MIRQ_LINK 0x0200 |
| Link status changed. More...
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#define | RDC_MIRQ_TX 0x0010 |
| Transmit complete. More...
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#define | RDC_MIRQ_RX_EARLY 0x0008 |
| Receive early interrupt. More...
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#define | RDC_MIRQ_RX_EMPTY 0x0002 |
| Receive descriptor unavailable. More...
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#define | RDC_MIRQ_RX 0x0001 |
| Receive complete. More...
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#define | RDC_MIER 0x40 |
| MAC interrupt enable register. More...
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#define | RDC_MID0 0x68 |
| MAC address word 0. More...
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#define | RDC_MID1 0x6a |
| MAC address word 1. More...
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#define | RDC_MID2 0x6c |
| MAC address word 2. More...
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#define | RDC_MPSCCR 0x88 |
| MAC PHY status change configuration register. More...
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#define | RDC_MPSCCR_EN 0x8000 |
| PHY status change enable. More...
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#define | RDC_MPSCCR_PHYAD(x) ( (x) << 8 ) |
| PHY address. More...
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#define | RDC_MPSCCR_SLOW 0x0007 |
| Poll slowly. More...
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#define | RDC_MACSM 0xac |
| MAC state machine register. More...
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#define | RDC_MACSM_RST 0x0002 |
| Reset state machine. More...
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#define | RDC_MACSM_RESET_DELAY_MS 10 |
| Time to wait after resetting MAC state machine. More...
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#define | RDC_NUM_TX_DESC 16 |
| Number of transmit descriptors. More...
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#define | RDC_NUM_RX_DESC 8 |
| Number of receive descriptors. More...
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#define | RDC_RX_MAX_LEN ( ETH_FRAME_LEN + 4 /* VLAN */ + 4 /* CRC */ ) |
| Receive buffer length. More...
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