14 #define AUTONEG_DISABLE 0x00 15 #define AUTONEG_ENABLE 0x01 17 #define DUPLEX_HALF 0x00 18 #define DUPLEX_FULL 0x01 22 #define SPEED_1000 1000 24 #define ADVERTISED_10baseT_Half (1 << 0) 25 #define ADVERTISED_10baseT_Full (1 << 1) 26 #define ADVERTISED_100baseT_Half (1 << 2) 27 #define ADVERTISED_100baseT_Full (1 << 3) 28 #define ADVERTISED_1000baseT_Half (1 << 4) 29 #define ADVERTISED_1000baseT_Full (1 << 5) 31 #define SUPPORTED_10baseT_Half (1 << 0) 32 #define SUPPORTED_10baseT_Full (1 << 1) 33 #define SUPPORTED_100baseT_Half (1 << 2) 34 #define SUPPORTED_100baseT_Full (1 << 3) 35 #define SUPPORTED_1000baseT_Half (1 << 4) 36 #define SUPPORTED_1000baseT_Full (1 << 5) 37 #define SUPPORTED_Autoneg (1 << 6) 38 #define SUPPORTED_TP (1 << 7) 39 #define SUPPORTED_FIBRE (1 << 10) 89 #define P_PEX_LTSSM_STAT(x) ((x << 25) & P_PEX_LTSSM_STAT_MSK) 183 #define PCI_STATUS_ERROR_BITS (PCI_STATUS_DETECTED_PARITY | \ 184 PCI_STATUS_SIG_SYSTEM_ERROR | \ 185 PCI_STATUS_REC_MASTER_ABORT | \ 186 PCI_STATUS_REC_TARGET_ABORT | \ 245 #define RAM_BUFFER(port, reg) (reg | (port <<6)) 524 #define CFG_LED_MODE(x) (((x) & CFG_LED_MODE_MSK) >> 2) 525 #define CFG_DUAL_MAC_MSK (CFG_LINK_2_AVAIL | CFG_LINK_1_AVAIL) 531 #define Y2_CLK_DIV_VAL(x) (((x)<<16) & Y2_CLK_DIV_VAL_MSK) 534 #define Y2_CLK_DIV_VAL_2(x) (((x)<<21) & Y2_CLK_DIV_VAL2_MSK) 535 #define Y2_CLK_SEL_VAL_2(x) (((x)<<16) & Y2_CLK_SELECT2_MSK) 559 #define RAM_ADR_RAN 0x0007ffffL 571 #define SK_RI_TO_53 36 575 #define SK_REG(port,reg) (((port)<<7)+(reg)) 583 #define TXA_MAX_VAL 0x00ffffffUL 648 #define Q_ADDR(reg, offs) (B8_Q_REGS + (reg) + (offs)) 679 #define Y2_QADDR(q,reg) (Y2_B8_PREF_REGS + (q) + (reg)) 715 #define RB_ADDR(offs, queue) ((u16) B16_RAM_REGS + (queue) + (offs)) 819 #define RB_MSK 0x0007ffff 981 #define WOL_REGS(port, x) (x + (port)*0x80) 987 #define WOL_PATT_RAM_BASE(port) (WOL_PATT_RAM_1 + (port)*0x400) 1185 #define PHY_M_PC_MDI_XMODE(x) (((u16)(x)<<5) & PHY_M_PC_MDIX_MSK) 1234 #define PHY_M_PS_PAUSE_MSK (PHY_M_PS_TX_P_EN | PHY_M_PS_RX_P_EN) 1287 #define PHY_M_EC_M_DSC(x) ((u16)(x)<<10 & PHY_M_EC_M_DSC_MSK) 1289 #define PHY_M_EC_S_DSC(x) ((u16)(x)<<8 & PHY_M_EC_S_DSC_MSK) 1291 #define PHY_M_EC_DSC_2(x) ((u16)(x)<<9 & PHY_M_EC_M_DSC_MSK2) 1293 #define PHY_M_EC_MAC_S(x) ((u16)(x)<<4 & PHY_M_EC_MAC_S_MSK) 1304 #define PHY_M_PC_DSC(x) (((u16)(x)<<12) & PHY_M_PC_DSC_MSK) 1334 #define PHY_M_LED_PULS_DUR(x) (((u16)(x)<<12) & PHY_M_LEDC_PULS_MSK) 1346 #define PHY_M_POLC_LS1_P_MIX(x) (((x)<<12) & PHY_M_POLC_LS1M_MSK) 1347 #define PHY_M_POLC_IS0_P_MIX(x) (((x)<<8) & PHY_M_POLC_IS0M_MSK) 1348 #define PHY_M_POLC_LOS_CTRL(x) (((x)<<6) & PHY_M_POLC_LOS_MSK) 1349 #define PHY_M_POLC_INIT_CTRL(x) (((x)<<4) & PHY_M_POLC_INIT_MSK) 1350 #define PHY_M_POLC_STA1_CTRL(x) (((x)<<2) & PHY_M_POLC_STA1_MSK) 1351 #define PHY_M_POLC_STA0_CTRL(x) (((x)<<0) & PHY_M_POLC_STA0_MSK) 1364 #define PHY_M_LED_BLINK_RT(x) (((u16)(x)<<8) & PHY_M_LEDC_BL_R_MSK) 1375 #define PHY_M_LED_MO_SGMII(x) ((x)<<14) 1377 #define PHY_M_LED_MO_DUP(x) ((x)<<10) 1378 #define PHY_M_LED_MO_10(x) ((x)<<8) 1379 #define PHY_M_LED_MO_100(x) ((x)<<6) 1380 #define PHY_M_LED_MO_1000(x) ((x)<<4) 1381 #define PHY_M_LED_MO_RX(x) ((x)<<2) 1382 #define PHY_M_LED_MO_TX(x) ((x)<<0) 1425 #define PHY_M_FELP_LED2_CTRL(x) (((u16)(x)<<8) & PHY_M_FELP_LED2_MSK) 1426 #define PHY_M_FELP_LED1_CTRL(x) (((u16)(x)<<4) & PHY_M_FELP_LED1_MSK) 1427 #define PHY_M_FELP_LED0_CTRL(x) (((u16)(x)<<0) & PHY_M_FELP_LED0_MSK) 1472 #define PHY_M_MAC_MODE_SEL(x) (((x)<<7) & PHY_M_MAC_MD_MSK) 1482 #define PHY_M_LEDC_LOS_CTRL(x) (((x)<<12) & PHY_M_LEDC_LOS_MSK) 1483 #define PHY_M_LEDC_INIT_CTRL(x) (((x)<<8) & PHY_M_LEDC_INIT_MSK) 1484 #define PHY_M_LEDC_STA1_CTRL(x) (((x)<<4) & PHY_M_LEDC_STA1_MSK) 1485 #define PHY_M_LEDC_STA0_CTRL(x) (((x)<<0) & PHY_M_LEDC_STA0_MSK) 1619 #define GM_GPCR_SPEED_1000 (GM_GPCR_GIGS_ENA | GM_GPCR_SPEED_100) 1620 #define GM_GPCR_AU_ALL_DIS (GM_GPCR_AU_DUP_DIS | GM_GPCR_AU_FCT_DIS|GM_GPCR_AU_SPD_DIS) 1630 #define TX_COL_THR(x) (((x)<<10) & GM_TXCR_COL_THR_MSK) 1631 #define TX_COL_DEF 0x04 1654 #define TX_JAM_LEN_VAL(x) (((x)<<14) & GM_TXPA_JAMLEN_MSK) 1655 #define TX_JAM_IPG_VAL(x) (((x)<<9) & GM_TXPA_JAMIPG_MSK) 1656 #define TX_IPG_JAM_DATA(x) (((x)<<4) & GM_TXPA_JAMDAT_MSK) 1657 #define TX_BACK_OFF_LIM(x) ((x) & GM_TXPA_BO_LIM_MSK) 1669 #define DATA_BLIND_VAL(x) (((x)<<11) & GM_SMOD_DATABL_MSK) 1670 #define DATA_BLIND_DEF 0x04 1672 #define IPG_DATA_VAL(x) (x & GM_SMOD_IPG_MSK) 1673 #define IPG_DATA_DEF 0x1e 1684 #define GM_SMI_CT_PHY_AD(x) (((u16)(x)<<11) & GM_SMI_CT_PHY_A_MSK) 1685 #define GM_SMI_CT_REG_AD(x) (((u16)(x)<<6) & GM_SMI_CT_REG_A_MSK) 1907 #define GMAC_DEF_MSK GM_IS_TX_FF_UR 2071 #define SKY2_HW_USE_MSI 0x00000001 2072 #define SKY2_HW_FIBRE_PHY 0x00000002 2073 #define SKY2_HW_GIGABIT 0x00000004 2074 #define SKY2_HW_NEWER_PHY 0x00000008 2075 #define SKY2_HW_RAM_BUFFER 0x00000010 2076 #define SKY2_HW_NEW_LE 0x00000020 2077 #define SKY2_HW_AUTO_TX_SUM 0x00000040 2078 #define SKY2_HW_ADV_POWER_CTL 0x00000080 2127 #define SK_GMAC_REG(port,reg) \ 2128 (BASE_GMAC_1 + (port) * (BASE_GMAC_2-BASE_GMAC_1) + (reg)) 2129 #define GM_PHY_RETRIES 100
static u16 sky2_read16(const struct sky2_hw *hw, unsigned reg)
static void gma_set_addr(struct sky2_hw *hw, unsigned port, unsigned reg, const u8 *addr)
uint8_t readb(volatile uint8_t *io_addr)
Read byte from memory-mapped device.
static void sky2_write32(const struct sky2_hw *hw, unsigned reg, u32 val)
static unsigned int unsigned int reg
uint16_t readw(volatile uint16_t *io_addr)
Read 16-bit word from memory-mapped device.
struct tx_ring_info __attribute
static u32 sky2_pci_read32(const struct sky2_hw *hw, unsigned reg)
uint32_t readl(volatile uint32_t *io_addr)
Read 32-bit dword from memory-mapped device.
static u16 sky2_pci_read16(const struct sky2_hw *hw, unsigned reg)
static u32 sky2_read32(const struct sky2_hw *hw, unsigned reg)
static u32 gma_read32(struct sky2_hw *hw, unsigned port, unsigned reg)
struct sky2_tx_le * tx_le
void writeb(uint8_t data, volatile uint8_t *io_addr)
Write byte to memory-mapped device.
static void sky2_pci_write16(struct sky2_hw *hw, unsigned reg, u16 val)
struct sky2_status_le * st_le
struct net_device * netdev
static void gma_write16(const struct sky2_hw *hw, unsigned port, int r, u16 v)
void writel(uint32_t data, volatile uint32_t *io_addr)
Write 32-bit dword to memory-mapped device.
struct tx_ring_info * tx_ring
struct rx_ring_info * rx_ring
static void sky2_write16(const struct sky2_hw *hw, unsigned reg, u16 val)
static int sky2_is_copper(const struct sky2_hw *hw)
enum flow_control flow_mode
static u16 gma_read16(const struct sky2_hw *hw, unsigned port, unsigned reg)
#define SK_GMAC_REG(port, reg)
static void sky2_write8(const struct sky2_hw *hw, unsigned reg, u8 val)
struct sky2_rx_le * rx_le
#define SKY2_HW_FIBRE_PHY
struct net_device * dev[2]
static u8 sky2_read8(const struct sky2_hw *hw, unsigned reg)
static void sky2_pci_write32(struct sky2_hw *hw, unsigned reg, u32 val)
enum flow_control flow_status
static const uint8_t r[3][4]
MD4 shift amounts.