iPXE
xhci.h
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1 #ifndef _IPXE_XHCI_H
2 #define _IPXE_XHCI_H
3 
4 /** @file
5  *
6  * USB eXtensible Host Controller Interface (xHCI) driver
7  *
8  */
9 
10 FILE_LICENCE ( GPL2_OR_LATER_OR_UBDL );
11 
12 #include <assert.h>
13 #include <ipxe/pci.h>
14 #include <ipxe/uaccess.h>
15 #include <ipxe/usb.h>
16 
17 /** Minimum alignment required for data structures
18  *
19  * With the exception of the scratchpad buffer pages (which are
20  * page-aligned), data structures used by xHCI generally require from
21  * 16 to 64 byte alignment and must not cross an (xHCI) page boundary.
22  * We simplify this requirement by aligning each structure on its own
23  * size, with a minimum of a 64 byte alignment.
24  */
25 #define XHCI_MIN_ALIGN 64
26 
27 /** Maximum transfer size */
28 #define XHCI_MTU 65536
29 
30 /** xHCI PCI BAR */
31 #define XHCI_BAR PCI_BASE_ADDRESS_0
32 
33 /** Capability register length */
34 #define XHCI_CAP_CAPLENGTH 0x00
35 
36 /** Host controller interface version number */
37 #define XHCI_CAP_HCIVERSION 0x02
38 
39 /** Structural parameters 1 */
40 #define XHCI_CAP_HCSPARAMS1 0x04
41 
42 /** Number of device slots */
43 #define XHCI_HCSPARAMS1_SLOTS(params) ( ( (params) >> 0 ) & 0xff )
44 
45 /** Number of interrupters */
46 #define XHCI_HCSPARAMS1_INTRS(params) ( ( (params) >> 8 ) & 0x3ff )
47 
48 /** Number of ports */
49 #define XHCI_HCSPARAMS1_PORTS(params) ( ( (params) >> 24 ) & 0xff )
50 
51 /** Structural parameters 2 */
52 #define XHCI_CAP_HCSPARAMS2 0x08
53 
54 /** Number of page-sized scratchpad buffers */
55 #define XHCI_HCSPARAMS2_SCRATCHPADS(params) \
56  ( ( ( (params) >> 16 ) & 0x3e0 ) | ( ( (params) >> 27 ) & 0x1f ) )
57 
58 /** Capability parameters */
59 #define XHCI_CAP_HCCPARAMS1 0x10
60 
61 /** 64-bit addressing capability */
62 #define XHCI_HCCPARAMS1_ADDR64(params) ( ( (params) >> 0 ) & 0x1 )
63 
64 /** Context size shift */
65 #define XHCI_HCCPARAMS1_CSZ_SHIFT(params) ( 5 + ( ( (params) >> 2 ) & 0x1 ) )
66 
67 /** xHCI extended capabilities pointer */
68 #define XHCI_HCCPARAMS1_XECP(params) ( ( ( (params) >> 16 ) & 0xffff ) << 2 )
69 
70 /** Doorbell offset */
71 #define XHCI_CAP_DBOFF 0x14
72 
73 /** Runtime register space offset */
74 #define XHCI_CAP_RTSOFF 0x18
75 
76 /** xHCI extended capability ID */
77 #define XHCI_XECP_ID(xecp) ( ( (xecp) >> 0 ) & 0xff )
78 
79 /** Next xHCI extended capability pointer */
80 #define XHCI_XECP_NEXT(xecp) ( ( ( (xecp) >> 8 ) & 0xff ) << 2 )
81 
82 /** USB legacy support extended capability */
83 #define XHCI_XECP_ID_LEGACY 1
84 
85 /** USB legacy support BIOS owned semaphore */
86 #define XHCI_USBLEGSUP_BIOS 0x02
87 
88 /** USB legacy support BIOS ownership flag */
89 #define XHCI_USBLEGSUP_BIOS_OWNED 0x01
90 
91 /** USB legacy support OS owned semaphore */
92 #define XHCI_USBLEGSUP_OS 0x03
93 
94 /** USB legacy support OS ownership flag */
95 #define XHCI_USBLEGSUP_OS_OWNED 0x01
96 
97 /** USB legacy support control/status */
98 #define XHCI_USBLEGSUP_CTLSTS 0x04
99 
100 /** Supported protocol extended capability */
101 #define XHCI_XECP_ID_SUPPORTED 2
102 
103 /** Supported protocol revision */
104 #define XHCI_SUPPORTED_REVISION 0x00
105 
106 /** Supported protocol minor revision */
107 #define XHCI_SUPPORTED_REVISION_VER(revision) ( ( (revision) >> 16 ) & 0xffff )
108 
109 /** Supported protocol name */
110 #define XHCI_SUPPORTED_NAME 0x04
111 
112 /** Supported protocol ports */
113 #define XHCI_SUPPORTED_PORTS 0x08
114 
115 /** Supported protocol port offset */
116 #define XHCI_SUPPORTED_PORTS_OFFSET(ports) ( ( (ports) >> 0 ) & 0xff )
117 
118 /** Supported protocol port count */
119 #define XHCI_SUPPORTED_PORTS_COUNT(ports) ( ( (ports) >> 8 ) & 0xff )
120 
121 /** Supported protocol PSI count */
122 #define XHCI_SUPPORTED_PORTS_PSIC(ports) ( ( (ports) >> 28 ) & 0x0f )
123 
124 /** Supported protocol slot */
125 #define XHCI_SUPPORTED_SLOT 0x0c
126 
127 /** Supported protocol slot type */
128 #define XHCI_SUPPORTED_SLOT_TYPE(slot) ( ( (slot) >> 0 ) & 0x1f )
129 
130 /** Supported protocol PSI */
131 #define XHCI_SUPPORTED_PSI(index) ( 0x10 + ( (index) * 4 ) )
132 
133 /** Supported protocol PSI value */
134 #define XHCI_SUPPORTED_PSI_VALUE(psi) ( ( (psi) >> 0 ) & 0x0f )
135 
136 /** Supported protocol PSI mantissa */
137 #define XHCI_SUPPORTED_PSI_MANTISSA(psi) ( ( (psi) >> 16 ) & 0xffff )
138 
139 /** Supported protocol PSI exponent */
140 #define XHCI_SUPPORTED_PSI_EXPONENT(psi) ( ( (psi) >> 4 ) & 0x03 )
141 
142 /** Default PSI values */
144  /** Full speed (12Mbps) */
146  /** Low speed (1.5Mbps) */
148  /** High speed (480Mbps) */
150  /** Super speed */
152 };
153 
154 /** USB command register */
155 #define XHCI_OP_USBCMD 0x00
156 
157 /** Run/stop */
158 #define XHCI_USBCMD_RUN 0x00000001UL
159 
160 /** Host controller reset */
161 #define XHCI_USBCMD_HCRST 0x00000002UL
162 
163 /** USB status register */
164 #define XHCI_OP_USBSTS 0x04
165 
166 /** Host controller halted */
167 #define XHCI_USBSTS_HCH 0x00000001UL
168 
169 /** Page size register */
170 #define XHCI_OP_PAGESIZE 0x08
171 
172 /** Page size */
173 #define XHCI_PAGESIZE(pagesize) ( (pagesize) << 12 )
174 
175 /** Device notifcation control register */
176 #define XHCI_OP_DNCTRL 0x14
177 
178 /** Command ring control register */
179 #define XHCI_OP_CRCR 0x18
180 
181 /** Command ring cycle state */
182 #define XHCI_CRCR_RCS 0x00000001UL
183 
184 /** Command abort */
185 #define XHCI_CRCR_CA 0x00000004UL
186 
187 /** Command ring running */
188 #define XHCI_CRCR_CRR 0x00000008UL
189 
190 /** Device context base address array pointer */
191 #define XHCI_OP_DCBAAP 0x30
192 
193 /** Configure register */
194 #define XHCI_OP_CONFIG 0x38
195 
196 /** Maximum device slots enabled */
197 #define XHCI_CONFIG_MAX_SLOTS_EN(slots) ( (slots) << 0 )
198 
199 /** Maximum device slots enabled mask */
200 #define XHCI_CONFIG_MAX_SLOTS_EN_MASK \
201  XHCI_CONFIG_MAX_SLOTS_EN ( 0xff )
202 
203 /** Port status and control register */
204 #define XHCI_OP_PORTSC(port) ( 0x400 - 0x10 + ( (port) << 4 ) )
205 
206 /** Current connect status */
207 #define XHCI_PORTSC_CCS 0x00000001UL
208 
209 /** Port enabled */
210 #define XHCI_PORTSC_PED 0x00000002UL
211 
212 /** Port reset */
213 #define XHCI_PORTSC_PR 0x00000010UL
214 
215 /** Port link state */
216 #define XHCI_PORTSC_PLS(pls) ( (pls) << 5 )
217 
218 /** Disabled port link state */
219 #define XHCI_PORTSC_PLS_DISABLED XHCI_PORTSC_PLS ( 4 )
220 
221 /** RxDetect port link state */
222 #define XHCI_PORTSC_PLS_RXDETECT XHCI_PORTSC_PLS ( 5 )
223 
224 /** Port link state mask */
225 #define XHCI_PORTSC_PLS_MASK XHCI_PORTSC_PLS ( 0xf )
226 
227 /** Port power */
228 #define XHCI_PORTSC_PP 0x00000200UL
229 
230 /** Time to delay after enabling power to a port */
231 #define XHCI_PORT_POWER_DELAY_MS 20
232 
233 /** Port speed ID value */
234 #define XHCI_PORTSC_PSIV(portsc) ( ( (portsc) >> 10 ) & 0xf )
235 
236 /** Port indicator control */
237 #define XHCI_PORTSC_PIC(indicators) ( (indicators) << 14 )
238 
239 /** Port indicator control mask */
240 #define XHCI_PORTSC_PIC_MASK XHCI_PORTSC_PIC ( 3 )
241 
242 /** Port link state write strobe */
243 #define XHCI_PORTSC_LWS 0x00010000UL
244 
245 /** Time to delay after writing the port link state */
246 #define XHCI_LINK_STATE_DELAY_MS 100
247 
248 /** Connect status change */
249 #define XHCI_PORTSC_CSC 0x00020000UL
250 
251 /** Port enabled/disabled change */
252 #define XHCI_PORTSC_PEC 0x00040000UL
253 
254 /** Warm port reset change */
255 #define XHCI_PORTSC_WRC 0x00080000UL
256 
257 /** Over-current change */
258 #define XHCI_PORTSC_OCC 0x00100000UL
259 
260 /** Port reset change */
261 #define XHCI_PORTSC_PRC 0x00200000UL
262 
263 /** Port link state change */
264 #define XHCI_PORTSC_PLC 0x00400000UL
265 
266 /** Port config error change */
267 #define XHCI_PORTSC_CEC 0x00800000UL
268 
269 /** Port status change mask */
270 #define XHCI_PORTSC_CHANGE \
271  ( XHCI_PORTSC_CSC | XHCI_PORTSC_PEC | XHCI_PORTSC_WRC | \
272  XHCI_PORTSC_OCC | XHCI_PORTSC_PRC | XHCI_PORTSC_PLC | \
273  XHCI_PORTSC_CEC )
274 
275 /** Port status and control bits which should be preserved
276  *
277  * The port status and control register is a horrendous mix of
278  * differing semantics. Some bits are written to only when a separate
279  * write strobe bit is set. Some bits should be preserved when
280  * modifying other bits. Some bits will be cleared if written back as
281  * a one. Most excitingly, the "port enabled" bit has the semantics
282  * that 1=enabled, 0=disabled, yet writing a 1 will disable the port.
283  */
284 #define XHCI_PORTSC_PRESERVE ( XHCI_PORTSC_PP | XHCI_PORTSC_PIC_MASK )
285 
286 /** Port power management status and control register */
287 #define XHCI_OP_PORTPMSC(port) ( 0x404 - 0x10 + ( (port) << 4 ) )
288 
289 /** Port link info register */
290 #define XHCI_OP_PORTLI(port) ( 0x408 - 0x10 + ( (port) << 4 ) )
291 
292 /** Port hardware link power management control register */
293 #define XHCI_OP_PORTHLPMC(port) ( 0x40c - 0x10 + ( (port) << 4 ) )
294 
295 /** Event ring segment table size register */
296 #define XHCI_RUN_ERSTSZ(intr) ( 0x28 + ( (intr) << 5 ) )
297 
298 /** Event ring segment table base address register */
299 #define XHCI_RUN_ERSTBA(intr) ( 0x30 + ( (intr) << 5 ) )
300 
301 /** Event ring dequeue pointer register */
302 #define XHCI_RUN_ERDP(intr) ( 0x38 + ( (intr) << 5 ) )
303 
304 /** A transfer request block template */
306  /** Parameter */
308  /** Status */
310  /** Control */
312 };
313 
314 /** A transfer request block */
316  /** Reserved */
318  /** Reserved */
320  /** Flags */
322  /** Type */
324  /** Reserved */
326 } __attribute__ (( packed ));
327 
328 /** Transfer request block cycle bit flag */
329 #define XHCI_TRB_C 0x01
330 
331 /** Transfer request block toggle cycle bit flag */
332 #define XHCI_TRB_TC 0x02
333 
334 /** Transfer request block chain flag */
335 #define XHCI_TRB_CH 0x10
336 
337 /** Transfer request block interrupt on completion flag */
338 #define XHCI_TRB_IOC 0x20
339 
340 /** Transfer request block immediate data flag */
341 #define XHCI_TRB_IDT 0x40
342 
343 /** Transfer request block type */
344 #define XHCI_TRB_TYPE(type) ( (type) << 2 )
345 
346 /** Transfer request block type mask */
347 #define XHCI_TRB_TYPE_MASK XHCI_TRB_TYPE ( 0x3f )
348 
349 /** A normal transfer request block */
351  /** Data buffer */
353  /** Length */
355  /** Flags */
357  /** Type */
359  /** Reserved */
361 } __attribute__ (( packed ));
362 
363 /** A normal transfer request block */
364 #define XHCI_TRB_NORMAL XHCI_TRB_TYPE ( 1 )
365 
366 /** Construct TD size field */
367 #define XHCI_TD_SIZE(remaining) \
368  ( ( ( (remaining) <= 0xf ) ? remaining : 0xf ) << 17 )
369 
370 /** A setup stage transfer request block */
372  /** Setup packet */
374  /** Length */
376  /** Flags */
378  /** Type */
380  /** Transfer direction */
382  /** Reserved */
384 } __attribute__ (( packed ));
385 
386 /** A setup stage transfer request block */
387 #define XHCI_TRB_SETUP XHCI_TRB_TYPE ( 2 )
388 
389 /** Setup stage input data direction */
390 #define XHCI_SETUP_IN 3
391 
392 /** Setup stage output data direction */
393 #define XHCI_SETUP_OUT 2
394 
395 /** A data stage transfer request block */
397  /** Data buffer */
399  /** Length */
401  /** Flags */
403  /** Type */
405  /** Transfer direction */
407  /** Reserved */
409 } __attribute__ (( packed ));
410 
411 /** A data stage transfer request block */
412 #define XHCI_TRB_DATA XHCI_TRB_TYPE ( 3 )
413 
414 /** Input data direction */
415 #define XHCI_DATA_IN 0x01
416 
417 /** Output data direction */
418 #define XHCI_DATA_OUT 0x00
419 
420 /** A status stage transfer request block */
422  /** Reserved */
424  /** Reserved */
426  /** Flags */
428  /** Type */
430  /** Direction */
432  /** Reserved */
434 } __attribute__ (( packed ));
435 
436 /** A status stage transfer request block */
437 #define XHCI_TRB_STATUS XHCI_TRB_TYPE ( 4 )
438 
439 /** Input status direction */
440 #define XHCI_STATUS_IN 0x01
441 
442 /** Output status direction */
443 #define XHCI_STATUS_OUT 0x00
444 
445 /** A link transfer request block */
447  /** Next ring segment */
449  /** Reserved */
451  /** Flags */
453  /** Type */
455  /** Reserved */
457 } __attribute__ (( packed ));
458 
459 /** A link transfer request block */
460 #define XHCI_TRB_LINK XHCI_TRB_TYPE ( 6 )
461 
462 /** A no-op transfer request block */
463 #define XHCI_TRB_NOP XHCI_TRB_TYPE ( 8 )
464 
465 /** An enable slot transfer request block */
467  /** Reserved */
469  /** Reserved */
471  /** Flags */
473  /** Type */
475  /** Slot type */
477  /** Reserved */
479 } __attribute__ (( packed ));
480 
481 /** An enable slot transfer request block */
482 #define XHCI_TRB_ENABLE_SLOT XHCI_TRB_TYPE ( 9 )
483 
484 /** A disable slot transfer request block */
486  /** Reserved */
488  /** Reserved */
490  /** Flags */
492  /** Type */
494  /** Reserved */
496  /** Slot ID */
498 } __attribute__ (( packed ));
499 
500 /** A disable slot transfer request block */
501 #define XHCI_TRB_DISABLE_SLOT XHCI_TRB_TYPE ( 10 )
502 
503 /** A context transfer request block */
505  /** Input context */
507  /** Reserved */
509  /** Flags */
511  /** Type */
513  /** Reserved */
515  /** Slot ID */
517 } __attribute__ (( packed ));
518 
519 /** An address device transfer request block */
520 #define XHCI_TRB_ADDRESS_DEVICE XHCI_TRB_TYPE ( 11 )
521 
522 /** A configure endpoint transfer request block */
523 #define XHCI_TRB_CONFIGURE_ENDPOINT XHCI_TRB_TYPE ( 12 )
524 
525 /** An evaluate context transfer request block */
526 #define XHCI_TRB_EVALUATE_CONTEXT XHCI_TRB_TYPE ( 13 )
527 
528 /** A reset endpoint transfer request block */
530  /** Reserved */
532  /** Reserved */
534  /** Flags */
536  /** Type */
538  /** Endpoint ID */
540  /** Slot ID */
542 } __attribute__ (( packed ));
543 
544 /** A reset endpoint transfer request block */
545 #define XHCI_TRB_RESET_ENDPOINT XHCI_TRB_TYPE ( 14 )
546 
547 /** A stop endpoint transfer request block */
549  /** Reserved */
551  /** Reserved */
553  /** Flags */
555  /** Type */
557  /** Endpoint ID */
559  /** Slot ID */
561 } __attribute__ (( packed ));
562 
563 /** A stop endpoint transfer request block */
564 #define XHCI_TRB_STOP_ENDPOINT XHCI_TRB_TYPE ( 15 )
565 
566 /** A set transfer ring dequeue pointer transfer request block */
568  /** Dequeue pointer */
570  /** Reserved */
572  /** Flags */
574  /** Type */
576  /** Endpoint ID */
578  /** Slot ID */
580 } __attribute__ (( packed ));
581 
582 /** A set transfer ring dequeue pointer transfer request block */
583 #define XHCI_TRB_SET_TR_DEQUEUE_POINTER XHCI_TRB_TYPE ( 16 )
584 
585 /** A no-op command transfer request block */
586 #define XHCI_TRB_NOP_CMD XHCI_TRB_TYPE ( 23 )
587 
588 /** A transfer event transfer request block */
590  /** Transfer TRB pointer */
592  /** Residual transfer length */
594  /** Reserved */
596  /** Completion code */
598  /** Flags */
600  /** Type */
602  /** Endpoint ID */
604  /** Slot ID */
606 } __attribute__ (( packed ));
607 
608 /** A transfer event transfer request block */
609 #define XHCI_TRB_TRANSFER XHCI_TRB_TYPE ( 32 )
610 
611 /** A command completion event transfer request block */
613  /** Command TRB pointer */
615  /** Parameter */
617  /** Completion code */
619  /** Flags */
621  /** Type */
623  /** Virtual function ID */
625  /** Slot ID */
627 } __attribute__ (( packed ));
628 
629 /** A command completion event transfer request block */
630 #define XHCI_TRB_COMPLETE XHCI_TRB_TYPE ( 33 )
631 
632 /** xHCI completion codes */
634  /** Success */
636  /** Short packet */
638  /** Command ring stopped */
640 };
641 
642 /** A port status change transfer request block */
644  /** Reserved */
646  /** Port ID */
648  /** Reserved */
650  /** Completion code */
652  /** Flags */
654  /** Type */
656  /** Reserved */
658 } __attribute__ (( packed ));
659 
660 /** A port status change transfer request block */
661 #define XHCI_TRB_PORT_STATUS XHCI_TRB_TYPE ( 34 )
662 
663 /** A port status change transfer request block */
665  /** Reserved */
667  /** Reserved */
669  /** Completion code */
671  /** Flags */
673  /** Type */
675  /** Reserved */
677 } __attribute__ (( packed ));
678 
679 /** A port status change transfer request block */
680 #define XHCI_TRB_HOST_CONTROLLER XHCI_TRB_TYPE ( 37 )
681 
682 /** A transfer request block */
683 union xhci_trb {
684  /** Template */
686  /** Common fields */
688  /** Normal TRB */
690  /** Setup stage TRB */
692  /** Data stage TRB */
694  /** Status stage TRB */
696  /** Link TRB */
698  /** Enable slot TRB */
700  /** Disable slot TRB */
702  /** Input context TRB */
704  /** Reset endpoint TRB */
706  /** Stop endpoint TRB */
708  /** Set transfer ring dequeue pointer TRB */
710  /** Transfer event */
712  /** Command completion event */
714  /** Port status changed event */
716  /** Host controller event */
718 } __attribute__ (( packed ));
719 
720 /** An input control context */
722  /** Drop context flags */
724  /** Add context flags */
726  /** Reserved */
728  /** Configuration value */
730  /** Interface number */
732  /** Alternate setting */
734  /** Reserved */
736 } __attribute__ (( packed ));
737 
738 /** A slot context */
740  /** Device info */
742  /** Maximum exit latency */
744  /** Root hub port number */
746  /** Number of downstream ports */
748  /** TT hub slot ID */
750  /** TT port number */
752  /** Interrupter target */
754  /** USB address */
756  /** Reserved */
758  /** Slot state */
760  /** Reserved */
762 } __attribute__ (( packed ));
763 
764 /** Construct slot context device info */
765 #define XHCI_SLOT_INFO( entries, hub, speed, route ) \
766  ( ( (entries) << 27 ) | ( (hub) << 26 ) | ( (speed) << 20 ) | (route) )
767 
768 /** An endpoint context */
770  /** Endpoint state */
772  /** Stream configuration */
774  /** Polling interval */
776  /** Max ESIT payload high */
778  /** Endpoint type */
780  /** Maximum burst size */
782  /** Maximum packet size */
784  /** Transfer ring dequeue pointer */
786  /** Average TRB length */
788  /** Max ESIT payload low */
790  /** Reserved */
792 } __attribute__ (( packed ));
793 
794 /** Endpoint states */
796  /** Endpoint is disabled */
798  /** Endpoint is running */
800  /** Endpoint is halted due to a USB Halt condition */
802  /** Endpoint is stopped */
804  /** Endpoint is halted due to a TRB error */
806 };
807 
808 /** Endpoint state mask */
809 #define XHCI_ENDPOINT_STATE_MASK 0x07
810 
811 /** Endpoint type */
812 #define XHCI_EP_TYPE(type) ( (type) << 3 )
813 
814 /** Control endpoint type */
815 #define XHCI_EP_TYPE_CONTROL XHCI_EP_TYPE ( 4 )
816 
817 /** Input endpoint type */
818 #define XHCI_EP_TYPE_IN XHCI_EP_TYPE ( 4 )
819 
820 /** Periodic endpoint type */
821 #define XHCI_EP_TYPE_PERIODIC XHCI_EP_TYPE ( 1 )
822 
823 /** Endpoint dequeue cycle state */
824 #define XHCI_EP_DCS 0x00000001UL
825 
826 /** Control endpoint average TRB length */
827 #define XHCI_EP0_TRB_LEN 8
828 
829 /** An event ring segment */
831  /** Base address */
833  /** Number of TRBs */
835  /** Reserved */
837 } __attribute__ (( packed ));
838 
839 /** A transfer request block command/transfer ring */
841  /** Producer counter */
842  unsigned int prod;
843  /** Consumer counter */
844  unsigned int cons;
845  /** Ring size (log2) */
846  unsigned int shift;
847  /** Ring counter mask */
848  unsigned int mask;
849 
850  /** I/O buffers */
851  struct io_buffer **iobuf;
852 
853  /** Transfer request blocks */
854  union xhci_trb *trb;
855  /** Length of transfer request blocks */
856  size_t len;
857  /** DMA mapping */
858  struct dma_mapping map;
859  /** Link TRB (if applicable) */
861 
862  /** Doorbell register */
863  void *db;
864  /** Doorbell register value */
866 };
867 
868 /** An event ring */
870  /** Consumer counter */
871  unsigned int cons;
872  /** Event ring segment table */
874  /** Event ring segment table DMA mapping */
876  /** Transfer request blocks */
877  union xhci_trb *trb;
878  /** Transfer request blocks DMA mapping */
880 };
881 
882 /**
883  * Calculate doorbell register value
884  *
885  * @v target Doorbell target
886  * @v stream Doorbell stream ID
887  * @ret dbval Doorbell register value
888  */
889 #define XHCI_DBVAL( target, stream ) ( (target) | ( (stream) << 16 ) )
890 
891 /**
892  * Calculate space used in TRB ring
893  *
894  * @v ring TRB ring
895  * @ret fill Number of entries used
896  */
897 static inline __attribute__ (( always_inline )) unsigned int
898 xhci_ring_fill ( struct xhci_trb_ring *ring ) {
899 
900  return ( ring->prod - ring->cons );
901 }
902 
903 /**
904  * Calculate space remaining in TRB ring
905  *
906  * @v ring TRB ring
907  * @ret remaining Number of entries remaining
908  *
909  * xHCI does not allow us to completely fill a ring; there must be at
910  * least one free entry (excluding the Link TRB).
911  */
912 static inline __attribute__ (( always_inline )) unsigned int
914  unsigned int fill = xhci_ring_fill ( ring );
915 
916  /* We choose to utilise rings with ( 2^n + 1 ) entries, with
917  * the final entry being a Link TRB. The maximum fill level
918  * is therefore
919  *
920  * ( ( 2^n + 1 ) - 1 (Link TRB) - 1 (one slot always empty)
921  * == ( 2^n - 1 )
922  *
923  * which is therefore equal to the ring mask.
924  */
925  assert ( fill <= ring->mask );
926  return ( ring->mask - fill );
927 }
928 
929 /**
930  * Calculate physical address of most recently consumed TRB
931  *
932  * @v ring TRB ring
933  * @ret trb TRB physical address
934  */
935 static inline __attribute__ (( always_inline )) physaddr_t
937  unsigned int index = ( ( ring->cons - 1 ) & ring->mask );
938 
939  return virt_to_phys ( &ring->trb[index] );
940 }
941 
942 /** Slot context index */
943 #define XHCI_CTX_SLOT 0
944 
945 /** Calculate context index from USB endpoint address */
946 #define XHCI_CTX(address) \
947  ( (address) ? ( ( ( (address) & 0x0f ) << 1 ) | \
948  ( ( (address) & 0x80 ) >> 7 ) ) : 1 )
949 
950 /** Endpoint zero context index */
951 #define XHCI_CTX_EP0 XHCI_CTX ( 0x00 )
952 
953 /** End of contexts */
954 #define XHCI_CTX_END 32
955 
956 /** Device context index */
957 #define XHCI_DCI(ctx) ( (ctx) + 0 )
958 
959 /** Input context index */
960 #define XHCI_ICI(ctx) ( (ctx) + 1 )
961 
962 /** Number of TRBs (excluding Link TRB) in the command ring
963  *
964  * This is a policy decision.
965  */
966 #define XHCI_CMD_TRBS_LOG2 2
967 
968 /** Number of TRBs in the event ring
969  *
970  * This is a policy decision.
971  */
972 #define XHCI_EVENT_TRBS_LOG2 6
973 
974 /** Number of TRBs in a transfer ring
975  *
976  * This is a policy decision.
977  */
978 #define XHCI_TRANSFER_TRBS_LOG2 6
979 
980 /** Maximum time to wait for BIOS to release ownership
981  *
982  * This is a policy decision.
983  */
984 #define XHCI_USBLEGSUP_MAX_WAIT_MS 100
985 
986 /** Maximum time to wait for host controller to stop
987  *
988  * This is a policy decision.
989  */
990 #define XHCI_STOP_MAX_WAIT_MS 100
991 
992 /** Maximum time to wait for reset to complete
993  *
994  * This is a policy decision.
995  */
996 #define XHCI_RESET_MAX_WAIT_MS 500
997 
998 /** Maximum time to wait for a command to complete
999  *
1000  * The "address device" command involves waiting for a response to a
1001  * USB control transaction, and so we must wait for up to the 5000ms
1002  * that USB allows for devices to respond to control transactions.
1003  */
1004 #define XHCI_COMMAND_MAX_WAIT_MS USB_CONTROL_MAX_WAIT_MS
1005 
1006 /** Time to delay after aborting a command
1007  *
1008  * This is a policy decision
1009  */
1010 #define XHCI_COMMAND_ABORT_DELAY_MS 500
1011 
1012 /** Maximum time to wait for a port reset to complete
1013  *
1014  * This is a policy decision.
1015  */
1016 #define XHCI_PORT_RESET_MAX_WAIT_MS 500
1017 
1018 /** Intel PCH quirk */
1019 struct xhci_pch {
1020  /** USB2 port routing register original value */
1022  /** USB3 port SuperSpeed enable register original value */
1024 };
1025 
1026 /** Intel PCH quirk flag */
1027 #define XHCI_PCH 0x0001
1028 
1029 /** Intel PCH USB2 port routing register */
1030 #define XHCI_PCH_XUSB2PR 0xd0
1031 
1032 /** Intel PCH USB2 port routing mask register */
1033 #define XHCI_PCH_XUSB2PRM 0xd4
1034 
1035 /** Intel PCH SuperSpeed enable register */
1036 #define XHCI_PCH_USB3PSSEN 0xd8
1037 
1038 /** Intel PCH USB3 port routing mask register */
1039 #define XHCI_PCH_USB3PRM 0xdc
1040 
1041 /** Invalid protocol speed ID values quirk */
1042 #define XHCI_BAD_PSIV 0x0002
1043 
1044 /** Device context base address array */
1045 struct xhci_dcbaa {
1046  /** Context base addresses */
1048  /** DMA mapping */
1050 };
1051 
1052 /** Scratchpad buffer */
1054  /** Number of page-sized scratchpad buffers */
1055  unsigned int count;
1056  /** Scratchpad buffer area */
1058  /** Buffer DMA mapping */
1060  /** Scratchpad array */
1062  /** Array DMA mapping */
1064 };
1065 
1066 /** An xHCI device */
1067 struct xhci_device {
1068  /** Registers */
1069  void *regs;
1070  /** DMA device */
1071  struct dma_device *dma;
1072  /** Name */
1073  const char *name;
1074  /** Quirks */
1075  unsigned int quirks;
1076 
1077  /** Capability registers */
1078  void *cap;
1079  /** Operational registers */
1080  void *op;
1081  /** Runtime registers */
1082  void *run;
1083  /** Doorbell registers */
1084  void *db;
1085 
1086  /** Number of device slots */
1087  unsigned int slots;
1088  /** Number of interrupters */
1089  unsigned int intrs;
1090  /** Number of ports */
1091  unsigned int ports;
1092 
1093  /** 64-bit addressing capability */
1094  int addr64;
1095  /** Context size shift */
1096  unsigned int csz_shift;
1097  /** xHCI extended capabilities offset */
1098  unsigned int xecp;
1099 
1100  /** Page size */
1101  size_t pagesize;
1102 
1103  /** USB legacy support capability (if present and enabled) */
1104  unsigned int legacy;
1105 
1106  /** Device context base address array */
1108 
1109  /** Scratchpad buffer */
1111 
1112  /** Command ring */
1114  /** Event ring */
1116  /** Current command (if any) */
1118 
1119  /** Device slots, indexed by slot ID */
1120  struct xhci_slot **slot;
1121 
1122  /** USB bus */
1123  struct usb_bus *bus;
1124 
1125  /** Intel PCH quirk */
1126  struct xhci_pch pch;
1127 };
1128 
1129 /** An xHCI device slot */
1130 struct xhci_slot {
1131  /** xHCI device */
1133  /** USB device */
1134  struct usb_device *usb;
1135  /** Slot ID */
1136  unsigned int id;
1137  /** Slot context */
1139  /** DMA mapping */
1141  /** Route string */
1142  unsigned int route;
1143  /** Root hub port number */
1144  unsigned int port;
1145  /** Protocol speed ID */
1146  unsigned int psiv;
1147  /** Number of ports (if this device is a hub) */
1148  unsigned int ports;
1149  /** Transaction translator slot ID */
1150  unsigned int tt_id;
1151  /** Transaction translator port */
1152  unsigned int tt_port;
1153  /** Endpoints, indexed by context ID */
1155 };
1156 
1157 /** An xHCI endpoint */
1159  /** xHCI device */
1161  /** xHCI slot */
1162  struct xhci_slot *slot;
1163  /** USB endpoint */
1164  struct usb_endpoint *ep;
1165  /** Context index */
1166  unsigned int ctx;
1167  /** Endpoint type */
1168  unsigned int type;
1169  /** Endpoint interval */
1170  unsigned int interval;
1171  /** Endpoint context */
1173  /** Transfer ring */
1175 };
1176 
1177 #endif /* _IPXE_XHCI_H */
uint8_t intf
Interface number.
Definition: xhci.h:731
An endpoint context.
Definition: xhci.h:769
Short packet.
Definition: xhci.h:637
uint8_t burst
Maximum burst size.
Definition: xhci.h:781
#define __attribute__(x)
Definition: compiler.h:10
An event ring.
Definition: xhci.h:869
uint32_t reserved
Reserved.
Definition: xhci.h:836
A disable slot transfer request block.
Definition: xhci.h:485
uint32_t reserved_b
Reserved.
Definition: xhci.h:425
uint8_t type
Endpoint type.
Definition: xhci.h:779
unsigned short uint16_t
Definition: stdint.h:11
A status stage transfer request block.
Definition: xhci.h:421
struct xhci_trb_context context
Input context TRB.
Definition: xhci.h:703
uint64_t command
Command TRB pointer.
Definition: xhci.h:614
A transfer request block.
Definition: xhci.h:315
uint32_t dbval
Doorbell register value.
Definition: xhci.h:865
struct xhci_trb_common common
Common fields.
Definition: xhci.h:687
uint8_t flags
Flags.
Definition: xhci.h:510
unsigned int ports
Number of ports.
Definition: xhci.h:1091
struct xhci_dcbaa dcbaa
Device context base address array.
Definition: xhci.h:1107
uint8_t reserved
Reserved.
Definition: xhci.h:595
uint8_t direction
Direction.
Definition: xhci.h:431
uint64_t data
Data buffer.
Definition: xhci.h:352
static physaddr_t xhci_ring_consumed(struct xhci_trb_ring *ring)
Calculate physical address of most recently consumed TRB.
Definition: xhci.h:936
#define XHCI_CTX_END
End of contexts.
Definition: xhci.h:954
uint32_t reserved_b
Reserved.
Definition: xhci.h:533
uint8_t reserved_c
Reserved.
Definition: xhci.h:495
struct xhci_device * xhci
xHCI device
Definition: xhci.h:1132
unsigned int cons
Consumer counter.
Definition: xhci.h:844
void * run
Runtime registers.
Definition: xhci.h:1082
An xHCI device.
Definition: xhci.h:1067
A set transfer ring dequeue pointer transfer request block.
Definition: xhci.h:567
size_t len
Length of transfer request blocks.
Definition: xhci.h:856
void * regs
Registers.
Definition: xhci.h:1069
An input control context.
Definition: xhci.h:721
uint8_t reserved_b
Reserved.
Definition: xhci.h:735
unsigned int port
Root hub port number.
Definition: xhci.h:1144
A command-line command.
Definition: command.h:9
xhci_endpoint_state
Endpoint states.
Definition: xhci.h:795
uint8_t slot
Slot type.
Definition: xhci.h:476
static unsigned int xhci_ring_fill(struct xhci_trb_ring *ring)
Calculate space used in TRB ring.
Definition: xhci.h:898
A command completion event transfer request block.
Definition: xhci.h:612
struct dma_mapping segment_map
Event ring segment table DMA mapping.
Definition: xhci.h:875
uint8_t state
Endpoint state.
Definition: xhci.h:771
uint8_t reserved_a[3]
Reserved.
Definition: xhci.h:645
struct xhci_trb_transfer transfer
Transfer event.
Definition: xhci.h:711
A port status change transfer request block.
Definition: xhci.h:664
uint16_t trb_len
Average TRB length.
Definition: xhci.h:787
union xhci_trb * pending
Current command (if any)
Definition: xhci.h:1117
uint64_t reserved_a
Reserved.
Definition: xhci.h:423
struct xhci_endpoint * endpoint[XHCI_CTX_END]
Endpoints, indexed by context ID.
Definition: xhci.h:1154
uint8_t type
Type.
Definition: xhci.h:323
uint8_t flags
Flags.
Definition: xhci.h:356
struct dma_mapping map
DMA mapping.
Definition: xhci.h:858
xhci_completion_code
xHCI completion codes
Definition: xhci.h:633
uint8_t code
Completion code.
Definition: xhci.h:670
struct xhci_trb_disable_slot disable
Disable slot TRB.
Definition: xhci.h:701
uint16_t reserved_c
Reserved.
Definition: xhci.h:325
uint16_t reserved_c
Reserved.
Definition: xhci.h:657
unsigned int route
Route string.
Definition: xhci.h:1142
An enable slot transfer request block.
Definition: xhci.h:466
unsigned long long uint64_t
Definition: stdint.h:13
struct usb_bus * bus
USB bus.
Definition: xhci.h:1123
struct xhci_trb_enable_slot enable
Enable slot TRB.
Definition: xhci.h:699
uint8_t slot
Slot ID.
Definition: xhci.h:497
struct dma_mapping buffer_map
Buffer DMA mapping.
Definition: xhci.h:1059
struct xhci_trb_setup setup
Setup stage TRB.
Definition: xhci.h:691
unsigned int count
Number of page-sized scratchpad buffers.
Definition: xhci.h:1055
A data stage transfer request block.
Definition: xhci.h:396
uint8_t code
Completion code.
Definition: xhci.h:597
Intel PCH quirk.
Definition: xhci.h:1019
void * db
Doorbell register.
Definition: xhci.h:863
xhci_default_psi_value
Default PSI values.
Definition: xhci.h:143
Full speed (12Mbps)
Definition: xhci.h:145
uint8_t slot
Slot ID.
Definition: xhci.h:626
uint8_t flags
Flags.
Definition: xhci.h:321
An xHCI endpoint.
Definition: xhci.h:1158
uint8_t type
Type.
Definition: xhci.h:537
uint8_t direction
Transfer direction.
Definition: xhci.h:381
unsigned int psiv
Protocol speed ID.
Definition: xhci.h:1146
Success.
Definition: xhci.h:635
uint8_t reserved_b[3]
Reserved.
Definition: xhci.h:668
uint8_t endpoint
Endpoint ID.
Definition: xhci.h:603
static __always_inline unsigned long virt_to_phys(volatile const void *addr)
Convert virtual address to a physical address.
Definition: uaccess.h:287
Access to external ("user") memory.
uint64_t dequeue
Dequeue pointer.
Definition: xhci.h:569
unsigned int slots
Number of device slots.
Definition: xhci.h:1087
uint32_t add
Add context flags.
Definition: xhci.h:725
uint64_t dequeue
Transfer ring dequeue pointer.
Definition: xhci.h:785
struct xhci_scratchpad scratch
Scratchpad buffer.
Definition: xhci.h:1110
static unsigned int xhci_ring_remaining(struct xhci_trb_ring *ring)
Calculate space remaining in TRB ring.
Definition: xhci.h:913
uint8_t esit_high
Max ESIT payload high.
Definition: xhci.h:777
uint64_t * array
Scratchpad array.
Definition: xhci.h:1061
uint8_t address
USB address.
Definition: xhci.h:755
uint8_t ports
Number of downstream ports.
Definition: xhci.h:747
Endpoint is halted due to a TRB error.
Definition: xhci.h:805
unsigned int type
Endpoint type.
Definition: xhci.h:1168
struct xhci_trb_host_controller host
Host controller event.
Definition: xhci.h:717
uint64_t input
Input context.
Definition: xhci.h:506
uint8_t type
Type.
Definition: xhci.h:404
uint32_t len
Length.
Definition: xhci.h:400
uint8_t type
Type.
Definition: xhci.h:655
uint8_t type
Type.
Definition: xhci.h:674
uint16_t reserved_a
Reserved.
Definition: xhci.h:757
A USB endpoint.
Definition: usb.h:389
struct dma_mapping array_map
Array DMA mapping.
Definition: xhci.h:1063
uint8_t endpoint
Endpoint ID.
Definition: xhci.h:558
uint32_t reserved_b
Reserved.
Definition: xhci.h:470
union xhci_trb * trb
Transfer request blocks.
Definition: xhci.h:854
Endpoint is halted due to a USB Halt condition.
Definition: xhci.h:801
uint8_t slot
Slot ID.
Definition: xhci.h:605
uint8_t reserved_c
Reserved.
Definition: xhci.h:478
uint8_t flags
Flags.
Definition: xhci.h:620
struct xhci_pch pch
Intel PCH quirk.
Definition: xhci.h:1126
uint8_t slot
Slot ID.
Definition: xhci.h:541
A reset endpoint transfer request block.
Definition: xhci.h:529
Assertions.
union xhci_trb * trb
Transfer request blocks.
Definition: xhci.h:877
uint8_t slot
Slot ID.
Definition: xhci.h:560
uint32_t drop
Drop context flags.
Definition: xhci.h:723
uint8_t alt
Alternate setting.
Definition: xhci.h:733
assert((readw(&hdr->flags) &(GTF_reading|GTF_writing))==0)
unsigned int ports
Number of ports (if this device is a hub)
Definition: xhci.h:1148
uint64_t reserved_a
Reserved.
Definition: xhci.h:317
uint8_t reserved_c
Reserved.
Definition: xhci.h:433
struct xhci_trb_stop_endpoint stop
Stop endpoint TRB.
Definition: xhci.h:707
struct xhci_trb_template template
Template.
Definition: xhci.h:685
unsigned int ctx
Context index.
Definition: xhci.h:1166
uint32_t len
Length.
Definition: xhci.h:375
struct usb_device * usb
USB device.
Definition: xhci.h:1134
uint32_t xusb2pr
USB2 port routing register original value.
Definition: xhci.h:1021
uint8_t vf
Virtual function ID.
Definition: xhci.h:624
uint64_t reserved_a
Reserved.
Definition: xhci.h:550
uint8_t flags
Flags.
Definition: xhci.h:554
uint8_t port
Root hub port number.
Definition: xhci.h:745
uint64_t reserved_a
Reserved.
Definition: xhci.h:666
uint64_t data
Data buffer.
Definition: xhci.h:398
A setup stage transfer request block.
Definition: xhci.h:371
uint16_t mtu
Maximum packet size.
Definition: xhci.h:783
A transfer event transfer request block.
Definition: xhci.h:589
uint8_t direction
Transfer direction.
Definition: xhci.h:406
Endpoint is disabled.
Definition: xhci.h:797
uint8_t flags
Flags.
Definition: xhci.h:491
uint8_t type
Type.
Definition: xhci.h:379
uint32_t usb3pssen
USB3 port SuperSpeed enable register original value.
Definition: xhci.h:1023
uint8_t flags
Flags.
Definition: xhci.h:599
uint8_t config
Configuration value.
Definition: xhci.h:729
uint32_t info
Device info.
Definition: xhci.h:741
FILE_LICENCE(GPL2_OR_LATER_OR_UBDL)
struct xhci_slot * slot
xHCI slot
Definition: xhci.h:1162
struct xhci_endpoint_context * context
Endpoint context.
Definition: xhci.h:1172
A USB device.
Definition: usb.h:708
uint8_t type
Type.
Definition: xhci.h:429
uint8_t flags
Flags.
Definition: xhci.h:377
uint32_t reserved_b
Reserved.
Definition: xhci.h:319
An xHCI device slot.
Definition: xhci.h:1130
uint32_t reserved_a[5]
Reserved.
Definition: xhci.h:727
A context transfer request block.
Definition: xhci.h:504
uint16_t reserved_c
Reserved.
Definition: xhci.h:676
uint64_t reserved_a
Reserved.
Definition: xhci.h:468
uint32_t status
Status.
Definition: xhci.h:309
uint64_t base
Base address.
Definition: xhci.h:832
A transfer request block.
Definition: xhci.h:683
const char * name
Name.
Definition: xhci.h:1073
PCI bus.
uint8_t slot
Slot ID.
Definition: xhci.h:579
uint8_t type
Type.
Definition: xhci.h:622
unsigned int id
Slot ID.
Definition: xhci.h:1136
Endpoint is stopped.
Definition: xhci.h:803
uint64_t * context
Context base addresses.
Definition: xhci.h:1047
Device context base address array.
Definition: xhci.h:1045
unsigned char uint8_t
Definition: stdint.h:10
struct xhci_trb_data data
Data stage TRB.
Definition: xhci.h:693
unsigned int intrs
Number of interrupters.
Definition: xhci.h:1089
unsigned int tt_id
Transaction translator slot ID.
Definition: xhci.h:1150
unsigned int prod
Producer counter.
Definition: xhci.h:842
uint8_t type
Type.
Definition: xhci.h:493
struct xhci_trb_complete complete
Command completion event.
Definition: xhci.h:713
struct xhci_trb_set_tr_dequeue_pointer dequeue
Set transfer ring dequeue pointer TRB.
Definition: xhci.h:709
uint8_t type
Type.
Definition: xhci.h:358
unsigned int uint32_t
Definition: stdint.h:12
A USB setup data packet.
Definition: usb.h:68
Scratchpad buffer.
Definition: xhci.h:1053
void * cap
Capability registers.
Definition: xhci.h:1078
unsigned int xecp
xHCI extended capabilities offset
Definition: xhci.h:1098
A normal transfer request block.
Definition: xhci.h:350
int addr64
64-bit addressing capability
Definition: xhci.h:1094
A port status change transfer request block.
Definition: xhci.h:643
uint8_t flags
Flags.
Definition: xhci.h:472
uint8_t port
Port ID.
Definition: xhci.h:647
struct xhci_trb_normal normal
Normal TRB.
Definition: xhci.h:689
uint8_t stream
Stream configuration.
Definition: xhci.h:773
userptr_t buffer
Scratchpad buffer area.
Definition: xhci.h:1057
unsigned long physaddr_t
Definition: stdint.h:20
uint64_t reserved_a
Reserved.
Definition: xhci.h:531
Endpoint is running.
Definition: xhci.h:799
uint8_t type
Type.
Definition: xhci.h:556
struct xhci_trb_reset_endpoint reset
Reset endpoint TRB.
Definition: xhci.h:705
uint32_t reserved
Reserved.
Definition: xhci.h:571
uint8_t code
Completion code.
Definition: xhci.h:651
Command ring stopped.
Definition: xhci.h:639
uint8_t flags
Flags.
Definition: xhci.h:653
uint8_t tt_id
TT hub slot ID.
Definition: xhci.h:749
struct usb_endpoint * ep
USB endpoint.
Definition: xhci.h:1164
uint8_t flags
Flags.
Definition: xhci.h:535
uint32_t control
Control.
Definition: xhci.h:311
uint64_t reserved_a
Reserved.
Definition: xhci.h:487
struct xhci_event_ring_segment * segment
Event ring segment table.
Definition: xhci.h:873
size_t pagesize
Page size.
Definition: xhci.h:1101
Universal Serial Bus (USB)
uint16_t latency
Maximum exit latency.
Definition: xhci.h:743
uint16_t intr
Interrupter target.
Definition: xhci.h:753
A stop endpoint transfer request block.
Definition: xhci.h:548
unsigned int mask
Ring counter mask.
Definition: xhci.h:848
uint8_t interval
Polling interval.
Definition: xhci.h:775
uint8_t reserved_b[7]
Reserved.
Definition: xhci.h:649
uint8_t tt_port
TT port number.
Definition: xhci.h:751
uint32_t reserved_b[4]
Reserved.
Definition: xhci.h:761
struct dma_mapping map
DMA mapping.
Definition: xhci.h:1049
uint8_t state
Slot state.
Definition: xhci.h:759
uint32_t reserved_b
Reserved.
Definition: xhci.h:489
struct io_buffer ** iobuf
I/O buffers.
Definition: xhci.h:851
uint32_t len
Length.
Definition: xhci.h:354
unsigned int cons
Consumer counter.
Definition: xhci.h:871
struct xhci_trb_ring ring
Transfer ring.
Definition: xhci.h:1174
unsigned int tt_port
Transaction translator port.
Definition: xhci.h:1152
uint8_t fill
Length pair.
Definition: deflate.h:12
struct xhci_slot_context * context
Slot context.
Definition: xhci.h:1138
struct dma_mapping map
DMA mapping.
Definition: xhci.h:1140
struct xhci_trb_port_status port
Port status changed event.
Definition: xhci.h:715
struct dma_device * dma
DMA device.
Definition: xhci.h:1071
uint8_t flags
Flags.
Definition: xhci.h:402
uint16_t residual
Residual transfer length.
Definition: xhci.h:593
Super speed.
Definition: xhci.h:151
uint8_t flags
Flags.
Definition: xhci.h:427
unsigned int legacy
USB legacy support capability (if present and enabled)
Definition: xhci.h:1104
struct xhci_trb_link * link
Link TRB (if applicable)
Definition: xhci.h:860
Low speed (1.5Mbps)
Definition: xhci.h:147
unsigned int shift
Ring size (log2)
Definition: xhci.h:846
A transfer request block command/transfer ring.
Definition: xhci.h:840
struct xhci_trb_status status
Status stage TRB.
Definition: xhci.h:695
uint16_t reserved
Reserved.
Definition: xhci.h:360
uint8_t type
Type.
Definition: xhci.h:601
uint32_t reserved[3]
Reserved.
Definition: xhci.h:791
A form parameter.
Definition: params.h:28
uint64_t transfer
Transfer TRB pointer.
Definition: xhci.h:591
unsigned int csz_shift
Context size shift.
Definition: xhci.h:1096
struct usb_setup_packet packet
Setup packet.
Definition: xhci.h:373
void * db
Doorbell registers.
Definition: xhci.h:1084
uint8_t reserved
Reserved.
Definition: xhci.h:383
unsigned int interval
Endpoint interval.
Definition: xhci.h:1170
uint8_t endpoint
Endpoint ID.
Definition: xhci.h:539
uint64_t index
Index of the first segment within the content.
Definition: pccrc.h:21
uint8_t code
Completion code.
Definition: xhci.h:618
uint8_t reserved
Reserved.
Definition: xhci.h:408
uint16_t esit_low
Max ESIT payload low.
Definition: xhci.h:789
struct xhci_trb_link link
Link TRB.
Definition: xhci.h:697
struct xhci_slot ** slot
Device slots, indexed by slot ID.
Definition: xhci.h:1120
uint32_t count
Number of TRBs.
Definition: xhci.h:834
High speed (480Mbps)
Definition: xhci.h:149
A DMA mapping.
Definition: dma.h:32
A transfer request block template.
Definition: xhci.h:305
unsigned int quirks
Quirks.
Definition: xhci.h:1075
uint64_t parameter
Parameter.
Definition: xhci.h:307
struct xhci_device * xhci
xHCI device
Definition: xhci.h:1160
struct xhci_event_ring event
Event ring.
Definition: xhci.h:1115
A USB bus.
Definition: usb.h:951
void * op
Operational registers.
Definition: xhci.h:1080
uint8_t type
Type.
Definition: xhci.h:474
A slot context.
Definition: xhci.h:739
uint8_t endpoint
Endpoint ID.
Definition: xhci.h:577
uint8_t flags
Flags.
Definition: xhci.h:672
uint8_t reserved_b
Reserved.
Definition: xhci.h:514
uint8_t type
Type.
Definition: xhci.h:512
unsigned long userptr_t
A pointer to a user buffer.
Definition: uaccess.h:33
An event ring segment.
Definition: xhci.h:830
uint8_t slot
Slot ID.
Definition: xhci.h:516
struct dma_mapping trb_map
Transfer request blocks DMA mapping.
Definition: xhci.h:879
A DMA-capable device.
Definition: dma.h:47
uint32_t reserved_a
Reserved.
Definition: xhci.h:508
A persistent I/O buffer.
Definition: iobuf.h:33
uint32_t reserved_b
Reserved.
Definition: xhci.h:552