PCI bus. More...

#include <stdint.h>
#include <ipxe/device.h>
#include <ipxe/tables.h>
#include <ipxe/dma.h>
#include <ipxe/pci_io.h>

Data Structures
struct	pci_device_id
	A PCI device ID list entry. More...

struct	pci_class_id
	A PCI class ID. More...

struct	pci_device
	A PCI device. More...

struct	pci_driver
	A PCI driver. More...

Macros
#define	PCI_VENDOR_ID 0x00
	PCI vendor ID. More...

#define	PCI_DEVICE_ID 0x02
	PCI device ID. More...

#define	PCI_COMMAND 0x04
	PCI command. More...

#define	PCI_COMMAND_IO 0x0001
	I/O space. More...

#define	PCI_COMMAND_MEM 0x0002
	Memory space. More...

#define	PCI_COMMAND_MASTER 0x0004
	Bus master. More...

#define	PCI_COMMAND_INVALIDATE 0x0010
	Mem. More...

#define	PCI_COMMAND_PARITY 0x0040
	Parity error response. More...

#define	PCI_COMMAND_SERR 0x0100
	SERR# enable. More...

#define	PCI_COMMAND_INTX_DISABLE 0x0400
	Interrupt disable. More...

#define	PCI_STATUS 0x06
	PCI status. More...

#define	PCI_STATUS_CAP_LIST 0x0010
	Capabilities list. More...

#define	PCI_STATUS_PARITY 0x0100
	Master data parity error. More...

#define	PCI_STATUS_REC_TARGET_ABORT 0x1000
	Received target abort. More...

#define	PCI_STATUS_REC_MASTER_ABORT 0x2000
	Received master abort. More...

#define	PCI_STATUS_SIG_SYSTEM_ERROR 0x4000
	Signalled system error. More...

#define	PCI_STATUS_DETECTED_PARITY 0x8000
	Detected parity error. More...

#define	PCI_REVISION 0x08
	PCI revision. More...

#define	PCI_CACHE_LINE_SIZE 0x0c
	PCI cache line size. More...

#define	PCI_LATENCY_TIMER 0x0d
	PCI latency timer. More...

#define	PCI_HEADER_TYPE 0x0e
	PCI header type. More...

#define	PCI_HEADER_TYPE_NORMAL 0x00
	Normal header. More...

#define	PCI_HEADER_TYPE_BRIDGE 0x01
	PCI-to-PCI bridge header. More...

#define	PCI_HEADER_TYPE_CARDBUS 0x02
	CardBus header. More...

#define	PCI_HEADER_TYPE_MASK 0x7f
	Header type mask. More...

#define	PCI_HEADER_TYPE_MULTI 0x80
	Multi-function device. More...

#define	PCI_BASE_ADDRESS(n) ( 0x10 + ( 4 * (n) ) )
	PCI base address registers. More...

#define	PCI_BASE_ADDRESS_0 PCI_BASE_ADDRESS ( 0 )

#define	PCI_BASE_ADDRESS_1 PCI_BASE_ADDRESS ( 1 )

#define	PCI_BASE_ADDRESS_2 PCI_BASE_ADDRESS ( 2 )

#define	PCI_BASE_ADDRESS_3 PCI_BASE_ADDRESS ( 3 )

#define	PCI_BASE_ADDRESS_4 PCI_BASE_ADDRESS ( 4 )

#define	PCI_BASE_ADDRESS_5 PCI_BASE_ADDRESS ( 5 )

#define	PCI_BASE_ADDRESS_SPACE_IO 0x00000001UL
	I/O BAR. More...

#define	PCI_BASE_ADDRESS_IO_MASK 0x00000003UL
	I/O BAR mask. More...

#define	PCI_BASE_ADDRESS_MEM_TYPE_64 0x00000004UL
	64-bit memory More...

#define	PCI_BASE_ADDRESS_MEM_TYPE_MASK 0x00000006UL
	Memory type mask. More...

#define	PCI_BASE_ADDRESS_MEM_MASK 0x0000000fUL
	Memory BAR mask. More...

#define	PCI_SUBSYSTEM_VENDOR_ID 0x2c
	PCI subsystem vendor ID. More...

#define	PCI_SUBSYSTEM_ID 0x2e
	PCI subsystem ID. More...

#define	PCI_ROM_ADDRESS 0x30
	PCI expansion ROM base address. More...

#define	PCI_CAPABILITY_LIST 0x34
	PCI capabilities pointer. More...

#define	PCI_CB_CAPABILITY_LIST 0x14
	CardBus capabilities pointer. More...

#define	PCI_INTERRUPT_LINE 0x3c
	PCI interrupt line. More...

#define	PCI_CAP_ID 0x00
	Capability ID. More...

#define	PCI_CAP_ID_PM 0x01
	Power management. More...

#define	PCI_CAP_ID_VPD 0x03
	Vital product data. More...

#define	PCI_CAP_ID_VNDR 0x09
	Vendor-specific. More...

#define	PCI_CAP_ID_EXP 0x10
	PCI Express. More...

#define	PCI_CAP_ID_MSIX 0x11
	MSI-X. More...

#define	PCI_CAP_ID_EA 0x14
	Enhanced Allocation. More...

#define	PCI_CAP_NEXT 0x01
	Next capability. More...

#define	PCI_PM_CTRL 0x04
	Power management control and status. More...

#define	PCI_PM_CTRL_STATE_MASK 0x0003
	Current power state. More...

#define	PCI_PM_CTRL_PME_ENABLE 0x0100
	PME pin enable. More...

#define	PCI_PM_CTRL_PME_STATUS 0x8000
	PME pin status. More...

#define	PCI_EXP_DEVCTL 0x08
	PCI Express. More...

#define	PCI_EXP_DEVCTL_FLR 0x8000
	Function level reset. More...

#define	PCI_MSIX_CTRL 0x02
	MSI-X interrupts. More...

#define	PCI_MSIX_CTRL_ENABLE 0x8000
	Enable MSI-X. More...

#define	PCI_MSIX_CTRL_MASK 0x4000
	Mask all interrupts. More...

#define	PCI_MSIX_CTRL_SIZE(x) ( (x) & 0x07ff )
	Table size. More...

#define	PCI_MSIX_DESC_TABLE 0x04

#define	PCI_MSIX_DESC_PBA 0x08

#define	PCI_MSIX_DESC_BIR(x) ( (x) & 0x00000007 )
	BAR index. More...

#define	PCI_MSIX_DESC_OFFSET(x) ( (x) & 0xfffffff8 )
	BAR offset. More...

#define	PCI_ERR_UNCOR_STATUS 0x04
	Uncorrectable error status. More...

#define	PCI_CLASS_NETWORK 0x02
	Network controller. More...

#define	PCI_CLASS_BRIDGE 0x06
	Bridge device. More...

#define	PCI_CLASS_BRIDGE_PCI 0x04
	PCI-to-PCI bridge. More...

#define	PCI_CLASS_SERIAL 0x0c
	Serial bus controller. More...

#define	PCI_CLASS_SERIAL_USB 0x03
	USB controller. More...

#define	PCI_CLASS_SERIAL_USB_UHCI 0x00
	UHCI USB controller. More...

#define	PCI_CLASS_SERIAL_USB_OHCI 0x10
	OHCI USB controller. More...

#define	PCI_CLASS_SERIAL_USB_EHCI 0x20
	ECHI USB controller. More...

#define	PCI_CLASS_SERIAL_USB_XHCI 0x30
	xHCI USB controller More...

#define	PCI_PRIMARY 0x18
	Primary bus number. More...

#define	PCI_SECONDARY 0x19
	Secondary bus number. More...

#define	PCI_SUBORDINATE 0x1a
	Subordinate bus number. More...

#define	PCI_MEM_BASE 0x20
	Memory base and limit. More...

#define	PCI_MEM_LIMIT 0x22

#define	PCI_MEM_MASK 0x000f

#define	PCI_CLASS(base, sub, progif)
	Construct PCI class. More...

#define	PCI_EXP_FLR_DELAY_MS 100
	PCI Express function level reset delay (in ms) More...

#define	PCI_ANY_ID 0xffff
	Match-anything ID. More...

#define	PCI_CLASS_ID(base, sub, progif)
	Construct PCI class ID. More...

#define	PCI_DRIVERS __table ( struct pci_driver, "pci_drivers" )
	PCI driver table. More...

#define	__pci_driver __table_entry ( PCI_DRIVERS, 01 )
	Declare a PCI driver. More...

#define	__pci_driver_fallback __table_entry ( PCI_DRIVERS, 02 )
	Declare a fallback PCI driver. More...

#define	PCI_SEG(busdevfn) ( ( (busdevfn) >> 16 ) & 0xffff )

#define	PCI_BUS(busdevfn) ( ( (busdevfn) >> 8 ) & 0xff )

#define	PCI_SLOT(busdevfn) ( ( (busdevfn) >> 3 ) & 0x1f )

#define	PCI_FUNC(busdevfn) ( ( (busdevfn) >> 0 ) & 0x07 )

#define	PCI_FIRST_FUNC(busdevfn) ( (busdevfn) & ~0x07 )

#define	PCI_LAST_FUNC(busdevfn) ( (busdevfn) \| 0x07 )

#define	PCI_BASE_CLASS(class) ( (class) >> 16 )

#define	PCI_SUB_CLASS(class) ( ( (class) >> 8 ) & 0xff )

#define	PCI_PROG_INTF(class) ( (class) & 0xff )

#define	PCI_ID(_vendor, _device, _name, _description, _data)

#define	PCI_ROM(_vendor, _device, _name, _description, _data) PCI_ID( _vendor, _device, _name, _description, _data )

#define	PCI_FMT "%04x:%02x:%02x.%x"
	PCI device debug message format. More...

#define	PCI_ARGS(pci)
	PCI device debug message arguments. More...

Functions
	FILE_LICENCE (GPL2_OR_LATER_OR_UBDL)

void	adjust_pci_device (struct pci_device *pci)
	Enable PCI device. More...

unsigned long	pci_bar_start (struct pci_device *pci, unsigned int reg)
	Find the start of a PCI BAR. More...

int	pci_read_config (struct pci_device *pci)
	Read PCI device configuration. More...

int	pci_find_next (struct pci_device pci, uint32_t busdevfn)
	Find next device on PCI bus. More...

int	pci_find_driver (struct pci_device *pci)
	Find driver for PCI device. More...

int	pci_probe (struct pci_device *pci)
	Probe a PCI device. More...

void	pci_remove (struct pci_device *pci)
	Remove a PCI device. More...

int	pci_find_capability (struct pci_device *pci, int capability)
	Look for a PCI capability. More...

int	pci_find_next_capability (struct pci_device *pci, int pos, int capability)
	Look for another PCI capability. More...

unsigned long	pci_bar_size (struct pci_device *pci, unsigned int reg)
	Find the size of a PCI BAR. More...

void	pci_reset (struct pci_device *pci, unsigned int exp)
	Perform PCI Express function-level reset (FLR) More...

static void	pci_init (struct pci_device *pci, unsigned int busdevfn)
	Initialise PCI device. More...

static void	pci_set_driver (struct pci_device pci, struct pci_driver driver, struct pci_device_id *id)
	Set PCI driver. More...

static void	pci_set_drvdata (struct pci_device pci, void priv)
	Set PCI driver-private data. More...

static void *	pci_get_drvdata (struct pci_device *pci)
	Get PCI driver-private data. More...

Variables
struct pci_device_id	__attribute__

Detailed Description

PCI bus.

Definition in file pci.h.

Macro Definition Documentation

◆ PCI_VENDOR_ID

#define PCI_VENDOR_ID 0x00

PCI vendor ID.

Definition at line 19 of file pci.h.

◆ PCI_DEVICE_ID

#define PCI_DEVICE_ID 0x02

PCI device ID.

Definition at line 22 of file pci.h.

◆ PCI_COMMAND

#define PCI_COMMAND 0x04

PCI command.

Definition at line 25 of file pci.h.

◆ PCI_COMMAND_IO

#define PCI_COMMAND_IO 0x0001

I/O space.

Definition at line 26 of file pci.h.

◆ PCI_COMMAND_MEM

#define PCI_COMMAND_MEM 0x0002

Memory space.

Definition at line 27 of file pci.h.

◆ PCI_COMMAND_MASTER

#define PCI_COMMAND_MASTER 0x0004

Bus master.

Definition at line 28 of file pci.h.

◆ PCI_COMMAND_INVALIDATE

#define PCI_COMMAND_INVALIDATE 0x0010

Mem.

write & invalidate

Definition at line 29 of file pci.h.

◆ PCI_COMMAND_PARITY

#define PCI_COMMAND_PARITY 0x0040

Parity error response.

Definition at line 30 of file pci.h.

◆ PCI_COMMAND_SERR

#define PCI_COMMAND_SERR 0x0100

SERR# enable.

Definition at line 31 of file pci.h.

◆ PCI_COMMAND_INTX_DISABLE

#define PCI_COMMAND_INTX_DISABLE 0x0400

Interrupt disable.

Definition at line 32 of file pci.h.

◆ PCI_STATUS

#define PCI_STATUS 0x06

PCI status.

Definition at line 35 of file pci.h.

◆ PCI_STATUS_CAP_LIST

#define PCI_STATUS_CAP_LIST 0x0010

Capabilities list.

Definition at line 36 of file pci.h.

◆ PCI_STATUS_PARITY

#define PCI_STATUS_PARITY 0x0100

Master data parity error.

Definition at line 37 of file pci.h.

◆ PCI_STATUS_REC_TARGET_ABORT

#define PCI_STATUS_REC_TARGET_ABORT 0x1000

Received target abort.

Definition at line 38 of file pci.h.

◆ PCI_STATUS_REC_MASTER_ABORT

#define PCI_STATUS_REC_MASTER_ABORT 0x2000

Received master abort.

Definition at line 39 of file pci.h.

◆ PCI_STATUS_SIG_SYSTEM_ERROR

#define PCI_STATUS_SIG_SYSTEM_ERROR 0x4000

Signalled system error.

Definition at line 40 of file pci.h.

◆ PCI_STATUS_DETECTED_PARITY

#define PCI_STATUS_DETECTED_PARITY 0x8000

Detected parity error.

Definition at line 41 of file pci.h.

◆ PCI_REVISION

#define PCI_REVISION 0x08

PCI revision.

Definition at line 44 of file pci.h.

◆ PCI_CACHE_LINE_SIZE

#define PCI_CACHE_LINE_SIZE 0x0c

PCI cache line size.

Definition at line 47 of file pci.h.

◆ PCI_LATENCY_TIMER

#define PCI_LATENCY_TIMER 0x0d

PCI latency timer.

Definition at line 50 of file pci.h.

◆ PCI_HEADER_TYPE

#define PCI_HEADER_TYPE 0x0e

PCI header type.

Definition at line 53 of file pci.h.

◆ PCI_HEADER_TYPE_NORMAL

#define PCI_HEADER_TYPE_NORMAL 0x00

Normal header.

Definition at line 54 of file pci.h.

◆ PCI_HEADER_TYPE_BRIDGE

#define PCI_HEADER_TYPE_BRIDGE 0x01

PCI-to-PCI bridge header.

Definition at line 55 of file pci.h.

◆ PCI_HEADER_TYPE_CARDBUS

#define PCI_HEADER_TYPE_CARDBUS 0x02

CardBus header.

Definition at line 56 of file pci.h.

◆ PCI_HEADER_TYPE_MASK

#define PCI_HEADER_TYPE_MASK 0x7f

Header type mask.

Definition at line 57 of file pci.h.

◆ PCI_HEADER_TYPE_MULTI

#define PCI_HEADER_TYPE_MULTI 0x80

Multi-function device.

Definition at line 58 of file pci.h.

◆ PCI_BASE_ADDRESS

#define PCI_BASE_ADDRESS ( n ) ( 0x10 + ( 4 * (n) ) )

PCI base address registers.

Definition at line 61 of file pci.h.

◆ PCI_BASE_ADDRESS_0

#define PCI_BASE_ADDRESS_0 PCI_BASE_ADDRESS ( 0 )

Definition at line 62 of file pci.h.

◆ PCI_BASE_ADDRESS_1

#define PCI_BASE_ADDRESS_1 PCI_BASE_ADDRESS ( 1 )

Definition at line 63 of file pci.h.

◆ PCI_BASE_ADDRESS_2

#define PCI_BASE_ADDRESS_2 PCI_BASE_ADDRESS ( 2 )

Definition at line 64 of file pci.h.

◆ PCI_BASE_ADDRESS_3

#define PCI_BASE_ADDRESS_3 PCI_BASE_ADDRESS ( 3 )

Definition at line 65 of file pci.h.

◆ PCI_BASE_ADDRESS_4

#define PCI_BASE_ADDRESS_4 PCI_BASE_ADDRESS ( 4 )

Definition at line 66 of file pci.h.

◆ PCI_BASE_ADDRESS_5

#define PCI_BASE_ADDRESS_5 PCI_BASE_ADDRESS ( 5 )

Definition at line 67 of file pci.h.

◆ PCI_BASE_ADDRESS_SPACE_IO

#define PCI_BASE_ADDRESS_SPACE_IO 0x00000001UL

I/O BAR.

Definition at line 68 of file pci.h.

◆ PCI_BASE_ADDRESS_IO_MASK

#define PCI_BASE_ADDRESS_IO_MASK 0x00000003UL

I/O BAR mask.

Definition at line 69 of file pci.h.

◆ PCI_BASE_ADDRESS_MEM_TYPE_64

#define PCI_BASE_ADDRESS_MEM_TYPE_64 0x00000004UL

64-bit memory

Definition at line 70 of file pci.h.

◆ PCI_BASE_ADDRESS_MEM_TYPE_MASK

#define PCI_BASE_ADDRESS_MEM_TYPE_MASK 0x00000006UL

Memory type mask.

Definition at line 71 of file pci.h.

◆ PCI_BASE_ADDRESS_MEM_MASK

#define PCI_BASE_ADDRESS_MEM_MASK 0x0000000fUL

Memory BAR mask.

Definition at line 72 of file pci.h.

◆ PCI_SUBSYSTEM_VENDOR_ID

#define PCI_SUBSYSTEM_VENDOR_ID 0x2c

PCI subsystem vendor ID.

Definition at line 75 of file pci.h.

◆ PCI_SUBSYSTEM_ID

#define PCI_SUBSYSTEM_ID 0x2e

PCI subsystem ID.

Definition at line 78 of file pci.h.

◆ PCI_ROM_ADDRESS

#define PCI_ROM_ADDRESS 0x30

PCI expansion ROM base address.

Definition at line 81 of file pci.h.

◆ PCI_CAPABILITY_LIST

#define PCI_CAPABILITY_LIST 0x34

PCI capabilities pointer.

Definition at line 84 of file pci.h.

◆ PCI_CB_CAPABILITY_LIST

#define PCI_CB_CAPABILITY_LIST 0x14

CardBus capabilities pointer.

Definition at line 87 of file pci.h.

◆ PCI_INTERRUPT_LINE

#define PCI_INTERRUPT_LINE 0x3c

PCI interrupt line.

Definition at line 90 of file pci.h.

◆ PCI_CAP_ID

#define PCI_CAP_ID 0x00

Capability ID.

Definition at line 93 of file pci.h.

◆ PCI_CAP_ID_PM

#define PCI_CAP_ID_PM 0x01

Power management.

Definition at line 94 of file pci.h.

◆ PCI_CAP_ID_VPD

#define PCI_CAP_ID_VPD 0x03

Vital product data.

Definition at line 95 of file pci.h.

◆ PCI_CAP_ID_VNDR

#define PCI_CAP_ID_VNDR 0x09

Vendor-specific.

Definition at line 96 of file pci.h.

◆ PCI_CAP_ID_EXP

#define PCI_CAP_ID_EXP 0x10

PCI Express.

Definition at line 97 of file pci.h.

◆ PCI_CAP_ID_MSIX

#define PCI_CAP_ID_MSIX 0x11

MSI-X.

Definition at line 98 of file pci.h.

◆ PCI_CAP_ID_EA

#define PCI_CAP_ID_EA 0x14

Enhanced Allocation.

Definition at line 99 of file pci.h.

◆ PCI_CAP_NEXT

#define PCI_CAP_NEXT 0x01

Next capability.

Definition at line 102 of file pci.h.

◆ PCI_PM_CTRL

#define PCI_PM_CTRL 0x04

Power management control and status.

Definition at line 105 of file pci.h.

◆ PCI_PM_CTRL_STATE_MASK

#define PCI_PM_CTRL_STATE_MASK 0x0003

Current power state.

Definition at line 106 of file pci.h.

◆ PCI_PM_CTRL_PME_ENABLE

#define PCI_PM_CTRL_PME_ENABLE 0x0100

PME pin enable.

Definition at line 107 of file pci.h.

◆ PCI_PM_CTRL_PME_STATUS

#define PCI_PM_CTRL_PME_STATUS 0x8000

PME pin status.

Definition at line 108 of file pci.h.

◆ PCI_EXP_DEVCTL

#define PCI_EXP_DEVCTL 0x08

PCI Express.

Definition at line 111 of file pci.h.

◆ PCI_EXP_DEVCTL_FLR

#define PCI_EXP_DEVCTL_FLR 0x8000

Function level reset.

Definition at line 112 of file pci.h.

◆ PCI_MSIX_CTRL

#define PCI_MSIX_CTRL 0x02

MSI-X interrupts.

Definition at line 115 of file pci.h.

◆ PCI_MSIX_CTRL_ENABLE

#define PCI_MSIX_CTRL_ENABLE 0x8000

Enable MSI-X.

Definition at line 116 of file pci.h.

◆ PCI_MSIX_CTRL_MASK

#define PCI_MSIX_CTRL_MASK 0x4000

Mask all interrupts.

Definition at line 117 of file pci.h.

◆ PCI_MSIX_CTRL_SIZE

#define PCI_MSIX_CTRL_SIZE ( x ) ( (x) & 0x07ff )

Table size.

Definition at line 118 of file pci.h.

◆ PCI_MSIX_DESC_TABLE

#define PCI_MSIX_DESC_TABLE 0x04

Definition at line 119 of file pci.h.

◆ PCI_MSIX_DESC_PBA

#define PCI_MSIX_DESC_PBA 0x08

Definition at line 120 of file pci.h.

◆ PCI_MSIX_DESC_BIR

#define PCI_MSIX_DESC_BIR ( x ) ( (x) & 0x00000007 )

BAR index.

Definition at line 121 of file pci.h.

◆ PCI_MSIX_DESC_OFFSET

#define PCI_MSIX_DESC_OFFSET ( x ) ( (x) & 0xfffffff8 )

BAR offset.

Definition at line 122 of file pci.h.

◆ PCI_ERR_UNCOR_STATUS

#define PCI_ERR_UNCOR_STATUS 0x04

Uncorrectable error status.

Definition at line 125 of file pci.h.

◆ PCI_CLASS_NETWORK

#define PCI_CLASS_NETWORK 0x02

Network controller.

Definition at line 128 of file pci.h.

◆ PCI_CLASS_BRIDGE

#define PCI_CLASS_BRIDGE 0x06

Bridge device.

Definition at line 131 of file pci.h.

◆ PCI_CLASS_BRIDGE_PCI

#define PCI_CLASS_BRIDGE_PCI 0x04

PCI-to-PCI bridge.

Definition at line 132 of file pci.h.

◆ PCI_CLASS_SERIAL

#define PCI_CLASS_SERIAL 0x0c

Serial bus controller.

Definition at line 135 of file pci.h.

◆ PCI_CLASS_SERIAL_USB

#define PCI_CLASS_SERIAL_USB 0x03

USB controller.

Definition at line 136 of file pci.h.

◆ PCI_CLASS_SERIAL_USB_UHCI

#define PCI_CLASS_SERIAL_USB_UHCI 0x00

UHCI USB controller.

Definition at line 137 of file pci.h.

◆ PCI_CLASS_SERIAL_USB_OHCI

#define PCI_CLASS_SERIAL_USB_OHCI 0x10

OHCI USB controller.

Definition at line 138 of file pci.h.

◆ PCI_CLASS_SERIAL_USB_EHCI

#define PCI_CLASS_SERIAL_USB_EHCI 0x20

ECHI USB controller.

Definition at line 139 of file pci.h.

◆ PCI_CLASS_SERIAL_USB_XHCI

#define PCI_CLASS_SERIAL_USB_XHCI 0x30

xHCI USB controller

Definition at line 140 of file pci.h.

◆ PCI_PRIMARY

#define PCI_PRIMARY 0x18

Primary bus number.

Definition at line 143 of file pci.h.

◆ PCI_SECONDARY

#define PCI_SECONDARY 0x19

Secondary bus number.

Definition at line 146 of file pci.h.

◆ PCI_SUBORDINATE

#define PCI_SUBORDINATE 0x1a

Subordinate bus number.

Definition at line 149 of file pci.h.

◆ PCI_MEM_BASE

#define PCI_MEM_BASE 0x20

Memory base and limit.

Definition at line 152 of file pci.h.

◆ PCI_MEM_LIMIT

#define PCI_MEM_LIMIT 0x22

Definition at line 153 of file pci.h.

◆ PCI_MEM_MASK

#define PCI_MEM_MASK 0x000f

Definition at line 154 of file pci.h.

◆ PCI_CLASS

#define PCI_CLASS	(	base,
		sub,
		progif
	)

Value:

( ( ( (base) & 0xff ) << 16 ) | ( ( (sub) & 0xff ) << 8 ) | \

( ( (progif) & 0xff) << 0 ) )

base

uint32_t base

Base.

Definition: librm.h:252

Construct PCI class.

Parameters

base	Base class (or PCI_ANY_ID)
sub	Subclass (or PCI_ANY_ID)
progif	Programming interface (or PCI_ANY_ID)

Definition at line 162 of file pci.h.

◆ PCI_EXP_FLR_DELAY_MS

#define PCI_EXP_FLR_DELAY_MS 100

PCI Express function level reset delay (in ms)

Definition at line 167 of file pci.h.

◆ PCI_ANY_ID

#define PCI_ANY_ID 0xffff

Match-anything ID.

Definition at line 182 of file pci.h.

◆ PCI_CLASS_ID

#define PCI_CLASS_ID	(	base,
		sub,
		progif
	)

Value:

{                                  \
        .class = PCI_CLASS ( base, sub, progif ),                          \
        .mask = ( ( ( ( (base) == PCI_ANY_ID ) ? 0x00 : 0xff ) << 16 ) |   \
                  ( ( ( (sub) == PCI_ANY_ID ) ? 0x00 : 0xff ) << 8 ) |     \
                  ( ( ( (progif) == PCI_ANY_ID ) ? 0x00 : 0xff ) << 0 ) ), \
        }

Construct PCI class ID.

Parameters

base	Base class (or PCI_ANY_ID)
sub	Subclass (or PCI_ANY_ID)
progif	Programming interface (or PCI_ANY_ID)

Definition at line 198 of file pci.h.

◆ PCI_DRIVERS

#define PCI_DRIVERS __table ( struct pci_driver, "pci_drivers" )

PCI driver table.

Definition at line 270 of file pci.h.

◆ __pci_driver

struct pci_driver txnic_bgx_driver __pci_driver __table_entry ( PCI_DRIVERS, 01 )

Declare a PCI driver.

BGX PCI driver.

Definition at line 273 of file pci.h.

◆ __pci_driver_fallback

#define __pci_driver_fallback __table_entry ( PCI_DRIVERS, 02 )

Declare a fallback PCI driver.

Definition at line 276 of file pci.h.

◆ PCI_SEG

#define PCI_SEG ( busdevfn ) ( ( (busdevfn) >> 16 ) & 0xffff )

Definition at line 278 of file pci.h.

◆ PCI_BUS

#define PCI_BUS ( busdevfn ) ( ( (busdevfn) >> 8 ) & 0xff )

Definition at line 279 of file pci.h.

◆ PCI_SLOT

#define PCI_SLOT ( busdevfn ) ( ( (busdevfn) >> 3 ) & 0x1f )

Definition at line 280 of file pci.h.

◆ PCI_FUNC

#define PCI_FUNC ( busdevfn ) ( ( (busdevfn) >> 0 ) & 0x07 )

Definition at line 281 of file pci.h.

◆ PCI_FIRST_FUNC

#define PCI_FIRST_FUNC ( busdevfn ) ( (busdevfn) & ~0x07 )

Definition at line 282 of file pci.h.

◆ PCI_LAST_FUNC

#define PCI_LAST_FUNC ( busdevfn ) ( (busdevfn) | 0x07 )

Definition at line 283 of file pci.h.

◆ PCI_BASE_CLASS

#define PCI_BASE_CLASS ( class ) ( (class) >> 16 )

Definition at line 285 of file pci.h.

◆ PCI_SUB_CLASS

#define PCI_SUB_CLASS ( class ) ( ( (class) >> 8 ) & 0xff )

Definition at line 286 of file pci.h.

◆ PCI_PROG_INTF

#define PCI_PROG_INTF ( class ) ( (class) & 0xff )

Definition at line 287 of file pci.h.

◆ PCI_ID

#define PCI_ID	(	_vendor,
		_device,
		_name,
		_description,
		_data
	)

Value:

{       \
        .vendor = _vendor,                                              \
        .device = _device,                                              \
        .name = _name,                                                  \
        .driver_data = _data                                            \
}

Definition at line 297 of file pci.h.

◆ PCI_ROM

#define PCI_ROM	(	_vendor,
		_device,
		_name,
		_description,
		_data
	)	PCI_ID( _vendor, _device, _name, _description, _data )

Definition at line 303 of file pci.h.

◆ PCI_FMT

#define PCI_FMT "%04x:%02x:%02x.%x"

PCI device debug message format.

Definition at line 307 of file pci.h.

◆ PCI_ARGS

#define PCI_ARGS ( pci )

Value:

PCI_SEG ( (pci)->busdevfn ), PCI_BUS ( (pci)->busdevfn ), \

PCI_SLOT ( (pci)->busdevfn ), PCI_FUNC ( (pci)->busdevfn )

PCI_FUNC

#define PCI_FUNC(busdevfn)

Definition: pci.h:281

PCI_BUS

#define PCI_BUS(busdevfn)

Definition: pci.h:279

busdevfn

uint16_t busdevfn

PCI bus:dev.fn address.

Definition: ena.h:28

PCI_SEG

#define PCI_SEG(busdevfn)

Definition: pci.h:278

PCI device debug message arguments.

Definition at line 310 of file pci.h.

Function Documentation

◆ FILE_LICENCE()

FILE_LICENCE ( GPL2_OR_LATER_OR_UBDL )

◆ adjust_pci_device()

void adjust_pci_device ( struct pci_device * pci )

Enable PCI device.

Parameters

pci	PCI device

Set device to be a busmaster in case BIOS neglected to do so. Also adjust PCI latency timer to a reasonable value, 32.

Definition at line 154 of file pci.c.

                                                   {
         unsigned short new_command, pci_command;
         unsigned char pci_latency;
 
         pci_read_config_word ( pci, PCI_COMMAND, &pci_command );
         new_command = ( pci_command | PCI_COMMAND_MASTER |
                         PCI_COMMAND_MEM | PCI_COMMAND_IO );
         if ( pci_command != new_command ) {
                 DBGC ( pci, PCI_FMT " device not enabled by BIOS! Updating "
                        "PCI command %04x->%04x\n",
                        PCI_ARGS ( pci ), pci_command, new_command );
                 pci_write_config_word ( pci, PCI_COMMAND, new_command );
         }
 
         pci_read_config_byte ( pci, PCI_LATENCY_TIMER, &pci_latency);
         if ( pci_latency < 32 ) {
                 DBGC ( pci, PCI_FMT " latency timer is unreasonably low at "
                        "%d. Setting to 32.\n", PCI_ARGS ( pci ), pci_latency );
                 pci_write_config_byte ( pci, PCI_LATENCY_TIMER, 32);
         }
 }

References DBGC, PCI_ARGS, PCI_COMMAND, PCI_COMMAND_IO, PCI_COMMAND_MASTER, PCI_COMMAND_MEM, PCI_FMT, PCI_LATENCY_TIMER, pci_read_config_byte(), pci_read_config_word(), pci_write_config_byte(), and pci_write_config_word().

Referenced by a3c90x_probe(), amd8111e_probe(), arbel_probe(), ath5k_probe(), ath_pci_probe(), atl1e_probe(), atl_probe(), b44_probe(), bnx2_init_board(), bnxt_init_one(), dmfe_probe(), efab_probe(), efx_probe(), ehci_probe(), ena_probe(), exanic_probe(), forcedeth_probe(), golan_pci_init(), gve_probe(), hermon_bofm_probe(), hermon_probe(), hvm_probe(), ice_probe(), icplus_probe(), ifec_pci_probe(), igbvf_probe(), intel_probe(), intelx_probe(), intelxl_probe(), intelxlvf_probe(), intelxvf_probe(), jme_probe(), linda_probe(), mlx_pci_init_priv(), myri10ge_pci_probe(), myson_probe(), natsemi_probe(), pcnet32_probe(), phantom_probe(), pnic_probe(), qib7322_probe(), rdc_probe(), realtek_probe(), rhine_probe(), rtl818x_probe(), sis190_init_board(), sis900_probe(), skeleton_probe(), skge_probe(), sky2_probe(), sundance_probe(), tg3_init_one(), tlan_probe(), tulip_probe(), txnic_bgx_probe(), txnic_pf_probe(), uhci_probe(), velocity_probe(), virtnet_probe_legacy(), virtnet_probe_modern(), vmxnet3_probe(), vxge_probe(), w89c840_probe(), and xhci_probe().

◆ pci_bar_start()

unsigned long pci_bar_start	(	struct pci_device *	pci,
		unsigned int	reg
	)

Find the start of a PCI BAR.

Parameters

pci	PCI device
reg	PCI register number

Return values

start BAR start address

Reads the specified PCI base address register, and returns the address portion of the BAR (i.e. without the flags).

If the address exceeds the size of an unsigned long (i.e. if a 64-bit BAR has a non-zero high dword on a 32-bit machine), the return value will be zero.

Definition at line 96 of file pci.c.

                                                                          {
         unsigned long bar;
 
         bar = pci_bar ( pci, reg );
         if ( bar & PCI_BASE_ADDRESS_SPACE_IO ) {
                 return ( bar & ~PCI_BASE_ADDRESS_IO_MASK );
         } else {
                 return ( bar & ~PCI_BASE_ADDRESS_MEM_MASK );
         }
 }

References pci_bar(), PCI_BASE_ADDRESS_IO_MASK, PCI_BASE_ADDRESS_MEM_MASK, PCI_BASE_ADDRESS_SPACE_IO, and reg.

Referenced by amd8111e_probe(), arbel_probe(), bnx2_init_board(), bnxt_pci_base(), dmfe_probe(), efab_probe(), efx_probe(), ehci_probe(), exanic_probe(), flexboot_nodnic_alloc_uar(), forcedeth_map_regs(), golan_alloc_uar(), golan_pci_init(), gve_probe(), hermon_bofm_probe(), hermon_probe(), hvm_probe(), igbvf_probe(), mlx_pci_init_priv(), pci_msix_ioremap(), phantom_map_crb(), skge_probe(), sky2_probe(), tg3_init_one(), undipci_find_rom(), virtio_pci_map_capability(), vmxnet3_probe(), vxge_probe(), and xhci_probe().

◆ pci_read_config()

int pci_read_config ( struct pci_device * pci )

Read PCI device configuration.

Parameters

pci	PCI device

Return values

rc	Return status code

Definition at line 182 of file pci.c.

                                                {
         uint32_t busdevfn;
         uint8_t hdrtype;
         uint32_t tmp;
 
         /* Ignore all but the first function on non-multifunction devices */
         if ( PCI_FUNC ( pci->busdevfn ) != 0 ) {
                 busdevfn = pci->busdevfn;
                 pci->busdevfn = PCI_FIRST_FUNC ( pci->busdevfn );
                 pci_read_config_byte ( pci, PCI_HEADER_TYPE, &hdrtype );
                 pci->busdevfn = busdevfn;
                 if ( ! ( hdrtype & PCI_HEADER_TYPE_MULTI ) )
                         return -ENODEV;
         }
 
         /* Check for physical device presence */
         pci_read_config_dword ( pci, PCI_VENDOR_ID, &tmp );
         if ( ( tmp == 0xffffffff ) || ( tmp == 0 ) )
                 return -ENODEV;
 
         /* Populate struct pci_device */
         pci->vendor = ( tmp & 0xffff );
         pci->device = ( tmp >> 16 );
         pci_read_config_dword ( pci, PCI_REVISION, &tmp );
         pci->class = ( tmp >> 8 );
         pci_read_config_byte ( pci, PCI_INTERRUPT_LINE, &pci->irq );
         pci_read_config_byte ( pci, PCI_HEADER_TYPE, &pci->hdrtype );
         pci_read_bases ( pci );
 
         /* Initialise generic device component */
         snprintf ( pci->dev.name, sizeof ( pci->dev.name ), "%04x:%02x:%02x.%x",
                    PCI_SEG ( pci->busdevfn ), PCI_BUS ( pci->busdevfn ),
                    PCI_SLOT ( pci->busdevfn ), PCI_FUNC ( pci->busdevfn ) );
         pci->dev.desc.bus_type = BUS_TYPE_PCI;
         pci->dev.desc.location = pci->busdevfn;
         pci->dev.desc.vendor = pci->vendor;
         pci->dev.desc.device = pci->device;
         pci->dev.desc.class = pci->class;
         pci->dev.desc.ioaddr = pci->ioaddr;
         pci->dev.desc.irq = pci->irq;
         INIT_LIST_HEAD ( &pci->dev.siblings );
         INIT_LIST_HEAD ( &pci->dev.children );
 
         return 0;
 }

References device_description::bus_type, BUS_TYPE_PCI, busdevfn, pci_device::busdevfn, device::children, device_description::class, pci_device::class, device::desc, pci_device::dev, device_description::device, pci_device::device, ENODEV, pci_device::hdrtype, INIT_LIST_HEAD, device_description::ioaddr, pci_device::ioaddr, device_description::irq, pci_device::irq, device_description::location, device::name, PCI_BUS, PCI_FIRST_FUNC, PCI_FUNC, PCI_HEADER_TYPE, PCI_HEADER_TYPE_MULTI, PCI_INTERRUPT_LINE, pci_read_bases(), pci_read_config_byte(), pci_read_config_dword(), PCI_REVISION, PCI_SEG, PCI_SLOT, PCI_VENDOR_ID, device::siblings, snprintf(), tmp, device_description::vendor, and pci_device::vendor.

Referenced by bofm_test_init(), efipci_open(), ehci_companion(), and pci_find_next().

◆ pci_find_next()

int pci_find_next	(	struct pci_device *	pci,
		uint32_t *	busdevfn
	)

Find next device on PCI bus.

Parameters

pci	PCI device to fill in
busdevfn	Starting bus:dev.fn address

Return values

busdevfn	Bus:dev.fn address of next PCI device
rc	Return status code

Definition at line 236 of file pci.c.

                                                                  {
         static struct pci_range range;
         uint8_t hdrtype;
         uint8_t sub;
         uint32_t end;
         unsigned int count;
         int rc;
 
         /* Find next PCI device, if any */
         do {
                 /* Find next PCI bus:dev.fn address range, if necessary */
                 if ( ( *busdevfn - range.start ) >= range.count ) {
                         pci_discover ( *busdevfn, &range );
                         if ( *busdevfn < range.start )
                                 *busdevfn = range.start;
                         if ( ( *busdevfn - range.start ) >= range.count )
                                 break;
                 }
 
                 /* Check for PCI device existence */
                 memset ( pci, 0, sizeof ( *pci ) );
                 pci_init ( pci, *busdevfn );
                 if ( ( rc = pci_read_config ( pci ) ) != 0 )
                         continue;
 
                 /* If device is a bridge, expand the PCI bus:dev.fn
                  * address range as needed.
                  */
                 pci_read_config_byte ( pci, PCI_HEADER_TYPE, &hdrtype );
                 hdrtype &= PCI_HEADER_TYPE_MASK;
                 if ( hdrtype == PCI_HEADER_TYPE_BRIDGE ) {
                         pci_read_config_byte ( pci, PCI_SUBORDINATE, &sub );
                         end = PCI_BUSDEVFN ( PCI_SEG ( *busdevfn ),
                                              ( sub + 1 ), 0, 0 );
                         count = ( end - range.start );
                         if ( count > range.count ) {
                                 DBGC ( pci, PCI_FMT " found subordinate bus "
                                        "%#02x\n", PCI_ARGS ( pci ), sub );
                                 range.count = count;
                         }
                 }
 
                 /* Return this device */
                 return 0;
 
         } while ( ++(*busdevfn) );
 
         return -ENODEV;
 }

References busdevfn, count, pci_range::count, DBGC, end, ENODEV, memset(), PCI_ARGS, PCI_BUSDEVFN, pci_discover(), PCI_FMT, PCI_HEADER_TYPE, PCI_HEADER_TYPE_BRIDGE, PCI_HEADER_TYPE_MASK, pci_init(), pci_read_config(), pci_read_config_byte(), PCI_SEG, PCI_SUBORDINATE, range, rc, and pci_range::start.

Referenced by pcibus_probe(), pcicloud_init(), and pciscan_exec().

◆ pci_find_driver()

int pci_find_driver ( struct pci_device * pci )

Find driver for PCI device.

Parameters

pci	PCI device

Return values

rc	Return status code

Definition at line 292 of file pci.c.

                                                {
         struct pci_driver *driver;
         struct pci_device_id *id;
         unsigned int i;
 
         for_each_table_entry ( driver, PCI_DRIVERS ) {
                 if ( ( driver->class.class ^ pci->class ) & driver->class.mask )
                         continue;
                 for ( i = 0 ; i < driver->id_count ; i++ ) {
                         id = &driver->ids[i];
                         if ( ( id->vendor != PCI_ANY_ID ) &&
                              ( id->vendor != pci->vendor ) )
                                 continue;
                         if ( ( id->device != PCI_ANY_ID ) &&
                              ( id->device != pci->device ) )
                                 continue;
                         pci_set_driver ( pci, driver, id );
                         return 0;
                 }
         }
         return -ENOENT;
 }

References pci_class_id::class, pci_device::class, pci_driver::class, pci_device::device, ENOENT, for_each_table_entry, id, pci_driver::id_count, pci_driver::ids, pci_class_id::mask, PCI_ANY_ID, PCI_DRIVERS, pci_set_driver(), and pci_device::vendor.

Referenced by efipci_start(), efipci_supported(), and pcibus_probe().

◆ pci_probe()

int pci_probe ( struct pci_device * pci )

Probe a PCI device.

Parameters

pci	PCI device

Return values

rc	Return status code

Searches for a driver for the PCI device. If a driver is found, its probe() routine is called.

Definition at line 324 of file pci.c.

                                          {
         int rc;
 
         DBGC ( pci, PCI_FMT " (%04x:%04x) has driver \"%s\"\n",
                PCI_ARGS ( pci ), pci->vendor, pci->device, pci->id->name );
         DBGC ( pci, PCI_FMT " has mem %lx io %lx irq %d\n",
                PCI_ARGS ( pci ), pci->membase, pci->ioaddr, pci->irq );
 
         if ( ( rc = pci->driver->probe ( pci ) ) != 0 ) {
                 DBGC ( pci, PCI_FMT " probe failed: %s\n",
                        PCI_ARGS ( pci ), strerror ( rc ) );
                 return rc;
         }
 
         return 0;
 }

References DBGC, pci_device::device, pci_device::driver, pci_device::id, pci_device::ioaddr, pci_device::irq, pci_device::membase, pci_device_id::name, PCI_ARGS, PCI_FMT, pci_driver::probe, rc, strerror(), and pci_device::vendor.

Referenced by bofm_probe(), efipci_start(), and pcibus_probe().

◆ pci_remove()

void pci_remove ( struct pci_device * pci )

Remove a PCI device.

Parameters

pci	PCI device

Definition at line 346 of file pci.c.

                                            {
         pci->driver->remove ( pci );
         DBGC ( pci, PCI_FMT " removed\n", PCI_ARGS ( pci ) );
 }

References DBGC, pci_device::driver, PCI_ARGS, PCI_FMT, and pci_driver::remove.

Referenced by bofm_remove(), efipci_start(), efipci_stop(), and pcibus_remove().

◆ pci_find_capability()

int pci_find_capability	(	struct pci_device *	pci,
		int	cap
	)

Look for a PCI capability.

Parameters

pci	PCI device to query
cap	Capability code

Return values

address Address of capability, or 0 if not found

Determine whether or not a device supports a given PCI capability. Returns the address of the requested capability structure within the device's PCI configuration space, or 0 if the device does not support it.

Definition at line 38 of file pciextra.c.

                                                             {
         uint16_t status;
         uint8_t pos;
         uint8_t hdr_type;
 
         pci_read_config_word ( pci, PCI_STATUS, &status );
         if ( ! ( status & PCI_STATUS_CAP_LIST ) )
                 return 0;
 
         pci_read_config_byte ( pci, PCI_HEADER_TYPE, &hdr_type );
         switch ( hdr_type & PCI_HEADER_TYPE_MASK ) {
         case PCI_HEADER_TYPE_NORMAL:
         case PCI_HEADER_TYPE_BRIDGE:
         default:
                 pci_read_config_byte ( pci, PCI_CAPABILITY_LIST, &pos );
                 break;
         case PCI_HEADER_TYPE_CARDBUS:
                 pci_read_config_byte ( pci, PCI_CB_CAPABILITY_LIST, &pos );
                 break;
         }
         return pci_find_capability_common ( pci, pos, cap );
 }

References PCI_CAPABILITY_LIST, PCI_CB_CAPABILITY_LIST, pci_find_capability_common(), PCI_HEADER_TYPE, PCI_HEADER_TYPE_BRIDGE, PCI_HEADER_TYPE_CARDBUS, PCI_HEADER_TYPE_MASK, PCI_HEADER_TYPE_NORMAL, pci_read_config_byte(), pci_read_config_word(), PCI_STATUS, PCI_STATUS_CAP_LIST, and status.

Referenced by ath5k_hw_attach(), ath5k_hw_nic_wakeup(), bnx2_init_board(), ice_probe(), intelxl_probe(), intelxlvf_probe(), myri10ge_pci_probe(), pci_msix_enable(), pci_vpd_init(), pciea_offset(), sky2_reset(), sky2_rx_start(), tg3_get_invariants(), and virtio_pci_find_capability().

◆ pci_find_next_capability()

int pci_find_next_capability	(	struct pci_device *	pci,
		int	pos,
		int	cap
	)

Look for another PCI capability.

Parameters

pci	PCI device to query
pos	Address of the current capability
cap	Capability code

Return values

address Address of capability, or 0 if not found

Determine whether or not a device supports a given PCI capability starting the search at a given address within the device's PCI configuration space. Returns the address of the next capability structure within the device's PCI configuration space, or 0 if the device does not support another such capability.

Definition at line 75 of file pciextra.c.

                                                                           {
         uint8_t new_pos;
 
         pci_read_config_byte ( pci, pos + PCI_CAP_NEXT, &new_pos );
         return pci_find_capability_common ( pci, new_pos, cap );
 }

References PCI_CAP_NEXT, pci_find_capability_common(), and pci_read_config_byte().

Referenced by virtio_pci_find_capability().

◆ pci_bar_size()

unsigned long pci_bar_size	(	struct pci_device *	pci,
		unsigned int	reg
	)

Find the size of a PCI BAR.

Parameters

pci	PCI device
reg	PCI register number

Return values

size BAR size

It should not be necessary for any Etherboot code to call this function.

Definition at line 92 of file pciextra.c.

                                                                         {
         uint16_t cmd;
         uint32_t start, size;
 
         /* Save the original command register */
         pci_read_config_word ( pci, PCI_COMMAND, &cmd );
         /* Save the original bar */
         pci_read_config_dword ( pci, reg, &start );
         /* Compute which bits can be set */
         pci_write_config_dword ( pci, reg, ~0 );
         pci_read_config_dword ( pci, reg, &size );
         /* Restore the original size */
         pci_write_config_dword ( pci, reg, start );
         /* Find the significant bits */
         /* Restore the original command register. This reenables decoding. */
         pci_write_config_word ( pci, PCI_COMMAND, cmd );
         if ( start & PCI_BASE_ADDRESS_SPACE_IO ) {
                 size &= ~PCI_BASE_ADDRESS_IO_MASK;
         } else {
                 size &= ~PCI_BASE_ADDRESS_MEM_MASK;
         }
         /* Find the lowest bit set */
         size = size & ~( size - 1 );
         return size;
 }

References cmd, PCI_BASE_ADDRESS_IO_MASK, PCI_BASE_ADDRESS_MEM_MASK, PCI_BASE_ADDRESS_SPACE_IO, PCI_COMMAND, pci_read_config_dword(), pci_read_config_word(), pci_write_config_dword(), pci_write_config_word(), reg, size, and start.

Referenced by __vxge_hw_device_get_legacy_reg(), amd8111e_probe(), bnxt_pci_base(), efab_probe(), efx_probe(), ehci_probe(), exanic_probe(), forcedeth_map_regs(), gve_probe(), hvm_probe(), igbvf_probe(), phantom_map_crb(), tg3_init_one(), virtio_pci_map_capability(), vxge_probe(), and xhci_probe().

◆ pci_reset()

void pci_reset	(	struct pci_device *	pci,
		unsigned int	exp
	)

Perform PCI Express function-level reset (FLR)

Parameters

pci	PCI device
exp	PCI Express Capability address

Definition at line 124 of file pciextra.c.

                                                             {
         struct pci_config_backup backup;
         uint16_t control;
 
         /* Back up configuration space */
         pci_backup ( pci, &backup, PCI_CONFIG_BACKUP_STANDARD, NULL );
 
         /* Perform a PCIe function-level reset */
         pci_read_config_word ( pci, ( exp + PCI_EXP_DEVCTL ), &control );
         control |= PCI_EXP_DEVCTL_FLR;
         pci_write_config_word ( pci, ( exp + PCI_EXP_DEVCTL ), control );
 
         /* Allow time for reset to complete */
         mdelay ( PCI_EXP_FLR_DELAY_MS );
 
         /* Restore configuration */
         pci_restore ( pci, &backup, PCI_CONFIG_BACKUP_STANDARD, NULL );
 }

References control, mdelay(), NULL, pci_backup(), PCI_CONFIG_BACKUP_STANDARD, PCI_EXP_DEVCTL, PCI_EXP_DEVCTL_FLR, PCI_EXP_FLR_DELAY_MS, pci_read_config_word(), pci_restore(), and pci_write_config_word().

Referenced by ice_probe(), ice_remove(), intelxl_probe(), intelxl_remove(), intelxlvf_probe(), and intelxlvf_remove().

◆ pci_init()

static void pci_init	(	struct pci_device *	pci,
		unsigned int	busdevfn
	)

inlinestatic

Initialise PCI device.

Parameters

pci	PCI device
busdevfn	PCI bus:dev.fn address

Definition at line 334 of file pci.h.

                                                                               {
         pci->busdevfn = busdevfn;
 }

References busdevfn, and pci_device::busdevfn.

Referenced by bofm_test_init(), efipci_discover(), efipci_open(), ehci_companion(), pci_find_next(), pci_settings_fetch(), uhci_root_speed(), and undinet_irq_is_broken().

◆ pci_set_driver()

static void pci_set_driver	(	struct pci_device *	pci,
		struct pci_driver *	driver,
		struct pci_device_id *	id
	)

inlinestatic

Set PCI driver.

Parameters

pci	PCI device
driver	PCI driver
id	PCI device ID

Definition at line 345 of file pci.h.

                                                                {
         pci->driver = driver;
         pci->id = id;
         pci->dev.driver_name = id->name;
 }

References pci_device::dev, pci_device::driver, device::driver_name, id, and pci_device::id.

Referenced by bofm_find_driver(), and pci_find_driver().

◆ pci_set_drvdata()

static void pci_set_drvdata	(	struct pci_device *	pci,
		void *	priv
	)

inlinestatic

Set PCI driver-private data.

Parameters

pci	PCI device
priv	Private data

Definition at line 359 of file pci.h.

                                                                           {
         pci->priv = priv;
 }

References priv, and pci_device::priv.

Referenced by a3c90x_probe(), arbel_probe(), ath5k_probe(), ath_pci_probe(), atl1e_init_netdev(), atl_probe(), b44_probe(), bnxt_init_one(), efab_probe(), ehci_probe(), ena_probe(), exanic_probe(), flexboot_nodnic_probe(), forcedeth_probe(), golan_probe_normal(), gve_probe(), hermon_bofm_probe(), hermon_probe(), hunt_probe(), hvm_probe(), ice_probe(), icplus_probe(), ifec_pci_probe(), igbvf_probe(), intel_probe(), intelx_probe(), intelxl_probe(), intelxlvf_probe(), intelxvf_probe(), jme_probe(), legacy_pci_set_drvdata(), linda_probe(), myri10ge_pci_probe(), myson_probe(), natsemi_probe(), pcibridge_probe(), pcnet32_probe(), phantom_probe(), pnic_probe(), qib7322_probe(), rdc_probe(), realtek_probe(), rhine_probe(), rtl818x_probe(), sis190_probe(), skeleton_probe(), skge_probe(), skge_remove(), sky2_probe(), sky2_remove(), tg3_init_one(), txnic_bgx_probe(), txnic_pf_probe(), uhci_probe(), undipci_probe(), undipci_remove(), velocity_probe(), virtnet_probe_legacy(), virtnet_probe_modern(), vmxnet3_probe(), vxge_probe(), vxge_remove(), and xhci_probe().

◆ pci_get_drvdata()

static void* pci_get_drvdata ( struct pci_device * pci )

inlinestatic

Get PCI driver-private data.

Parameters

pci	PCI device

Return values

priv	Private data

Definition at line 369 of file pci.h.

                                                                 {
         return pci->priv;
 }

References pci_device::priv.

Referenced by a3c90x_remove(), arbel_remove(), ath5k_remove(), ath_pci_remove(), atl1e_remove(), atl_remove(), b44_remove(), bnxt_remove_one(), efab_remove(), ehci_remove(), ena_remove(), exanic_remove(), flexboot_nodnic_remove(), forcedeth_remove(), golan_remove_normal(), gve_remove(), hermon_bofm_remove(), hermon_remove(), hunt_remove(), hvm_remove(), ice_remove(), icplus_remove(), ifec_pci_remove(), igbvf_remove(), intel_remove(), intelx_remove(), intelxl_remove(), intelxlvf_remove(), intelxvf_remove(), jme_remove(), legacy_pci_get_drvdata(), linda_remove(), myri10ge_pci_remove(), myson_remove(), natsemi_remove(), pcibridge_remove(), pcnet32_remove(), phantom_remove(), pnic_remove(), qib7322_remove(), rdc_remove(), realtek_remove(), rhine_remove(), rtl818x_remove(), sis190_remove(), skeleton_remove(), skge_remove(), sky2_remove(), tg3_remove_one(), txnic_bgx_remove(), txnic_pf_remove(), uhci_remove(), undipci_remove(), velocity_remove(), virtnet_remove(), vmxnet3_remove(), vxge_close(), vxge_irq(), vxge_open(), vxge_open_vpaths(), vxge_poll(), vxge_remove(), and xhci_remove().

Variable Documentation

◆ attribute

struct pci_device_id __attribute__

Data Structures

Macros

Functions

Variables

Detailed Description

Macro Definition Documentation

◆ PCI_VENDOR_ID

◆ PCI_DEVICE_ID

◆ PCI_COMMAND

◆ PCI_COMMAND_IO

◆ PCI_COMMAND_MEM

◆ PCI_COMMAND_MASTER

◆ PCI_COMMAND_INVALIDATE

◆ PCI_COMMAND_PARITY

◆ PCI_COMMAND_SERR

◆ PCI_COMMAND_INTX_DISABLE

◆ PCI_STATUS

◆ PCI_STATUS_CAP_LIST

◆ PCI_STATUS_PARITY

◆ PCI_STATUS_REC_TARGET_ABORT

◆ PCI_STATUS_REC_MASTER_ABORT

◆ PCI_STATUS_SIG_SYSTEM_ERROR

◆ PCI_STATUS_DETECTED_PARITY

◆ PCI_REVISION

◆ PCI_CACHE_LINE_SIZE

◆ PCI_LATENCY_TIMER

◆ PCI_HEADER_TYPE

◆ PCI_HEADER_TYPE_NORMAL

◆ PCI_HEADER_TYPE_BRIDGE

◆ PCI_HEADER_TYPE_CARDBUS

◆ PCI_HEADER_TYPE_MASK

◆ PCI_HEADER_TYPE_MULTI

◆ PCI_BASE_ADDRESS

◆ PCI_BASE_ADDRESS_0

◆ PCI_BASE_ADDRESS_1

◆ PCI_BASE_ADDRESS_2

◆ PCI_BASE_ADDRESS_3

◆ PCI_BASE_ADDRESS_4

◆ PCI_BASE_ADDRESS_5

◆ PCI_BASE_ADDRESS_SPACE_IO

◆ PCI_BASE_ADDRESS_IO_MASK

◆ PCI_BASE_ADDRESS_MEM_TYPE_64

◆ PCI_BASE_ADDRESS_MEM_TYPE_MASK

◆ PCI_BASE_ADDRESS_MEM_MASK

◆ PCI_SUBSYSTEM_VENDOR_ID

◆ PCI_SUBSYSTEM_ID

◆ PCI_ROM_ADDRESS

◆ PCI_CAPABILITY_LIST

◆ PCI_CB_CAPABILITY_LIST

◆ PCI_INTERRUPT_LINE

◆ PCI_CAP_ID

◆ PCI_CAP_ID_PM

◆ PCI_CAP_ID_VPD

◆ PCI_CAP_ID_VNDR

◆ PCI_CAP_ID_EXP

◆ PCI_CAP_ID_MSIX

◆ PCI_CAP_ID_EA

◆ PCI_CAP_NEXT

◆ PCI_PM_CTRL

◆ PCI_PM_CTRL_STATE_MASK

◆ PCI_PM_CTRL_PME_ENABLE

◆ PCI_PM_CTRL_PME_STATUS

◆ PCI_EXP_DEVCTL

◆ PCI_EXP_DEVCTL_FLR

◆ PCI_MSIX_CTRL

◆ PCI_MSIX_CTRL_ENABLE

◆ PCI_MSIX_CTRL_MASK

◆ PCI_MSIX_CTRL_SIZE

◆ PCI_MSIX_DESC_TABLE

◆ PCI_MSIX_DESC_PBA

◆ PCI_MSIX_DESC_BIR

◆ PCI_MSIX_DESC_OFFSET

◆ PCI_ERR_UNCOR_STATUS

◆ PCI_CLASS_NETWORK

◆ PCI_CLASS_BRIDGE

◆ PCI_CLASS_BRIDGE_PCI

◆ PCI_CLASS_SERIAL

◆ PCI_CLASS_SERIAL_USB

◆ PCI_CLASS_SERIAL_USB_UHCI

◆ PCI_CLASS_SERIAL_USB_OHCI

◆ attribute