|
#define | PCI_VENDOR_ID 0x00 |
| PCI vendor ID. More...
|
|
#define | PCI_DEVICE_ID 0x02 |
| PCI device ID. More...
|
|
#define | PCI_COMMAND 0x04 |
| PCI command. More...
|
|
#define | PCI_COMMAND_IO 0x0001 |
| I/O space. More...
|
|
#define | PCI_COMMAND_MEM 0x0002 |
| Memory space. More...
|
|
#define | PCI_COMMAND_MASTER 0x0004 |
| Bus master. More...
|
|
#define | PCI_COMMAND_INVALIDATE 0x0010 |
| Mem. More...
|
|
#define | PCI_COMMAND_PARITY 0x0040 |
| Parity error response. More...
|
|
#define | PCI_COMMAND_SERR 0x0100 |
| SERR# enable. More...
|
|
#define | PCI_COMMAND_INTX_DISABLE 0x0400 |
| Interrupt disable. More...
|
|
#define | PCI_STATUS 0x06 |
| PCI status. More...
|
|
#define | PCI_STATUS_CAP_LIST 0x0010 |
| Capabilities list. More...
|
|
#define | PCI_STATUS_PARITY 0x0100 |
| Master data parity error. More...
|
|
#define | PCI_STATUS_REC_TARGET_ABORT 0x1000 |
| Received target abort. More...
|
|
#define | PCI_STATUS_REC_MASTER_ABORT 0x2000 |
| Received master abort. More...
|
|
#define | PCI_STATUS_SIG_SYSTEM_ERROR 0x4000 |
| Signalled system error. More...
|
|
#define | PCI_STATUS_DETECTED_PARITY 0x8000 |
| Detected parity error. More...
|
|
#define | PCI_REVISION 0x08 |
| PCI revision. More...
|
|
#define | PCI_CACHE_LINE_SIZE 0x0c |
| PCI cache line size. More...
|
|
#define | PCI_LATENCY_TIMER 0x0d |
| PCI latency timer. More...
|
|
#define | PCI_HEADER_TYPE 0x0e |
| PCI header type. More...
|
|
#define | PCI_HEADER_TYPE_NORMAL 0x00 |
| Normal header. More...
|
|
#define | PCI_HEADER_TYPE_BRIDGE 0x01 |
| PCI-to-PCI bridge header. More...
|
|
#define | PCI_HEADER_TYPE_CARDBUS 0x02 |
| CardBus header. More...
|
|
#define | PCI_HEADER_TYPE_MASK 0x7f |
| Header type mask. More...
|
|
#define | PCI_HEADER_TYPE_MULTI 0x80 |
| Multi-function device. More...
|
|
#define | PCI_BASE_ADDRESS(n) ( 0x10 + ( 4 * (n) ) ) |
| PCI base address registers. More...
|
|
#define | PCI_BASE_ADDRESS_0 PCI_BASE_ADDRESS ( 0 ) |
|
#define | PCI_BASE_ADDRESS_1 PCI_BASE_ADDRESS ( 1 ) |
|
#define | PCI_BASE_ADDRESS_2 PCI_BASE_ADDRESS ( 2 ) |
|
#define | PCI_BASE_ADDRESS_3 PCI_BASE_ADDRESS ( 3 ) |
|
#define | PCI_BASE_ADDRESS_4 PCI_BASE_ADDRESS ( 4 ) |
|
#define | PCI_BASE_ADDRESS_5 PCI_BASE_ADDRESS ( 5 ) |
|
#define | PCI_BASE_ADDRESS_SPACE_IO 0x00000001UL |
| I/O BAR. More...
|
|
#define | PCI_BASE_ADDRESS_IO_MASK 0x00000003UL |
| I/O BAR mask. More...
|
|
#define | PCI_BASE_ADDRESS_MEM_TYPE_64 0x00000004UL |
| 64-bit memory More...
|
|
#define | PCI_BASE_ADDRESS_MEM_TYPE_MASK 0x00000006UL |
| Memory type mask. More...
|
|
#define | PCI_BASE_ADDRESS_MEM_MASK 0x0000000fUL |
| Memory BAR mask. More...
|
|
#define | PCI_SUBSYSTEM_VENDOR_ID 0x2c |
| PCI subsystem vendor ID. More...
|
|
#define | PCI_SUBSYSTEM_ID 0x2e |
| PCI subsystem ID. More...
|
|
#define | PCI_ROM_ADDRESS 0x30 |
| PCI expansion ROM base address. More...
|
|
#define | PCI_CAPABILITY_LIST 0x34 |
| PCI capabilities pointer. More...
|
|
#define | PCI_CB_CAPABILITY_LIST 0x14 |
| CardBus capabilities pointer. More...
|
|
#define | PCI_INTERRUPT_LINE 0x3c |
| PCI interrupt line. More...
|
|
#define | PCI_CAP_ID 0x00 |
| Capability ID. More...
|
|
#define | PCI_CAP_ID_PM 0x01 |
| Power management. More...
|
|
#define | PCI_CAP_ID_VPD 0x03 |
| Vital product data. More...
|
|
#define | PCI_CAP_ID_VNDR 0x09 |
| Vendor-specific. More...
|
|
#define | PCI_CAP_ID_EXP 0x10 |
| PCI Express. More...
|
|
#define | PCI_CAP_ID_MSIX 0x11 |
| MSI-X. More...
|
|
#define | PCI_CAP_ID_EA 0x14 |
| Enhanced Allocation. More...
|
|
#define | PCI_CAP_NEXT 0x01 |
| Next capability. More...
|
|
#define | PCI_PM_CTRL 0x04 |
| Power management control and status. More...
|
|
#define | PCI_PM_CTRL_STATE_MASK 0x0003 |
| Current power state. More...
|
|
#define | PCI_PM_CTRL_PME_ENABLE 0x0100 |
| PME pin enable. More...
|
|
#define | PCI_PM_CTRL_PME_STATUS 0x8000 |
| PME pin status. More...
|
|
#define | PCI_EXP_DEVCTL 0x08 |
| PCI Express. More...
|
|
#define | PCI_EXP_DEVCTL_FLR 0x8000 |
| Function level reset. More...
|
|
#define | PCI_MSIX_CTRL 0x02 |
| MSI-X interrupts. More...
|
|
#define | PCI_MSIX_CTRL_ENABLE 0x8000 |
| Enable MSI-X. More...
|
|
#define | PCI_MSIX_CTRL_MASK 0x4000 |
| Mask all interrupts. More...
|
|
#define | PCI_MSIX_CTRL_SIZE(x) ( (x) & 0x07ff ) |
| Table size. More...
|
|
#define | PCI_MSIX_DESC_TABLE 0x04 |
|
#define | PCI_MSIX_DESC_PBA 0x08 |
|
#define | PCI_MSIX_DESC_BIR(x) ( (x) & 0x00000007 ) |
| BAR index. More...
|
|
#define | PCI_MSIX_DESC_OFFSET(x) ( (x) & 0xfffffff8 ) |
| BAR offset. More...
|
|
#define | PCI_ERR_UNCOR_STATUS 0x04 |
| Uncorrectable error status. More...
|
|
#define | PCI_CLASS_NETWORK 0x02 |
| Network controller. More...
|
|
#define | PCI_CLASS_BRIDGE 0x06 |
| Bridge device. More...
|
|
#define | PCI_CLASS_BRIDGE_PCI 0x04 |
| PCI-to-PCI bridge. More...
|
|
#define | PCI_CLASS_SERIAL 0x0c |
| Serial bus controller. More...
|
|
#define | PCI_CLASS_SERIAL_USB 0x03 |
| USB controller. More...
|
|
#define | PCI_CLASS_SERIAL_USB_UHCI 0x00 |
| UHCI USB controller. More...
|
|
#define | PCI_CLASS_SERIAL_USB_OHCI 0x10 |
| OHCI USB controller. More...
|
|
#define | PCI_CLASS_SERIAL_USB_EHCI 0x20 |
| ECHI USB controller. More...
|
|
#define | PCI_CLASS_SERIAL_USB_XHCI 0x30 |
| xHCI USB controller More...
|
|
#define | PCI_PRIMARY 0x18 |
| Primary bus number. More...
|
|
#define | PCI_SECONDARY 0x19 |
| Secondary bus number. More...
|
|
#define | PCI_SUBORDINATE 0x1a |
| Subordinate bus number. More...
|
|
#define | PCI_MEM_BASE 0x20 |
| Memory base and limit. More...
|
|
#define | PCI_MEM_LIMIT 0x22 |
|
#define | PCI_MEM_MASK 0x000f |
|
#define | PCI_CLASS(base, sub, progif) |
| Construct PCI class. More...
|
|
#define | PCI_EXP_FLR_DELAY_MS 100 |
| PCI Express function level reset delay (in ms) More...
|
|
#define | PCI_ANY_ID 0xffff |
| Match-anything ID. More...
|
|
#define | PCI_CLASS_ID(base, sub, progif) |
| Construct PCI class ID. More...
|
|
#define | PCI_DRIVERS __table ( struct pci_driver, "pci_drivers" ) |
| PCI driver table. More...
|
|
#define | __pci_driver __table_entry ( PCI_DRIVERS, 01 ) |
| Declare a PCI driver. More...
|
|
#define | __pci_driver_fallback __table_entry ( PCI_DRIVERS, 02 ) |
| Declare a fallback PCI driver. More...
|
|
#define | PCI_SEG(busdevfn) ( ( (busdevfn) >> 16 ) & 0xffff ) |
|
#define | PCI_BUS(busdevfn) ( ( (busdevfn) >> 8 ) & 0xff ) |
|
#define | PCI_SLOT(busdevfn) ( ( (busdevfn) >> 3 ) & 0x1f ) |
|
#define | PCI_FUNC(busdevfn) ( ( (busdevfn) >> 0 ) & 0x07 ) |
|
#define | PCI_FIRST_FUNC(busdevfn) ( (busdevfn) & ~0x07 ) |
|
#define | PCI_LAST_FUNC(busdevfn) ( (busdevfn) | 0x07 ) |
|
#define | PCI_BASE_CLASS(class) ( (class) >> 16 ) |
|
#define | PCI_SUB_CLASS(class) ( ( (class) >> 8 ) & 0xff ) |
|
#define | PCI_PROG_INTF(class) ( (class) & 0xff ) |
|
#define | PCI_ID(_vendor, _device, _name, _description, _data) |
|
#define | PCI_ROM(_vendor, _device, _name, _description, _data) PCI_ID( _vendor, _device, _name, _description, _data ) |
|
#define | PCI_FMT "%04x:%02x:%02x.%x" |
| PCI device debug message format. More...
|
|
#define | PCI_ARGS(pci) |
| PCI device debug message arguments. More...
|
|
|
| FILE_LICENCE (GPL2_OR_LATER_OR_UBDL) |
|
void | adjust_pci_device (struct pci_device *pci) |
| Enable PCI device. More...
|
|
unsigned long | pci_bar_start (struct pci_device *pci, unsigned int reg) |
| Find the start of a PCI BAR. More...
|
|
int | pci_read_config (struct pci_device *pci) |
| Read PCI device configuration. More...
|
|
int | pci_find_next (struct pci_device *pci, uint32_t *busdevfn) |
| Find next device on PCI bus. More...
|
|
int | pci_find_driver (struct pci_device *pci) |
| Find driver for PCI device. More...
|
|
int | pci_probe (struct pci_device *pci) |
| Probe a PCI device. More...
|
|
void | pci_remove (struct pci_device *pci) |
| Remove a PCI device. More...
|
|
int | pci_find_capability (struct pci_device *pci, int capability) |
| Look for a PCI capability. More...
|
|
int | pci_find_next_capability (struct pci_device *pci, int pos, int capability) |
| Look for another PCI capability. More...
|
|
unsigned long | pci_bar_size (struct pci_device *pci, unsigned int reg) |
| Find the size of a PCI BAR. More...
|
|
void | pci_reset (struct pci_device *pci, unsigned int exp) |
| Perform PCI Express function-level reset (FLR) More...
|
|
static void | pci_init (struct pci_device *pci, unsigned int busdevfn) |
| Initialise PCI device. More...
|
|
static void | pci_set_driver (struct pci_device *pci, struct pci_driver *driver, struct pci_device_id *id) |
| Set PCI driver. More...
|
|
static void | pci_set_drvdata (struct pci_device *pci, void *priv) |
| Set PCI driver-private data. More...
|
|
static void * | pci_get_drvdata (struct pci_device *pci) |
| Get PCI driver-private data. More...
|
|
PCI bus.
Definition in file pci.h.
Enable PCI device.
- Parameters
-
Set device to be a busmaster in case BIOS neglected to do so. Also adjust PCI latency timer to a reasonable value, 32.
Definition at line 154 of file pci.c.
155 unsigned short new_command, pci_command;
156 unsigned char pci_latency;
161 if ( pci_command != new_command ) {
162 DBGC ( pci,
PCI_FMT " device not enabled by BIOS! Updating " 163 "PCI command %04x->%04x\n",
164 PCI_ARGS ( pci ), pci_command, new_command );
169 if ( pci_latency < 32 ) {
170 DBGC ( pci,
PCI_FMT " latency timer is unreasonably low at " 171 "%d. Setting to 32.\n",
PCI_ARGS ( pci ), pci_latency );
#define PCI_LATENCY_TIMER
PCI latency timer.
int pci_write_config_word(struct pci_device *pci, unsigned int where, uint16_t value)
Write 16-bit word to PCI configuration space.
int pci_read_config_word(struct pci_device *pci, unsigned int where, uint16_t *value)
Read 16-bit word from PCI configuration space.
#define PCI_COMMAND
PCI command.
#define PCI_COMMAND_MASTER
Bus master.
#define PCI_COMMAND_IO
I/O space.
int pci_write_config_byte(struct pci_device *pci, unsigned int where, uint8_t value)
Write byte to PCI configuration space.
#define PCI_FMT
PCI device debug message format.
#define PCI_ARGS(pci)
PCI device debug message arguments.
#define PCI_COMMAND_MEM
Memory space.
int pci_read_config_byte(struct pci_device *pci, unsigned int where, uint8_t *value)
Read byte from PCI configuration space.
References DBGC, PCI_ARGS, PCI_COMMAND, PCI_COMMAND_IO, PCI_COMMAND_MASTER, PCI_COMMAND_MEM, PCI_FMT, PCI_LATENCY_TIMER, pci_read_config_byte(), pci_read_config_word(), pci_write_config_byte(), and pci_write_config_word().
Referenced by a3c90x_probe(), amd8111e_probe(), arbel_probe(), ath5k_probe(), ath_pci_probe(), atl1e_probe(), atl_probe(), b44_probe(), bnx2_init_board(), bnxt_init_one(), dmfe_probe(), efab_probe(), efx_probe(), ehci_probe(), ena_probe(), exanic_probe(), forcedeth_probe(), golan_pci_init(), gve_probe(), hermon_bofm_probe(), hermon_probe(), hvm_probe(), ice_probe(), icplus_probe(), ifec_pci_probe(), igbvf_probe(), intel_probe(), intelx_probe(), intelxl_probe(), intelxlvf_probe(), intelxvf_probe(), jme_probe(), linda_probe(), mlx_pci_init_priv(), myri10ge_pci_probe(), myson_probe(), natsemi_probe(), pcnet32_probe(), phantom_probe(), pnic_probe(), qib7322_probe(), rdc_probe(), realtek_probe(), rhine_probe(), rtl818x_probe(), sis190_init_board(), sis900_probe(), skeleton_probe(), skge_probe(), sky2_probe(), sundance_probe(), tg3_init_one(), tlan_probe(), tulip_probe(), txnic_bgx_probe(), txnic_pf_probe(), uhci_probe(), velocity_probe(), virtnet_probe_legacy(), virtnet_probe_modern(), vmxnet3_probe(), vxge_probe(), w89c840_probe(), and xhci_probe().
unsigned long pci_bar_start |
( |
struct pci_device * |
pci, |
|
|
unsigned int |
reg |
|
) |
| |
Find the start of a PCI BAR.
- Parameters
-
pci | PCI device |
reg | PCI register number |
- Return values
-
Reads the specified PCI base address register, and returns the address portion of the BAR (i.e. without the flags).
If the address exceeds the size of an unsigned long (i.e. if a 64-bit BAR has a non-zero high dword on a 32-bit machine), the return value will be zero.
Definition at line 96 of file pci.c.
static unsigned int unsigned int reg
#define PCI_BASE_ADDRESS_IO_MASK
I/O BAR mask.
#define PCI_BASE_ADDRESS_MEM_MASK
Memory BAR mask.
#define PCI_BASE_ADDRESS_SPACE_IO
I/O BAR.
static unsigned long pci_bar(struct pci_device *pci, unsigned int reg)
Read PCI BAR.
References pci_bar(), PCI_BASE_ADDRESS_IO_MASK, PCI_BASE_ADDRESS_MEM_MASK, PCI_BASE_ADDRESS_SPACE_IO, and reg.
Referenced by amd8111e_probe(), arbel_probe(), bnx2_init_board(), bnxt_pci_base(), dmfe_probe(), efab_probe(), efx_probe(), ehci_probe(), exanic_probe(), flexboot_nodnic_alloc_uar(), forcedeth_map_regs(), golan_alloc_uar(), golan_pci_init(), gve_probe(), hermon_bofm_probe(), hermon_probe(), hvm_probe(), igbvf_probe(), mlx_pci_init_priv(), pci_msix_ioremap(), phantom_map_crb(), skge_probe(), sky2_probe(), tg3_init_one(), undipci_find_rom(), virtio_pci_map_capability(), vmxnet3_probe(), vxge_probe(), and xhci_probe().
Read PCI device configuration.
- Parameters
-
- Return values
-
Definition at line 182 of file pci.c.
199 if ( (
tmp == 0xffffffff ) || (
tmp == 0 ) )
#define PCI_FUNC(busdevfn)
uint8_t irq
Interrupt number.
#define PCI_BUS(busdevfn)
uint32_t class
Device class.
unsigned long ioaddr
I/O address.
unsigned long ioaddr
I/O address.
#define PCI_INTERRUPT_LINE
PCI interrupt line.
unsigned long class
Device class.
unsigned int vendor
Vendor ID.
struct device dev
Generic device.
#define PCI_HEADER_TYPE
PCI header type.
uint16_t busdevfn
PCI bus:dev.fn address.
uint16_t device
Device ID.
#define BUS_TYPE_PCI
PCI bus type.
static void pci_read_bases(struct pci_device *pci)
Read membase and ioaddr for a PCI device.
int pci_read_config_dword(struct pci_device *pci, unsigned int where, uint32_t *value)
Read 32-bit dword from PCI configuration space.
#define PCI_FIRST_FUNC(busdevfn)
unsigned int location
Location.
uint8_t hdrtype
Header type.
#define PCI_SLOT(busdevfn)
struct list_head siblings
Devices on the same bus.
#define ENODEV
No such device.
#define PCI_VENDOR_ID
PCI vendor ID.
uint16_t vendor
Vendor ID.
uint32_t busdevfn
Segment, bus, device, and function (bus:dev.fn) number.
#define INIT_LIST_HEAD(list)
Initialise a list head.
unsigned int bus_type
Bus type.
unsigned int device
Device ID.
struct list_head children
Devices attached to this device.
#define PCI_REVISION
PCI revision.
struct device_description desc
Device description.
int snprintf(char *buf, size_t size, const char *fmt,...)
Write a formatted string to a buffer.
#define PCI_SEG(busdevfn)
#define PCI_HEADER_TYPE_MULTI
Multi-function device.
int pci_read_config_byte(struct pci_device *pci, unsigned int where, uint8_t *value)
Read byte from PCI configuration space.
References device_description::bus_type, BUS_TYPE_PCI, busdevfn, pci_device::busdevfn, device::children, device_description::class, pci_device::class, device::desc, pci_device::dev, device_description::device, pci_device::device, ENODEV, pci_device::hdrtype, INIT_LIST_HEAD, device_description::ioaddr, pci_device::ioaddr, device_description::irq, pci_device::irq, device_description::location, device::name, PCI_BUS, PCI_FIRST_FUNC, PCI_FUNC, PCI_HEADER_TYPE, PCI_HEADER_TYPE_MULTI, PCI_INTERRUPT_LINE, pci_read_bases(), pci_read_config_byte(), pci_read_config_dword(), PCI_REVISION, PCI_SEG, PCI_SLOT, PCI_VENDOR_ID, device::siblings, snprintf(), tmp, device_description::vendor, and pci_device::vendor.
Referenced by bofm_test_init(), efipci_open(), ehci_companion(), and pci_find_next().